sys/dev/aic7xxx/aic79xx_pci.c

   1 /*-
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#88 $
  42  */
  43
  44 #ifdef __linux__
  45 #include "aic79xx_osm.h"
  46 #include "aic79xx_inline.h"
  47 #else
  48 #include <sys/cdefs.h>
  49 __FBSDID("$FreeBSD$");
  50 #include <dev/aic7xxx/aic79xx_osm.h>
  51 #include <dev/aic7xxx/aic79xx_inline.h>
  52 #endif
  53
  54 static __inline uint64_t
  55 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  56 {
  57         uint64_t id;
  58
  59         id = subvendor
  60            | (subdevice << 16)
  61            | ((uint64_t)vendor << 32)
  62            | ((uint64_t)device << 48);
  63
  64         return (id);
  65 }
  66
  67 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  68 #define ID_ALL_IROC_MASK                0xFF7FFFFFFFFFFFFFull
  69 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  70 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  71 #define ID_9005_GENERIC_IROC_MASK       0xFF70FFFF00000000ull
  72
  73 #define ID_AIC7901                      0x800F9005FFFF9005ull
  74 #define ID_AHA_29320A                   0x8000900500609005ull
  75 #define ID_AHA_29320ALP                 0x8017900500449005ull
  76
  77 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  78 #define ID_AHA_29320LP                  0x8014900500449005ull
  79
  80 #define ID_AIC7902                      0x801F9005FFFF9005ull
  81 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  82 #define ID_AHA_39320                    0x8010900500409005ull
  83 #define ID_AHA_29320                    0x8012900500429005ull
  84 #define ID_AHA_29320B                   0x8013900500439005ull
  85 #define ID_AHA_39320_B                  0x8015900500409005ull
  86 #define ID_AHA_39320_B_DELL             0x8015900501681028ull
  87 #define ID_AHA_39320A                   0x8016900500409005ull
  88 #define ID_AHA_39320D                   0x8011900500419005ull
  89 #define ID_AHA_39320D_B                 0x801C900500419005ull
  90 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  91 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  92 #define ID_AHA_39320LPE                 0x8017900500459005ull
  93 #define ID_AIC7902_PCI_REV_A4           0x3
  94 #define ID_AIC7902_PCI_REV_B0           0x10
  95 #define SUBID_HP                        0x0E11
  96 #define DEVICE8081                      0x8081
  97 #define DEVICE8088                      0x8088
  98 #define DEVICE8089                      0x8089
  99 #define ADAPTECVENDORID                 0x9005
 100 #define SUBVENDOR9005                   0x9005
 101
 102 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
 103
 104 #define DEVID_9005_TYPE(id) ((id) & 0xF)
 105 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 106 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
 107 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 108
 109 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 110
 111 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 112
 113 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 114 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 115 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 116
 117 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 118
 119 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 120
 121 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 122 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 123 #define         SUBID_9005_SEEPTYPE_4K          0x1
 124
 125 static ahd_device_setup_t ahd_aic7901_setup;
 126 static ahd_device_setup_t ahd_aic7901A_setup;
 127 static ahd_device_setup_t ahd_aic7902_setup;
 128 static ahd_device_setup_t ahd_aic790X_setup;
 129
 130 struct ahd_pci_identity ahd_pci_ident_table [] =
 131 {
 132         /* aic7901 based controllers */
 133         {
 134                 ID_AHA_29320A,
 135                 ID_ALL_MASK,
 136                 "Adaptec 29320A Ultra320 SCSI adapter",
 137                 ahd_aic7901_setup
 138         },
 139         {
 140                 ID_AHA_29320ALP,
 141                 ID_ALL_MASK,
 142                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 143                 ahd_aic7901_setup
 144         },
 145         /* aic7901A based controllers */
 146         {
 147                 ID_AHA_29320LP,
 148                 ID_ALL_MASK,
 149                 "Adaptec 29320LP Ultra320 SCSI adapter",
 150                 ahd_aic7901A_setup
 151         },
 152         /* aic7902 based controllers */
 153         {
 154                 ID_AHA_29320,
 155                 ID_ALL_MASK,
 156                 "Adaptec 29320 Ultra320 SCSI adapter",
 157                 ahd_aic7902_setup
 158         },
 159         {
 160                 ID_AHA_29320B,
 161                 ID_ALL_MASK,
 162                 "Adaptec 29320B Ultra320 SCSI adapter",
 163                 ahd_aic7902_setup
 164         },
 165         {
 166                 ID_AHA_39320,
 167                 ID_ALL_MASK,
 168                 "Adaptec 39320 Ultra320 SCSI adapter",
 169                 ahd_aic7902_setup
 170         },
 171         {
 172                 ID_AHA_39320_B,
 173                 ID_ALL_MASK,
 174                 "Adaptec 39320 Ultra320 SCSI adapter",
 175                 ahd_aic7902_setup
 176         },
 177         {
 178                 ID_AHA_39320_B_DELL,
 179                 ID_ALL_MASK,
 180                 "Adaptec (Dell OEM) 39320 Ultra320 SCSI adapter",
 181                 ahd_aic7902_setup
 182         },
 183         {
 184                 ID_AHA_39320A,
 185                 ID_ALL_MASK,
 186                 "Adaptec 39320A Ultra320 SCSI adapter",
 187                 ahd_aic7902_setup
 188         },
 189         {
 190                 ID_AHA_39320D,
 191                 ID_ALL_MASK,
 192                 "Adaptec 39320D Ultra320 SCSI adapter",
 193                 ahd_aic7902_setup
 194         },
 195         {
 196                 ID_AHA_39320D_HP,
 197                 ID_ALL_MASK,
 198                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 199                 ahd_aic7902_setup
 200         },
 201         {
 202                 ID_AHA_39320D_B,
 203                 ID_ALL_MASK,
 204                 "Adaptec 39320D Ultra320 SCSI adapter",
 205                 ahd_aic7902_setup
 206         },
 207         {
 208                 ID_AHA_39320D_B_HP,
 209                 ID_ALL_MASK,
 210                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 211                 ahd_aic7902_setup
 212         },
 213         {
 214                 ID_AHA_39320LPE,
 215                 ID_ALL_MASK,
 216                 "Adaptec 39320LPE Ultra320 SCSI adapter",
 217                 ahd_aic7902_setup
 218         },
 219         /* Generic chip probes for devices we don't know 'exactly' */
 220         {
 221                 ID_AIC7901 & ID_9005_GENERIC_MASK,
 222                 ID_9005_GENERIC_MASK,
 223                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 224                 ahd_aic7901_setup
 225         },
 226         {
 227                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 228                 ID_DEV_VENDOR_MASK,
 229                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 230                 ahd_aic7901A_setup
 231         },
 232         {
 233                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 234                 ID_9005_GENERIC_MASK,
 235                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 236                 ahd_aic7902_setup
 237         }
 238 };
 239
 240 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 241
 242 #define DEVCONFIG               0x40
 243 #define         PCIXINITPAT     0x0000E000ul
 244 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 245 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 246 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 247 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 248 #define PCI_BUS_MODES_INDEX(devconfig)  \
 249         (((devconfig) & PCIXINITPAT) >> 13)
 250 static const char *pci_bus_modes[] =
 251 {
 252         "PCI bus mode unknown",
 253         "PCI bus mode unknown",
 254         "PCI bus mode unknown",
 255         "PCI bus mode unknown",
 256         "PCI-X 101-133MHz",
 257         "PCI-X 67-100MHz",
 258         "PCI-X 50-66MHz",
 259         "PCI 33 or 66MHz"
 260 };
 261
 262 #define         TESTMODE        0x00000800ul
 263 #define         IRDY_RST        0x00000200ul
 264 #define         FRAME_RST       0x00000100ul
 265 #define         PCI64BIT        0x00000080ul
 266 #define         MRDCEN          0x00000040ul
 267 #define         ENDIANSEL       0x00000020ul
 268 #define         MIXQWENDIANEN   0x00000008ul
 269 #define         DACEN           0x00000004ul
 270 #define         STPWLEVEL       0x00000002ul
 271 #define         QWENDIANSEL     0x00000001ul
 272
 273 #define DEVCONFIG1              0x44
 274 #define         PREQDIS         0x01
 275
 276 #define CSIZE_LATTIME           0x0c
 277 #define         CACHESIZE       0x000000fful
 278 #define         LATTIME         0x0000ff00ul
 279
 280 static int      ahd_check_extport(struct ahd_softc *ahd);
 281 static void     ahd_configure_termination(struct ahd_softc *ahd,
 282                                           u_int adapter_control);
 283 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 284
 285 struct ahd_pci_identity *
 286 ahd_find_pci_device(aic_dev_softc_t pci)
 287 {
 288         uint64_t  full_id;
 289         uint16_t  device;
 290         uint16_t  vendor;
 291         uint16_t  subdevice;
 292         uint16_t  subvendor;
 293         struct    ahd_pci_identity *entry;
 294         u_int     i;
 295
 296         vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 297         device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 298         subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 299         subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 300
 301         if ((vendor == ADAPTECVENDORID) && (subvendor == SUBVENDOR9005)) {
 302                 if ((device == DEVICE8081) || (device == DEVICE8088) ||
 303                         (device == DEVICE8089)) {
 304                         printf("Controller device ID conflict with PMC Adaptec HBA\n");
 305                         return (NULL);
 306                 }
 307         }
 308
 309         full_id = ahd_compose_id(device,
 310                                  vendor,
 311                                  subdevice,
 312                                  subvendor);
 313
 314         /*
 315          * If we are configured to attach to HostRAID
 316          * controllers, mask out the IROC/HostRAID bit
 317          * in the
 318          */
 319         if (ahd_attach_to_HostRAID_controllers)
 320                 full_id &= ID_ALL_IROC_MASK;
 321
 322         for (i = 0; i < ahd_num_pci_devs; i++) {
 323                 entry = &ahd_pci_ident_table[i];
 324                 if (entry->full_id == (full_id & entry->id_mask)) {
 325                         /* Honor exclusion entries. */
 326                         if (entry->name == NULL)
 327                                 return (NULL);
 328                         return (entry);
 329                 }
 330         }
 331         return (NULL);
 332 }
 333
 334 int
 335 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 336 {
 337         struct scb_data *shared_scb_data;
 338         u_int            command;
 339         uint32_t         devconfig;
 340         uint16_t         device;
 341         uint16_t         subvendor;
 342         int              error;
 343
 344         shared_scb_data = NULL;
 345         ahd->description = entry->name;
 346         /*
 347          * Record if this is a HostRAID board.
 348          */
 349         device = aic_pci_read_config(ahd->dev_softc,
 350                                      PCIR_DEVICE, /*bytes*/2);
 351         if (DEVID_9005_HOSTRAID(device))
 352                 ahd->flags |= AHD_HOSTRAID_BOARD;
 353
 354         /*
 355          * Record if this is an HP board.
 356          */
 357         subvendor = aic_pci_read_config(ahd->dev_softc,
 358                                         PCIR_SUBVEND_0, /*bytes*/2);
 359         if (subvendor == SUBID_HP)
 360                 ahd->flags |= AHD_HP_BOARD;
 361
 362         error = entry->setup(ahd);
 363         if (error != 0)
 364                 return (error);
 365
 366         /*
 367          * Find the PCI-X cap pointer.  If we don't find it,
 368          * pcix_ptr will be 0.
 369          */
 370         pci_find_cap(ahd->dev_softc, PCIY_PCIX, &ahd->pcix_ptr);
 371         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 372         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 373                 ahd->chip |= AHD_PCI;
 374                 /* Disable PCIX workarounds when running in PCI mode. */
 375                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 376         } else {
 377                 ahd->chip |= AHD_PCIX;
 378                 if (ahd->pcix_ptr == 0)
 379                         return (ENXIO);
 380         }
 381         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 382
 383         aic_power_state_change(ahd, AIC_POWER_STATE_D0);
 384
 385         error = ahd_pci_map_registers(ahd);
 386         if (error != 0)
 387                 return (error);
 388
 389         /*
 390          * If we need to support high memory, enable dual
 391          * address cycles.  This bit must be set to enable
 392          * high address bit generation even if we are on a
 393          * 64bit bus (PCI64BIT set in devconfig).
 394          */
 395         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 396                 uint32_t devconfig;
 397
 398                 if (bootverbose)
 399                         printf("%s: Enabling 39Bit Addressing\n",
 400                                ahd_name(ahd));
 401                 devconfig = aic_pci_read_config(ahd->dev_softc,
 402                                                 DEVCONFIG, /*bytes*/4);
 403                 devconfig |= DACEN;
 404                 aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
 405                                      devconfig, /*bytes*/4);
 406         }
 407
 408         /* Ensure busmastering is enabled */
 409         command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 410         command |= PCIM_CMD_BUSMASTEREN;
 411         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 412
 413         error = ahd_softc_init(ahd);
 414         if (error != 0)
 415                 return (error);
 416
 417         ahd->bus_intr = ahd_pci_intr;
 418
 419         error = ahd_reset(ahd, /*reinit*/FALSE);
 420         if (error != 0)
 421                 return (ENXIO);
 422
 423         ahd->pci_cachesize =
 424             aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 425                                 /*bytes*/1) & CACHESIZE;
 426         ahd->pci_cachesize *= 4;
 427
 428         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 429         /* See if we have a SEEPROM and perform auto-term */
 430         error = ahd_check_extport(ahd);
 431         if (error != 0)
 432                 return (error);
 433
 434         /* Core initialization */
 435         error = ahd_init(ahd);
 436         if (error != 0)
 437                 return (error);
 438
 439         /*
 440          * Allow interrupts now that we are completely setup.
 441          */
 442         error = ahd_pci_map_int(ahd);
 443         if (error != 0)
 444                 return (error);
 445
 446         ahd_lock(ahd);
 447         /*
 448          * Link this softc in with all other ahd instances.
 449          */
 450         ahd_softc_insert(ahd);
 451         ahd_unlock(ahd);
 452         return (0);
 453 }
 454
 455 /*
 456  * Perform some simple tests that should catch situations where
 457  * our registers are invalidly mapped.
 458  */
 459 int
 460 ahd_pci_test_register_access(struct ahd_softc *ahd)
 461 {
 462         uint32_t cmd;
 463         u_int    targpcistat;
 464         u_int    pci_status1;
 465         int      error;
 466         uint8_t  hcntrl;
 467
 468         error = EIO;
 469
 470         /*
 471          * Enable PCI error interrupt status, but suppress NMIs
 472          * generated by SERR raised due to target aborts.
 473          */
 474         cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 475         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 476                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 477
 478         /*
 479          * First a simple test to see if any
 480          * registers can be read.  Reading
 481          * HCNTRL has no side effects and has
 482          * at least one bit that is guaranteed to
 483          * be zero so it is a good register to
 484          * use for this test.
 485          */
 486         hcntrl = ahd_inb(ahd, HCNTRL);
 487         if (hcntrl == 0xFF)
 488                 goto fail;
 489
 490         /*
 491          * Next create a situation where write combining
 492          * or read prefetching could be initiated by the
 493          * CPU or host bridge.  Our device does not support
 494          * either, so look for data corruption and/or flaged
 495          * PCI errors.  First pause without causing another
 496          * chip reset.
 497          */
 498         hcntrl &= ~CHIPRST;
 499         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 500         while (ahd_is_paused(ahd) == 0)
 501                 ;
 502
 503         /* Clear any PCI errors that occurred before our driver attached. */
 504         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 505         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 506         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 507         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 508                                           PCIR_STATUS + 1, /*bytes*/1);
 509         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 510                              pci_status1, /*bytes*/1);
 511         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 512         ahd_outb(ahd, CLRINT, CLRPCIINT);
 513
 514         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 515         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 516         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 517                 goto fail;
 518
 519         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 520                 u_int targpcistat;
 521
 522                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 523                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 524                 if ((targpcistat & STA) != 0)
 525                         goto fail;
 526         }
 527
 528         error = 0;
 529
 530 fail:
 531         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 532
 533                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 534                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 535
 536                 /* Silently clear any latched errors. */
 537                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 538                 pci_status1 = aic_pci_read_config(ahd->dev_softc,
 539                                                   PCIR_STATUS + 1, /*bytes*/1);
 540                 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 541                                      pci_status1, /*bytes*/1);
 542                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 543         }
 544         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 545         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 546         return (error);
 547 }
 548
 549 /*
 550  * Check the external port logic for a serial eeprom
 551  * and termination/cable detection contrls.
 552  */
 553 static int
 554 ahd_check_extport(struct ahd_softc *ahd)
 555 {
 556         struct  vpd_config vpd;
 557         struct  seeprom_config *sc;
 558         u_int   adapter_control;
 559         int     have_seeprom;
 560         int     error;
 561
 562         sc = ahd->seep_config;
 563         have_seeprom = ahd_acquire_seeprom(ahd);
 564         if (have_seeprom) {
 565                 u_int start_addr;
 566
 567                 /*
 568                  * Fetch VPD for this function and parse it.
 569                  */
 570                 if (bootverbose)
 571                         printf("%s: Reading VPD from SEEPROM...",
 572                                ahd_name(ahd));
 573
 574                 /* Address is always in units of 16bit words */
 575                 start_addr = ((2 * sizeof(*sc))
 576                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 577
 578                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 579                                          start_addr, sizeof(vpd)/2,
 580                                          /*bytestream*/TRUE);
 581                 if (error == 0)
 582                         error = ahd_parse_vpddata(ahd, &vpd);
 583                 if (bootverbose)
 584                         printf("%s: VPD parsing %s\n",
 585                                ahd_name(ahd),
 586                                error == 0 ? "successful" : "failed");
 587
 588                 if (bootverbose)
 589                         printf("%s: Reading SEEPROM...", ahd_name(ahd));
 590
 591                 /* Address is always in units of 16bit words */
 592                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 593
 594                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 595                                          start_addr, sizeof(*sc)/2,
 596                                          /*bytestream*/FALSE);
 597
 598                 if (error != 0) {
 599                         printf("Unable to read SEEPROM\n");
 600                         have_seeprom = 0;
 601                 } else {
 602                         have_seeprom = ahd_verify_cksum(sc);
 603
 604                         if (bootverbose) {
 605                                 if (have_seeprom == 0)
 606                                         printf ("checksum error\n");
 607                                 else
 608                                         printf ("done.\n");
 609                         }
 610                 }
 611                 ahd_release_seeprom(ahd);
 612         }
 613
 614         if (!have_seeprom) {
 615                 u_int     nvram_scb;
 616
 617                 /*
 618                  * Pull scratch ram settings and treat them as
 619                  * if they are the contents of an seeprom if
 620                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 621                  * in SCB 0xFF.  We manually compose the data as 16bit
 622                  * values to avoid endian issues.
 623                  */
 624                 ahd_set_scbptr(ahd, 0xFF);
 625                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 626                 if (nvram_scb != 0xFF
 627                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 628                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 629                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 630                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 631                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 632                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 633                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 634                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 635                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 636                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 637                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 638                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 639                         uint16_t *sc_data;
 640                         int       i;
 641
 642                         ahd_set_scbptr(ahd, nvram_scb);
 643                         sc_data = (uint16_t *)sc;
 644                         for (i = 0; i < 64; i += 2)
 645                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 646                         have_seeprom = ahd_verify_cksum(sc);
 647                         if (have_seeprom)
 648                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 649                 }
 650         }
 651
 652 #ifdef AHD_DEBUG
 653         if (have_seeprom != 0
 654          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 655                 uint16_t *sc_data;
 656                 int       i;
 657
 658                 printf("%s: Seeprom Contents:", ahd_name(ahd));
 659                 sc_data = (uint16_t *)sc;
 660                 for (i = 0; i < (sizeof(*sc)); i += 2)
 661                         printf("\n\t0x%.4x", sc_data[i]);
 662                 printf("\n");
 663         }
 664 #endif
 665
 666         if (!have_seeprom) {
 667                 if (bootverbose)
 668                         printf("%s: No SEEPROM available.\n", ahd_name(ahd));
 669                 ahd->flags |= AHD_USEDEFAULTS;
 670                 error = ahd_default_config(ahd);
 671                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 672                 free(ahd->seep_config, M_DEVBUF);
 673                 ahd->seep_config = NULL;
 674         } else {
 675                 error = ahd_parse_cfgdata(ahd, sc);
 676                 adapter_control = sc->adapter_control;
 677         }
 678         if (error != 0)
 679                 return (error);
 680
 681         ahd_configure_termination(ahd, adapter_control);
 682
 683         return (0);
 684 }
 685
 686 static void
 687 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 688 {
 689         int      error;
 690         u_int    sxfrctl1;
 691         uint8_t  termctl;
 692         uint32_t devconfig;
 693
 694         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 695         devconfig &= ~STPWLEVEL;
 696         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 697                 devconfig |= STPWLEVEL;
 698         if (bootverbose)
 699                 printf("%s: STPWLEVEL is %s\n",
 700                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 701         aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 702
 703         /* Make sure current sensing is off. */
 704         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 705                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 706         }
 707
 708         /*
 709          * Read to sense.  Write to set.
 710          */
 711         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 712         if ((adapter_control & CFAUTOTERM) == 0) {
 713                 if (bootverbose)
 714                         printf("%s: Manual Primary Termination\n",
 715                                ahd_name(ahd));
 716                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 717                 if ((adapter_control & CFSTERM) != 0)
 718                         termctl |= FLX_TERMCTL_ENPRILOW;
 719                 if ((adapter_control & CFWSTERM) != 0)
 720                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 721         } else if (error != 0) {
 722                 printf("%s: Primary Auto-Term Sensing failed! "
 723                        "Using Defaults.\n", ahd_name(ahd));
 724                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 725         }
 726
 727         if ((adapter_control & CFSEAUTOTERM) == 0) {
 728                 if (bootverbose)
 729                         printf("%s: Manual Secondary Termination\n",
 730                                ahd_name(ahd));
 731                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 732                 if ((adapter_control & CFSELOWTERM) != 0)
 733                         termctl |= FLX_TERMCTL_ENSECLOW;
 734                 if ((adapter_control & CFSEHIGHTERM) != 0)
 735                         termctl |= FLX_TERMCTL_ENSECHIGH;
 736         } else if (error != 0) {
 737                 printf("%s: Secondary Auto-Term Sensing failed! "
 738                        "Using Defaults.\n", ahd_name(ahd));
 739                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 740         }
 741
 742         /*
 743          * Now set the termination based on what we found.
 744          */
 745         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 746         ahd->flags &= ~AHD_TERM_ENB_A;
 747         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 748                 ahd->flags |= AHD_TERM_ENB_A;
 749                 sxfrctl1 |= STPWEN;
 750         }
 751         /* Must set the latch once in order to be effective. */
 752         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 753         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 754
 755         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 756         if (error != 0) {
 757                 printf("%s: Unable to set termination settings!\n",
 758                        ahd_name(ahd));
 759         } else if (bootverbose) {
 760                 printf("%s: Primary High byte termination %sabled\n",
 761                        ahd_name(ahd),
 762                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 763
 764                 printf("%s: Primary Low byte termination %sabled\n",
 765                        ahd_name(ahd),
 766                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 767
 768                 printf("%s: Secondary High byte termination %sabled\n",
 769                        ahd_name(ahd),
 770                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 771
 772                 printf("%s: Secondary Low byte termination %sabled\n",
 773                        ahd_name(ahd),
 774                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 775         }
 776         return;
 777 }
 778
 779 #define DPE     0x80
 780 #define SSE     0x40
 781 #define RMA     0x20
 782 #define RTA     0x10
 783 #define STA     0x08
 784 #define DPR     0x01
 785
 786 static const char *split_status_source[] =
 787 {
 788         "DFF0",
 789         "DFF1",
 790         "OVLY",
 791         "CMC",
 792 };
 793
 794 static const char *pci_status_source[] =
 795 {
 796         "DFF0",
 797         "DFF1",
 798         "SG",
 799         "CMC",
 800         "OVLY",
 801         "NONE",
 802         "MSI",
 803         "TARG"
 804 };
 805
 806 static const char *split_status_strings[] =
 807 {
 808         "%s: Received split response in %s.\n",
 809         "%s: Received split completion error message in %s\n",
 810         "%s: Receive overrun in %s\n",
 811         "%s: Count not complete in %s\n",
 812         "%s: Split completion data bucket in %s\n",
 813         "%s: Split completion address error in %s\n",
 814         "%s: Split completion byte count error in %s\n",
 815         "%s: Signaled Target-abort to early terminate a split in %s\n"
 816 };
 817
 818 static const char *pci_status_strings[] =
 819 {
 820         "%s: Data Parity Error has been reported via PERR# in %s\n",
 821         "%s: Target initial wait state error in %s\n",
 822         "%s: Split completion read data parity error in %s\n",
 823         "%s: Split completion address attribute parity error in %s\n",
 824         "%s: Received a Target Abort in %s\n",
 825         "%s: Received a Master Abort in %s\n",
 826         "%s: Signal System Error Detected in %s\n",
 827         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 828 };
 829
 830 void
 831 ahd_pci_intr(struct ahd_softc *ahd)
 832 {
 833         uint8_t         pci_status[8];
 834         ahd_mode_state  saved_modes;
 835         u_int           pci_status1;
 836         u_int           intstat;
 837         u_int           i;
 838         u_int           reg;
 839
 840         intstat = ahd_inb(ahd, INTSTAT);
 841
 842         if ((intstat & SPLTINT) != 0)
 843                 ahd_pci_split_intr(ahd, intstat);
 844
 845         if ((intstat & PCIINT) == 0)
 846                 return;
 847
 848         printf("%s: PCI error Interrupt\n", ahd_name(ahd));
 849         saved_modes = ahd_save_modes(ahd);
 850         ahd_dump_card_state(ahd);
 851         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 852         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 853
 854                 if (i == 5)
 855                         continue;
 856                 pci_status[i] = ahd_inb(ahd, reg);
 857                 /* Clear latched errors.  So our interrupt deasserts. */
 858                 ahd_outb(ahd, reg, pci_status[i]);
 859         }
 860
 861         for (i = 0; i < 8; i++) {
 862                 u_int bit;
 863
 864                 if (i == 5)
 865                         continue;
 866
 867                 for (bit = 0; bit < 8; bit++) {
 868
 869                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 870                                 static const char *s;
 871
 872                                 s = pci_status_strings[bit];
 873                                 if (i == 7/*TARG*/ && bit == 3)
 874                                         s = "%s: Signaled Target Abort\n";
 875                                 printf(s, ahd_name(ahd), pci_status_source[i]);
 876                         }
 877                 }
 878         }
 879         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 880                                           PCIR_STATUS + 1, /*bytes*/1);
 881         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 882                              pci_status1, /*bytes*/1);
 883         ahd_restore_modes(ahd, saved_modes);
 884         ahd_outb(ahd, CLRINT, CLRPCIINT);
 885         ahd_unpause(ahd);
 886 }
 887
 888 static void
 889 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 890 {
 891         uint8_t         split_status[4];
 892         uint8_t         split_status1[4];
 893         uint8_t         sg_split_status[2];
 894         uint8_t         sg_split_status1[2];
 895         ahd_mode_state  saved_modes;
 896         u_int           i;
 897         uint32_t        pcix_status;
 898
 899         /*
 900          * Check for splits in all modes.  Modes 0 and 1
 901          * additionally have SG engine splits to look at.
 902          */
 903         pcix_status = aic_pci_read_config(ahd->dev_softc,
 904             ahd->pcix_ptr + PCIXR_STATUS, /*bytes*/ 4);
 905         printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 906                ahd_name(ahd), pcix_status >> 16);
 907         saved_modes = ahd_save_modes(ahd);
 908         for (i = 0; i < 4; i++) {
 909                 ahd_set_modes(ahd, i, i);
 910
 911                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 912                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 913                 /* Clear latched errors.  So our interrupt deasserts. */
 914                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 915                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 916                 if (i > 1)
 917                         continue;
 918                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 919                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 920                 /* Clear latched errors.  So our interrupt deasserts. */
 921                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 922                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 923         }
 924
 925         for (i = 0; i < 4; i++) {
 926                 u_int bit;
 927
 928                 for (bit = 0; bit < 8; bit++) {
 929
 930                         if ((split_status[i] & (0x1 << bit)) != 0) {
 931                                 static const char *s;
 932
 933                                 s = split_status_strings[bit];
 934                                 printf(s, ahd_name(ahd),
 935                                        split_status_source[i]);
 936                         }
 937
 938                         if (i > 1)
 939                                 continue;
 940
 941                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 942                                 static const char *s;
 943
 944                                 s = split_status_strings[bit];
 945                                 printf(s, ahd_name(ahd), "SG");
 946                         }
 947                 }
 948         }
 949         /*
 950          * Clear PCI-X status bits.
 951          */
 952         aic_pci_write_config(ahd->dev_softc, ahd->pcix_ptr + PCIXR_STATUS,
 953                              pcix_status, /*bytes*/4);
 954         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 955         ahd_restore_modes(ahd, saved_modes);
 956 }
 957
 958 static int
 959 ahd_aic7901_setup(struct ahd_softc *ahd)
 960 {
 961
 962         ahd->chip = AHD_AIC7901;
 963         ahd->features = AHD_AIC7901_FE;
 964         return (ahd_aic790X_setup(ahd));
 965 }
 966
 967 static int
 968 ahd_aic7901A_setup(struct ahd_softc *ahd)
 969 {
 970
 971         ahd->chip = AHD_AIC7901A;
 972         ahd->features = AHD_AIC7901A_FE;
 973         return (ahd_aic790X_setup(ahd));
 974 }
 975
 976 static int
 977 ahd_aic7902_setup(struct ahd_softc *ahd)
 978 {
 979         ahd->chip = AHD_AIC7902;
 980         ahd->features = AHD_AIC7902_FE;
 981         return (ahd_aic790X_setup(ahd));
 982 }
 983
 984 static int
 985 ahd_aic790X_setup(struct ahd_softc *ahd)
 986 {
 987         aic_dev_softc_t pci;
 988         u_int rev;
 989
 990         pci = ahd->dev_softc;
 991         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 992         if (rev < ID_AIC7902_PCI_REV_A4) {
 993                 printf("%s: Unable to attach to unsupported chip revision %d\n",
 994                        ahd_name(ahd), rev);
 995                 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 996                 return (ENXIO);
 997         }
 998         ahd->channel = aic_get_pci_function(pci) + 'A';
 999         if (rev < ID_AIC7902_PCI_REV_B0) {
1000                 /*
1001                  * Enable A series workarounds.
1002                  */
1003                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
1004                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
1005                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
1006                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
1007                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
1008                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
1009                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
1010                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
1011                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
1012                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
1013                           |  AHD_FAINT_LED_BUG;
1014
1015                 /*
1016                  * IO Cell paramter setup.
1017                  */
1018                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1019
1020                 if ((ahd->flags & AHD_HP_BOARD) == 0)
1021                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
1022         } else {
1023                 u_int devconfig1;
1024
1025                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
1026                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
1027                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
1028
1029                 /*
1030                  * Some issues have been resolved in the 7901B.
1031                  */
1032                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
1033                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG
1034                                   |  AHD_BUSFREEREV_BUG;
1035
1036                 /*
1037                  * IO Cell paramter setup.
1038                  */
1039                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1040                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1041                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1042
1043                 /*
1044                  * Set the PREQDIS bit for H2B which disables some workaround
1045                  * that doesn't work on regular PCI busses.
1046                  * XXX - Find out exactly what this does from the hardware
1047                  *       folks!
1048                  */
1049                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1050                 aic_pci_write_config(pci, DEVCONFIG1,
1051                                      devconfig1|PREQDIS, /*bytes*/1);
1052                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1053         }
1054
1055         return (0);
1056 }