sys/dev/arcmsr/arcmsr.c

   1 /*
   2 ********************************************************************************
   3 **        OS    : FreeBSD
   4 **   FILE NAME  : arcmsr.c
   5 **        BY    : Erich Chen, Ching Huang
   6 **   Description: SCSI RAID Device Driver for
   7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
   8 **                SATA/SAS RAID HOST Adapter
   9 ********************************************************************************
  10 ********************************************************************************
  11 **
  12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
  13 **
  14 ** Redistribution and use in source and binary forms, with or without
  15 ** modification, are permitted provided that the following conditions
  16 ** are met:
  17 ** 1. Redistributions of source code must retain the above copyright
  18 **    notice, this list of conditions and the following disclaimer.
  19 ** 2. Redistributions in binary form must reproduce the above copyright
  20 **    notice, this list of conditions and the following disclaimer in the
  21 **    documentation and/or other materials provided with the distribution.
  22 ** 3. The name of the author may not be used to endorse or promote products
  23 **    derived from this software without specific prior written permission.
  24 **
  25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
  30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 ********************************************************************************
  36 ** History
  37 **
  38 **    REV#         DATE         NAME        DESCRIPTION
  39 ** 1.00.00.00   03/31/2004  Erich Chen      First release
  40 ** 1.20.00.02   11/29/2004  Erich Chen      bug fix with arcmsr_bus_reset when PHY error
  41 ** 1.20.00.03   04/19/2005  Erich Chen      add SATA 24 Ports adapter type support
  42 **                                          clean unused function
  43 ** 1.20.00.12   09/12/2005  Erich Chen      bug fix with abort command handling,
  44 **                                          firmware version check
  45 **                                          and firmware update notify for hardware bug fix
  46 **                                          handling if none zero high part physical address
  47 **                                          of srb resource
  48 ** 1.20.00.13   08/18/2006  Erich Chen      remove pending srb and report busy
  49 **                                          add iop message xfer
  50 **                                          with scsi pass-through command
  51 **                                          add new device id of sas raid adapters
  52 **                                          code fit for SPARC64 & PPC
  53 ** 1.20.00.14   02/05/2007  Erich Chen      bug fix for incorrect ccb_h.status report
  54 **                                          and cause g_vfs_done() read write error
  55 ** 1.20.00.15   10/10/2007  Erich Chen      support new RAID adapter type ARC120x
  56 ** 1.20.00.16   10/10/2009  Erich Chen      Bug fix for RAID adapter type ARC120x
  57 **                                          bus_dmamem_alloc() with BUS_DMA_ZERO
  58 ** 1.20.00.17   07/15/2010  Ching Huang     Added support ARC1880
  59 **                                          report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
  60 **                                          prevent cam_periph_error removing all LUN devices of one Target id
  61 **                                          for any one LUN device failed
  62 ** 1.20.00.18   10/14/2010  Ching Huang     Fixed "inquiry data fails comparion at DV1 step"
  63 **              10/25/2010  Ching Huang     Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
  64 ** 1.20.00.19   11/11/2010  Ching Huang     Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
  65 ** 1.20.00.20   12/08/2010  Ching Huang     Avoid calling atomic_set_int function
  66 ** 1.20.00.21   02/08/2011  Ching Huang     Implement I/O request timeout
  67 **              02/14/2011  Ching Huang     Modified pktRequestCount
  68 ** 1.20.00.21   03/03/2011  Ching Huang     if a command timeout, then wait its ccb back before free it
  69 ** 1.20.00.22   07/04/2011  Ching Huang     Fixed multiple MTX panic
  70 ** 1.20.00.23   10/28/2011  Ching Huang     Added TIMEOUT_DELAY in case of too many HDDs need to start
  71 ** 1.20.00.23   11/08/2011  Ching Huang     Added report device transfer speed
  72 ** 1.20.00.23   01/30/2012  Ching Huang     Fixed Request requeued and Retrying command
  73 ** 1.20.00.24   06/11/2012  Ching Huang     Fixed return sense data condition
  74 ** 1.20.00.25   08/17/2012  Ching Huang     Fixed hotplug device no function on type A adapter
  75 ** 1.20.00.26   12/14/2012  Ching Huang     Added support ARC1214,1224,1264,1284
  76 ** 1.20.00.27   05/06/2013  Ching Huang     Fixed out standing cmd full on ARC-12x4
  77 ** 1.20.00.28   09/13/2013  Ching Huang     Removed recursive mutex in arcmsr_abort_dr_ccbs
  78 ******************************************************************************************
  79 */
  80
  81 #include <sys/cdefs.h>
  82 __FBSDID("$FreeBSD$");
  83
  84 #if 0
  85 #define ARCMSR_DEBUG1                   1
  86 #endif
  87 #include <sys/param.h>
  88 #include <sys/systm.h>
  89 #include <sys/malloc.h>
  90 #include <sys/kernel.h>
  91 #include <sys/bus.h>
  92 #include <sys/queue.h>
  93 #include <sys/stat.h>
  94 #include <sys/devicestat.h>
  95 #include <sys/kthread.h>
  96 #include <sys/module.h>
  97 #include <sys/proc.h>
  98 #include <sys/lock.h>
  99 #include <sys/sysctl.h>
 100 #include <sys/poll.h>
 101 #include <sys/ioccom.h>
 102 #include <vm/vm.h>
 103 #include <vm/vm_param.h>
 104 #include <vm/pmap.h>
 105
 106 #include <isa/rtc.h>
 107
 108 #include <machine/bus.h>
 109 #include <machine/resource.h>
 110 #include <machine/atomic.h>
 111 #include <sys/conf.h>
 112 #include <sys/rman.h>
 113
 114 #include <cam/cam.h>
 115 #include <cam/cam_ccb.h>
 116 #include <cam/cam_sim.h>
 117 #include <cam/cam_periph.h>
 118 #include <cam/cam_xpt_periph.h>
 119 #include <cam/cam_xpt_sim.h>
 120 #include <cam/cam_debug.h>
 121 #include <cam/scsi/scsi_all.h>
 122 #include <cam/scsi/scsi_message.h>
 123 /*
 124 **************************************************************************
 125 **************************************************************************
 126 */
 127 #if __FreeBSD_version >= 500005
 128     #include <sys/selinfo.h>
 129     #include <sys/mutex.h>
 130     #include <sys/endian.h>
 131     #include <dev/pci/pcivar.h>
 132     #include <dev/pci/pcireg.h>
 133 #else
 134     #include <sys/select.h>
 135     #include <pci/pcivar.h>
 136     #include <pci/pcireg.h>
 137 #endif
 138
 139 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
 140 #define CAM_NEW_TRAN_CODE       1
 141 #endif
 142
 143 #if __FreeBSD_version > 500000
 144 #define arcmsr_callout_init(a)  callout_init(a, /*mpsafe*/1);
 145 #else
 146 #define arcmsr_callout_init(a)  callout_init(a);
 147 #endif
 148
 149 #define ARCMSR_DRIVER_VERSION   "arcmsr version 1.20.00.28 2013-09-13"
 150 #include <dev/arcmsr/arcmsr.h>
 151 /*
 152 **************************************************************************
 153 **************************************************************************
 154 */
 155 static void arcmsr_free_srb(struct CommandControlBlock *srb);
 156 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
 157 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
 158 static int arcmsr_probe(device_t dev);
 159 static int arcmsr_attach(device_t dev);
 160 static int arcmsr_detach(device_t dev);
 161 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
 162 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
 163 static int arcmsr_shutdown(device_t dev);
 164 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
 165 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
 166 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
 167 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
 168 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
 169 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
 170 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
 171 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
 172 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
 173 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
 174 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
 175 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
 176 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
 177 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
 178 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
 179 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
 180 static int arcmsr_resume(device_t dev);
 181 static int arcmsr_suspend(device_t dev);
 182 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
 183 static void     arcmsr_polling_devmap(void *arg);
 184 static void     arcmsr_srb_timeout(void *arg);
 185 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
 186 #ifdef ARCMSR_DEBUG1
 187 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
 188 #endif
 189 /*
 190 **************************************************************************
 191 **************************************************************************
 192 */
 193 static void UDELAY(u_int32_t us) { DELAY(us); }
 194 /*
 195 **************************************************************************
 196 **************************************************************************
 197 */
 198 static bus_dmamap_callback_t arcmsr_map_free_srb;
 199 static bus_dmamap_callback_t arcmsr_execute_srb;
 200 /*
 201 **************************************************************************
 202 **************************************************************************
 203 */
 204 static d_open_t arcmsr_open;
 205 static d_close_t arcmsr_close;
 206 static d_ioctl_t arcmsr_ioctl;
 207
 208 static device_method_t arcmsr_methods[]={
 209         DEVMETHOD(device_probe,         arcmsr_probe),
 210         DEVMETHOD(device_attach,        arcmsr_attach),
 211         DEVMETHOD(device_detach,        arcmsr_detach),
 212         DEVMETHOD(device_shutdown,      arcmsr_shutdown),
 213         DEVMETHOD(device_suspend,       arcmsr_suspend),
 214         DEVMETHOD(device_resume,        arcmsr_resume),
 215
 216 #if __FreeBSD_version >= 803000
 217         DEVMETHOD_END
 218 #else
 219         { 0, 0 }
 220 #endif
 221 };
 222
 223 static driver_t arcmsr_driver={
 224         "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
 225 };
 226
 227 static devclass_t arcmsr_devclass;
 228 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
 229 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
 230 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
 231 #ifndef BUS_DMA_COHERENT
 232         #define BUS_DMA_COHERENT        0x04    /* hint: map memory in a coherent way */
 233 #endif
 234 #if __FreeBSD_version >= 501000
 235 static struct cdevsw arcmsr_cdevsw={
 236         #if __FreeBSD_version >= 503000
 237                 .d_version = D_VERSION,
 238         #endif
 239         #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
 240                 .d_flags   = D_NEEDGIANT,
 241         #endif
 242                 .d_open    = arcmsr_open,       /* open     */
 243                 .d_close   = arcmsr_close,      /* close    */
 244                 .d_ioctl   = arcmsr_ioctl,      /* ioctl    */
 245                 .d_name    = "arcmsr",          /* name     */
 246         };
 247 #else
 248         #define ARCMSR_CDEV_MAJOR       180
 249
 250 static struct cdevsw arcmsr_cdevsw = {
 251                 arcmsr_open,                            /* open     */
 252                 arcmsr_close,                           /* close    */
 253                 noread,                                         /* read     */
 254                 nowrite,                                        /* write    */
 255                 arcmsr_ioctl,                           /* ioctl    */
 256                 nopoll,                                         /* poll     */
 257                 nommap,                                         /* mmap     */
 258                 nostrategy,                                     /* strategy */
 259                 "arcmsr",                                       /* name     */
 260                 ARCMSR_CDEV_MAJOR,                      /* major    */
 261                 nodump,                                         /* dump     */
 262                 nopsize,                                        /* psize    */
 263                 0                                                       /* flags    */
 264         };
 265 #endif
 266 /*
 267 **************************************************************************
 268 **************************************************************************
 269 */
 270 #if __FreeBSD_version < 500005
 271         static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
 272 #else
 273         #if __FreeBSD_version < 503000
 274         static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
 275         #else
 276         static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
 277         #endif
 278 #endif
 279 {
 280         #if __FreeBSD_version < 503000
 281                 struct AdapterControlBlock *acb = dev->si_drv1;
 282         #else
 283                 int     unit = dev2unit(dev);
 284                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 285         #endif
 286         if(acb == NULL) {
 287                 return ENXIO;
 288         }
 289         return (0);
 290 }
 291 /*
 292 **************************************************************************
 293 **************************************************************************
 294 */
 295 #if __FreeBSD_version < 500005
 296         static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
 297 #else
 298         #if __FreeBSD_version < 503000
 299         static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
 300         #else
 301         static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
 302         #endif
 303 #endif
 304 {
 305         #if __FreeBSD_version < 503000
 306                 struct AdapterControlBlock *acb = dev->si_drv1;
 307         #else
 308                 int     unit = dev2unit(dev);
 309                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 310         #endif
 311         if(acb == NULL) {
 312                 return ENXIO;
 313         }
 314         return 0;
 315 }
 316 /*
 317 **************************************************************************
 318 **************************************************************************
 319 */
 320 #if __FreeBSD_version < 500005
 321         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
 322 #else
 323         #if __FreeBSD_version < 503000
 324         static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 325         #else
 326         static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
 327         #endif
 328 #endif
 329 {
 330         #if __FreeBSD_version < 503000
 331                 struct AdapterControlBlock *acb = dev->si_drv1;
 332         #else
 333                 int     unit = dev2unit(dev);
 334                 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
 335         #endif
 336
 337         if(acb == NULL) {
 338                 return ENXIO;
 339         }
 340         return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
 341 }
 342 /*
 343 **********************************************************************
 344 **********************************************************************
 345 */
 346 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
 347 {
 348         u_int32_t intmask_org = 0;
 349
 350         switch (acb->adapter_type) {
 351         case ACB_ADAPTER_TYPE_A: {
 352                         /* disable all outbound interrupt */
 353                         intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
 354                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
 355                 }
 356                 break;
 357         case ACB_ADAPTER_TYPE_B: {
 358                         /* disable all outbound interrupt */
 359                         intmask_org = CHIP_REG_READ32(HBB_DOORBELL,
 360                                                 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
 361                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
 362                 }
 363                 break;
 364         case ACB_ADAPTER_TYPE_C: {
 365                         /* disable all outbound interrupt */
 366                         intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)        ; /* disable outbound message0 int */
 367                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
 368                 }
 369                 break;
 370         case ACB_ADAPTER_TYPE_D: {
 371                         /* disable all outbound interrupt */
 372                         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
 373                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
 374                 }
 375                 break;
 376         }
 377         return (intmask_org);
 378 }
 379 /*
 380 **********************************************************************
 381 **********************************************************************
 382 */
 383 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
 384 {
 385         u_int32_t mask;
 386
 387         switch (acb->adapter_type) {
 388         case ACB_ADAPTER_TYPE_A: {
 389                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 390                         mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
 391                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
 392                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
 393                 }
 394                 break;
 395         case ACB_ADAPTER_TYPE_B: {
 396                         /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
 397                         mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
 398                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
 399                         acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
 400                 }
 401                 break;
 402         case ACB_ADAPTER_TYPE_C: {
 403                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 404                         mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
 405                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
 406                         acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
 407                 }
 408                 break;
 409         case ACB_ADAPTER_TYPE_D: {
 410                         /* enable outbound Post Queue, outbound doorbell Interrupt */
 411                         mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
 412                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
 413                         CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
 414                         acb->outbound_int_enable = mask;
 415                 }
 416                 break;
 417         }
 418 }
 419 /*
 420 **********************************************************************
 421 **********************************************************************
 422 */
 423 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
 424 {
 425         u_int32_t Index;
 426         u_int8_t Retries = 0x00;
 427
 428         do {
 429                 for(Index=0; Index < 100; Index++) {
 430                         if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
 431                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
 432                                 return TRUE;
 433                         }
 434                         UDELAY(10000);
 435                 }/*max 1 seconds*/
 436         }while(Retries++ < 20);/*max 20 sec*/
 437         return (FALSE);
 438 }
 439 /*
 440 **********************************************************************
 441 **********************************************************************
 442 */
 443 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
 444 {
 445         u_int32_t Index;
 446         u_int8_t Retries = 0x00;
 447
 448         do {
 449                 for(Index=0; Index < 100; Index++) {
 450                         if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
 451                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
 452                                 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
 453                                 return TRUE;
 454                         }
 455                         UDELAY(10000);
 456                 }/*max 1 seconds*/
 457         }while(Retries++ < 20);/*max 20 sec*/
 458         return (FALSE);
 459 }
 460 /*
 461 **********************************************************************
 462 **********************************************************************
 463 */
 464 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
 465 {
 466         u_int32_t Index;
 467         u_int8_t Retries = 0x00;
 468
 469         do {
 470                 for(Index=0; Index < 100; Index++) {
 471                         if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
 472                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
 473                                 return TRUE;
 474                         }
 475                         UDELAY(10000);
 476                 }/*max 1 seconds*/
 477         }while(Retries++ < 20);/*max 20 sec*/
 478         return (FALSE);
 479 }
 480 /*
 481 **********************************************************************
 482 **********************************************************************
 483 */
 484 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
 485 {
 486         u_int32_t Index;
 487         u_int8_t Retries = 0x00;
 488
 489         do {
 490                 for(Index=0; Index < 100; Index++) {
 491                         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
 492                                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
 493                                 return TRUE;
 494                         }
 495                         UDELAY(10000);
 496                 }/*max 1 seconds*/
 497         }while(Retries++ < 20);/*max 20 sec*/
 498         return (FALSE);
 499 }
 500 /*
 501 ************************************************************************
 502 ************************************************************************
 503 */
 504 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
 505 {
 506         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 507
 508         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 509         do {
 510                 if(arcmsr_hba_wait_msgint_ready(acb)) {
 511                         break;
 512                 } else {
 513                         retry_count--;
 514                 }
 515         }while(retry_count != 0);
 516 }
 517 /*
 518 ************************************************************************
 519 ************************************************************************
 520 */
 521 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
 522 {
 523         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 524
 525         CHIP_REG_WRITE32(HBB_DOORBELL,
 526         0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
 527         do {
 528                 if(arcmsr_hbb_wait_msgint_ready(acb)) {
 529                         break;
 530                 } else {
 531                         retry_count--;
 532                 }
 533         }while(retry_count != 0);
 534 }
 535 /*
 536 ************************************************************************
 537 ************************************************************************
 538 */
 539 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
 540 {
 541         int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
 542
 543         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 544         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 545         do {
 546                 if(arcmsr_hbc_wait_msgint_ready(acb)) {
 547                         break;
 548                 } else {
 549                         retry_count--;
 550                 }
 551         }while(retry_count != 0);
 552 }
 553 /*
 554 ************************************************************************
 555 ************************************************************************
 556 */
 557 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
 558 {
 559         int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
 560
 561         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
 562         do {
 563                 if(arcmsr_hbd_wait_msgint_ready(acb)) {
 564                         break;
 565                 } else {
 566                         retry_count--;
 567                 }
 568         }while(retry_count != 0);
 569 }
 570 /*
 571 ************************************************************************
 572 ************************************************************************
 573 */
 574 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
 575 {
 576         switch (acb->adapter_type) {
 577         case ACB_ADAPTER_TYPE_A: {
 578                         arcmsr_flush_hba_cache(acb);
 579                 }
 580                 break;
 581         case ACB_ADAPTER_TYPE_B: {
 582                         arcmsr_flush_hbb_cache(acb);
 583                 }
 584                 break;
 585         case ACB_ADAPTER_TYPE_C: {
 586                         arcmsr_flush_hbc_cache(acb);
 587                 }
 588                 break;
 589         case ACB_ADAPTER_TYPE_D: {
 590                         arcmsr_flush_hbd_cache(acb);
 591                 }
 592                 break;
 593         }
 594 }
 595 /*
 596 *******************************************************************************
 597 *******************************************************************************
 598 */
 599 static int arcmsr_suspend(device_t dev)
 600 {
 601         struct AdapterControlBlock      *acb = device_get_softc(dev);
 602
 603         /* flush controller */
 604         arcmsr_iop_parking(acb);
 605         /* disable all outbound interrupt */
 606         arcmsr_disable_allintr(acb);
 607         return(0);
 608 }
 609 /*
 610 *******************************************************************************
 611 *******************************************************************************
 612 */
 613 static int arcmsr_resume(device_t dev)
 614 {
 615         struct AdapterControlBlock      *acb = device_get_softc(dev);
 616
 617         arcmsr_iop_init(acb);
 618         return(0);
 619 }
 620 /*
 621 *********************************************************************************
 622 *********************************************************************************
 623 */
 624 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
 625 {
 626         struct AdapterControlBlock *acb;
 627         u_int8_t target_id, target_lun;
 628         struct cam_sim *sim;
 629
 630         sim = (struct cam_sim *) cb_arg;
 631         acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
 632         switch (code) {
 633         case AC_LOST_DEVICE:
 634                 target_id = xpt_path_target_id(path);
 635                 target_lun = xpt_path_lun_id(path);
 636                 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
 637                         break;
 638                 }
 639         //      printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
 640                 break;
 641         default:
 642                 break;
 643         }
 644 }
 645 /*
 646 **********************************************************************
 647 **********************************************************************
 648 */
 649 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
 650 {
 651         union ccb *pccb = srb->pccb;
 652
 653         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
 654         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
 655         if(pccb->csio.sense_len) {
 656                 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
 657                 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
 658                 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
 659                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
 660                 pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
 661         }
 662 }
 663 /*
 664 *********************************************************************
 665 *********************************************************************
 666 */
 667 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
 668 {
 669         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 670         if(!arcmsr_hba_wait_msgint_ready(acb)) {
 671                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 672         }
 673 }
 674 /*
 675 *********************************************************************
 676 *********************************************************************
 677 */
 678 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
 679 {
 680         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
 681         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
 682                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 683         }
 684 }
 685 /*
 686 *********************************************************************
 687 *********************************************************************
 688 */
 689 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
 690 {
 691         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 692         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
 693         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
 694                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 695         }
 696 }
 697 /*
 698 *********************************************************************
 699 *********************************************************************
 700 */
 701 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
 702 {
 703         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
 704         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
 705                 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
 706         }
 707 }
 708 /*
 709 *********************************************************************
 710 *********************************************************************
 711 */
 712 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
 713 {
 714         switch (acb->adapter_type) {
 715         case ACB_ADAPTER_TYPE_A: {
 716                         arcmsr_abort_hba_allcmd(acb);
 717                 }
 718                 break;
 719         case ACB_ADAPTER_TYPE_B: {
 720                         arcmsr_abort_hbb_allcmd(acb);
 721                 }
 722                 break;
 723         case ACB_ADAPTER_TYPE_C: {
 724                         arcmsr_abort_hbc_allcmd(acb);
 725                 }
 726                 break;
 727         case ACB_ADAPTER_TYPE_D: {
 728                         arcmsr_abort_hbd_allcmd(acb);
 729                 }
 730                 break;
 731         }
 732 }
 733 /*
 734 **********************************************************************
 735 **********************************************************************
 736 */
 737 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
 738 {
 739         struct AdapterControlBlock *acb = srb->acb;
 740         union ccb *pccb = srb->pccb;
 741
 742         if(srb->srb_flags & SRB_FLAG_TIMER_START)
 743                 callout_stop(&srb->ccb_callout);
 744         if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 745                 bus_dmasync_op_t op;
 746
 747                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
 748                         op = BUS_DMASYNC_POSTREAD;
 749                 } else {
 750                         op = BUS_DMASYNC_POSTWRITE;
 751                 }
 752                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
 753                 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
 754         }
 755         if(stand_flag == 1) {
 756                 atomic_subtract_int(&acb->srboutstandingcount, 1);
 757                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
 758                 acb->srboutstandingcount < (acb->maxOutstanding -10))) {
 759                         acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
 760                         pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 761                 }
 762         }
 763         if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
 764                 arcmsr_free_srb(srb);
 765         acb->pktReturnCount++;
 766         xpt_done(pccb);
 767 }
 768 /*
 769 **************************************************************************
 770 **************************************************************************
 771 */
 772 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
 773 {
 774         int target, lun;
 775
 776         target = srb->pccb->ccb_h.target_id;
 777         lun = srb->pccb->ccb_h.target_lun;
 778         if(error == FALSE) {
 779                 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
 780                         acb->devstate[target][lun] = ARECA_RAID_GOOD;
 781                 }
 782                 srb->pccb->ccb_h.status |= CAM_REQ_CMP;
 783                 arcmsr_srb_complete(srb, 1);
 784         } else {
 785                 switch(srb->arcmsr_cdb.DeviceStatus) {
 786                 case ARCMSR_DEV_SELECT_TIMEOUT: {
 787                                 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
 788                                         printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
 789                                 }
 790                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 791                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 792                                 arcmsr_srb_complete(srb, 1);
 793                         }
 794                         break;
 795                 case ARCMSR_DEV_ABORTED:
 796                 case ARCMSR_DEV_INIT_FAIL: {
 797                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
 798                                 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
 799                                 arcmsr_srb_complete(srb, 1);
 800                         }
 801                         break;
 802                 case SCSISTAT_CHECK_CONDITION: {
 803                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
 804                                 arcmsr_report_sense_info(srb);
 805                                 arcmsr_srb_complete(srb, 1);
 806                         }
 807                         break;
 808                 default:
 809                         printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
 810                                         , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
 811                         acb->devstate[target][lun] = ARECA_RAID_GONE;
 812                         srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
 813                         /*unknown error or crc error just for retry*/
 814                         arcmsr_srb_complete(srb, 1);
 815                         break;
 816                 }
 817         }
 818 }
 819 /*
 820 **************************************************************************
 821 **************************************************************************
 822 */
 823 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
 824 {
 825         struct CommandControlBlock *srb;
 826
 827         /* check if command done with no error*/
 828         switch (acb->adapter_type) {
 829         case ACB_ADAPTER_TYPE_C:
 830         case ACB_ADAPTER_TYPE_D:
 831                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
 832                 break;
 833         case ACB_ADAPTER_TYPE_A:
 834         case ACB_ADAPTER_TYPE_B:
 835         default:
 836                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
 837                 break;
 838         }
 839         if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
 840                 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
 841                         arcmsr_free_srb(srb);
 842                         printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
 843                         return;
 844                 }
 845                 printf("arcmsr%d: return srb has been completed\n"
 846                         "srb='%p' srb_state=0x%x outstanding srb count=%d \n",
 847                         acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
 848                 return;
 849         }
 850         arcmsr_report_srb_state(acb, srb, error);
 851 }
 852 /*
 853 **************************************************************************
 854 **************************************************************************
 855 */
 856 static void     arcmsr_srb_timeout(void *arg)
 857 {
 858         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
 859         struct AdapterControlBlock *acb;
 860         int target, lun;
 861         u_int8_t cmd;
 862
 863         target = srb->pccb->ccb_h.target_id;
 864         lun = srb->pccb->ccb_h.target_lun;
 865         acb = srb->acb;
 866         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
 867         if(srb->srb_state == ARCMSR_SRB_START)
 868         {
 869                 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
 870                 srb->srb_state = ARCMSR_SRB_TIMEOUT;
 871                 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
 872                 arcmsr_srb_complete(srb, 1);
 873                 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
 874                                  acb->pci_unit, target, lun, cmd, srb);
 875         }
 876         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
 877 #ifdef ARCMSR_DEBUG1
 878         arcmsr_dump_data(acb);
 879 #endif
 880 }
 881
 882 /*
 883 **********************************************************************
 884 **********************************************************************
 885 */
 886 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
 887 {
 888         int i=0;
 889         u_int32_t flag_srb;
 890         u_int16_t error;
 891
 892         switch (acb->adapter_type) {
 893         case ACB_ADAPTER_TYPE_A: {
 894                         u_int32_t outbound_intstatus;
 895
 896                         /*clear and abort all outbound posted Q*/
 897                         outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
 898                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
 899                         while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 900                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 901                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 902                         }
 903                 }
 904                 break;
 905         case ACB_ADAPTER_TYPE_B: {
 906                         struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
 907
 908                         /*clear all outbound posted Q*/
 909                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
 910                         for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
 911                                 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
 912                                         phbbmu->done_qbuffer[i] = 0;
 913                         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
 914                                         arcmsr_drain_donequeue(acb, flag_srb, error);
 915                                 }
 916                                 phbbmu->post_qbuffer[i] = 0;
 917                         }/*drain reply FIFO*/
 918                         phbbmu->doneq_index = 0;
 919                         phbbmu->postq_index = 0;
 920                 }
 921                 break;
 922         case ACB_ADAPTER_TYPE_C: {
 923
 924                         while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
 925                                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
 926                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
 927                                 arcmsr_drain_donequeue(acb, flag_srb, error);
 928                         }
 929                 }
 930                 break;
 931         case ACB_ADAPTER_TYPE_D: {
 932                         arcmsr_hbd_postqueue_isr(acb);
 933                 }
 934                 break;
 935         }
 936 }
 937 /*
 938 ****************************************************************************
 939 ****************************************************************************
 940 */
 941 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
 942 {
 943         struct CommandControlBlock *srb;
 944         u_int32_t intmask_org;
 945         u_int32_t i=0;
 946
 947         if(acb->srboutstandingcount>0) {
 948                 /* disable all outbound interrupt */
 949                 intmask_org = arcmsr_disable_allintr(acb);
 950                 /*clear and abort all outbound posted Q*/
 951                 arcmsr_done4abort_postqueue(acb);
 952                 /* talk to iop 331 outstanding command aborted*/
 953                 arcmsr_abort_allcmd(acb);
 954                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
 955                         srb = acb->psrb_pool[i];
 956                         if(srb->srb_state == ARCMSR_SRB_START) {
 957                                 srb->srb_state = ARCMSR_SRB_ABORTED;
 958                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
 959                                 arcmsr_srb_complete(srb, 1);
 960                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
 961                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id
 962                                                 , srb->pccb->ccb_h.target_lun, srb);
 963                         }
 964                 }
 965                 /* enable all outbound interrupt */
 966                 arcmsr_enable_allintr(acb, intmask_org);
 967         }
 968         acb->srboutstandingcount = 0;
 969         acb->workingsrb_doneindex = 0;
 970         acb->workingsrb_startindex = 0;
 971         acb->pktRequestCount = 0;
 972         acb->pktReturnCount = 0;
 973 }
 974 /*
 975 **********************************************************************
 976 **********************************************************************
 977 */
 978 static void arcmsr_build_srb(struct CommandControlBlock *srb,
 979                 bus_dma_segment_t *dm_segs, u_int32_t nseg)
 980 {
 981         struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
 982         u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
 983         u_int32_t address_lo, address_hi;
 984         union ccb *pccb = srb->pccb;
 985         struct ccb_scsiio *pcsio = &pccb->csio;
 986         u_int32_t arccdbsize = 0x30;
 987
 988         memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
 989         arcmsr_cdb->Bus = 0;
 990         arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
 991         arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
 992         arcmsr_cdb->Function = 1;
 993         arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
 994         bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
 995         if(nseg != 0) {
 996                 struct AdapterControlBlock *acb = srb->acb;
 997                 bus_dmasync_op_t op;
 998                 u_int32_t length, i, cdb_sgcount = 0;
 999
1000                 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
1001                         op = BUS_DMASYNC_PREREAD;
1002                 } else {
1003                         op = BUS_DMASYNC_PREWRITE;
1004                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1005                         srb->srb_flags |= SRB_FLAG_WRITE;
1006                 }
1007                 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1008                 for(i=0; i < nseg; i++) {
1009                         /* Get the physical address of the current data pointer */
1010                         length = arcmsr_htole32(dm_segs[i].ds_len);
1011                         address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1012                         address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1013                         if(address_hi == 0) {
1014                                 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1015                                 pdma_sg->address = address_lo;
1016                                 pdma_sg->length = length;
1017                                 psge += sizeof(struct SG32ENTRY);
1018                                 arccdbsize += sizeof(struct SG32ENTRY);
1019                         } else {
1020                                 u_int32_t sg64s_size = 0, tmplength = length;
1021
1022                                 while(1) {
1023                                         u_int64_t span4G, length0;
1024                                         struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1025
1026                                         span4G = (u_int64_t)address_lo + tmplength;
1027                                         pdma_sg->addresshigh = address_hi;
1028                                         pdma_sg->address = address_lo;
1029                                         if(span4G > 0x100000000) {
1030                                                 /*see if cross 4G boundary*/
1031                                                 length0 = 0x100000000-address_lo;
1032                                                 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1033                                                 address_hi = address_hi+1;
1034                                                 address_lo = 0;
1035                                                 tmplength = tmplength - (u_int32_t)length0;
1036                                                 sg64s_size += sizeof(struct SG64ENTRY);
1037                                                 psge += sizeof(struct SG64ENTRY);
1038                                                 cdb_sgcount++;
1039                                         } else {
1040                                                 pdma_sg->length = tmplength | IS_SG64_ADDR;
1041                                                 sg64s_size += sizeof(struct SG64ENTRY);
1042                                                 psge += sizeof(struct SG64ENTRY);
1043                                                 break;
1044                                         }
1045                                 }
1046                                 arccdbsize += sg64s_size;
1047                         }
1048                         cdb_sgcount++;
1049                 }
1050                 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1051                 arcmsr_cdb->DataLength = pcsio->dxfer_len;
1052                 if( arccdbsize > 256) {
1053                         arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1054                 }
1055         } else {
1056                 arcmsr_cdb->DataLength = 0;
1057         }
1058     srb->arc_cdb_size = arccdbsize;
1059     arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1060 }
1061 /*
1062 **************************************************************************
1063 **************************************************************************
1064 */
1065 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1066 {
1067         u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1068         struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1069
1070         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1071         atomic_add_int(&acb->srboutstandingcount, 1);
1072         srb->srb_state = ARCMSR_SRB_START;
1073
1074         switch (acb->adapter_type) {
1075         case ACB_ADAPTER_TYPE_A: {
1076                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1077                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1078                         } else {
1079                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1080                         }
1081                 }
1082                 break;
1083         case ACB_ADAPTER_TYPE_B: {
1084                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1085                         int ending_index, index;
1086
1087                         index = phbbmu->postq_index;
1088                         ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1089                         phbbmu->post_qbuffer[ending_index] = 0;
1090                         if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1091                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1092                         } else {
1093                                 phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1094                         }
1095                         index++;
1096                         index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1097                         phbbmu->postq_index = index;
1098                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1099                 }
1100                 break;
1101     case ACB_ADAPTER_TYPE_C: {
1102             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1103
1104             arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1105             ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1106                         cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1107             if(cdb_phyaddr_hi32)
1108             {
1109                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1110                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1111             }
1112             else
1113             {
1114                             CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1115             }
1116         }
1117         break;
1118         case ACB_ADAPTER_TYPE_D: {
1119                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1120                         u_int16_t index_stripped;
1121                         u_int16_t postq_index;
1122                         struct InBound_SRB *pinbound_srb;
1123
1124                         ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1125                         postq_index = phbdmu->postq_index;
1126                         pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1127                         pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1128                         pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1129                         pinbound_srb->length = srb->arc_cdb_size >> 2;
1130                         arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1131                         if (postq_index & 0x4000) {
1132                                 index_stripped = postq_index & 0xFF;
1133                                 index_stripped += 1;
1134                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1135                                 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1136                         } else {
1137                                 index_stripped = postq_index;
1138                                 index_stripped += 1;
1139                                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1140                                 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1141                         }
1142                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1143                         ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1144                 }
1145                 break;
1146         }
1147 }
1148 /*
1149 ************************************************************************
1150 ************************************************************************
1151 */
1152 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1153 {
1154         struct QBUFFER *qbuffer=NULL;
1155
1156         switch (acb->adapter_type) {
1157         case ACB_ADAPTER_TYPE_A: {
1158                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1159
1160                         qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1161                 }
1162                 break;
1163         case ACB_ADAPTER_TYPE_B: {
1164                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1165
1166                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1167                 }
1168                 break;
1169         case ACB_ADAPTER_TYPE_C: {
1170                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1171
1172                         qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1173                 }
1174                 break;
1175         case ACB_ADAPTER_TYPE_D: {
1176                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1177
1178                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1179                 }
1180                 break;
1181         }
1182         return(qbuffer);
1183 }
1184 /*
1185 ************************************************************************
1186 ************************************************************************
1187 */
1188 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1189 {
1190         struct QBUFFER *qbuffer = NULL;
1191
1192         switch (acb->adapter_type) {
1193         case ACB_ADAPTER_TYPE_A: {
1194                         struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1195
1196                         qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1197                 }
1198                 break;
1199         case ACB_ADAPTER_TYPE_B: {
1200                         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1201
1202                         qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1203                 }
1204                 break;
1205         case ACB_ADAPTER_TYPE_C: {
1206                         struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1207
1208                         qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1209                 }
1210                 break;
1211         case ACB_ADAPTER_TYPE_D: {
1212                         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1213
1214                         qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1215                 }
1216                 break;
1217         }
1218         return(qbuffer);
1219 }
1220 /*
1221 **************************************************************************
1222 **************************************************************************
1223 */
1224 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1225 {
1226         switch (acb->adapter_type) {
1227         case ACB_ADAPTER_TYPE_A: {
1228                         /* let IOP know data has been read */
1229                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1230                 }
1231                 break;
1232         case ACB_ADAPTER_TYPE_B: {
1233                         /* let IOP know data has been read */
1234                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1235                 }
1236                 break;
1237         case ACB_ADAPTER_TYPE_C: {
1238                         /* let IOP know data has been read */
1239                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1240                 }
1241                 break;
1242         case ACB_ADAPTER_TYPE_D: {
1243                         /* let IOP know data has been read */
1244                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1245                 }
1246                 break;
1247         }
1248 }
1249 /*
1250 **************************************************************************
1251 **************************************************************************
1252 */
1253 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1254 {
1255         switch (acb->adapter_type) {
1256         case ACB_ADAPTER_TYPE_A: {
1257                         /*
1258                         ** push inbound doorbell tell iop, driver data write ok
1259                         ** and wait reply on next hwinterrupt for next Qbuffer post
1260                         */
1261                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1262                 }
1263                 break;
1264         case ACB_ADAPTER_TYPE_B: {
1265                         /*
1266                         ** push inbound doorbell tell iop, driver data write ok
1267                         ** and wait reply on next hwinterrupt for next Qbuffer post
1268                         */
1269                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1270                 }
1271                 break;
1272         case ACB_ADAPTER_TYPE_C: {
1273                         /*
1274                         ** push inbound doorbell tell iop, driver data write ok
1275                         ** and wait reply on next hwinterrupt for next Qbuffer post
1276                         */
1277                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1278                 }
1279                 break;
1280         case ACB_ADAPTER_TYPE_D: {
1281                         /*
1282                         ** push inbound doorbell tell iop, driver data write ok
1283                         ** and wait reply on next hwinterrupt for next Qbuffer post
1284                         */
1285                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1286                 }
1287                 break;
1288         }
1289 }
1290 /*
1291 ************************************************************************
1292 ************************************************************************
1293 */
1294 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1295 {
1296         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1297         CHIP_REG_WRITE32(HBA_MessageUnit,
1298         0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1299         if(!arcmsr_hba_wait_msgint_ready(acb)) {
1300                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1301                         , acb->pci_unit);
1302         }
1303 }
1304 /*
1305 ************************************************************************
1306 ************************************************************************
1307 */
1308 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1309 {
1310         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1311         CHIP_REG_WRITE32(HBB_DOORBELL,
1312         0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1313         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1314                 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1315                         , acb->pci_unit);
1316         }
1317 }
1318 /*
1319 ************************************************************************
1320 ************************************************************************
1321 */
1322 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1323 {
1324         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1325         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1326         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1327         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1328                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1329         }
1330 }
1331 /*
1332 ************************************************************************
1333 ************************************************************************
1334 */
1335 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1336 {
1337         acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1338         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1339         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1340                 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1341         }
1342 }
1343 /*
1344 ************************************************************************
1345 ************************************************************************
1346 */
1347 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1348 {
1349         switch (acb->adapter_type) {
1350         case ACB_ADAPTER_TYPE_A: {
1351                         arcmsr_stop_hba_bgrb(acb);
1352                 }
1353                 break;
1354         case ACB_ADAPTER_TYPE_B: {
1355                         arcmsr_stop_hbb_bgrb(acb);
1356                 }
1357                 break;
1358         case ACB_ADAPTER_TYPE_C: {
1359                         arcmsr_stop_hbc_bgrb(acb);
1360                 }
1361                 break;
1362         case ACB_ADAPTER_TYPE_D: {
1363                         arcmsr_stop_hbd_bgrb(acb);
1364                 }
1365                 break;
1366         }
1367 }
1368 /*
1369 ************************************************************************
1370 ************************************************************************
1371 */
1372 static void arcmsr_poll(struct cam_sim *psim)
1373 {
1374         struct AdapterControlBlock *acb;
1375         int     mutex;
1376
1377         acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1378         mutex = mtx_owned(&acb->isr_lock);
1379         if( mutex == 0 )
1380                 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1381         arcmsr_interrupt(acb);
1382         if( mutex == 0 )
1383                 ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1384 }
1385 /*
1386 **************************************************************************
1387 **************************************************************************
1388 */
1389 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1390     struct QBUFFER *prbuffer) {
1391
1392         u_int8_t *pQbuffer;
1393         u_int8_t *buf1 = 0;
1394         u_int32_t *iop_data, *buf2 = 0;
1395         u_int32_t iop_len, data_len;
1396
1397         iop_data = (u_int32_t *)prbuffer->data;
1398         iop_len = (u_int32_t)prbuffer->data_len;
1399         if ( iop_len > 0 )
1400         {
1401                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1402                 buf2 = (u_int32_t *)buf1;
1403                 if( buf1 == NULL)
1404                         return (0);
1405                 data_len = iop_len;
1406                 while(data_len >= 4)
1407                 {
1408                         *buf2++ = *iop_data++;
1409                         data_len -= 4;
1410                 }
1411                 if(data_len)
1412                         *buf2 = *iop_data;
1413                 buf2 = (u_int32_t *)buf1;
1414         }
1415         while (iop_len > 0) {
1416                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1417                 *pQbuffer = *buf1;
1418                 acb->rqbuf_lastindex++;
1419                 /* if last, index number set it to 0 */
1420                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1421                 buf1++;
1422                 iop_len--;
1423         }
1424         if(buf2)
1425                 free( (u_int8_t *)buf2, M_DEVBUF);
1426         /* let IOP know data has been read */
1427         arcmsr_iop_message_read(acb);
1428         return (1);
1429 }
1430 /*
1431 **************************************************************************
1432 **************************************************************************
1433 */
1434 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1435     struct QBUFFER *prbuffer) {
1436
1437         u_int8_t *pQbuffer;
1438         u_int8_t *iop_data;
1439         u_int32_t iop_len;
1440
1441         if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1442                 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1443         }
1444         iop_data = (u_int8_t *)prbuffer->data;
1445         iop_len = (u_int32_t)prbuffer->data_len;
1446         while (iop_len > 0) {
1447                 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1448                 *pQbuffer = *iop_data;
1449                 acb->rqbuf_lastindex++;
1450                 /* if last, index number set it to 0 */
1451                 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1452                 iop_data++;
1453                 iop_len--;
1454         }
1455         /* let IOP know data has been read */
1456         arcmsr_iop_message_read(acb);
1457         return (1);
1458 }
1459 /*
1460 **************************************************************************
1461 **************************************************************************
1462 */
1463 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1464 {
1465         struct QBUFFER *prbuffer;
1466         int my_empty_len;
1467
1468         /*check this iop data if overflow my rqbuffer*/
1469         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1470         prbuffer = arcmsr_get_iop_rqbuffer(acb);
1471         my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1472             (ARCMSR_MAX_QBUFFER-1);
1473         if(my_empty_len >= prbuffer->data_len) {
1474                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1475                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1476         } else {
1477                 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1478         }
1479         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1480 }
1481 /*
1482 **********************************************************************
1483 **********************************************************************
1484 */
1485 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1486 {
1487         u_int8_t *pQbuffer;
1488         struct QBUFFER *pwbuffer;
1489         u_int8_t *buf1 = 0;
1490         u_int32_t *iop_data, *buf2 = 0;
1491         u_int32_t allxfer_len = 0, data_len;
1492
1493         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1494                 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1495                 buf2 = (u_int32_t *)buf1;
1496                 if( buf1 == NULL)
1497                         return;
1498
1499                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1500                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1501                 iop_data = (u_int32_t *)pwbuffer->data;
1502                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1503                         && (allxfer_len < 124)) {
1504                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1505                         *buf1 = *pQbuffer;
1506                         acb->wqbuf_firstindex++;
1507                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1508                         buf1++;
1509                         allxfer_len++;
1510                 }
1511                 pwbuffer->data_len = allxfer_len;
1512                 data_len = allxfer_len;
1513                 buf1 = (u_int8_t *)buf2;
1514                 while(data_len >= 4)
1515                 {
1516                         *iop_data++ = *buf2++;
1517                         data_len -= 4;
1518                 }
1519                 if(data_len)
1520                         *iop_data = *buf2;
1521                 free( buf1, M_DEVBUF);
1522                 arcmsr_iop_message_wrote(acb);
1523         }
1524 }
1525 /*
1526 **********************************************************************
1527 **********************************************************************
1528 */
1529 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1530 {
1531         u_int8_t *pQbuffer;
1532         struct QBUFFER *pwbuffer;
1533         u_int8_t *iop_data;
1534         int32_t allxfer_len=0;
1535
1536         if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1537                 arcmsr_Write_data_2iop_wqbuffer_D(acb);
1538                 return;
1539         }
1540         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1541                 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1542                 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1543                 iop_data = (u_int8_t *)pwbuffer->data;
1544                 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1545                         && (allxfer_len < 124)) {
1546                         pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1547                         *iop_data = *pQbuffer;
1548                         acb->wqbuf_firstindex++;
1549                         acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1550                         iop_data++;
1551                         allxfer_len++;
1552                 }
1553                 pwbuffer->data_len = allxfer_len;
1554                 arcmsr_iop_message_wrote(acb);
1555         }
1556 }
1557 /*
1558 **************************************************************************
1559 **************************************************************************
1560 */
1561 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1562 {
1563         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1564         acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1565         /*
1566         *****************************************************************
1567         **   check if there are any mail packages from user space program
1568         **   in my post bag, now is the time to send them into Areca's firmware
1569         *****************************************************************
1570         */
1571         if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1572                 arcmsr_Write_data_2iop_wqbuffer(acb);
1573         }
1574         if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1575                 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1576         }
1577         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1578 }
1579 /*
1580 **************************************************************************
1581 **************************************************************************
1582 */
1583 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1584 {
1585 /*
1586         if (ccb->ccb_h.status != CAM_REQ_CMP)
1587                 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1588                     "failure status=%x\n", ccb->ccb_h.target_id,
1589                     ccb->ccb_h.target_lun, ccb->ccb_h.status);
1590         else
1591                 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1592 */
1593         xpt_free_path(ccb->ccb_h.path);
1594         xpt_free_ccb(ccb);
1595 }
1596
1597 static void     arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1598 {
1599         struct cam_path     *path;
1600         union ccb           *ccb;
1601
1602         if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1603                 return;
1604         if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1605         {
1606                 xpt_free_ccb(ccb);
1607                 return;
1608         }
1609 /*      printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1610         bzero(ccb, sizeof(union ccb));
1611         xpt_setup_ccb(&ccb->ccb_h, path, 5);
1612         ccb->ccb_h.func_code = XPT_SCAN_LUN;
1613         ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1614         ccb->crcn.flags = CAM_FLAG_NONE;
1615         xpt_action(ccb);
1616 }
1617
1618
1619 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1620 {
1621         struct CommandControlBlock *srb;
1622         u_int32_t intmask_org;
1623         int i;
1624
1625         /* disable all outbound interrupts */
1626         intmask_org = arcmsr_disable_allintr(acb);
1627         for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1628         {
1629                 srb = acb->psrb_pool[i];
1630                 if (srb->srb_state == ARCMSR_SRB_START)
1631                 {
1632                 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1633             {
1634                         srb->srb_state = ARCMSR_SRB_ABORTED;
1635                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1636                         arcmsr_srb_complete(srb, 1);
1637                                 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1638                 }
1639                 }
1640         }
1641         /* enable outbound Post Queue, outbound doorbell Interrupt */
1642         arcmsr_enable_allintr(acb, intmask_org);
1643 }
1644 /*
1645 **************************************************************************
1646 **************************************************************************
1647 */
1648 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1649         u_int32_t       devicemap;
1650         u_int32_t       target, lun;
1651     u_int32_t   deviceMapCurrent[4]={0};
1652     u_int8_t    *pDevMap;
1653
1654         switch (acb->adapter_type) {
1655         case ACB_ADAPTER_TYPE_A:
1656                         devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1657                         for (target = 0; target < 4; target++)
1658                         {
1659                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1660                 devicemap += 4;
1661                         }
1662                         break;
1663
1664         case ACB_ADAPTER_TYPE_B:
1665                         devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1666                         for (target = 0; target < 4; target++)
1667                         {
1668                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1669                 devicemap += 4;
1670                         }
1671                         break;
1672
1673         case ACB_ADAPTER_TYPE_C:
1674                         devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1675                         for (target = 0; target < 4; target++)
1676                         {
1677                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1678                 devicemap += 4;
1679                         }
1680                         break;
1681         case ACB_ADAPTER_TYPE_D:
1682                         devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1683                         for (target = 0; target < 4; target++)
1684                         {
1685                 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1686                 devicemap += 4;
1687                         }
1688                         break;
1689         }
1690
1691                 if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1692                 {
1693                         acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1694                 }
1695                 /*
1696                 ** adapter posted CONFIG message
1697                 ** copy the new map, note if there are differences with the current map
1698                 */
1699                 pDevMap = (u_int8_t     *)&deviceMapCurrent[0];
1700                 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1701                 {
1702                         if (*pDevMap != acb->device_map[target])
1703                         {
1704                 u_int8_t difference, bit_check;
1705
1706                 difference = *pDevMap ^ acb->device_map[target];
1707                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1708                 {
1709                     bit_check = (1 << lun);                                             /*check bit from 0....31*/
1710                     if(difference & bit_check)
1711                     {
1712                         if(acb->device_map[target] & bit_check)
1713                         {/* unit departed */
1714                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1715                                                         arcmsr_abort_dr_ccbs(acb, target, lun);
1716                                 arcmsr_rescan_lun(acb, target, lun);
1717                                                 acb->devstate[target][lun] = ARECA_RAID_GONE;
1718                         }
1719                         else
1720                         {/* unit arrived */
1721                                                         printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1722                                 arcmsr_rescan_lun(acb, target, lun);
1723                                                 acb->devstate[target][lun] = ARECA_RAID_GOOD;
1724                         }
1725                     }
1726                 }
1727 /*                              printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1728                                 acb->device_map[target] = *pDevMap;
1729                         }
1730                         pDevMap++;
1731                 }
1732 }
1733 /*
1734 **************************************************************************
1735 **************************************************************************
1736 */
1737 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1738         u_int32_t outbound_message;
1739
1740         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1741         outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1742         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1743                 arcmsr_dr_handle( acb );
1744 }
1745 /*
1746 **************************************************************************
1747 **************************************************************************
1748 */
1749 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1750         u_int32_t outbound_message;
1751
1752         /* clear interrupts */
1753         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1754         outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1755         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1756                 arcmsr_dr_handle( acb );
1757 }
1758 /*
1759 **************************************************************************
1760 **************************************************************************
1761 */
1762 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1763         u_int32_t outbound_message;
1764
1765         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1766         outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1767         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1768                 arcmsr_dr_handle( acb );
1769 }
1770 /*
1771 **************************************************************************
1772 **************************************************************************
1773 */
1774 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1775         u_int32_t outbound_message;
1776
1777         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1778         outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1779         if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1780                 arcmsr_dr_handle( acb );
1781 }
1782 /*
1783 **************************************************************************
1784 **************************************************************************
1785 */
1786 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1787 {
1788         u_int32_t outbound_doorbell;
1789
1790         /*
1791         *******************************************************************
1792         **  Maybe here we need to check wrqbuffer_lock is lock or not
1793         **  DOORBELL: din! don!
1794         **  check if there are any mail need to pack from firmware
1795         *******************************************************************
1796         */
1797         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit,
1798         0, outbound_doorbell);
1799         CHIP_REG_WRITE32(HBA_MessageUnit,
1800         0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
1801         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1802                 arcmsr_iop2drv_data_wrote_handle(acb);
1803         }
1804         if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1805                 arcmsr_iop2drv_data_read_handle(acb);
1806         }
1807 }
1808 /*
1809 **************************************************************************
1810 **************************************************************************
1811 */
1812 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1813 {
1814         u_int32_t outbound_doorbell;
1815
1816         /*
1817         *******************************************************************
1818         **  Maybe here we need to check wrqbuffer_lock is lock or not
1819         **  DOORBELL: din! don!
1820         **  check if there are any mail need to pack from firmware
1821         *******************************************************************
1822         */
1823         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1824         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
1825         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1826                 arcmsr_iop2drv_data_wrote_handle(acb);
1827         }
1828         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1829                 arcmsr_iop2drv_data_read_handle(acb);
1830         }
1831         if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1832                 arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1833         }
1834 }
1835 /*
1836 **************************************************************************
1837 **************************************************************************
1838 */
1839 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1840 {
1841         u_int32_t outbound_Doorbell;
1842
1843         /*
1844         *******************************************************************
1845         **  Maybe here we need to check wrqbuffer_lock is lock or not
1846         **  DOORBELL: din! don!
1847         **  check if there are any mail need to pack from firmware
1848         *******************************************************************
1849         */
1850         outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1851         if(outbound_Doorbell)
1852                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1853         while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1854                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1855                         arcmsr_iop2drv_data_wrote_handle(acb);
1856                 }
1857                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1858                         arcmsr_iop2drv_data_read_handle(acb);
1859                 }
1860                 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1861                         arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1862                 }
1863                 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1864                 if(outbound_Doorbell)
1865                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1866         }
1867 }
1868 /*
1869 **************************************************************************
1870 **************************************************************************
1871 */
1872 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1873 {
1874         u_int32_t flag_srb;
1875         u_int16_t error;
1876
1877         /*
1878         *****************************************************************************
1879         **               areca cdb command done
1880         *****************************************************************************
1881         */
1882         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1883                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1884         while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1885                 0, outbound_queueport)) != 0xFFFFFFFF) {
1886                 /* check if command done with no error*/
1887         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1888                 arcmsr_drain_donequeue(acb, flag_srb, error);
1889         }       /*drain reply FIFO*/
1890 }
1891 /*
1892 **************************************************************************
1893 **************************************************************************
1894 */
1895 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1896 {
1897         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1898         u_int32_t flag_srb;
1899         int index;
1900         u_int16_t error;
1901
1902         /*
1903         *****************************************************************************
1904         **               areca cdb command done
1905         *****************************************************************************
1906         */
1907         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1908                 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1909         index = phbbmu->doneq_index;
1910         while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1911                 phbbmu->done_qbuffer[index] = 0;
1912                 index++;
1913                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1914                 phbbmu->doneq_index = index;
1915                 /* check if command done with no error*/
1916         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1917                 arcmsr_drain_donequeue(acb, flag_srb, error);
1918         }       /*drain reply FIFO*/
1919 }
1920 /*
1921 **************************************************************************
1922 **************************************************************************
1923 */
1924 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1925 {
1926         u_int32_t flag_srb,throttling = 0;
1927         u_int16_t error;
1928
1929         /*
1930         *****************************************************************************
1931         **               areca cdb command done
1932         *****************************************************************************
1933         */
1934         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1935
1936         while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1937
1938                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1939                 /* check if command done with no error*/
1940         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1941                 arcmsr_drain_donequeue(acb, flag_srb, error);
1942         throttling++;
1943         if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1944             CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1945                         throttling = 0;
1946         }
1947         }       /*drain reply FIFO*/
1948 }
1949 /*
1950 **********************************************************************
1951 **
1952 **********************************************************************
1953 */
1954 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1955 {
1956         uint16_t doneq_index, index_stripped;
1957
1958         doneq_index = phbdmu->doneq_index;
1959         if (doneq_index & 0x4000) {
1960                 index_stripped = doneq_index & 0xFF;
1961                 index_stripped += 1;
1962                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1963                 phbdmu->doneq_index = index_stripped ?
1964                     (index_stripped | 0x4000) : index_stripped;
1965         } else {
1966                 index_stripped = doneq_index;
1967                 index_stripped += 1;
1968                 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1969                 phbdmu->doneq_index = index_stripped ?
1970                     index_stripped : (index_stripped | 0x4000);
1971         }
1972         return (phbdmu->doneq_index);
1973 }
1974 /*
1975 **************************************************************************
1976 **************************************************************************
1977 */
1978 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1979 {
1980         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1981         u_int32_t outbound_write_pointer;
1982         u_int32_t addressLow;
1983         uint16_t doneq_index;
1984         u_int16_t error;
1985         /*
1986         *****************************************************************************
1987         **               areca cdb command done
1988         *****************************************************************************
1989         */
1990         if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1991             ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
1992             return;
1993         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1994                 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1995         outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
1996         doneq_index = phbdmu->doneq_index;
1997         while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
1998                 doneq_index = arcmsr_get_doneq_index(phbdmu);
1999                 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2000                 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2001                 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2002                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2003                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2004         }
2005         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2006         CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2007 }
2008 /*
2009 **********************************************************************
2010 **********************************************************************
2011 */
2012 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2013 {
2014         u_int32_t outbound_intStatus;
2015         /*
2016         *********************************************
2017         **   check outbound intstatus
2018         *********************************************
2019         */
2020         outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2021         if(!outbound_intStatus) {
2022                 /*it must be share irq*/
2023                 return;
2024         }
2025         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2026         /* MU doorbell interrupts*/
2027         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2028                 arcmsr_hba_doorbell_isr(acb);
2029         }
2030         /* MU post queue interrupts*/
2031         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2032                 arcmsr_hba_postqueue_isr(acb);
2033         }
2034         if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2035                 arcmsr_hba_message_isr(acb);
2036         }
2037 }
2038 /*
2039 **********************************************************************
2040 **********************************************************************
2041 */
2042 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2043 {
2044         u_int32_t outbound_doorbell;
2045         /*
2046         *********************************************
2047         **   check outbound intstatus
2048         *********************************************
2049         */
2050         outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
2051         if(!outbound_doorbell) {
2052                 /*it must be share irq*/
2053                 return;
2054         }
2055         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2056         CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
2057         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2058         /* MU ioctl transfer doorbell interrupts*/
2059         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2060                 arcmsr_iop2drv_data_wrote_handle(acb);
2061         }
2062         if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2063                 arcmsr_iop2drv_data_read_handle(acb);
2064         }
2065         /* MU post queue interrupts*/
2066         if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2067                 arcmsr_hbb_postqueue_isr(acb);
2068         }
2069         if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2070                 arcmsr_hbb_message_isr(acb);
2071         }
2072 }
2073 /*
2074 **********************************************************************
2075 **********************************************************************
2076 */
2077 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2078 {
2079         u_int32_t host_interrupt_status;
2080         /*
2081         *********************************************
2082         **   check outbound intstatus
2083         *********************************************
2084         */
2085         host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2086         if(!host_interrupt_status) {
2087                 /*it must be share irq*/
2088                 return;
2089         }
2090         /* MU doorbell interrupts*/
2091         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2092                 arcmsr_hbc_doorbell_isr(acb);
2093         }
2094         /* MU post queue interrupts*/
2095         if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2096                 arcmsr_hbc_postqueue_isr(acb);
2097         }
2098 }
2099 /*
2100 **********************************************************************
2101 **********************************************************************
2102 */
2103 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2104 {
2105         u_int32_t host_interrupt_status;
2106         u_int32_t intmask_org;
2107         /*
2108         *********************************************
2109         **   check outbound intstatus
2110         *********************************************
2111         */
2112         host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2113         if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2114                 /*it must be share irq*/
2115                 return;
2116         }
2117         /* disable outbound interrupt */
2118         intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)    ; /* disable outbound message0 int */
2119         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2120         /* MU doorbell interrupts*/
2121         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2122                 arcmsr_hbd_doorbell_isr(acb);
2123         }
2124         /* MU post queue interrupts*/
2125         if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2126                 arcmsr_hbd_postqueue_isr(acb);
2127         }
2128         /* enable all outbound interrupt */
2129         CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2130 //      CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2131 }
2132 /*
2133 ******************************************************************************
2134 ******************************************************************************
2135 */
2136 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2137 {
2138         switch (acb->adapter_type) {
2139         case ACB_ADAPTER_TYPE_A:
2140                 arcmsr_handle_hba_isr(acb);
2141                 break;
2142         case ACB_ADAPTER_TYPE_B:
2143                 arcmsr_handle_hbb_isr(acb);
2144                 break;
2145         case ACB_ADAPTER_TYPE_C:
2146                 arcmsr_handle_hbc_isr(acb);
2147                 break;
2148         case ACB_ADAPTER_TYPE_D:
2149                 arcmsr_handle_hbd_isr(acb);
2150                 break;
2151         default:
2152                 printf("arcmsr%d: interrupt service,"
2153                 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2154                 break;
2155         }
2156 }
2157 /*
2158 **********************************************************************
2159 **********************************************************************
2160 */
2161 static void arcmsr_intr_handler(void *arg)
2162 {
2163         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2164
2165         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2166         arcmsr_interrupt(acb);
2167         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2168 }
2169 /*
2170 ******************************************************************************
2171 ******************************************************************************
2172 */
2173 static void     arcmsr_polling_devmap(void *arg)
2174 {
2175         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2176         switch (acb->adapter_type) {
2177         case ACB_ADAPTER_TYPE_A:
2178                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2179                 break;
2180
2181         case ACB_ADAPTER_TYPE_B:
2182                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2183                 break;
2184
2185         case ACB_ADAPTER_TYPE_C:
2186                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2187                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2188                 break;
2189
2190         case ACB_ADAPTER_TYPE_D:
2191                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2192                 break;
2193         }
2194
2195         if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2196         {
2197                 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);        /* polling per 5 seconds */
2198         }
2199 }
2200
2201 /*
2202 *******************************************************************************
2203 **
2204 *******************************************************************************
2205 */
2206 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2207 {
2208         u_int32_t intmask_org;
2209
2210         if(acb != NULL) {
2211                 /* stop adapter background rebuild */
2212                 if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2213                         intmask_org = arcmsr_disable_allintr(acb);
2214                         arcmsr_stop_adapter_bgrb(acb);
2215                         arcmsr_flush_adapter_cache(acb);
2216                         arcmsr_enable_allintr(acb, intmask_org);
2217                 }
2218         }
2219 }
2220 /*
2221 ***********************************************************************
2222 **
2223 ************************************************************************
2224 */
2225 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2226 {
2227         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2228         u_int32_t retvalue = EINVAL;
2229
2230         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2231         if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2232                 return retvalue;
2233         }
2234         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2235         switch(ioctl_cmd) {
2236         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2237                         u_int8_t *pQbuffer;
2238                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2239                         u_int32_t allxfer_len=0;
2240
2241                         while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2242                                 && (allxfer_len < 1031)) {
2243                                 /*copy READ QBUFFER to srb*/
2244                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2245                                 *ptmpQbuffer = *pQbuffer;
2246                                 acb->rqbuf_firstindex++;
2247                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2248                                 /*if last index number set it to 0 */
2249                                 ptmpQbuffer++;
2250                                 allxfer_len++;
2251                         }
2252                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2253                                 struct QBUFFER *prbuffer;
2254
2255                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2256                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2257                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2258                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2259                         }
2260                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2261                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2262                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2263                 }
2264                 break;
2265         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2266                         u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2267                         u_int8_t *pQbuffer;
2268                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2269
2270                         user_len = pcmdmessagefld->cmdmessage.Length;
2271                         /*check if data xfer length of this request will overflow my array qbuffer */
2272                         wqbuf_lastindex = acb->wqbuf_lastindex;
2273                         wqbuf_firstindex = acb->wqbuf_firstindex;
2274                         if(wqbuf_lastindex != wqbuf_firstindex) {
2275                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2276                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2277                         } else {
2278                                 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2279                                     (ARCMSR_MAX_QBUFFER - 1);
2280                                 if(my_empty_len >= user_len) {
2281                                         while(user_len > 0) {
2282                                                 /*copy srb data to wqbuffer*/
2283                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2284                                                 *pQbuffer = *ptmpuserbuffer;
2285                                                 acb->wqbuf_lastindex++;
2286                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2287                                                 /*if last index number set it to 0 */
2288                                                 ptmpuserbuffer++;
2289                                                 user_len--;
2290                                         }
2291                                         /*post fist Qbuffer*/
2292                                         if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2293                                                 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2294                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2295                                         }
2296                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2297                                 } else {
2298                                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2299                                 }
2300                         }
2301                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2302                 }
2303                 break;
2304         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2305                         u_int8_t *pQbuffer = acb->rqbuffer;
2306
2307                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2308                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2309                                 arcmsr_iop_message_read(acb);
2310                                 /*signature, let IOP know data has been readed */
2311                         }
2312                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2313                         acb->rqbuf_firstindex = 0;
2314                         acb->rqbuf_lastindex = 0;
2315                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2316                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2317                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2318                 }
2319                 break;
2320         case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2321                 {
2322                         u_int8_t *pQbuffer = acb->wqbuffer;
2323
2324                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2325                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2326                 arcmsr_iop_message_read(acb);
2327                                 /*signature, let IOP know data has been readed */
2328                         }
2329                         acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2330                         acb->wqbuf_firstindex = 0;
2331                         acb->wqbuf_lastindex = 0;
2332                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2333                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2334                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2335                 }
2336                 break;
2337         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2338                         u_int8_t *pQbuffer;
2339
2340                         if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2341                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2342                 arcmsr_iop_message_read(acb);
2343                                 /*signature, let IOP know data has been readed */
2344                         }
2345                         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2346                                         |ACB_F_MESSAGE_RQBUFFER_CLEARED
2347                                         |ACB_F_MESSAGE_WQBUFFER_READ);
2348                         acb->rqbuf_firstindex = 0;
2349                         acb->rqbuf_lastindex = 0;
2350                         acb->wqbuf_firstindex = 0;
2351                         acb->wqbuf_lastindex = 0;
2352                         pQbuffer = acb->rqbuffer;
2353                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2354                         pQbuffer = acb->wqbuffer;
2355                         memset(pQbuffer, 0, sizeof(struct QBUFFER));
2356                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2357                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2358                 }
2359                 break;
2360         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2361                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2362                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2363                 }
2364                 break;
2365         case ARCMSR_MESSAGE_SAY_HELLO: {
2366                         u_int8_t *hello_string = "Hello! I am ARCMSR";
2367                         u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2368
2369                         if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2370                                 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2371                                 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2372                                 return ENOIOCTL;
2373                         }
2374                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2375                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2376                 }
2377                 break;
2378         case ARCMSR_MESSAGE_SAY_GOODBYE: {
2379                         arcmsr_iop_parking(acb);
2380                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2381                 }
2382                 break;
2383         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2384                         arcmsr_flush_adapter_cache(acb);
2385                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2386                 }
2387                 break;
2388         }
2389         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2390         return (retvalue);
2391 }
2392 /*
2393 **************************************************************************
2394 **************************************************************************
2395 */
2396 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2397 {
2398         struct AdapterControlBlock      *acb;
2399
2400         acb = srb->acb;
2401         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2402         srb->srb_state = ARCMSR_SRB_DONE;
2403         srb->srb_flags = 0;
2404         acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2405         acb->workingsrb_doneindex++;
2406         acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2407         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2408 }
2409 /*
2410 **************************************************************************
2411 **************************************************************************
2412 */
2413 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2414 {
2415         struct CommandControlBlock *srb = NULL;
2416         u_int32_t workingsrb_startindex, workingsrb_doneindex;
2417
2418         ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2419         workingsrb_doneindex = acb->workingsrb_doneindex;
2420         workingsrb_startindex = acb->workingsrb_startindex;
2421         srb = acb->srbworkingQ[workingsrb_startindex];
2422         workingsrb_startindex++;
2423         workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2424         if(workingsrb_doneindex != workingsrb_startindex) {
2425                 acb->workingsrb_startindex = workingsrb_startindex;
2426         } else {
2427                 srb = NULL;
2428         }
2429         ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2430         return(srb);
2431 }
2432 /*
2433 **************************************************************************
2434 **************************************************************************
2435 */
2436 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2437 {
2438         struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2439         int retvalue = 0, transfer_len = 0;
2440         char *buffer;
2441         u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
2442                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
2443                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
2444                                 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
2445                                         /* 4 bytes: Areca io control code */
2446         if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2447                 buffer = pccb->csio.data_ptr;
2448                 transfer_len = pccb->csio.dxfer_len;
2449         } else {
2450                 retvalue = ARCMSR_MESSAGE_FAIL;
2451                 goto message_out;
2452         }
2453         if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2454                 retvalue = ARCMSR_MESSAGE_FAIL;
2455                 goto message_out;
2456         }
2457         pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2458         switch(controlcode) {
2459         case ARCMSR_MESSAGE_READ_RQBUFFER: {
2460                         u_int8_t *pQbuffer;
2461                         u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2462                         int32_t allxfer_len = 0;
2463
2464                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2465                         while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2466                                 && (allxfer_len < 1031)) {
2467                                 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2468                                 *ptmpQbuffer = *pQbuffer;
2469                                 acb->rqbuf_firstindex++;
2470                                 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2471                                 ptmpQbuffer++;
2472                                 allxfer_len++;
2473                         }
2474                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2475                                 struct QBUFFER  *prbuffer;
2476
2477                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2478                                 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2479                                 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2480                                         acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2481                         }
2482                         pcmdmessagefld->cmdmessage.Length = allxfer_len;
2483                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2484                         retvalue = ARCMSR_MESSAGE_SUCCESS;
2485                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2486                 }
2487                 break;
2488         case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2489                         int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2490                         u_int8_t *pQbuffer;
2491                         u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2492
2493                         user_len = pcmdmessagefld->cmdmessage.Length;
2494                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2495                         wqbuf_lastindex = acb->wqbuf_lastindex;
2496                         wqbuf_firstindex = acb->wqbuf_firstindex;
2497                         if (wqbuf_lastindex != wqbuf_firstindex) {
2498                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2499                                 /* has error report sensedata */
2500                             if(pccb->csio.sense_len) {
2501                                 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2502                                 /* Valid,ErrorCode */
2503                                 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2504                                 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2505                                 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2506                                 /* AdditionalSenseLength */
2507                                 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2508                                 /* AdditionalSenseCode */
2509                                 }
2510                                 retvalue = ARCMSR_MESSAGE_FAIL;
2511                         } else {
2512                                 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2513                                                 &(ARCMSR_MAX_QBUFFER - 1);
2514                                 if (my_empty_len >= user_len) {
2515                                         while (user_len > 0) {
2516                                                 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2517                                                 *pQbuffer = *ptmpuserbuffer;
2518                                                 acb->wqbuf_lastindex++;
2519                                                 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2520                                                 ptmpuserbuffer++;
2521                                                 user_len--;
2522                                         }
2523                                         if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2524                                                 acb->acb_flags &=
2525                                                     ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2526                                                 arcmsr_Write_data_2iop_wqbuffer(acb);
2527                                         }
2528                                 } else {
2529                                         /* has error report sensedata */
2530                                         if(pccb->csio.sense_len) {
2531                                         ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2532                                         /* Valid,ErrorCode */
2533                                         ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2534                                         /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2535                                         ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2536                                         /* AdditionalSenseLength */
2537                                         ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2538                                         /* AdditionalSenseCode */
2539                                         }
2540                                         retvalue = ARCMSR_MESSAGE_FAIL;
2541                                 }
2542                         }
2543                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2544                 }
2545                 break;
2546         case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2547                         u_int8_t *pQbuffer = acb->rqbuffer;
2548
2549                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2550                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2551                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2552                                 arcmsr_iop_message_read(acb);
2553                         }
2554                         acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2555                         acb->rqbuf_firstindex = 0;
2556                         acb->rqbuf_lastindex = 0;
2557                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2558                         pcmdmessagefld->cmdmessage.ReturnCode =
2559                             ARCMSR_MESSAGE_RETURNCODE_OK;
2560                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2561                 }
2562                 break;
2563         case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2564                         u_int8_t *pQbuffer = acb->wqbuffer;
2565
2566                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2567                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2568                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2569                                 arcmsr_iop_message_read(acb);
2570                         }
2571                         acb->acb_flags |=
2572                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2573                                         ACB_F_MESSAGE_WQBUFFER_READ);
2574                         acb->wqbuf_firstindex = 0;
2575                         acb->wqbuf_lastindex = 0;
2576                         memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2577                         pcmdmessagefld->cmdmessage.ReturnCode =
2578                                 ARCMSR_MESSAGE_RETURNCODE_OK;
2579                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2580                 }
2581                 break;
2582         case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2583                         u_int8_t *pQbuffer;
2584
2585                         ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2586                         if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2587                                 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2588                                 arcmsr_iop_message_read(acb);
2589                         }
2590                         acb->acb_flags |=
2591                                 (ACB_F_MESSAGE_WQBUFFER_CLEARED
2592                                 | ACB_F_MESSAGE_RQBUFFER_CLEARED
2593                                 | ACB_F_MESSAGE_WQBUFFER_READ);
2594                         acb->rqbuf_firstindex = 0;
2595                         acb->rqbuf_lastindex = 0;
2596                         acb->wqbuf_firstindex = 0;
2597                         acb->wqbuf_lastindex = 0;
2598                         pQbuffer = acb->rqbuffer;
2599                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2600                         pQbuffer = acb->wqbuffer;
2601                         memset(pQbuffer, 0, sizeof (struct QBUFFER));
2602                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2603                         ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2604                 }
2605                 break;
2606         case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2607                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2608                 }
2609                 break;
2610         case ARCMSR_MESSAGE_SAY_HELLO: {
2611                         int8_t *hello_string = "Hello! I am ARCMSR";
2612
2613                         memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2614                                 , (int16_t)strlen(hello_string));
2615                         pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2616                 }
2617                 break;
2618         case ARCMSR_MESSAGE_SAY_GOODBYE:
2619                 arcmsr_iop_parking(acb);
2620                 break;
2621         case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2622                 arcmsr_flush_adapter_cache(acb);
2623                 break;
2624         default:
2625                 retvalue = ARCMSR_MESSAGE_FAIL;
2626         }
2627 message_out:
2628         return (retvalue);
2629 }
2630 /*
2631 *********************************************************************
2632 *********************************************************************
2633 */
2634 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2635 {
2636         struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2637         struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2638         union ccb *pccb;
2639         int target, lun;
2640
2641         pccb = srb->pccb;
2642         target = pccb->ccb_h.target_id;
2643         lun = pccb->ccb_h.target_lun;
2644         acb->pktRequestCount++;
2645         if(error != 0) {
2646                 if(error != EFBIG) {
2647                         printf("arcmsr%d: unexpected error %x"
2648                                 " returned from 'bus_dmamap_load' \n"
2649                                 , acb->pci_unit, error);
2650                 }
2651                 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2652                         pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2653                 }
2654                 arcmsr_srb_complete(srb, 0);
2655                 return;
2656         }
2657         if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2658                 pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2659                 arcmsr_srb_complete(srb, 0);
2660                 return;
2661         }
2662         if(acb->acb_flags & ACB_F_BUS_RESET) {
2663                 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2664                 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2665                 arcmsr_srb_complete(srb, 0);
2666                 return;
2667         }
2668         if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2669                 u_int8_t block_cmd, cmd;
2670
2671                 cmd = pccb->csio.cdb_io.cdb_bytes[0];
2672                 block_cmd = cmd & 0x0f;
2673                 if(block_cmd == 0x08 || block_cmd == 0x0a) {
2674                         printf("arcmsr%d:block 'read/write' command "
2675                                 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2676                                 , acb->pci_unit, cmd, target, lun);
2677                         pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2678                         arcmsr_srb_complete(srb, 0);
2679                         return;
2680                 }
2681         }
2682         if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2683                 if(nseg != 0) {
2684                         bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2685                 }
2686                 arcmsr_srb_complete(srb, 0);
2687                 return;
2688         }
2689         if(acb->srboutstandingcount >= acb->maxOutstanding) {
2690                 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2691                 {
2692                         xpt_freeze_simq(acb->psim, 1);
2693                         acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2694                 }
2695                 pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2696                 pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2697                 arcmsr_srb_complete(srb, 0);
2698                 return;
2699         }
2700         pccb->ccb_h.status |= CAM_SIM_QUEUED;
2701         arcmsr_build_srb(srb, dm_segs, nseg);
2702         arcmsr_post_srb(acb, srb);
2703         if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2704         {
2705                 arcmsr_callout_init(&srb->ccb_callout);
2706                 callout_reset_sbt(&srb->ccb_callout, SBT_1MS *
2707                     (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0,
2708                     arcmsr_srb_timeout, srb, 0);
2709                 srb->srb_flags |= SRB_FLAG_TIMER_START;
2710         }
2711 }
2712 /*
2713 *****************************************************************************************
2714 *****************************************************************************************
2715 */
2716 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2717 {
2718         struct CommandControlBlock *srb;
2719         struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2720         u_int32_t intmask_org;
2721         int i = 0;
2722
2723         acb->num_aborts++;
2724         /*
2725         ***************************************************************************
2726         ** It is the upper layer do abort command this lock just prior to calling us.
2727         ** First determine if we currently own this command.
2728         ** Start by searching the device queue. If not found
2729         ** at all, and the system wanted us to just abort the
2730         ** command return success.
2731         ***************************************************************************
2732         */
2733         if(acb->srboutstandingcount != 0) {
2734                 /* disable all outbound interrupt */
2735                 intmask_org = arcmsr_disable_allintr(acb);
2736                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2737                         srb = acb->psrb_pool[i];
2738                         if(srb->srb_state == ARCMSR_SRB_START) {
2739                                 if(srb->pccb == abortccb) {
2740                                         srb->srb_state = ARCMSR_SRB_ABORTED;
2741                                         printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
2742                                                 "outstanding command \n"
2743                                                 , acb->pci_unit, abortccb->ccb_h.target_id
2744                                                 , abortccb->ccb_h.target_lun, srb);
2745                                         arcmsr_polling_srbdone(acb, srb);
2746                                         /* enable outbound Post Queue, outbound doorbell Interrupt */
2747                                         arcmsr_enable_allintr(acb, intmask_org);
2748                                         return (TRUE);
2749                                 }
2750                         }
2751                 }
2752                 /* enable outbound Post Queue, outbound doorbell Interrupt */
2753                 arcmsr_enable_allintr(acb, intmask_org);
2754         }
2755         return(FALSE);
2756 }
2757 /*
2758 ****************************************************************************
2759 ****************************************************************************
2760 */
2761 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2762 {
2763         int retry = 0;
2764
2765         acb->num_resets++;
2766         acb->acb_flags |= ACB_F_BUS_RESET;
2767         while(acb->srboutstandingcount != 0 && retry < 400) {
2768                 arcmsr_interrupt(acb);
2769                 UDELAY(25000);
2770                 retry++;
2771         }
2772         arcmsr_iop_reset(acb);
2773         acb->acb_flags &= ~ACB_F_BUS_RESET;
2774 }
2775 /*
2776 **************************************************************************
2777 **************************************************************************
2778 */
2779 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2780                 union ccb *pccb)
2781 {
2782         if (pccb->ccb_h.target_lun) {
2783                 pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2784                 xpt_done(pccb);
2785                 return;
2786         }
2787         pccb->ccb_h.status |= CAM_REQ_CMP;
2788         switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2789         case INQUIRY: {
2790                 unsigned char inqdata[36];
2791                 char *buffer = pccb->csio.data_ptr;
2792
2793                 inqdata[0] = T_PROCESSOR;       /* Periph Qualifier & Periph Dev Type */
2794                 inqdata[1] = 0;                         /* rem media bit & Dev Type Modifier */
2795                 inqdata[2] = 0;                         /* ISO, ECMA, & ANSI versions */
2796                 inqdata[3] = 0;
2797                 inqdata[4] = 31;                        /* length of additional data */
2798                 inqdata[5] = 0;
2799                 inqdata[6] = 0;
2800                 inqdata[7] = 0;
2801                 strncpy(&inqdata[8], "Areca   ", 8);    /* Vendor Identification */
2802                 strncpy(&inqdata[16], "RAID controller ", 16);  /* Product Identification */
2803                 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2804                 memcpy(buffer, inqdata, sizeof(inqdata));
2805                 xpt_done(pccb);
2806         }
2807         break;
2808         case WRITE_BUFFER:
2809         case READ_BUFFER: {
2810                 if (arcmsr_iop_message_xfer(acb, pccb)) {
2811                         pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2812                         pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2813                 }
2814                 xpt_done(pccb);
2815         }
2816         break;
2817         default:
2818                 xpt_done(pccb);
2819         }
2820 }
2821 /*
2822 *********************************************************************
2823 *********************************************************************
2824 */
2825 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2826 {
2827         struct AdapterControlBlock *acb;
2828
2829         acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2830         if(acb == NULL) {
2831                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2832                 xpt_done(pccb);
2833                 return;
2834         }
2835         switch (pccb->ccb_h.func_code) {
2836         case XPT_SCSI_IO: {
2837                         struct CommandControlBlock *srb;
2838                         int target = pccb->ccb_h.target_id;
2839                         int error;
2840
2841                         if(target == 16) {
2842                                 /* virtual device for iop message transfer */
2843                                 arcmsr_handle_virtual_command(acb, pccb);
2844                                 return;
2845                         }
2846                         if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2847                                 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2848                                 xpt_done(pccb);
2849                                 return;
2850                         }
2851                         pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2852                         pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2853                         srb->pccb = pccb;
2854                         error = bus_dmamap_load_ccb(acb->dm_segs_dmat
2855                                 , srb->dm_segs_dmamap
2856                                 , pccb
2857                                 , arcmsr_execute_srb, srb, /*flags*/0);
2858                         if(error == EINPROGRESS) {
2859                                 xpt_freeze_simq(acb->psim, 1);
2860                                 pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2861                         }
2862                         break;
2863                 }
2864         case XPT_TARGET_IO: {
2865                         /* target mode not yet support vendor specific commands. */
2866                         pccb->ccb_h.status |= CAM_REQ_CMP;
2867                         xpt_done(pccb);
2868                         break;
2869                 }
2870         case XPT_PATH_INQ: {
2871                         struct ccb_pathinq *cpi = &pccb->cpi;
2872
2873                         cpi->version_num = 1;
2874                         cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2875                         cpi->target_sprt = 0;
2876                         cpi->hba_misc = 0;
2877                         cpi->hba_eng_cnt = 0;
2878                         cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
2879                         cpi->max_lun = ARCMSR_MAX_TARGETLUN;        /* 0-7 */
2880                         cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2881                         cpi->bus_id = cam_sim_bus(psim);
2882                         strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2883                         strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2884                         strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2885                         cpi->unit_number = cam_sim_unit(psim);
2886                 #ifdef  CAM_NEW_TRAN_CODE
2887                         if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2888                                 cpi->base_transfer_speed = 600000;
2889                         else
2890                                 cpi->base_transfer_speed = 300000;
2891                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2892                            (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2893                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2894                         {
2895                                 cpi->transport = XPORT_SAS;
2896                                 cpi->transport_version = 0;
2897                                 cpi->protocol_version = SCSI_REV_SPC2;
2898                         }
2899                         else
2900                         {
2901                                 cpi->transport = XPORT_SPI;
2902                                 cpi->transport_version = 2;
2903                                 cpi->protocol_version = SCSI_REV_2;
2904                         }
2905                         cpi->protocol = PROTO_SCSI;
2906                 #endif
2907                         cpi->ccb_h.status |= CAM_REQ_CMP;
2908                         xpt_done(pccb);
2909                         break;
2910                 }
2911         case XPT_ABORT: {
2912                         union ccb *pabort_ccb;
2913
2914                         pabort_ccb = pccb->cab.abort_ccb;
2915                         switch (pabort_ccb->ccb_h.func_code) {
2916                         case XPT_ACCEPT_TARGET_IO:
2917                         case XPT_IMMED_NOTIFY:
2918                         case XPT_CONT_TARGET_IO:
2919                                 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2920                                         pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2921                                         xpt_done(pabort_ccb);
2922                                         pccb->ccb_h.status |= CAM_REQ_CMP;
2923                                 } else {
2924                                         xpt_print_path(pabort_ccb->ccb_h.path);
2925                                         printf("Not found\n");
2926                                         pccb->ccb_h.status |= CAM_PATH_INVALID;
2927                                 }
2928                                 break;
2929                         case XPT_SCSI_IO:
2930                                 pccb->ccb_h.status |= CAM_UA_ABORT;
2931                                 break;
2932                         default:
2933                                 pccb->ccb_h.status |= CAM_REQ_INVALID;
2934                                 break;
2935                         }
2936                         xpt_done(pccb);
2937                         break;
2938                 }
2939         case XPT_RESET_BUS:
2940         case XPT_RESET_DEV: {
2941                         u_int32_t     i;
2942
2943                         arcmsr_bus_reset(acb);
2944                         for (i=0; i < 500; i++) {
2945                                 DELAY(1000);
2946                         }
2947                         pccb->ccb_h.status |= CAM_REQ_CMP;
2948                         xpt_done(pccb);
2949                         break;
2950                 }
2951         case XPT_TERM_IO: {
2952                         pccb->ccb_h.status |= CAM_REQ_INVALID;
2953                         xpt_done(pccb);
2954                         break;
2955                 }
2956         case XPT_GET_TRAN_SETTINGS: {
2957                         struct ccb_trans_settings *cts;
2958
2959                         if(pccb->ccb_h.target_id == 16) {
2960                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2961                                 xpt_done(pccb);
2962                                 break;
2963                         }
2964                         cts = &pccb->cts;
2965                 #ifdef  CAM_NEW_TRAN_CODE
2966                         {
2967                                 struct ccb_trans_settings_scsi *scsi;
2968                                 struct ccb_trans_settings_spi *spi;
2969                                 struct ccb_trans_settings_sas *sas;
2970
2971                                 scsi = &cts->proto_specific.scsi;
2972                                 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2973                                 scsi->valid = CTS_SCSI_VALID_TQ;
2974                                 cts->protocol = PROTO_SCSI;
2975
2976                                 if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2977                                    (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2978                                    (acb->vendor_device_id == PCIDevVenIDARC1214))
2979                                 {
2980                                         cts->protocol_version = SCSI_REV_SPC2;
2981                                         cts->transport_version = 0;
2982                                         cts->transport = XPORT_SAS;
2983                                         sas = &cts->xport_specific.sas;
2984                                         sas->valid = CTS_SAS_VALID_SPEED;
2985                                         if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2986                                            (acb->vendor_device_id == PCIDevVenIDARC1214))
2987                                                 sas->bitrate = 600000;
2988                                         else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2989                                                 sas->bitrate = 300000;
2990                                 }
2991                                 else
2992                                 {
2993                                         cts->protocol_version = SCSI_REV_2;
2994                                         cts->transport_version = 2;
2995                                         cts->transport = XPORT_SPI;
2996                                         spi = &cts->xport_specific.spi;
2997                                         spi->flags = CTS_SPI_FLAGS_DISC_ENB;
2998                                         spi->sync_period = 2;
2999                                         spi->sync_offset = 32;
3000                                         spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3001                                         spi->valid = CTS_SPI_VALID_DISC
3002                                                 | CTS_SPI_VALID_SYNC_RATE
3003                                                 | CTS_SPI_VALID_SYNC_OFFSET
3004                                                 | CTS_SPI_VALID_BUS_WIDTH;
3005                                 }
3006                         }
3007                 #else
3008                         {
3009                                 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3010                                 cts->sync_period = 2;
3011                                 cts->sync_offset = 32;
3012                                 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3013                                 cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3014                                 CCB_TRANS_SYNC_OFFSET_VALID |
3015                                 CCB_TRANS_BUS_WIDTH_VALID |
3016                                 CCB_TRANS_DISC_VALID |
3017                                 CCB_TRANS_TQ_VALID;
3018                         }
3019                 #endif
3020                         pccb->ccb_h.status |= CAM_REQ_CMP;
3021                         xpt_done(pccb);
3022                         break;
3023                 }
3024         case XPT_SET_TRAN_SETTINGS: {
3025                         pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3026                         xpt_done(pccb);
3027                         break;
3028                 }
3029         case XPT_CALC_GEOMETRY:
3030                         if(pccb->ccb_h.target_id == 16) {
3031                                 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3032                                 xpt_done(pccb);
3033                                 break;
3034                         }
3035 #if __FreeBSD_version >= 500000
3036                         cam_calc_geometry(&pccb->ccg, 1);
3037 #else
3038                         {
3039                         struct ccb_calc_geometry *ccg;
3040                         u_int32_t size_mb;
3041                         u_int32_t secs_per_cylinder;
3042
3043                         ccg = &pccb->ccg;
3044                         if (ccg->block_size == 0) {
3045                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3046                                 xpt_done(pccb);
3047                                 break;
3048                         }
3049                         if(((1024L * 1024L)/ccg->block_size) < 0) {
3050                                 pccb->ccb_h.status = CAM_REQ_INVALID;
3051                                 xpt_done(pccb);
3052                                 break;
3053                         }
3054                         size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3055                         if(size_mb > 1024 ) {
3056                                 ccg->heads = 255;
3057                                 ccg->secs_per_track = 63;
3058                         } else {
3059                                 ccg->heads = 64;
3060                                 ccg->secs_per_track = 32;
3061                         }
3062                         secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3063                         ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3064                         pccb->ccb_h.status |= CAM_REQ_CMP;
3065                         }
3066 #endif
3067                         xpt_done(pccb);
3068                         break;
3069         default:
3070                 pccb->ccb_h.status |= CAM_REQ_INVALID;
3071                 xpt_done(pccb);
3072                 break;
3073         }
3074 }
3075 /*
3076 **********************************************************************
3077 **********************************************************************
3078 */
3079 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3080 {
3081         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3082         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3083         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3084                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3085         }
3086 }
3087 /*
3088 **********************************************************************
3089 **********************************************************************
3090 */
3091 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3092 {
3093         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3094         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,  ARCMSR_MESSAGE_START_BGRB);
3095         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3096                 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3097         }
3098 }
3099 /*
3100 **********************************************************************
3101 **********************************************************************
3102 */
3103 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3104 {
3105         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3106         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3107         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3108         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3109                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3110         }
3111 }
3112 /*
3113 **********************************************************************
3114 **********************************************************************
3115 */
3116 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3117 {
3118         acb->acb_flags |= ACB_F_MSG_START_BGRB;
3119         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3120         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3121                 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3122         }
3123 }
3124 /*
3125 **********************************************************************
3126 **********************************************************************
3127 */
3128 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3129 {
3130         switch (acb->adapter_type) {
3131         case ACB_ADAPTER_TYPE_A:
3132                 arcmsr_start_hba_bgrb(acb);
3133                 break;
3134         case ACB_ADAPTER_TYPE_B:
3135                 arcmsr_start_hbb_bgrb(acb);
3136                 break;
3137         case ACB_ADAPTER_TYPE_C:
3138                 arcmsr_start_hbc_bgrb(acb);
3139                 break;
3140         case ACB_ADAPTER_TYPE_D:
3141                 arcmsr_start_hbd_bgrb(acb);
3142                 break;
3143         }
3144 }
3145 /*
3146 **********************************************************************
3147 **
3148 **********************************************************************
3149 */
3150 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3151 {
3152         struct CommandControlBlock *srb;
3153         u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3154         u_int16_t       error;
3155
3156 polling_ccb_retry:
3157         poll_count++;
3158         outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3159         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);   /*clear interrupt*/
3160         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3161         while(1) {
3162                 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3163                         0, outbound_queueport)) == 0xFFFFFFFF) {
3164                         if(poll_srb_done) {
3165                                 break;/*chip FIFO no ccb for completion already*/
3166                         } else {
3167                                 UDELAY(25000);
3168                                 if ((poll_count > 100) && (poll_srb != NULL)) {
3169                                         break;
3170                                 }
3171                                 goto polling_ccb_retry;
3172                         }
3173                 }
3174                 /* check if command done with no error*/
3175                 srb = (struct CommandControlBlock *)
3176                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3177         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3178                 poll_srb_done = (srb == poll_srb) ? 1:0;
3179                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3180                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3181                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3182                                         "poll command abort successfully \n"
3183                                         , acb->pci_unit
3184                                         , srb->pccb->ccb_h.target_id
3185                                         , srb->pccb->ccb_h.target_lun, srb);
3186                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3187                                 arcmsr_srb_complete(srb, 1);
3188                                 continue;
3189                         }
3190                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3191                                 "srboutstandingcount=%d \n"
3192                                 , acb->pci_unit
3193                                 , srb, acb->srboutstandingcount);
3194                         continue;
3195                 }
3196                 arcmsr_report_srb_state(acb, srb, error);
3197         }       /*drain reply FIFO*/
3198 }
3199 /*
3200 **********************************************************************
3201 **
3202 **********************************************************************
3203 */
3204 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3205 {
3206         struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3207         struct CommandControlBlock *srb;
3208         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3209         int index;
3210         u_int16_t       error;
3211
3212 polling_ccb_retry:
3213         poll_count++;
3214         CHIP_REG_WRITE32(HBB_DOORBELL,
3215         0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3216         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3217         while(1) {
3218                 index = phbbmu->doneq_index;
3219                 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3220                         if(poll_srb_done) {
3221                                 break;/*chip FIFO no ccb for completion already*/
3222                         } else {
3223                                 UDELAY(25000);
3224                             if ((poll_count > 100) && (poll_srb != NULL)) {
3225                                         break;
3226                                 }
3227                                 goto polling_ccb_retry;
3228                         }
3229                 }
3230                 phbbmu->done_qbuffer[index] = 0;
3231                 index++;
3232                 index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3233                 phbbmu->doneq_index = index;
3234                 /* check if command done with no error*/
3235                 srb = (struct CommandControlBlock *)
3236                         (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3237         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3238                 poll_srb_done = (srb == poll_srb) ? 1:0;
3239                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3240                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3241                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3242                                         "poll command abort successfully \n"
3243                                         , acb->pci_unit
3244                                         , srb->pccb->ccb_h.target_id
3245                                         , srb->pccb->ccb_h.target_lun, srb);
3246                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3247                                 arcmsr_srb_complete(srb, 1);
3248                                 continue;
3249                         }
3250                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3251                                 "srboutstandingcount=%d \n"
3252                                 , acb->pci_unit
3253                                 , srb, acb->srboutstandingcount);
3254                         continue;
3255                 }
3256                 arcmsr_report_srb_state(acb, srb, error);
3257         }       /*drain reply FIFO*/
3258 }
3259 /*
3260 **********************************************************************
3261 **
3262 **********************************************************************
3263 */
3264 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3265 {
3266         struct CommandControlBlock *srb;
3267         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3268         u_int16_t       error;
3269
3270 polling_ccb_retry:
3271         poll_count++;
3272         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3273         while(1) {
3274                 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3275                         if(poll_srb_done) {
3276                                 break;/*chip FIFO no ccb for completion already*/
3277                         } else {
3278                                 UDELAY(25000);
3279                             if ((poll_count > 100) && (poll_srb != NULL)) {
3280                                         break;
3281                                 }
3282                             if (acb->srboutstandingcount == 0) {
3283                                     break;
3284                             }
3285                                 goto polling_ccb_retry;
3286                         }
3287                 }
3288                 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3289                 /* check if command done with no error*/
3290                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3291         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3292                 if (poll_srb != NULL)
3293                         poll_srb_done = (srb == poll_srb) ? 1:0;
3294                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3295                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3296                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3297                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3298                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3299                                 arcmsr_srb_complete(srb, 1);
3300                                 continue;
3301                         }
3302                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3303                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3304                         continue;
3305                 }
3306                 arcmsr_report_srb_state(acb, srb, error);
3307         }       /*drain reply FIFO*/
3308 }
3309 /*
3310 **********************************************************************
3311 **
3312 **********************************************************************
3313 */
3314 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3315 {
3316         struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3317         struct CommandControlBlock *srb;
3318         u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3319         u_int32_t outbound_write_pointer;
3320         u_int16_t       error, doneq_index;
3321
3322 polling_ccb_retry:
3323         poll_count++;
3324         bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3325         while(1) {
3326                 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3327                 doneq_index = phbdmu->doneq_index;
3328                 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3329                         if(poll_srb_done) {
3330                                 break;/*chip FIFO no ccb for completion already*/
3331                         } else {
3332                                 UDELAY(25000);
3333                             if ((poll_count > 100) && (poll_srb != NULL)) {
3334                                         break;
3335                                 }
3336                             if (acb->srboutstandingcount == 0) {
3337                                     break;
3338                             }
3339                                 goto polling_ccb_retry;
3340                         }
3341                 }
3342                 doneq_index = arcmsr_get_doneq_index(phbdmu);
3343                 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3344                 /* check if command done with no error*/
3345                 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3346         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3347                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3348                 if (poll_srb != NULL)
3349                         poll_srb_done = (srb == poll_srb) ? 1:0;
3350                 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3351                         if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3352                                 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3353                                                 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3354                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3355                                 arcmsr_srb_complete(srb, 1);
3356                                 continue;
3357                         }
3358                         printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3359                                         , acb->pci_unit, srb, acb->srboutstandingcount);
3360                         continue;
3361                 }
3362                 arcmsr_report_srb_state(acb, srb, error);
3363         }       /*drain reply FIFO*/
3364 }
3365 /*
3366 **********************************************************************
3367 **********************************************************************
3368 */
3369 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3370 {
3371         switch (acb->adapter_type) {
3372         case ACB_ADAPTER_TYPE_A: {
3373                         arcmsr_polling_hba_srbdone(acb, poll_srb);
3374                 }
3375                 break;
3376         case ACB_ADAPTER_TYPE_B: {
3377                         arcmsr_polling_hbb_srbdone(acb, poll_srb);
3378                 }
3379                 break;
3380         case ACB_ADAPTER_TYPE_C: {
3381                         arcmsr_polling_hbc_srbdone(acb, poll_srb);
3382                 }
3383                 break;
3384         case ACB_ADAPTER_TYPE_D: {
3385                         arcmsr_polling_hbd_srbdone(acb, poll_srb);
3386                 }
3387                 break;
3388         }
3389 }
3390 /*
3391 **********************************************************************
3392 **********************************************************************
3393 */
3394 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3395 {
3396         char *acb_firm_model = acb->firm_model;
3397         char *acb_firm_version = acb->firm_version;
3398         char *acb_device_map = acb->device_map;
3399         size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);      /*firm_model,15,60-67*/
3400         size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);     /*firm_version,17,68-83*/
3401         size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3402         int i;
3403
3404         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3405         if(!arcmsr_hba_wait_msgint_ready(acb)) {
3406                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3407         }
3408         i = 0;
3409         while(i < 8) {
3410                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3411                 /* 8 bytes firm_model, 15, 60-67*/
3412                 acb_firm_model++;
3413                 i++;
3414         }
3415         i=0;
3416         while(i < 16) {
3417                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3418                 /* 16 bytes firm_version, 17, 68-83*/
3419                 acb_firm_version++;
3420                 i++;
3421         }
3422         i=0;
3423         while(i < 16) {
3424                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3425                 acb_device_map++;
3426                 i++;
3427         }
3428         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3429         acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3430         acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3431         acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3432         acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3433         acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version,  25,          */
3434         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3435                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3436         else
3437                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3438 }
3439 /*
3440 **********************************************************************
3441 **********************************************************************
3442 */
3443 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3444 {
3445         char *acb_firm_model = acb->firm_model;
3446         char *acb_firm_version = acb->firm_version;
3447         char *acb_device_map = acb->device_map;
3448         size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);        /*firm_model,15,60-67*/
3449         size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);       /*firm_version,17,68-83*/
3450         size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3451         int i;
3452
3453         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3454         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3455                 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3456         }
3457         i = 0;
3458         while(i < 8) {
3459                 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3460                 /* 8 bytes firm_model, 15, 60-67*/
3461                 acb_firm_model++;
3462                 i++;
3463         }
3464         i = 0;
3465         while(i < 16) {
3466                 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3467                 /* 16 bytes firm_version, 17, 68-83*/
3468                 acb_firm_version++;
3469                 i++;
3470         }
3471         i = 0;
3472         while(i < 16) {
3473                 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3474                 acb_device_map++;
3475                 i++;
3476         }
3477         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3478         acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3479         acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3480         acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3481         acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3482         acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);    /*firm_cfg_version,  25,          */
3483         if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE)
3484                 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1;
3485         else
3486                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3487 }
3488 /*
3489 **********************************************************************
3490 **********************************************************************
3491 */
3492 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3493 {
3494         char *acb_firm_model = acb->firm_model;
3495         char *acb_firm_version = acb->firm_version;
3496         char *acb_device_map = acb->device_map;
3497         size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3498         size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3499         size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3500         int i;
3501
3502         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3503         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3504         if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3505                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3506         }
3507         i = 0;
3508         while(i < 8) {
3509                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3510                 /* 8 bytes firm_model, 15, 60-67*/
3511                 acb_firm_model++;
3512                 i++;
3513         }
3514         i = 0;
3515         while(i < 16) {
3516                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3517                 /* 16 bytes firm_version, 17, 68-83*/
3518                 acb_firm_version++;
3519                 i++;
3520         }
3521         i = 0;
3522         while(i < 16) {
3523                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3524                 acb_device_map++;
3525                 i++;
3526         }
3527         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3528         acb->firm_request_len   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);     /*firm_request_len,   1, 04-07*/
3529         acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_numbers_queue, 2, 08-11*/
3530         acb->firm_sdram_size    = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_sdram_size,    3, 12-15*/
3531         acb->firm_ide_channels  = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_ide_channels,  4, 16-19*/
3532         acb->firm_cfg_version   = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3533         if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
3534                 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1;
3535         else
3536                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3537 }
3538 /*
3539 **********************************************************************
3540 **********************************************************************
3541 */
3542 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3543 {
3544         char *acb_firm_model = acb->firm_model;
3545         char *acb_firm_version = acb->firm_version;
3546         char *acb_device_map = acb->device_map;
3547         size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3548         size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3549         size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3550         int i;
3551
3552         if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3553                 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3554         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3555         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3556                 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3557         }
3558         i = 0;
3559         while(i < 8) {
3560                 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3561                 /* 8 bytes firm_model, 15, 60-67*/
3562                 acb_firm_model++;
3563                 i++;
3564         }
3565         i = 0;
3566         while(i < 16) {
3567                 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3568                 /* 16 bytes firm_version, 17, 68-83*/
3569                 acb_firm_version++;
3570                 i++;
3571         }
3572         i = 0;
3573         while(i < 16) {
3574                 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3575                 acb_device_map++;
3576                 i++;
3577         }
3578         printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version);
3579         acb->firm_request_len   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);     /*firm_request_len,   1, 04-07*/
3580         acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);     /*firm_numbers_queue, 2, 08-11*/
3581         acb->firm_sdram_size    = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);     /*firm_sdram_size,    3, 12-15*/
3582         acb->firm_ide_channels  = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]);     /*firm_ide_channels,  4, 16-19*/
3583         acb->firm_cfg_version   = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);       /*firm_cfg_version,  25,          */
3584         if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE)
3585                 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1;
3586         else
3587                 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3588 }
3589 /*
3590 **********************************************************************
3591 **********************************************************************
3592 */
3593 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3594 {
3595         switch (acb->adapter_type) {
3596         case ACB_ADAPTER_TYPE_A: {
3597                         arcmsr_get_hba_config(acb);
3598                 }
3599                 break;
3600         case ACB_ADAPTER_TYPE_B: {
3601                         arcmsr_get_hbb_config(acb);
3602                 }
3603                 break;
3604         case ACB_ADAPTER_TYPE_C: {
3605                         arcmsr_get_hbc_config(acb);
3606                 }
3607                 break;
3608         case ACB_ADAPTER_TYPE_D: {
3609                         arcmsr_get_hbd_config(acb);
3610                 }
3611                 break;
3612         }
3613 }
3614 /*
3615 **********************************************************************
3616 **********************************************************************
3617 */
3618 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3619 {
3620         int     timeout=0;
3621
3622         switch (acb->adapter_type) {
3623         case ACB_ADAPTER_TYPE_A: {
3624                         while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3625                         {
3626                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3627                                 {
3628                                         printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3629                                         return;
3630                                 }
3631                                 UDELAY(15000); /* wait 15 milli-seconds */
3632                         }
3633                 }
3634                 break;
3635         case ACB_ADAPTER_TYPE_B: {
3636                         while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3637                         {
3638                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3639                                 {
3640                                         printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3641                                         return;
3642                                 }
3643                                 UDELAY(15000); /* wait 15 milli-seconds */
3644                         }
3645                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3646                 }
3647                 break;
3648         case ACB_ADAPTER_TYPE_C: {
3649                         while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3650                         {
3651                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3652                                 {
3653                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3654                                         return;
3655                                 }
3656                                 UDELAY(15000); /* wait 15 milli-seconds */
3657                         }
3658                 }
3659                 break;
3660         case ACB_ADAPTER_TYPE_D: {
3661                         while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3662                         {
3663                                 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3664                                 {
3665                                         printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3666                                         return;
3667                                 }
3668                                 UDELAY(15000); /* wait 15 milli-seconds */
3669                         }
3670                 }
3671                 break;
3672         }
3673 }
3674 /*
3675 **********************************************************************
3676 **********************************************************************
3677 */
3678 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3679 {
3680         u_int32_t outbound_doorbell;
3681
3682         switch (acb->adapter_type) {
3683         case ACB_ADAPTER_TYPE_A: {
3684                         /* empty doorbell Qbuffer if door bell ringed */
3685                         outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3686                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3687                         CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3688
3689                 }
3690                 break;
3691         case ACB_ADAPTER_TYPE_B: {
3692                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3693                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3694                         /* let IOP know data has been read */
3695                 }
3696                 break;
3697         case ACB_ADAPTER_TYPE_C: {
3698                         /* empty doorbell Qbuffer if door bell ringed */
3699                         outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3700                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);       /*clear doorbell interrupt */
3701                         CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3702                         CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3703                         CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3704                 }
3705                 break;
3706         case ACB_ADAPTER_TYPE_D: {
3707                         /* empty doorbell Qbuffer if door bell ringed */
3708                         outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3709                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);     /*clear doorbell interrupt */
3710                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3711
3712                 }
3713                 break;
3714         }
3715 }
3716 /*
3717 ************************************************************************
3718 ************************************************************************
3719 */
3720 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3721 {
3722         unsigned long srb_phyaddr;
3723         u_int32_t srb_phyaddr_hi32;
3724         u_int32_t srb_phyaddr_lo32;
3725
3726         /*
3727         ********************************************************************
3728         ** here we need to tell iop 331 our freesrb.HighPart
3729         ** if freesrb.HighPart is not zero
3730         ********************************************************************
3731         */
3732         srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3733         srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3734         srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3735         switch (acb->adapter_type) {
3736         case ACB_ADAPTER_TYPE_A: {
3737                         if(srb_phyaddr_hi32 != 0) {
3738                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3739                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3740                                 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3741                                 if(!arcmsr_hba_wait_msgint_ready(acb)) {
3742                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3743                                         return FALSE;
3744                                 }
3745                         }
3746                 }
3747                 break;
3748                 /*
3749                 ***********************************************************************
3750                 **    if adapter type B, set window of "post command Q"
3751                 ***********************************************************************
3752                 */
3753         case ACB_ADAPTER_TYPE_B: {
3754                         u_int32_t post_queue_phyaddr;
3755                         struct HBB_MessageUnit *phbbmu;
3756
3757                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3758                         phbbmu->postq_index = 0;
3759                         phbbmu->doneq_index = 0;
3760                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3761                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3762                                 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3763                                 return FALSE;
3764                         }
3765                         post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3766                                                                 + offsetof(struct HBB_MessageUnit, post_qbuffer);
3767                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3768                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3769                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3770                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3771                         CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3772                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3773                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3774                                 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3775                                 return FALSE;
3776                         }
3777                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3778                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3779                                 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3780                                 return FALSE;
3781                         }
3782                 }
3783                 break;
3784         case ACB_ADAPTER_TYPE_C: {
3785                         if(srb_phyaddr_hi32 != 0) {
3786                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3787                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3788                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3789                                 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3790                                 if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3791                                         printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3792                                         return FALSE;
3793                                 }
3794                         }
3795                 }
3796                 break;
3797         case ACB_ADAPTER_TYPE_D: {
3798                         u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3799                         struct HBD_MessageUnit0 *phbdmu;
3800
3801                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3802                         phbdmu->postq_index = 0;
3803                         phbdmu->doneq_index = 0x40FF;
3804                         post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3805                                                                 + offsetof(struct HBD_MessageUnit0, post_qbuffer);
3806                         done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3807                                                                 + offsetof(struct HBD_MessageUnit0, done_qbuffer);
3808                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3809                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3810                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3811                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3812                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3813                         CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3814                         if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3815                                 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3816                                 return FALSE;
3817                         }
3818                 }
3819                 break;
3820         }
3821         return (TRUE);
3822 }
3823 /*
3824 ************************************************************************
3825 ************************************************************************
3826 */
3827 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3828 {
3829         switch (acb->adapter_type)
3830         {
3831         case ACB_ADAPTER_TYPE_A:
3832         case ACB_ADAPTER_TYPE_C:
3833         case ACB_ADAPTER_TYPE_D:
3834                 break;
3835         case ACB_ADAPTER_TYPE_B: {
3836                         CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3837                         if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3838                                 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3839                                 return;
3840                         }
3841                 }
3842                 break;
3843         }
3844 }
3845 /*
3846 **********************************************************************
3847 **********************************************************************
3848 */
3849 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3850 {
3851         u_int32_t intmask_org;
3852
3853         /* disable all outbound interrupt */
3854         intmask_org = arcmsr_disable_allintr(acb);
3855         arcmsr_wait_firmware_ready(acb);
3856         arcmsr_iop_confirm(acb);
3857         arcmsr_get_firmware_spec(acb);
3858         /*start background rebuild*/
3859         arcmsr_start_adapter_bgrb(acb);
3860         /* empty doorbell Qbuffer if door bell ringed */
3861         arcmsr_clear_doorbell_queue_buffer(acb);
3862         arcmsr_enable_eoi_mode(acb);
3863         /* enable outbound Post Queue, outbound doorbell Interrupt */
3864         arcmsr_enable_allintr(acb, intmask_org);
3865         acb->acb_flags |= ACB_F_IOP_INITED;
3866 }
3867 /*
3868 **********************************************************************
3869 **********************************************************************
3870 */
3871 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3872 {
3873         struct AdapterControlBlock *acb = arg;
3874         struct CommandControlBlock *srb_tmp;
3875         u_int32_t i;
3876         unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3877
3878         acb->srb_phyaddr.phyaddr = srb_phyaddr;
3879         srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3880         for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3881                 if(bus_dmamap_create(acb->dm_segs_dmat,
3882                          /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3883                         acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3884                         printf("arcmsr%d:"
3885                         " srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3886                         return;
3887                 }
3888                 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3889                 {
3890                         srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3891                         srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3892                 }
3893                 else
3894                         srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3895                 srb_tmp->acb = acb;
3896                 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3897                 srb_phyaddr = srb_phyaddr + SRB_SIZE;
3898                 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3899         }
3900         acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3901 }
3902 /*
3903 ************************************************************************
3904 ************************************************************************
3905 */
3906 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3907 {
3908         /* remove the control device */
3909         if(acb->ioctl_dev != NULL) {
3910                 destroy_dev(acb->ioctl_dev);
3911         }
3912         bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3913         bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3914         bus_dma_tag_destroy(acb->srb_dmat);
3915         bus_dma_tag_destroy(acb->dm_segs_dmat);
3916         bus_dma_tag_destroy(acb->parent_dmat);
3917 }
3918 /*
3919 ************************************************************************
3920 ************************************************************************
3921 */
3922 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3923 {
3924         ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3925         ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3926         ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3927         ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3928 }
3929 /*
3930 ************************************************************************
3931 ************************************************************************
3932 */
3933 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3934 {
3935         ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3936         ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3937         ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3938         ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3939 }
3940 /*
3941 ************************************************************************
3942 ************************************************************************
3943 */
3944 static u_int32_t arcmsr_initialize(device_t dev)
3945 {
3946         struct AdapterControlBlock *acb = device_get_softc(dev);
3947         u_int16_t pci_command;
3948         int i, j,max_coherent_size;
3949         u_int32_t vendor_dev_id;
3950
3951         vendor_dev_id = pci_get_devid(dev);
3952         acb->vendor_device_id = vendor_dev_id;
3953         switch (vendor_dev_id) {
3954         case PCIDevVenIDARC1880:
3955         case PCIDevVenIDARC1882:
3956         case PCIDevVenIDARC1213:
3957         case PCIDevVenIDARC1223: {
3958                         acb->adapter_type = ACB_ADAPTER_TYPE_C;
3959                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3960                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3961                 }
3962                 break;
3963         case PCIDevVenIDARC1214: {
3964                         acb->adapter_type = ACB_ADAPTER_TYPE_D;
3965                         acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3966                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
3967                 }
3968                 break;
3969         case PCIDevVenIDARC1200:
3970         case PCIDevVenIDARC1201: {
3971                         acb->adapter_type = ACB_ADAPTER_TYPE_B;
3972                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3973                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
3974                 }
3975                 break;
3976         case PCIDevVenIDARC1110:
3977         case PCIDevVenIDARC1120:
3978         case PCIDevVenIDARC1130:
3979         case PCIDevVenIDARC1160:
3980         case PCIDevVenIDARC1170:
3981         case PCIDevVenIDARC1210:
3982         case PCIDevVenIDARC1220:
3983         case PCIDevVenIDARC1230:
3984         case PCIDevVenIDARC1231:
3985         case PCIDevVenIDARC1260:
3986         case PCIDevVenIDARC1261:
3987         case PCIDevVenIDARC1270:
3988         case PCIDevVenIDARC1280:
3989         case PCIDevVenIDARC1212:
3990         case PCIDevVenIDARC1222:
3991         case PCIDevVenIDARC1380:
3992         case PCIDevVenIDARC1381:
3993         case PCIDevVenIDARC1680:
3994         case PCIDevVenIDARC1681: {
3995                         acb->adapter_type = ACB_ADAPTER_TYPE_A;
3996                         acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3997                         max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3998                 }
3999                 break;
4000         default: {
4001                         printf("arcmsr%d:"
4002                         " unknown RAID adapter type \n", device_get_unit(dev));
4003                         return ENOMEM;
4004                 }
4005         }
4006 #if __FreeBSD_version >= 700000
4007         if(bus_dma_tag_create(  /*PCI parent*/          bus_get_dma_tag(dev),
4008 #else
4009         if(bus_dma_tag_create(  /*PCI parent*/          NULL,
4010 #endif
4011                                                         /*alignemnt*/   1,
4012                                                         /*boundary*/    0,
4013                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4014                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4015                                                         /*filter*/              NULL,
4016                                                         /*filterarg*/   NULL,
4017                                                         /*maxsize*/             BUS_SPACE_MAXSIZE_32BIT,
4018                                                         /*nsegments*/   BUS_SPACE_UNRESTRICTED,
4019                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4020                                                         /*flags*/               0,
4021 #if __FreeBSD_version >= 501102
4022                                                         /*lockfunc*/    NULL,
4023                                                         /*lockarg*/             NULL,
4024 #endif
4025                                                 &acb->parent_dmat) != 0)
4026         {
4027                 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4028                 return ENOMEM;
4029         }
4030
4031         /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4032         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4033                                                         /*alignment*/   1,
4034                                                         /*boundary*/    0,
4035 #ifdef PAE
4036                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4037 #else
4038                                                         /*lowaddr*/             BUS_SPACE_MAXADDR,
4039 #endif
4040                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4041                                                         /*filter*/              NULL,
4042                                                         /*filterarg*/   NULL,
4043                                                         /*maxsize*/             ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4044                                                         /*nsegments*/   ARCMSR_MAX_SG_ENTRIES,
4045                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4046                                                         /*flags*/               0,
4047 #if __FreeBSD_version >= 501102
4048                                                         /*lockfunc*/    busdma_lock_mutex,
4049                                                         /*lockarg*/             &acb->isr_lock,
4050 #endif
4051                                                 &acb->dm_segs_dmat) != 0)
4052         {
4053                 bus_dma_tag_destroy(acb->parent_dmat);
4054                 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4055                 return ENOMEM;
4056         }
4057
4058         /* DMA tag for our srb structures.... Allocate the freesrb memory */
4059         if(bus_dma_tag_create(  /*parent_dmat*/ acb->parent_dmat,
4060                                                         /*alignment*/   0x20,
4061                                                         /*boundary*/    0,
4062                                                         /*lowaddr*/             BUS_SPACE_MAXADDR_32BIT,
4063                                                         /*highaddr*/    BUS_SPACE_MAXADDR,
4064                                                         /*filter*/              NULL,
4065                                                         /*filterarg*/   NULL,
4066                                                         /*maxsize*/             max_coherent_size,
4067                                                         /*nsegments*/   1,
4068                                                         /*maxsegsz*/    BUS_SPACE_MAXSIZE_32BIT,
4069                                                         /*flags*/               0,
4070 #if __FreeBSD_version >= 501102
4071                                                         /*lockfunc*/    NULL,
4072                                                         /*lockarg*/             NULL,
4073 #endif
4074                                                 &acb->srb_dmat) != 0)
4075         {
4076                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4077                 bus_dma_tag_destroy(acb->parent_dmat);
4078                 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4079                 return ENXIO;
4080         }
4081         /* Allocation for our srbs */
4082         if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4083                 bus_dma_tag_destroy(acb->srb_dmat);
4084                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4085                 bus_dma_tag_destroy(acb->parent_dmat);
4086                 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4087                 return ENXIO;
4088         }
4089         /* And permanently map them */
4090         if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4091                 bus_dma_tag_destroy(acb->srb_dmat);
4092                 bus_dma_tag_destroy(acb->dm_segs_dmat);
4093                 bus_dma_tag_destroy(acb->parent_dmat);
4094                 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4095                 return ENXIO;
4096         }
4097         pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4098         pci_command |= PCIM_CMD_BUSMASTEREN;
4099         pci_command |= PCIM_CMD_PERRESPEN;
4100         pci_command |= PCIM_CMD_MWRICEN;
4101         /* Enable Busmaster */
4102         pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4103         switch(acb->adapter_type) {
4104         case ACB_ADAPTER_TYPE_A: {
4105                         u_int32_t rid0 = PCIR_BAR(0);
4106                         vm_offset_t     mem_base0;
4107
4108                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
4109                         if(acb->sys_res_arcmsr[0] == NULL) {
4110                                 arcmsr_free_resource(acb);
4111                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4112                                 return ENOMEM;
4113                         }
4114                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4115                                 arcmsr_free_resource(acb);
4116                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4117                                 return ENXIO;
4118                         }
4119                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4120                         if(mem_base0 == 0) {
4121                                 arcmsr_free_resource(acb);
4122                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4123                                 return ENXIO;
4124                         }
4125                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4126                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4127                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4128                 }
4129                 break;
4130         case ACB_ADAPTER_TYPE_B: {
4131                         struct HBB_MessageUnit *phbbmu;
4132                         struct CommandControlBlock *freesrb;
4133                         u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4134                         vm_offset_t     mem_base[]={0,0};
4135                         for(i=0; i < 2; i++) {
4136                                 if(i == 0) {
4137                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
4138                                                                                         0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
4139                                 } else {
4140                                         acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
4141                                                                                         0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
4142                                 }
4143                                 if(acb->sys_res_arcmsr[i] == NULL) {
4144                                         arcmsr_free_resource(acb);
4145                                         printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4146                                         return ENOMEM;
4147                                 }
4148                                 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4149                                         arcmsr_free_resource(acb);
4150                                         printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4151                                         return ENXIO;
4152                                 }
4153                                 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4154                                 if(mem_base[i] == 0) {
4155                                         arcmsr_free_resource(acb);
4156                                         printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4157                                         return ENXIO;
4158                                 }
4159                                 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4160                                 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4161                         }
4162                         freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4163                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4164                         phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4165                         phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4166                         phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4167                 }
4168                 break;
4169         case ACB_ADAPTER_TYPE_C: {
4170                         u_int32_t rid0 = PCIR_BAR(1);
4171                         vm_offset_t     mem_base0;
4172
4173                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
4174                         if(acb->sys_res_arcmsr[0] == NULL) {
4175                                 arcmsr_free_resource(acb);
4176                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4177                                 return ENOMEM;
4178                         }
4179                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4180                                 arcmsr_free_resource(acb);
4181                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4182                                 return ENXIO;
4183                         }
4184                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4185                         if(mem_base0 == 0) {
4186                                 arcmsr_free_resource(acb);
4187                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4188                                 return ENXIO;
4189                         }
4190                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4191                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4192                         acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4193                 }
4194                 break;
4195         case ACB_ADAPTER_TYPE_D: {
4196                         struct HBD_MessageUnit0 *phbdmu;
4197                         u_int32_t rid0 = PCIR_BAR(0);
4198                         vm_offset_t     mem_base0;
4199
4200                         acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
4201                         if(acb->sys_res_arcmsr[0] == NULL) {
4202                                 arcmsr_free_resource(acb);
4203                                 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4204                                 return ENOMEM;
4205                         }
4206                         if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4207                                 arcmsr_free_resource(acb);
4208                                 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4209                                 return ENXIO;
4210                         }
4211                         mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4212                         if(mem_base0 == 0) {
4213                                 arcmsr_free_resource(acb);
4214                                 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4215                                 return ENXIO;
4216                         }
4217                         acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4218                         acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4219                         acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4220                         phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4221                         phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4222                 }
4223                 break;
4224         }
4225         if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4226                 arcmsr_free_resource(acb);
4227                 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4228                 return ENXIO;
4229         }
4230         acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4231         acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4232         /*
4233         ********************************************************************
4234         ** init raid volume state
4235         ********************************************************************
4236         */
4237         for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4238                 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4239                         acb->devstate[i][j] = ARECA_RAID_GONE;
4240                 }
4241         }
4242         arcmsr_iop_init(acb);
4243         return(0);
4244 }
4245 /*
4246 ************************************************************************
4247 ************************************************************************
4248 */
4249 static int arcmsr_attach(device_t dev)
4250 {
4251         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4252         u_int32_t unit=device_get_unit(dev);
4253         struct ccb_setasync csa;
4254         struct cam_devq *devq;  /* Device Queue to use for this SIM */
4255         struct resource *irqres;
4256         int     rid;
4257
4258         if(acb == NULL) {
4259                 printf("arcmsr%d: cannot allocate softc\n", unit);
4260                 return (ENOMEM);
4261         }
4262         arcmsr_mutex_init(acb);
4263         acb->pci_dev = dev;
4264         acb->pci_unit = unit;
4265         if(arcmsr_initialize(dev)) {
4266                 printf("arcmsr%d: initialize failure!\n", unit);
4267                 arcmsr_mutex_destroy(acb);
4268                 return ENXIO;
4269         }
4270         /* After setting up the adapter, map our interrupt */
4271         rid = 0;
4272         irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
4273         if(irqres == NULL ||
4274 #if __FreeBSD_version >= 700025
4275                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4276 #else
4277                 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4278 #endif
4279                 arcmsr_free_resource(acb);
4280                 arcmsr_mutex_destroy(acb);
4281                 printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4282                 return ENXIO;
4283         }
4284         acb->irqres = irqres;
4285         /*
4286          * Now let the CAM generic SCSI layer find the SCSI devices on
4287          * the bus *  start queue to reset to the idle loop. *
4288          * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4289          * max_sim_transactions
4290         */
4291         devq = cam_simq_alloc(ARCMSR_MAX_START_JOB);
4292         if(devq == NULL) {
4293             arcmsr_free_resource(acb);
4294                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4295                 arcmsr_mutex_destroy(acb);
4296                 printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4297                 return ENXIO;
4298         }
4299 #if __FreeBSD_version >= 700025
4300         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4301 #else
4302         acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4303 #endif
4304         if(acb->psim == NULL) {
4305                 arcmsr_free_resource(acb);
4306                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4307                 cam_simq_free(devq);
4308                 arcmsr_mutex_destroy(acb);
4309                 printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4310                 return ENXIO;
4311         }
4312         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4313 #if __FreeBSD_version >= 700044
4314         if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4315 #else
4316         if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4317 #endif
4318                 arcmsr_free_resource(acb);
4319                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4320                 cam_sim_free(acb->psim, /*free_devq*/TRUE);
4321                 arcmsr_mutex_destroy(acb);
4322                 printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4323                 return ENXIO;
4324         }
4325         if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4326                 arcmsr_free_resource(acb);
4327                 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4328                 xpt_bus_deregister(cam_sim_path(acb->psim));
4329                 cam_sim_free(acb->psim, /* free_simq */ TRUE);
4330                 arcmsr_mutex_destroy(acb);
4331                 printf("arcmsr%d: xpt_create_path failure!\n", unit);
4332                 return ENXIO;
4333         }
4334         /*
4335         ****************************************************
4336         */
4337         xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4338         csa.ccb_h.func_code = XPT_SASYNC_CB;
4339         csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4340         csa.callback = arcmsr_async;
4341         csa.callback_arg = acb->psim;
4342         xpt_action((union ccb *)&csa);
4343         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4344         /* Create the control device.  */
4345         acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4346
4347 #if __FreeBSD_version < 503000
4348         acb->ioctl_dev->si_drv1 = acb;
4349 #endif
4350 #if __FreeBSD_version > 500005
4351         (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4352 #endif
4353         arcmsr_callout_init(&acb->devmap_callout);
4354         callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4355         return (0);
4356 }
4357
4358 /*
4359 ************************************************************************
4360 ************************************************************************
4361 */
4362 static int arcmsr_probe(device_t dev)
4363 {
4364         u_int32_t id;
4365         static char buf[256];
4366         char x_type[]={"unknown"};
4367         char *type;
4368         int raid6 = 1;
4369
4370         if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4371                 return (ENXIO);
4372         }
4373         switch(id = pci_get_devid(dev)) {
4374         case PCIDevVenIDARC1110:
4375         case PCIDevVenIDARC1200:
4376         case PCIDevVenIDARC1201:
4377         case PCIDevVenIDARC1210:
4378                 raid6 = 0;
4379                 /*FALLTHRU*/
4380         case PCIDevVenIDARC1120:
4381         case PCIDevVenIDARC1130:
4382         case PCIDevVenIDARC1160:
4383         case PCIDevVenIDARC1170:
4384         case PCIDevVenIDARC1220:
4385         case PCIDevVenIDARC1230:
4386         case PCIDevVenIDARC1231:
4387         case PCIDevVenIDARC1260:
4388         case PCIDevVenIDARC1261:
4389         case PCIDevVenIDARC1270:
4390         case PCIDevVenIDARC1280:
4391                 type = "SATA 3G";
4392                 break;
4393         case PCIDevVenIDARC1212:
4394         case PCIDevVenIDARC1222:
4395         case PCIDevVenIDARC1380:
4396         case PCIDevVenIDARC1381:
4397         case PCIDevVenIDARC1680:
4398         case PCIDevVenIDARC1681:
4399                 type = "SAS 3G";
4400                 break;
4401         case PCIDevVenIDARC1880:
4402         case PCIDevVenIDARC1882:
4403         case PCIDevVenIDARC1213:
4404         case PCIDevVenIDARC1223:
4405                 type = "SAS 6G";
4406                 break;
4407         case PCIDevVenIDARC1214:
4408                 type = "SATA 6G";
4409                 break;
4410         default:
4411                 type = x_type;
4412                 raid6 = 0;
4413                 break;
4414         }
4415         if(type == x_type)
4416                 return(ENXIO);
4417         sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n",
4418                 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
4419         device_set_desc_copy(dev, buf);
4420         return (BUS_PROBE_DEFAULT);
4421 }
4422 /*
4423 ************************************************************************
4424 ************************************************************************
4425 */
4426 static int arcmsr_shutdown(device_t dev)
4427 {
4428         u_int32_t  i;
4429         u_int32_t intmask_org;
4430         struct CommandControlBlock *srb;
4431         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4432
4433         /* stop adapter background rebuild */
4434         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4435         /* disable all outbound interrupt */
4436         intmask_org = arcmsr_disable_allintr(acb);
4437         arcmsr_stop_adapter_bgrb(acb);
4438         arcmsr_flush_adapter_cache(acb);
4439         /* abort all outstanding command */
4440         acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4441         acb->acb_flags &= ~ACB_F_IOP_INITED;
4442         if(acb->srboutstandingcount != 0) {
4443                 /*clear and abort all outbound posted Q*/
4444                 arcmsr_done4abort_postqueue(acb);
4445                 /* talk to iop 331 outstanding command aborted*/
4446                 arcmsr_abort_allcmd(acb);
4447                 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4448                         srb = acb->psrb_pool[i];
4449                         if(srb->srb_state == ARCMSR_SRB_START) {
4450                                 srb->srb_state = ARCMSR_SRB_ABORTED;
4451                                 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4452                                 arcmsr_srb_complete(srb, 1);
4453                         }
4454                 }
4455         }
4456         acb->srboutstandingcount = 0;
4457         acb->workingsrb_doneindex = 0;
4458         acb->workingsrb_startindex = 0;
4459         acb->pktRequestCount = 0;
4460         acb->pktReturnCount = 0;
4461         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4462         return (0);
4463 }
4464 /*
4465 ************************************************************************
4466 ************************************************************************
4467 */
4468 static int arcmsr_detach(device_t dev)
4469 {
4470         struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4471         int i;
4472
4473         callout_stop(&acb->devmap_callout);
4474         bus_teardown_intr(dev, acb->irqres, acb->ih);
4475         arcmsr_shutdown(dev);
4476         arcmsr_free_resource(acb);
4477         for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4478                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4479         }
4480         bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4481         ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4482         xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4483         xpt_free_path(acb->ppath);
4484         xpt_bus_deregister(cam_sim_path(acb->psim));
4485         cam_sim_free(acb->psim, TRUE);
4486         ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4487         arcmsr_mutex_destroy(acb);
4488         return (0);
4489 }
4490
4491 #ifdef ARCMSR_DEBUG1
4492 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4493 {
4494         if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4495                 return;
4496         printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4497         printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4498         printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4499         printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4500 }
4501 #endif
4502