2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #ifndef _DEV_ATH_AR5416PHY_H_
20 #define _DEV_ATH_AR5416PHY_H_
22 #include "ar5212/ar5212phy.h"
24 #define AR_BT_COEX_MODE 0x8170
25 #define AR_BT_TIME_EXTEND 0x000000ff
26 #define AR_BT_TIME_EXTEND_S 0
27 #define AR_BT_TXSTATE_EXTEND 0x00000100
28 #define AR_BT_TXSTATE_EXTEND_S 8
29 #define AR_BT_TX_FRAME_EXTEND 0x00000200
30 #define AR_BT_TX_FRAME_EXTEND_S 9
31 #define AR_BT_MODE 0x00000c00
32 #define AR_BT_MODE_S 10
33 #define AR_BT_QUIET 0x00001000
34 #define AR_BT_QUIET_S 12
35 #define AR_BT_QCU_THRESH 0x0001e000
36 #define AR_BT_QCU_THRESH_S 13
37 #define AR_BT_RX_CLEAR_POLARITY 0x00020000
38 #define AR_BT_RX_CLEAR_POLARITY_S 17
39 #define AR_BT_PRIORITY_TIME 0x00fc0000
40 #define AR_BT_PRIORITY_TIME_S 18
41 #define AR_BT_FIRST_SLOT_TIME 0xff000000
42 #define AR_BT_FIRST_SLOT_TIME_S 24
44 #define AR_BT_COEX_WEIGHT 0x8174
45 #define AR_BT_BT_WGHT 0x0000ffff
46 #define AR_BT_BT_WGHT_S 0
47 #define AR_BT_WL_WGHT 0xffff0000
48 #define AR_BT_WL_WGHT_S 16
50 #define AR_BT_COEX_MODE2 0x817c
51 #define AR_BT_BCN_MISS_THRESH 0x000000ff
52 #define AR_BT_BCN_MISS_THRESH_S 0
53 #define AR_BT_BCN_MISS_CNT 0x0000ff00
54 #define AR_BT_BCN_MISS_CNT_S 8
55 #define AR_BT_HOLD_RX_CLEAR 0x00010000
56 #define AR_BT_HOLD_RX_CLEAR_S 16
57 #define AR_BT_DISABLE_BT_ANT 0x00100000
58 #define AR_BT_DISABLE_BT_ANT_S 20
60 #define AR_PHY_SPECTRAL_SCAN 0x9910
61 #define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001
62 #define AR_PHY_SPECTRAL_SCAN_ENA_S 0
63 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
64 #define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1
65 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
66 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
67 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
68 #define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
70 /* Scan count and Short repeat flags are different for Kiwi and Merlin */
71 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000
72 #define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
73 #define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI 0x0FFF0000
74 #define AR_PHY_SPECTRAL_SCAN_COUNT_KIWI_S 16
76 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000
77 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24
78 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI 0x10000000
79 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_KIWI_S 28
82 * Kiwi only, bit 30 is used to set the error type, if set it is 0x5 (HAL_PHYERR_RADAR)
83 * Else it is 38 (new error type)
85 #define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI 0x40000000 /* Spectral Error select bit mask */
86 #define AR_PHY_SPECTRAL_SCAN_PHYERR_MASK_SELECT_KIWI_S 30 /* Spectral Error select bit 30 */
88 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_KIWI 0x20000000 /* Spectral Error select bit mask */
89 #define AR_PHY_SPECTRAL_SCAN_PRIORITY_SELECT_SELECT_KIWI_S 29 /* Spectral Error select bit 30 */
91 /* For AR_PHY_RADAR0 */
92 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
94 #define AR_PHY_RADAR_EXT 0x9940
95 #define AR_PHY_RADAR_EXT_ENA 0x00004000
97 #define AR_PHY_RADAR_1 0x9958
98 #define AR_PHY_RADAR_1_BIN_THRESH_SELECT 0x07000000
99 #define AR_PHY_RADAR_1_BIN_THRESH_SELECT_S 24
100 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
101 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
102 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
103 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
104 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
105 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
106 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
107 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
108 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
109 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
110 #define AR_PHY_RADAR_1_MAXLEN_S 0
112 #define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */
113 #define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */
115 #define RFSILENT_BB 0x00002000 /* shush bb */
116 #define AR_PHY_RESTART 0x9970 /* restart */
117 #define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */
118 #define AR_PHY_RESTART_DIV_GC_S 18
120 /* PLL settling times */
121 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
122 #define HT40_CHANNEL_CENTER_SHIFT 10 /* MHz */
124 #define AR_PHY_RFBUS_REQ 0x997C
125 #define AR_PHY_RFBUS_REQ_EN 0x00000001
127 #define AR_2040_MODE 0x8318
128 #define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca
130 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
131 #define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */
132 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
133 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/
134 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
135 #define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */
136 #define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
137 #define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */
138 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
139 #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
141 #define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */
142 #define AR_PHY_TIMING2_USE_FORCE 0x00001000
143 #define AR_PHY_TIMING2_FORCE_VAL 0x00000fff
145 #define AR_PHY_TIMING_CTRL4_CHAIN(_i) \
146 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
147 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 /* perform calibration */
148 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
149 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */
150 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */
151 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */
152 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */
153 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */
154 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */
156 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
157 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 /* Enable spur filter */
158 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
159 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
161 #define AR_PHY_ADC_SERIAL_CTL 0x9830
162 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
163 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
165 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
166 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
167 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
168 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
170 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
171 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
172 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
173 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
174 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
175 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
176 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
177 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
179 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
180 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
181 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
182 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
184 #define AR_PHY_SEARCH_START_DELAY 0x9918 /* search start delay */
186 #define AR_PHY_EXT_CCA 0x99bc
187 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
188 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
189 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000
190 #define AR_PHY_EXT_MINCCA_PWR_S 23
191 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
192 #define AR_PHY_EXT_CCA_THRESH62_S 16
194 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
195 #define AR9280_PHY_EXT_MINCCA_PWR_S 16
197 #define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */
198 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
199 #define AR_PHY_HALFGI_DSC_MAN_S 4
200 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F
201 #define AR_PHY_HALFGI_DSC_EXP_S 0
203 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
205 #define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec
206 #define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
208 #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */
209 #define AR_PHY_REFCLKDLY 0x99f4
210 #define AR_PHY_REFCLKPD 0x99f8
212 #define AR_PHY_CALMODE 0x99f0
213 /* Calibration Types */
214 #define AR_PHY_CALMODE_IQ 0x00000000
215 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
216 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
217 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
218 /* Calibration results */
219 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
220 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
221 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
222 /* This is AR9130 and later */
223 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
226 * AR5416 still uses AR_PHY(263) for current RSSI;
227 * AR9130 and later uses AR_PHY(271).
229 #define AR9130_PHY_CURRENT_RSSI 0x9c3c /* rssi of current frame rx'd */
231 #define AR_PHY_CCA 0x9864
232 #define AR_PHY_MINCCA_PWR 0x0FF80000
233 #define AR_PHY_MINCCA_PWR_S 19
234 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
235 #define AR9280_PHY_MINCCA_PWR_S 20
236 #define AR9280_PHY_CCA_THRESH62 0x000FF000
237 #define AR9280_PHY_CCA_THRESH62_S 12
239 #define AR_PHY_CH1_CCA 0xa864
240 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
241 #define AR_PHY_CH1_MINCCA_PWR_S 19
242 #define AR_PHY_CCA_THRESH62 0x0007F000
243 #define AR_PHY_CCA_THRESH62_S 12
244 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
245 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
247 #define AR_PHY_CH2_CCA 0xb864
248 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
249 #define AR_PHY_CH2_MINCCA_PWR_S 19
251 #define AR_PHY_CH1_EXT_CCA 0xa9bc
252 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
253 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
254 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
255 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
257 #define AR_PHY_CH2_EXT_CCA 0xb9bc
258 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
259 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
261 #define AR_PHY_RX_CHAINMASK 0x99a4
263 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
264 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
265 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
266 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
268 #define AR_PHY_EXT_CCA0 0x99b8
269 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
270 #define AR_PHY_EXT_CCA0_THRESH62_S 0
272 #define AR_PHY_CH1_EXT_CCA 0xa9bc
273 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
274 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
276 #define AR_PHY_CH2_EXT_CCA 0xb9bc
277 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
278 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
279 #define AR_PHY_ANALOG_SWAP 0xa268
280 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
281 #define AR_PHY_CAL_CHAINMASK 0xa39c
283 #define AR_PHY_SWITCH_CHAIN_0 0x9960
284 #define AR_PHY_SWITCH_COM 0x9964
286 #define AR_PHY_RF_CTL2 0x9824
287 #define AR_PHY_TX_FRAME_TO_DATA_START 0x000000FF
288 #define AR_PHY_TX_FRAME_TO_DATA_START_S 0
289 #define AR_PHY_TX_FRAME_TO_PA_ON 0x0000FF00
290 #define AR_PHY_TX_FRAME_TO_PA_ON_S 8
292 #define AR_PHY_RF_CTL3 0x9828
293 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
294 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16
296 #define AR_PHY_RF_CTL4 0x9834
297 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
298 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
299 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
300 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
301 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
302 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
303 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
304 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
306 #define AR_PHY_SYNTH_CONTROL 0x9874
308 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C
309 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
311 #define AR_PHY_POWER_TX_SUB 0xA3C8
312 #define AR_PHY_POWER_TX_RATE5 0xA38C
313 #define AR_PHY_POWER_TX_RATE6 0xA390
314 #define AR_PHY_POWER_TX_RATE7 0xA3CC
315 #define AR_PHY_POWER_TX_RATE8 0xA3D0
316 #define AR_PHY_POWER_TX_RATE9 0xA3D4
318 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
319 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16
320 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
321 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18
322 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
323 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20
325 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
326 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
328 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
329 #define AR_PHY_MASK2_M_31_45 0xa3a4
330 #define AR_PHY_MASK2_M_16_30 0xa3a8
331 #define AR_PHY_MASK2_M_00_15 0xa3ac
332 #define AR_PHY_MASK2_P_15_01 0xa3b8
333 #define AR_PHY_MASK2_P_30_16 0xa3bc
334 #define AR_PHY_MASK2_P_45_31 0xa3c0
335 #define AR_PHY_MASK2_P_61_45 0xa3c4
337 #define AR_PHY_SPUR_REG 0x994c
338 #define AR_PHY_SFCORR_EXT 0x99c0
339 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
340 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
341 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
342 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
343 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
344 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
345 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
346 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
347 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
349 /* enable vit puncture per rate, 8 bits, lsb is low rate */
350 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
351 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
353 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
354 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) /* use mask1 or mask2, one per rate */
355 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
356 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
357 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
358 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
360 #define AR_PHY_PILOT_MASK_01_30 0xa3b0
361 #define AR_PHY_PILOT_MASK_31_60 0xa3b4
363 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4
364 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8
366 #define AR_PHY_CL_CAL_CTL 0xA358 /* carrier leak cal control */
367 #define AR_PHY_CL_CAL_ENABLE 0x00000002
368 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
370 /* empirically determined "good" CCA value ranges from atheros */
371 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90
372 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100
373 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100
374 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110
375 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80
376 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90
378 /* ar9280 specific? */
379 #define AR_PHY_XPA_CFG 0xA3D8
380 #define AR_PHY_FORCE_XPA_CFG 0x000000001
381 #define AR_PHY_FORCE_XPA_CFG_S 0
383 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
384 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
386 #define AR_PHY_TX_PWRCTRL9 0xa27C
387 #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
388 #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
389 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
390 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
392 #define AR_PHY_MODE_ASYNCFIFO 0x80 /* Enable async fifo */
394 #endif /* _DEV_ATH_AR5416PHY_H_ */