2 * Copyright (c) 2014 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
35 #include <sys/param.h>
36 #include <sys/eventhandler.h>
38 #include <sys/types.h>
40 #include <sys/selinfo.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <machine/bus.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <net/if_var.h>
48 #include <net/if_clone.h>
49 #include <net/if_types.h>
50 #include <net/netmap.h>
51 #include <dev/netmap/netmap_kern.h>
53 #include "common/common.h"
54 #include "common/t4_regs.h"
55 #include "common/t4_regs_values.h"
57 extern int fl_pad; /* XXXNM */
58 extern int spg_len; /* XXXNM */
59 extern int fl_pktshift; /* XXXNM */
61 SYSCTL_NODE(_hw, OID_AUTO, cxgbe, CTLFLAG_RD, 0, "cxgbe netmap parameters");
64 * 0 = normal netmap rx
66 * 2 = supermassive black hole (buffer packing enabled)
69 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_black_hole, CTLFLAG_RDTUN, &black_hole, 0,
70 "Sink incoming packets.");
73 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_rx_ndesc, CTLFLAG_RWTUN,
74 &rx_ndesc, 0, "# of rx descriptors after which the hw cidx is updated.");
76 int holdoff_tmr_idx = 2;
77 SYSCTL_INT(_hw_cxgbe, OID_AUTO, nm_holdoff_tmr_idx, CTLFLAG_RWTUN,
78 &holdoff_tmr_idx, 0, "Holdoff timer index for netmap rx queues.");
80 /* netmap ifnet routines */
81 static void cxgbe_nm_init(void *);
82 static int cxgbe_nm_ioctl(struct ifnet *, unsigned long, caddr_t);
83 static int cxgbe_nm_transmit(struct ifnet *, struct mbuf *);
84 static void cxgbe_nm_qflush(struct ifnet *);
86 static int cxgbe_nm_init_synchronized(struct port_info *);
87 static int cxgbe_nm_uninit_synchronized(struct port_info *);
90 cxgbe_nm_init(void *arg)
92 struct port_info *pi = arg;
93 struct adapter *sc = pi->adapter;
95 if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nminit") != 0)
97 cxgbe_nm_init_synchronized(pi);
98 end_synchronized_op(sc, 0);
104 cxgbe_nm_init_synchronized(struct port_info *pi)
106 struct adapter *sc = pi->adapter;
107 struct ifnet *ifp = pi->nm_ifp;
110 ASSERT_SYNCHRONIZED_OP(sc);
112 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
113 return (0); /* already running */
115 if (!(sc->flags & FULL_INIT_DONE) &&
116 ((rc = adapter_full_init(sc)) != 0))
117 return (rc); /* error message displayed already */
119 if (!(pi->flags & PORT_INIT_DONE) &&
120 ((rc = port_full_init(pi)) != 0))
121 return (rc); /* error message displayed already */
123 rc = update_mac_settings(ifp, XGMAC_ALL);
125 return (rc); /* error message displayed already */
127 ifp->if_drv_flags |= IFF_DRV_RUNNING;
133 cxgbe_nm_uninit_synchronized(struct port_info *pi)
136 struct adapter *sc = pi->adapter;
138 struct ifnet *ifp = pi->nm_ifp;
140 ASSERT_SYNCHRONIZED_OP(sc);
142 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
148 cxgbe_nm_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
150 int rc = 0, mtu, flags;
151 struct port_info *pi = ifp->if_softc;
152 struct adapter *sc = pi->adapter;
153 struct ifreq *ifr = (struct ifreq *)data;
156 MPASS(pi->nm_ifp == ifp);
161 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
164 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmtu");
168 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
169 rc = update_mac_settings(ifp, XGMAC_MTU);
170 end_synchronized_op(sc, 0);
174 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nflg");
178 if (ifp->if_flags & IFF_UP) {
179 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
180 flags = pi->nmif_flags;
181 if ((ifp->if_flags ^ flags) &
182 (IFF_PROMISC | IFF_ALLMULTI)) {
183 rc = update_mac_settings(ifp,
184 XGMAC_PROMISC | XGMAC_ALLMULTI);
187 rc = cxgbe_nm_init_synchronized(pi);
188 pi->nmif_flags = ifp->if_flags;
189 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
190 rc = cxgbe_nm_uninit_synchronized(pi);
191 end_synchronized_op(sc, 0);
195 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
196 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4nmulti");
199 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
200 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
201 end_synchronized_op(sc, LOCK_HELD);
205 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
206 if (mask & IFCAP_TXCSUM) {
207 ifp->if_capenable ^= IFCAP_TXCSUM;
208 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
210 if (mask & IFCAP_TXCSUM_IPV6) {
211 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
212 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
214 if (mask & IFCAP_RXCSUM)
215 ifp->if_capenable ^= IFCAP_RXCSUM;
216 if (mask & IFCAP_RXCSUM_IPV6)
217 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
222 ifmedia_ioctl(ifp, ifr, &pi->nm_media, cmd);
226 rc = ether_ioctl(ifp, cmd, data);
233 cxgbe_nm_transmit(struct ifnet *ifp, struct mbuf *m)
241 cxgbe_nm_qflush(struct ifnet *ifp)
248 alloc_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int cong)
252 struct adapter *sc = pi->adapter;
253 struct netmap_adapter *na = NA(pi->nm_ifp);
257 MPASS(nm_rxq->iq_desc != NULL);
258 MPASS(nm_rxq->fl_desc != NULL);
260 bzero(nm_rxq->iq_desc, pi->qsize_rxq * IQ_ESIZE);
261 bzero(nm_rxq->fl_desc, na->num_rx_desc * EQ_ESIZE + spg_len);
263 bzero(&c, sizeof(c));
264 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
265 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
267 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
269 if (pi->flags & INTR_NM_RXQ) {
270 KASSERT(nm_rxq->intr_idx < sc->intr_count,
271 ("%s: invalid direct intr_idx %d", __func__,
273 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx);
275 CXGBE_UNIMPLEMENTED(__func__); /* XXXNM: needs review */
276 v = V_FW_IQ_CMD_IQANDSTINDEX(nm_rxq->intr_idx) |
279 c.type_to_iqandstindex = htobe32(v |
280 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
281 V_FW_IQ_CMD_VIID(pi->nm_viid) |
282 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
283 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
284 F_FW_IQ_CMD_IQGTSMODE |
285 V_FW_IQ_CMD_IQINTCNTTHRESH(0) |
286 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
287 c.iqsize = htobe16(pi->qsize_rxq);
288 c.iqaddr = htobe64(nm_rxq->iq_ba);
290 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN |
291 V_FW_IQ_CMD_FL0CNGCHMAP(cong) | F_FW_IQ_CMD_FL0CONGCIF |
292 F_FW_IQ_CMD_FL0CONGEN);
294 c.iqns_to_fl0congen |=
295 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
296 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
297 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
298 (black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
299 c.fl0dcaen_to_fl0cidxfthresh =
300 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
301 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
302 c.fl0size = htobe16(na->num_rx_desc / 8 + spg_len / EQ_ESIZE);
303 c.fl0addr = htobe64(nm_rxq->fl_ba);
305 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
307 device_printf(sc->dev,
308 "failed to create netmap ingress queue: %d\n", rc);
313 MPASS(nm_rxq->iq_sidx == pi->qsize_rxq - spg_len / IQ_ESIZE);
314 nm_rxq->iq_gen = F_RSPD_GEN;
315 nm_rxq->iq_cntxt_id = be16toh(c.iqid);
316 nm_rxq->iq_abs_id = be16toh(c.physiqid);
317 cntxt_id = nm_rxq->iq_cntxt_id - sc->sge.iq_start;
318 if (cntxt_id >= sc->sge.niq) {
319 panic ("%s: nm_rxq->iq_cntxt_id (%d) more than the max (%d)",
320 __func__, cntxt_id, sc->sge.niq - 1);
322 sc->sge.iqmap[cntxt_id] = (void *)nm_rxq;
324 nm_rxq->fl_cntxt_id = be16toh(c.fl0id);
325 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
326 MPASS(nm_rxq->fl_sidx == na->num_rx_desc);
327 cntxt_id = nm_rxq->fl_cntxt_id - sc->sge.eq_start;
328 if (cntxt_id >= sc->sge.neq) {
329 panic("%s: nm_rxq->fl_cntxt_id (%d) more than the max (%d)",
330 __func__, cntxt_id, sc->sge.neq - 1);
332 sc->sge.eqmap[cntxt_id] = (void *)nm_rxq;
334 nm_rxq->fl_db_val = F_DBPRIO | V_QID(nm_rxq->fl_cntxt_id) | V_PIDX(0);
336 nm_rxq->fl_db_val |= F_DBTYPE;
338 if (is_t5(sc) && cong >= 0) {
341 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
342 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
343 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
344 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
345 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
346 V_FW_PARAMS_PARAM_YZ(nm_rxq->iq_cntxt_id);
351 for (i = 0; i < 4; i++) {
353 val |= 1 << (i << 2);
357 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
359 /* report error but carry on */
360 device_printf(sc->dev,
361 "failed to set congestion manager context for "
362 "ingress queue %d: %d\n", nm_rxq->iq_cntxt_id, rc);
366 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
367 V_INGRESSQID(nm_rxq->iq_cntxt_id) |
368 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));
374 free_nm_rxq_hwq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
376 struct adapter *sc = pi->adapter;
379 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
380 nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, 0xffff);
382 device_printf(sc->dev, "%s: failed for iq %d, fl %d: %d\n",
383 __func__, nm_rxq->iq_cntxt_id, nm_rxq->fl_cntxt_id, rc);
388 alloc_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
392 struct adapter *sc = pi->adapter;
393 struct netmap_adapter *na = NA(pi->nm_ifp);
394 struct fw_eq_eth_cmd c;
397 MPASS(nm_txq->desc != NULL);
399 len = na->num_tx_desc * EQ_ESIZE + spg_len;
400 bzero(nm_txq->desc, len);
402 bzero(&c, sizeof(c));
403 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
404 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
405 V_FW_EQ_ETH_CMD_VFN(0));
406 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
407 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
408 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUEQE |
409 V_FW_EQ_ETH_CMD_VIID(pi->nm_viid));
411 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
412 V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
413 V_FW_EQ_ETH_CMD_IQID(sc->sge.nm_rxq[nm_txq->iqidx].iq_cntxt_id));
414 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
415 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
416 V_FW_EQ_ETH_CMD_EQSIZE(len / EQ_ESIZE));
417 c.eqaddr = htobe64(nm_txq->ba);
419 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
421 device_printf(pi->dev,
422 "failed to create netmap egress queue: %d\n", rc);
426 nm_txq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
427 cntxt_id = nm_txq->cntxt_id - sc->sge.eq_start;
428 if (cntxt_id >= sc->sge.neq)
429 panic("%s: nm_txq->cntxt_id (%d) more than the max (%d)", __func__,
430 cntxt_id, sc->sge.neq - 1);
431 sc->sge.eqmap[cntxt_id] = (void *)nm_txq;
433 nm_txq->pidx = nm_txq->cidx = 0;
434 MPASS(nm_txq->sidx == na->num_tx_desc);
435 nm_txq->equiqidx = nm_txq->equeqidx = nm_txq->dbidx = 0;
437 nm_txq->doorbells = sc->doorbells;
438 if (isset(&nm_txq->doorbells, DOORBELL_UDB) ||
439 isset(&nm_txq->doorbells, DOORBELL_UDBWC) ||
440 isset(&nm_txq->doorbells, DOORBELL_WCWR)) {
441 uint32_t s_qpp = sc->sge.eq_s_qpp;
442 uint32_t mask = (1 << s_qpp) - 1;
443 volatile uint8_t *udb;
445 udb = sc->udbs_base + UDBS_DB_OFFSET;
446 udb += (nm_txq->cntxt_id >> s_qpp) << PAGE_SHIFT;
447 nm_txq->udb_qid = nm_txq->cntxt_id & mask;
448 if (nm_txq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
449 clrbit(&nm_txq->doorbells, DOORBELL_WCWR);
451 udb += nm_txq->udb_qid << UDBS_SEG_SHIFT;
454 nm_txq->udb = (volatile void *)udb;
461 free_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
463 struct adapter *sc = pi->adapter;
466 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, nm_txq->cntxt_id);
468 device_printf(sc->dev, "%s: failed for eq %d: %d\n", __func__,
469 nm_txq->cntxt_id, rc);
474 cxgbe_netmap_on(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
475 struct netmap_adapter *na)
477 struct netmap_slot *slot;
478 struct sge_nm_rxq *nm_rxq;
479 struct sge_nm_txq *nm_txq;
481 struct hw_buf_info *hwb;
484 ASSERT_SYNCHRONIZED_OP(sc);
486 if ((pi->flags & PORT_INIT_DONE) == 0 ||
487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
490 hwb = &sc->sge.hw_buf_info[0];
491 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
492 if (hwb->size == NETMAP_BUF_SIZE(na))
495 if (i >= SGE_FLBUF_SIZES) {
496 if_printf(ifp, "no hwidx for netmap buffer size %d.\n",
497 NETMAP_BUF_SIZE(na));
502 /* Must set caps before calling netmap_reset */
503 nm_set_native_flags(na);
505 for_each_nm_rxq(pi, i, nm_rxq) {
506 alloc_nm_rxq_hwq(pi, nm_rxq, tnl_cong(pi));
507 nm_rxq->fl_hwidx = hwidx;
508 slot = netmap_reset(na, NR_RX, i, 0);
509 MPASS(slot != NULL); /* XXXNM: error check, not assert */
511 /* We deal with 8 bufs at a time */
512 MPASS((na->num_rx_desc & 7) == 0);
513 MPASS(na->num_rx_desc == nm_rxq->fl_sidx);
514 for (j = 0; j < nm_rxq->fl_sidx; j++) {
517 PNMB(na, &slot[j], &ba);
519 nm_rxq->fl_desc[j] = htobe64(ba | hwidx);
521 j = nm_rxq->fl_pidx = nm_rxq->fl_sidx - 8;
523 j /= 8; /* driver pidx to hardware pidx */
525 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
526 nm_rxq->fl_db_val | V_PIDX(j));
529 for_each_nm_txq(pi, i, nm_txq) {
530 alloc_nm_txq_hwq(pi, nm_txq);
531 slot = netmap_reset(na, NR_TX, i, 0);
532 MPASS(slot != NULL); /* XXXNM: error check, not assert */
535 rss = malloc(pi->nm_rss_size * sizeof (*rss), M_CXGBE, M_ZERO |
537 for (i = 0; i < pi->nm_rss_size;) {
538 for_each_nm_rxq(pi, j, nm_rxq) {
539 rss[i++] = nm_rxq->iq_abs_id;
540 if (i == pi->nm_rss_size)
544 rc = -t4_config_rss_range(sc, sc->mbox, pi->nm_viid, 0, pi->nm_rss_size,
545 rss, pi->nm_rss_size);
547 if_printf(ifp, "netmap rss_config failed: %d\n", rc);
550 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, true, true);
552 if_printf(ifp, "netmap enable_vi failed: %d\n", rc);
558 cxgbe_netmap_off(struct adapter *sc, struct port_info *pi, struct ifnet *ifp,
559 struct netmap_adapter *na)
562 struct sge_nm_txq *nm_txq;
563 struct sge_nm_rxq *nm_rxq;
565 ASSERT_SYNCHRONIZED_OP(sc);
567 rc = -t4_enable_vi(sc, sc->mbox, pi->nm_viid, false, false);
569 if_printf(ifp, "netmap disable_vi failed: %d\n", rc);
570 nm_clear_native_flags(na);
572 for_each_nm_txq(pi, i, nm_txq) {
573 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
575 /* Wait for hw pidx to catch up ... */
576 while (be16toh(nm_txq->pidx) != spg->pidx)
579 /* ... and then for the cidx. */
580 while (spg->pidx != spg->cidx)
583 free_nm_txq_hwq(pi, nm_txq);
585 for_each_nm_rxq(pi, i, nm_rxq) {
586 free_nm_rxq_hwq(pi, nm_rxq);
593 cxgbe_netmap_reg(struct netmap_adapter *na, int on)
595 struct ifnet *ifp = na->ifp;
596 struct port_info *pi = ifp->if_softc;
597 struct adapter *sc = pi->adapter;
600 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4nmreg");
604 rc = cxgbe_netmap_on(sc, pi, ifp, na);
606 rc = cxgbe_netmap_off(sc, pi, ifp, na);
607 end_synchronized_op(sc, 0);
612 /* How many packets can a single type1 WR carry in n descriptors */
614 ndesc_to_npkt(const int n)
617 MPASS(n > 0 && n <= SGE_MAX_WR_NDESC);
621 #define MAX_NPKT_IN_TYPE1_WR (ndesc_to_npkt(SGE_MAX_WR_NDESC))
623 /* Space (in descriptors) needed for a type1 WR that carries n packets */
625 npkt_to_ndesc(const int n)
628 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
630 return ((n + 2) / 2);
633 /* Space (in 16B units) needed for a type1 WR that carries n packets */
635 npkt_to_len16(const int n)
638 MPASS(n > 0 && n <= MAX_NPKT_IN_TYPE1_WR);
643 #define NMIDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->sidx)
646 ring_nm_txq_db(struct adapter *sc, struct sge_nm_txq *nm_txq)
649 u_int db = nm_txq->doorbells;
651 MPASS(nm_txq->pidx != nm_txq->dbidx);
653 n = NMIDXDIFF(nm_txq, dbidx);
655 clrbit(&db, DOORBELL_WCWR);
658 switch (ffs(db) - 1) {
660 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
663 case DOORBELL_WCWR: {
664 volatile uint64_t *dst, *src;
667 * Queues whose 128B doorbell segment fits in the page do not
668 * use relative qid (udb_qid is always 0). Only queues with
669 * doorbell segments can do WCWR.
671 KASSERT(nm_txq->udb_qid == 0 && n == 1,
672 ("%s: inappropriate doorbell (0x%x, %d, %d) for nm_txq %p",
673 __func__, nm_txq->doorbells, n, nm_txq->pidx, nm_txq));
675 dst = (volatile void *)((uintptr_t)nm_txq->udb +
676 UDBS_WR_OFFSET - UDBS_DB_OFFSET);
677 src = (void *)&nm_txq->desc[nm_txq->dbidx];
678 while (src != (void *)&nm_txq->desc[nm_txq->dbidx + 1])
685 *nm_txq->udb = htole32(V_QID(nm_txq->udb_qid) | V_PIDX(n));
690 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
691 V_QID(nm_txq->cntxt_id) | V_PIDX(n));
694 nm_txq->dbidx = nm_txq->pidx;
697 int lazy_tx_credit_flush = 1;
700 * Write work requests to send 'npkt' frames and ring the doorbell to send them
701 * on their way. No need to check for wraparound.
704 cxgbe_nm_tx(struct adapter *sc, struct sge_nm_txq *nm_txq,
705 struct netmap_kring *kring, int npkt, int npkt_remaining, int txcsum)
707 struct netmap_ring *ring = kring->ring;
708 struct netmap_slot *slot;
709 const u_int lim = kring->nkr_num_slots - 1;
710 struct fw_eth_tx_pkts_wr *wr = (void *)&nm_txq->desc[nm_txq->pidx];
713 struct cpl_tx_pkt_core *cpl;
714 struct ulptx_sgl *usgl;
718 n = min(npkt, MAX_NPKT_IN_TYPE1_WR);
721 wr = (void *)&nm_txq->desc[nm_txq->pidx];
722 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
723 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(npkt_to_len16(n)));
727 cpl = (void *)(wr + 1);
729 for (i = 0; i < n; i++) {
730 slot = &ring->slot[kring->nr_hwcur];
731 PNMB(kring->na, slot, &ba);
734 cpl->ctrl0 = nm_txq->cpl_ctrl0;
736 cpl->len = htobe16(slot->len);
738 * netmap(4) says "netmap does not use features such as
739 * checksum offloading, TCP segmentation offloading,
740 * encryption, VLAN encapsulation/decapsulation, etc."
742 * So the ncxl interfaces have tx hardware checksumming
743 * disabled by default. But you can override netmap by
744 * enabling IFCAP_TXCSUM on the interface manully.
746 cpl->ctrl1 = txcsum ? 0 :
747 htobe64(F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
749 usgl = (void *)(cpl + 1);
750 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
752 usgl->len0 = htobe32(slot->len);
753 usgl->addr0 = htobe64(ba);
755 slot->flags &= ~(NS_REPORT | NS_BUF_CHANGED);
756 cpl = (void *)(usgl + 1);
757 MPASS(slot->len + len <= UINT16_MAX);
759 kring->nr_hwcur = nm_next(kring->nr_hwcur, lim);
761 wr->plen = htobe16(len);
764 nm_txq->pidx += npkt_to_ndesc(n);
765 MPASS(nm_txq->pidx <= nm_txq->sidx);
766 if (__predict_false(nm_txq->pidx == nm_txq->sidx)) {
768 * This routine doesn't know how to write WRs that wrap
769 * around. Make sure it wasn't asked to.
775 if (npkt == 0 && npkt_remaining == 0) {
777 if (lazy_tx_credit_flush == 0) {
778 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
780 nm_txq->equeqidx = nm_txq->pidx;
781 nm_txq->equiqidx = nm_txq->pidx;
783 ring_nm_txq_db(sc, nm_txq);
787 if (NMIDXDIFF(nm_txq, equiqidx) >= nm_txq->sidx / 2) {
788 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ |
790 nm_txq->equeqidx = nm_txq->pidx;
791 nm_txq->equiqidx = nm_txq->pidx;
792 } else if (NMIDXDIFF(nm_txq, equeqidx) >= 64) {
793 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
794 nm_txq->equeqidx = nm_txq->pidx;
796 if (NMIDXDIFF(nm_txq, dbidx) >= 2 * SGE_MAX_WR_NDESC)
797 ring_nm_txq_db(sc, nm_txq);
800 /* Will get called again. */
801 MPASS(npkt_remaining);
804 /* How many contiguous free descriptors starting at pidx */
806 contiguous_ndesc_available(struct sge_nm_txq *nm_txq)
809 if (nm_txq->cidx > nm_txq->pidx)
810 return (nm_txq->cidx - nm_txq->pidx - 1);
811 else if (nm_txq->cidx > 0)
812 return (nm_txq->sidx - nm_txq->pidx);
814 return (nm_txq->sidx - nm_txq->pidx - 1);
818 reclaim_nm_tx_desc(struct sge_nm_txq *nm_txq)
820 struct sge_qstat *spg = (void *)&nm_txq->desc[nm_txq->sidx];
821 uint16_t hw_cidx = spg->cidx; /* snapshot */
822 struct fw_eth_tx_pkts_wr *wr;
825 hw_cidx = be16toh(hw_cidx);
827 while (nm_txq->cidx != hw_cidx) {
828 wr = (void *)&nm_txq->desc[nm_txq->cidx];
830 MPASS(wr->op_pkd == htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR)));
831 MPASS(wr->type == 1);
832 MPASS(wr->npkt > 0 && wr->npkt <= MAX_NPKT_IN_TYPE1_WR);
835 nm_txq->cidx += npkt_to_ndesc(wr->npkt);
838 * We never sent a WR that wrapped around so the credits coming
839 * back, WR by WR, should never cause the cidx to wrap around
842 MPASS(nm_txq->cidx <= nm_txq->sidx);
843 if (__predict_false(nm_txq->cidx == nm_txq->sidx))
851 cxgbe_netmap_txsync(struct netmap_kring *kring, int flags)
853 struct netmap_adapter *na = kring->na;
854 struct ifnet *ifp = na->ifp;
855 struct port_info *pi = ifp->if_softc;
856 struct adapter *sc = pi->adapter;
857 struct sge_nm_txq *nm_txq = &sc->sge.nm_txq[pi->first_nm_txq + kring->ring_id];
858 const u_int head = kring->rhead;
860 int n, d, npkt_remaining, ndesc_remaining, txcsum;
863 * Tx was at kring->nr_hwcur last time around and now we need to advance
864 * to kring->rhead. Note that the driver's pidx moves independent of
865 * netmap's kring->nr_hwcur (pidx counts descriptors and the relation
866 * between descriptors and frames isn't 1:1).
869 npkt_remaining = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
870 kring->nkr_num_slots - kring->nr_hwcur + head;
871 txcsum = ifp->if_capenable & (IFCAP_TXCSUM | IFCAP_TXCSUM_IPV6);
872 while (npkt_remaining) {
873 reclaimed += reclaim_nm_tx_desc(nm_txq);
874 ndesc_remaining = contiguous_ndesc_available(nm_txq);
875 /* Can't run out of descriptors with packets still remaining */
876 MPASS(ndesc_remaining > 0);
878 /* # of desc needed to tx all remaining packets */
879 d = (npkt_remaining / MAX_NPKT_IN_TYPE1_WR) * SGE_MAX_WR_NDESC;
880 if (npkt_remaining % MAX_NPKT_IN_TYPE1_WR)
881 d += npkt_to_ndesc(npkt_remaining % MAX_NPKT_IN_TYPE1_WR);
883 if (d <= ndesc_remaining)
886 /* Can't send all, calculate how many can be sent */
887 n = (ndesc_remaining / SGE_MAX_WR_NDESC) *
888 MAX_NPKT_IN_TYPE1_WR;
889 if (ndesc_remaining % SGE_MAX_WR_NDESC)
890 n += ndesc_to_npkt(ndesc_remaining % SGE_MAX_WR_NDESC);
893 /* Send n packets and update nm_txq->pidx and kring->nr_hwcur */
895 cxgbe_nm_tx(sc, nm_txq, kring, n, npkt_remaining, txcsum);
897 MPASS(npkt_remaining == 0);
898 MPASS(kring->nr_hwcur == head);
899 MPASS(nm_txq->dbidx == nm_txq->pidx);
902 * Second part: reclaim buffers for completed transmissions.
904 if (reclaimed || flags & NAF_FORCE_RECLAIM || nm_kr_txempty(kring)) {
905 reclaimed += reclaim_nm_tx_desc(nm_txq);
906 kring->nr_hwtail += reclaimed;
907 if (kring->nr_hwtail >= kring->nkr_num_slots)
908 kring->nr_hwtail -= kring->nkr_num_slots;
911 nm_txsync_finalize(kring);
917 cxgbe_netmap_rxsync(struct netmap_kring *kring, int flags)
919 struct netmap_adapter *na = kring->na;
920 struct netmap_ring *ring = kring->ring;
921 struct ifnet *ifp = na->ifp;
922 struct port_info *pi = ifp->if_softc;
923 struct adapter *sc = pi->adapter;
924 struct sge_nm_rxq *nm_rxq = &sc->sge.nm_rxq[pi->first_nm_rxq + kring->ring_id];
925 u_int const head = nm_rxsync_prologue(kring);
927 int force_update = (flags & NAF_FORCE_READ) || kring->nr_kflags & NKR_PENDINTR;
930 return (0); /* No updates ever. */
932 if (netmap_no_pendintr || force_update) {
933 kring->nr_hwtail = atomic_load_acq_32(&nm_rxq->fl_cidx);
934 kring->nr_kflags &= ~NKR_PENDINTR;
937 /* Userspace done with buffers from kring->nr_hwcur to head */
938 n = head >= kring->nr_hwcur ? head - kring->nr_hwcur :
939 kring->nkr_num_slots - kring->nr_hwcur + head;
942 u_int fl_pidx = nm_rxq->fl_pidx;
943 struct netmap_slot *slot = &ring->slot[fl_pidx];
945 int i, dbinc = 0, hwidx = nm_rxq->fl_hwidx;
948 * We always deal with 8 buffers at a time. We must have
949 * stopped at an 8B boundary (fl_pidx) last time around and we
950 * must have a multiple of 8B buffers to give to the freelist.
952 MPASS((fl_pidx & 7) == 0);
955 IDXINCR(kring->nr_hwcur, n, kring->nkr_num_slots);
956 IDXINCR(nm_rxq->fl_pidx, n, nm_rxq->fl_sidx);
959 for (i = 0; i < 8; i++, fl_pidx++, slot++) {
962 nm_rxq->fl_desc[fl_pidx] = htobe64(ba | hwidx);
963 slot->flags &= ~NS_BUF_CHANGED;
964 MPASS(fl_pidx <= nm_rxq->fl_sidx);
967 if (fl_pidx == nm_rxq->fl_sidx) {
969 slot = &ring->slot[0];
971 if (++dbinc == 8 && n >= 32) {
973 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
974 nm_rxq->fl_db_val | V_PIDX(dbinc));
978 MPASS(nm_rxq->fl_pidx == fl_pidx);
982 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
983 nm_rxq->fl_db_val | V_PIDX(dbinc));
987 nm_rxsync_finalize(kring);
993 * Create an ifnet solely for netmap use and register it with the kernel.
996 create_netmap_ifnet(struct port_info *pi)
998 struct adapter *sc = pi->adapter;
999 struct netmap_adapter na;
1001 device_t dev = pi->dev;
1002 uint8_t mac[ETHER_ADDR_LEN];
1005 if (pi->nnmtxq <= 0 || pi->nnmrxq <= 0)
1007 MPASS(pi->nm_ifp == NULL);
1010 * Allocate a virtual interface exclusively for netmap use. Give it the
1011 * MAC address normally reserved for use by a TOE interface. (The TOE
1012 * driver on FreeBSD doesn't use it).
1014 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1, &mac[0],
1015 &pi->nm_rss_size, FW_VI_FUNC_OFLD, 0);
1017 device_printf(dev, "unable to allocate netmap virtual "
1018 "interface for port %d: %d\n", pi->port_id, -rc);
1022 pi->nm_xact_addr_filt = -1;
1024 ifp = if_alloc(IFT_ETHER);
1026 device_printf(dev, "Cannot allocate netmap ifnet\n");
1032 if_initname(ifp, is_t4(pi->adapter) ? "ncxgbe" : "ncxl",
1033 device_get_unit(dev));
1034 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1036 ifp->if_init = cxgbe_nm_init;
1037 ifp->if_ioctl = cxgbe_nm_ioctl;
1038 ifp->if_transmit = cxgbe_nm_transmit;
1039 ifp->if_qflush = cxgbe_nm_qflush;
1042 * netmap(4) says "netmap does not use features such as checksum
1043 * offloading, TCP segmentation offloading, encryption, VLAN
1044 * encapsulation/decapsulation, etc."
1046 * By default we comply with the statement above. But we do declare the
1047 * ifnet capable of L3/L4 checksumming so that a user can override
1048 * netmap and have the hardware do the L3/L4 checksums.
1050 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_JUMBO_MTU |
1052 ifp->if_capenable = 0;
1053 ifp->if_hwassist = 0;
1055 /* nm_media has already been setup by the caller */
1057 ether_ifattach(ifp, mac);
1060 * Register with netmap in the kernel.
1062 bzero(&na, sizeof(na));
1064 na.ifp = pi->nm_ifp;
1065 na.na_flags = NAF_BDG_MAYSLEEP;
1067 /* Netmap doesn't know about the space reserved for the status page. */
1068 na.num_tx_desc = pi->qsize_txq - spg_len / EQ_ESIZE;
1071 * The freelist's cidx/pidx drives netmap's rx cidx/pidx. So
1072 * num_rx_desc is based on the number of buffers that can be held in the
1073 * freelist, and not the number of entries in the iq. (These two are
1074 * not exactly the same due to the space taken up by the status page).
1076 na.num_rx_desc = (pi->qsize_rxq / 8) * 8;
1077 na.nm_txsync = cxgbe_netmap_txsync;
1078 na.nm_rxsync = cxgbe_netmap_rxsync;
1079 na.nm_register = cxgbe_netmap_reg;
1080 na.num_tx_rings = pi->nnmtxq;
1081 na.num_rx_rings = pi->nnmrxq;
1082 netmap_attach(&na); /* This adds IFCAP_NETMAP to if_capabilities */
1088 destroy_netmap_ifnet(struct port_info *pi)
1090 struct adapter *sc = pi->adapter;
1092 if (pi->nm_ifp == NULL)
1095 netmap_detach(pi->nm_ifp);
1096 ifmedia_removeall(&pi->nm_media);
1097 ether_ifdetach(pi->nm_ifp);
1098 if_free(pi->nm_ifp);
1099 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->nm_viid);
1105 handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp,
1106 const struct cpl_fw6_msg *cpl)
1108 const struct cpl_sge_egr_update *egr;
1110 struct sge_nm_txq *nm_txq;
1112 if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL)
1113 panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type);
1115 /* data[0] is RSS header */
1116 egr = (const void *)&cpl->data[1];
1117 oq = be32toh(egr->opcode_qid);
1118 MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
1119 nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
1121 netmap_tx_irq(ifp, nm_txq->nid);
1125 t4_nm_intr(void *arg)
1127 struct sge_nm_rxq *nm_rxq = arg;
1128 struct port_info *pi = nm_rxq->pi;
1129 struct adapter *sc = pi->adapter;
1130 struct ifnet *ifp = pi->nm_ifp;
1131 struct netmap_adapter *na = NA(ifp);
1132 struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
1133 struct netmap_ring *ring = kring->ring;
1134 struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
1136 u_int n = 0, work = 0;
1138 uint32_t fl_cidx = atomic_load_acq_32(&nm_rxq->fl_cidx);
1139 u_int fl_credits = fl_cidx & 7;
1141 while ((d->rsp.u.type_gen & F_RSPD_GEN) == nm_rxq->iq_gen) {
1145 lq = be32toh(d->rsp.pldbuflen_qid);
1146 opcode = d->rss.opcode;
1148 switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
1149 case X_RSPD_TYPE_FLBUF:
1150 if (black_hole != 2) {
1151 /* No buffer packing so new buf every time */
1152 MPASS(lq & F_RSPD_NEWBUF);
1157 case X_RSPD_TYPE_CPL:
1158 MPASS(opcode < NUM_CPL_CMDS);
1163 handle_nm_fw6_msg(sc, ifp,
1164 (const void *)&d->cpl[0]);
1167 ring->slot[fl_cidx].len = G_RSPD_LEN(lq) - fl_pktshift;
1168 ring->slot[fl_cidx].flags = kring->nkr_slot_flags;
1169 fl_cidx += (lq & F_RSPD_NEWBUF) ? 1 : 0;
1170 fl_credits += (lq & F_RSPD_NEWBUF) ? 1 : 0;
1171 if (__predict_false(fl_cidx == nm_rxq->fl_sidx))
1175 panic("%s: unexpected opcode 0x%x on nm_rxq %p",
1176 __func__, opcode, nm_rxq);
1180 case X_RSPD_TYPE_INTR:
1181 /* Not equipped to handle forwarded interrupts. */
1182 panic("%s: netmap queue received interrupt for iq %u\n",
1186 panic("%s: illegal response type %d on nm_rxq %p",
1187 __func__, G_RSPD_TYPE(d->rsp.u.type_gen), nm_rxq);
1191 if (__predict_false(++nm_rxq->iq_cidx == nm_rxq->iq_sidx)) {
1192 nm_rxq->iq_cidx = 0;
1193 d = &nm_rxq->iq_desc[0];
1194 nm_rxq->iq_gen ^= F_RSPD_GEN;
1197 if (__predict_false(++n == rx_ndesc)) {
1198 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1199 if (black_hole && fl_credits >= 8) {
1201 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8,
1203 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
1204 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1205 fl_credits = fl_cidx & 7;
1206 } else if (!black_hole) {
1207 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1210 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1211 V_CIDXINC(n) | V_INGRESSQID(nm_rxq->iq_cntxt_id) |
1212 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1217 atomic_store_rel_32(&nm_rxq->fl_cidx, fl_cidx);
1220 IDXINCR(nm_rxq->fl_pidx, fl_credits * 8, nm_rxq->fl_sidx);
1221 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
1222 nm_rxq->fl_db_val | V_PIDX(fl_credits));
1224 netmap_rx_irq(ifp, nm_rxq->nid, &work);
1226 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(n) |
1227 V_INGRESSQID((u32)nm_rxq->iq_cntxt_id) |
1228 V_SEINTARM(V_QINTR_TIMER_IDX(holdoff_tmr_idx)));