sys/dev/drm2/i915/i915_debug.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <dev/drm2/drmP.h>
  33 #include <dev/drm2/drm.h>
  34 #include <dev/drm2/i915/i915_drm.h>
  35 #include <dev/drm2/i915/i915_drv.h>
  36 #include <dev/drm2/i915/intel_drv.h>
  37 #include <dev/drm2/i915/intel_ringbuffer.h>
  38
  39 #include <sys/sysctl.h>
  40
  41 enum {
  42         ACTIVE_LIST,
  43         FLUSHING_LIST,
  44         INACTIVE_LIST,
  45         PINNED_LIST,
  46 };
  47
  48 static const char *yesno(int v)
  49 {
  50         return v ? "yes" : "no";
  51 }
  52
  53 static int i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data)
  54 {
  55         const struct intel_device_info *info = INTEL_INFO(dev);
  56
  57         sbuf_printf(m, "gen: %d\n", info->gen);
  58         if (HAS_PCH_SPLIT(dev))
  59                 sbuf_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  60 #define B(x) sbuf_printf(m, #x ": %s\n", yesno(info->x))
  61         B(is_mobile);
  62         B(is_i85x);
  63         B(is_i915g);
  64         B(is_i945gm);
  65         B(is_g33);
  66         B(need_gfx_hws);
  67         B(is_g4x);
  68         B(is_pineview);
  69         B(has_fbc);
  70         B(has_pipe_cxsr);
  71         B(has_hotplug);
  72         B(cursor_needs_physical);
  73         B(has_overlay);
  74         B(overlay_needs_physical);
  75         B(supports_tv);
  76         B(has_bsd_ring);
  77         B(has_blt_ring);
  78         B(has_llc);
  79 #undef B
  80
  81         return 0;
  82 }
  83
  84 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  85 {
  86         if (obj->user_pin_count > 0)
  87                 return "P";
  88         else if (obj->pin_count > 0)
  89                 return "p";
  90         else
  91                 return " ";
  92 }
  93
  94 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
  95 {
  96         switch (obj->tiling_mode) {
  97         default:
  98         case I915_TILING_NONE: return " ";
  99         case I915_TILING_X: return "X";
 100         case I915_TILING_Y: return "Y";
 101         }
 102 }
 103
 104 static const char *cache_level_str(int type)
 105 {
 106         switch (type) {
 107         case I915_CACHE_NONE: return " uncached";
 108         case I915_CACHE_LLC: return " snooped (LLC)";
 109         case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
 110         default: return "";
 111         }
 112 }
 113
 114 static void
 115 describe_obj(struct sbuf *m, struct drm_i915_gem_object *obj)
 116 {
 117
 118         sbuf_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
 119                    &obj->base,
 120                    get_pin_flag(obj),
 121                    get_tiling_flag(obj),
 122                    obj->base.size / 1024,
 123                    obj->base.read_domains,
 124                    obj->base.write_domain,
 125                    obj->last_rendering_seqno,
 126                    obj->last_fenced_seqno,
 127                    cache_level_str(obj->cache_level),
 128                    obj->dirty ? " dirty" : "",
 129                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 130         if (obj->base.name)
 131                 sbuf_printf(m, " (name: %d)", obj->base.name);
 132         if (obj->pin_display)
 133                 sbuf_printf(m, " (display)");
 134         if (obj->fence_reg != I915_FENCE_REG_NONE)
 135                 sbuf_printf(m, " (fence: %d)", obj->fence_reg);
 136         if (obj->gtt_space != NULL)
 137                 sbuf_printf(m, " (gtt offset: %08x, size: %08x)",
 138                            obj->gtt_offset, (unsigned int)obj->gtt_space->size);
 139         if (obj->pin_mappable || obj->fault_mappable) {
 140                 char s[3], *t = s;
 141                 if (obj->pin_mappable)
 142                         *t++ = 'p';
 143                 if (obj->fault_mappable)
 144                         *t++ = 'f';
 145                 *t = '\0';
 146                 sbuf_printf(m, " (%s mappable)", s);
 147         }
 148         if (obj->ring != NULL)
 149                 sbuf_printf(m, " (%s)", obj->ring->name);
 150 }
 151
 152 static int i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data)
 153 {
 154         uintptr_t list = (uintptr_t)data;
 155         struct list_head *head;
 156         drm_i915_private_t *dev_priv = dev->dev_private;
 157         struct drm_i915_gem_object *obj;
 158         size_t total_obj_size, total_gtt_size;
 159         int count;
 160
 161         if (sx_xlock_sig(&dev->dev_struct_lock))
 162                 return -EINTR;
 163
 164         switch (list) {
 165         case ACTIVE_LIST:
 166                 sbuf_printf(m, "Active:\n");
 167                 head = &dev_priv->mm.active_list;
 168                 break;
 169         case INACTIVE_LIST:
 170                 sbuf_printf(m, "Inactive:\n");
 171                 head = &dev_priv->mm.inactive_list;
 172                 break;
 173         case FLUSHING_LIST:
 174                 sbuf_printf(m, "Flushing:\n");
 175                 head = &dev_priv->mm.flushing_list;
 176                 break;
 177         default:
 178                 DRM_UNLOCK(dev);
 179                 return -EINVAL;
 180         }
 181
 182         total_obj_size = total_gtt_size = count = 0;
 183         list_for_each_entry(obj, head, mm_list) {
 184                 sbuf_printf(m, "   ");
 185                 describe_obj(m, obj);
 186                 sbuf_printf(m, "\n");
 187                 total_obj_size += obj->base.size;
 188                 total_gtt_size += obj->gtt_space->size;
 189                 count++;
 190         }
 191         DRM_UNLOCK(dev);
 192
 193         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 194                    count, total_obj_size, total_gtt_size);
 195         return 0;
 196 }
 197
 198 #define count_objects(list, member) do { \
 199         list_for_each_entry(obj, list, member) { \
 200                 size += obj->gtt_space->size; \
 201                 ++count; \
 202                 if (obj->map_and_fenceable) { \
 203                         mappable_size += obj->gtt_space->size; \
 204                         ++mappable_count; \
 205                 } \
 206         } \
 207 } while (0)
 208
 209 static int i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data)
 210 {
 211         struct drm_i915_private *dev_priv = dev->dev_private;
 212         u32 count, mappable_count;
 213         size_t size, mappable_size;
 214         struct drm_i915_gem_object *obj;
 215
 216         if (sx_xlock_sig(&dev->dev_struct_lock))
 217                 return -EINTR;
 218         sbuf_printf(m, "%u objects, %zu bytes\n",
 219                    dev_priv->mm.object_count,
 220                    dev_priv->mm.object_memory);
 221
 222         size = count = mappable_size = mappable_count = 0;
 223         count_objects(&dev_priv->mm.gtt_list, gtt_list);
 224         sbuf_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 225                    count, mappable_count, size, mappable_size);
 226
 227         size = count = mappable_size = mappable_count = 0;
 228         count_objects(&dev_priv->mm.active_list, mm_list);
 229         count_objects(&dev_priv->mm.flushing_list, mm_list);
 230         sbuf_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 231                    count, mappable_count, size, mappable_size);
 232
 233         size = count = mappable_size = mappable_count = 0;
 234         count_objects(&dev_priv->mm.inactive_list, mm_list);
 235         sbuf_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 236                    count, mappable_count, size, mappable_size);
 237
 238         size = count = mappable_size = mappable_count = 0;
 239         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 240                 if (obj->fault_mappable) {
 241                         size += obj->gtt_space->size;
 242                         ++count;
 243                 }
 244                 if (obj->pin_mappable) {
 245                         mappable_size += obj->gtt_space->size;
 246                         ++mappable_count;
 247                 }
 248         }
 249         sbuf_printf(m, "%u pinned mappable objects, %zu bytes\n",
 250                    mappable_count, mappable_size);
 251         sbuf_printf(m, "%u fault mappable objects, %zu bytes\n",
 252                    count, size);
 253
 254         sbuf_printf(m, "%zu [%zu] gtt total\n",
 255                    dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
 256
 257         DRM_UNLOCK(dev);
 258
 259         return 0;
 260 }
 261
 262 static int i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void *data)
 263 {
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         uintptr_t list = (uintptr_t)data;
 266         struct drm_i915_gem_object *obj;
 267         size_t total_obj_size, total_gtt_size;
 268         int count;
 269
 270         if (sx_xlock_sig(&dev->dev_struct_lock))
 271                 return -EINTR;
 272
 273         total_obj_size = total_gtt_size = count = 0;
 274         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 275                 if (list == PINNED_LIST && obj->pin_count == 0)
 276                         continue;
 277
 278                 sbuf_printf(m, "   ");
 279                 describe_obj(m, obj);
 280                 sbuf_printf(m, "\n");
 281                 total_obj_size += obj->base.size;
 282                 total_gtt_size += obj->gtt_space->size;
 283                 count++;
 284         }
 285
 286         DRM_UNLOCK(dev);
 287
 288         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 289                    count, total_obj_size, total_gtt_size);
 290
 291         return 0;
 292 }
 293
 294 static int i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data)
 295 {
 296         struct intel_crtc *crtc;
 297         struct drm_i915_gem_object *obj;
 298         struct intel_unpin_work *work;
 299         char pipe;
 300         char plane;
 301
 302         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 303                 pipe = pipe_name(crtc->pipe);
 304                 plane = plane_name(crtc->plane);
 305
 306                 mtx_lock(&dev->event_lock);
 307                 work = crtc->unpin_work;
 308                 if (work == NULL) {
 309                         sbuf_printf(m, "No flip due on pipe %c (plane %c)\n",
 310                                    pipe, plane);
 311                 } else {
 312                         if (!work->pending) {
 313                                 sbuf_printf(m, "Flip queued on pipe %c (plane %c)\n",
 314                                            pipe, plane);
 315                         } else {
 316                                 sbuf_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 317                                            pipe, plane);
 318                         }
 319                         if (work->enable_stall_check)
 320                                 sbuf_printf(m, "Stall check enabled, ");
 321                         else
 322                                 sbuf_printf(m, "Stall check waiting for page flip ioctl, ");
 323                         sbuf_printf(m, "%d prepares\n", work->pending);
 324
 325                         if (work->old_fb_obj) {
 326                                 obj = work->old_fb_obj;
 327                                 if (obj)
 328                                         sbuf_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 329                         }
 330                         if (work->pending_flip_obj) {
 331                                 obj = work->pending_flip_obj;
 332                                 if (obj)
 333                                         sbuf_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 334                         }
 335                 }
 336                 mtx_unlock(&dev->event_lock);
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data)
 343 {
 344         drm_i915_private_t *dev_priv = dev->dev_private;
 345         struct drm_i915_gem_request *gem_request;
 346         int count;
 347
 348         if (sx_xlock_sig(&dev->dev_struct_lock))
 349                 return -EINTR;
 350
 351         count = 0;
 352         if (!list_empty(&dev_priv->rings[RCS].request_list)) {
 353                 sbuf_printf(m, "Render requests:\n");
 354                 list_for_each_entry(gem_request,
 355                                     &dev_priv->rings[RCS].request_list,
 356                                     list) {
 357                         sbuf_printf(m, "    %d @ %d\n",
 358                                    gem_request->seqno,
 359                                    (int) (jiffies - gem_request->emitted_jiffies));
 360                 }
 361                 count++;
 362         }
 363         if (!list_empty(&dev_priv->rings[VCS].request_list)) {
 364                 sbuf_printf(m, "BSD requests:\n");
 365                 list_for_each_entry(gem_request,
 366                                     &dev_priv->rings[VCS].request_list,
 367                                     list) {
 368                         sbuf_printf(m, "    %d @ %d\n",
 369                                    gem_request->seqno,
 370                                    (int) (jiffies - gem_request->emitted_jiffies));
 371                 }
 372                 count++;
 373         }
 374         if (!list_empty(&dev_priv->rings[BCS].request_list)) {
 375                 sbuf_printf(m, "BLT requests:\n");
 376                 list_for_each_entry(gem_request,
 377                                     &dev_priv->rings[BCS].request_list,
 378                                     list) {
 379                         sbuf_printf(m, "    %d @ %d\n",
 380                                    gem_request->seqno,
 381                                    (int) (jiffies - gem_request->emitted_jiffies));
 382                 }
 383                 count++;
 384         }
 385         DRM_UNLOCK(dev);
 386
 387         if (count == 0)
 388                 sbuf_printf(m, "No requests\n");
 389
 390         return 0;
 391 }
 392
 393 static void i915_ring_seqno_info(struct sbuf *m, struct intel_ring_buffer *ring)
 394 {
 395         if (ring->get_seqno) {
 396                 sbuf_printf(m, "Current sequence (%s): %d\n",
 397                            ring->name, ring->get_seqno(ring));
 398         }
 399 }
 400
 401 static int i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data)
 402 {
 403         drm_i915_private_t *dev_priv = dev->dev_private;
 404         int i;
 405
 406         if (sx_xlock_sig(&dev->dev_struct_lock))
 407                 return -EINTR;
 408
 409         for (i = 0; i < I915_NUM_RINGS; i++)
 410                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 411
 412         DRM_UNLOCK(dev);
 413
 414         return 0;
 415 }
 416
 417
 418 static int i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data)
 419 {
 420         drm_i915_private_t *dev_priv = dev->dev_private;
 421         int i, pipe;
 422
 423         if (sx_xlock_sig(&dev->dev_struct_lock))
 424                 return -EINTR;
 425
 426         if (IS_VALLEYVIEW(dev)) {
 427                 sbuf_printf(m, "Display IER:\t%08x\n",
 428                            I915_READ(VLV_IER));
 429                 sbuf_printf(m, "Display IIR:\t%08x\n",
 430                            I915_READ(VLV_IIR));
 431                 sbuf_printf(m, "Display IIR_RW:\t%08x\n",
 432                            I915_READ(VLV_IIR_RW));
 433                 sbuf_printf(m, "Display IMR:\t%08x\n",
 434                            I915_READ(VLV_IMR));
 435                 for_each_pipe(pipe)
 436                         sbuf_printf(m, "Pipe %c stat:\t%08x\n",
 437                                    pipe_name(pipe),
 438                                    I915_READ(PIPESTAT(pipe)));
 439
 440                 sbuf_printf(m, "Master IER:\t%08x\n",
 441                            I915_READ(VLV_MASTER_IER));
 442
 443                 sbuf_printf(m, "Render IER:\t%08x\n",
 444                            I915_READ(GTIER));
 445                 sbuf_printf(m, "Render IIR:\t%08x\n",
 446                            I915_READ(GTIIR));
 447                 sbuf_printf(m, "Render IMR:\t%08x\n",
 448                            I915_READ(GTIMR));
 449
 450                 sbuf_printf(m, "PM IER:\t\t%08x\n",
 451                            I915_READ(GEN6_PMIER));
 452                 sbuf_printf(m, "PM IIR:\t\t%08x\n",
 453                            I915_READ(GEN6_PMIIR));
 454                 sbuf_printf(m, "PM IMR:\t\t%08x\n",
 455                            I915_READ(GEN6_PMIMR));
 456
 457                 sbuf_printf(m, "Port hotplug:\t%08x\n",
 458                            I915_READ(PORT_HOTPLUG_EN));
 459                 sbuf_printf(m, "DPFLIPSTAT:\t%08x\n",
 460                            I915_READ(VLV_DPFLIPSTAT));
 461                 sbuf_printf(m, "DPINVGTT:\t%08x\n",
 462                            I915_READ(DPINVGTT));
 463
 464         } else if (!HAS_PCH_SPLIT(dev)) {
 465                 sbuf_printf(m, "Interrupt enable:    %08x\n",
 466                            I915_READ(IER));
 467                 sbuf_printf(m, "Interrupt identity:  %08x\n",
 468                            I915_READ(IIR));
 469                 sbuf_printf(m, "Interrupt mask:      %08x\n",
 470                            I915_READ(IMR));
 471                 for_each_pipe(pipe)
 472                         sbuf_printf(m, "Pipe %c stat:         %08x\n",
 473                                    pipe_name(pipe),
 474                                    I915_READ(PIPESTAT(pipe)));
 475         } else {
 476                 sbuf_printf(m, "North Display Interrupt enable:         %08x\n",
 477                            I915_READ(DEIER));
 478                 sbuf_printf(m, "North Display Interrupt identity:       %08x\n",
 479                            I915_READ(DEIIR));
 480                 sbuf_printf(m, "North Display Interrupt mask:           %08x\n",
 481                            I915_READ(DEIMR));
 482                 sbuf_printf(m, "South Display Interrupt enable:         %08x\n",
 483                            I915_READ(SDEIER));
 484                 sbuf_printf(m, "South Display Interrupt identity:       %08x\n",
 485                            I915_READ(SDEIIR));
 486                 sbuf_printf(m, "South Display Interrupt mask:           %08x\n",
 487                            I915_READ(SDEIMR));
 488                 sbuf_printf(m, "Graphics Interrupt enable:              %08x\n",
 489                            I915_READ(GTIER));
 490                 sbuf_printf(m, "Graphics Interrupt identity:            %08x\n",
 491                            I915_READ(GTIIR));
 492                 sbuf_printf(m, "Graphics Interrupt mask:                %08x\n",
 493                            I915_READ(GTIMR));
 494         }
 495         sbuf_printf(m, "Interrupts received: %d\n",
 496                    atomic_read(&dev_priv->irq_received));
 497         for (i = 0; i < I915_NUM_RINGS; i++) {
 498                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 499                         sbuf_printf(m, "Graphics Interrupt mask (%s):   %08x\n",
 500                                    dev_priv->rings[i].name,
 501                                    I915_READ_IMR(&dev_priv->rings[i]));
 502                 }
 503                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 504         }
 505         DRM_UNLOCK(dev);
 506
 507         return 0;
 508 }
 509
 510 static int i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data)
 511 {
 512         drm_i915_private_t *dev_priv = dev->dev_private;
 513         int i;
 514
 515         if (sx_xlock_sig(&dev->dev_struct_lock))
 516                 return -EINTR;
 517
 518         sbuf_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 519         sbuf_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 520         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 521                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 522
 523                 sbuf_printf(m, "Fenced object[%2d] = ", i);
 524                 if (obj == NULL)
 525                         sbuf_printf(m, "unused");
 526                 else
 527                         describe_obj(m, obj);
 528                 sbuf_printf(m, "\n");
 529         }
 530
 531         DRM_UNLOCK(dev);
 532         return 0;
 533 }
 534
 535 static int i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data)
 536 {
 537         drm_i915_private_t *dev_priv = dev->dev_private;
 538         struct intel_ring_buffer *ring;
 539         const volatile u32 __iomem *hws;
 540         int i;
 541
 542         ring = &dev_priv->rings[(uintptr_t)data];
 543         hws = (volatile u32 *)ring->status_page.page_addr;
 544         if (hws == NULL)
 545                 return 0;
 546
 547         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 548                 sbuf_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 549                            i * 4,
 550                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 551         }
 552         return 0;
 553 }
 554
 555 static const char *ring_str(int ring)
 556 {
 557         switch (ring) {
 558         case RCS: return " render";
 559         case VCS: return " bsd";
 560         case BCS: return " blt";
 561         default: return "";
 562         }
 563 }
 564
 565 static const char *pin_flag(int pinned)
 566 {
 567         if (pinned > 0)
 568                 return " P";
 569         else if (pinned < 0)
 570                 return " p";
 571         else
 572                 return "";
 573 }
 574
 575 static const char *tiling_flag(int tiling)
 576 {
 577         switch (tiling) {
 578         default:
 579         case I915_TILING_NONE: return "";
 580         case I915_TILING_X: return " X";
 581         case I915_TILING_Y: return " Y";
 582         }
 583 }
 584
 585 static const char *dirty_flag(int dirty)
 586 {
 587         return dirty ? " dirty" : "";
 588 }
 589
 590 static const char *purgeable_flag(int purgeable)
 591 {
 592         return purgeable ? " purgeable" : "";
 593 }
 594
 595 static void print_error_buffers(struct sbuf *m,
 596                                 const char *name,
 597                                 struct drm_i915_error_buffer *err,
 598                                 int count)
 599 {
 600
 601         sbuf_printf(m, "%s [%d]:\n", name, count);
 602
 603         while (count--) {
 604                 sbuf_printf(m, "  %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
 605                            err->gtt_offset,
 606                            err->size,
 607                            err->read_domains,
 608                            err->write_domain,
 609                            err->seqno,
 610                            pin_flag(err->pinned),
 611                            tiling_flag(err->tiling),
 612                            dirty_flag(err->dirty),
 613                            purgeable_flag(err->purgeable),
 614                            err->ring != -1 ? " " : "",
 615                            ring_str(err->ring),
 616                            cache_level_str(err->cache_level));
 617
 618                 if (err->name)
 619                         sbuf_printf(m, " (name: %d)", err->name);
 620                 if (err->fence_reg != I915_FENCE_REG_NONE)
 621                         sbuf_printf(m, " (fence: %d)", err->fence_reg);
 622
 623                 sbuf_printf(m, "\n");
 624                 err++;
 625         }
 626 }
 627
 628 static void i915_ring_error_state(struct sbuf *m,
 629                                   struct drm_device *dev,
 630                                   struct drm_i915_error_state *error,
 631                                   unsigned ring)
 632 {
 633
 634         MPASS((ring < I915_NUM_RINGS)); /* shut up confused gcc */
 635         sbuf_printf(m, "%s command stream:\n", ring_str(ring));
 636         sbuf_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
 637         sbuf_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
 638         sbuf_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
 639         sbuf_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
 640         sbuf_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
 641         sbuf_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
 642         if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
 643                 sbuf_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
 644                 sbuf_printf(m, "  BBADDR: 0x%08jx\n", (uintmax_t)error->bbaddr);
 645         }
 646         if (INTEL_INFO(dev)->gen >= 4)
 647                 sbuf_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
 648         sbuf_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
 649         sbuf_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
 650         if (INTEL_INFO(dev)->gen >= 6) {
 651                 sbuf_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
 652                 sbuf_printf(m, "  SYNC_0: 0x%08x\n",
 653                            error->semaphore_mboxes[ring][0]);
 654                 sbuf_printf(m, "  SYNC_1: 0x%08x\n",
 655                            error->semaphore_mboxes[ring][1]);
 656         }
 657         sbuf_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
 658         sbuf_printf(m, "  waiting: %s\n", yesno(error->waiting[ring]));
 659         sbuf_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
 660         sbuf_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
 661 }
 662
 663 static int i915_error_state(struct drm_device *dev, struct sbuf *m,
 664     void *unused)
 665 {
 666         drm_i915_private_t *dev_priv = dev->dev_private;
 667         struct drm_i915_error_state *error;
 668         struct intel_ring_buffer *ring;
 669         int i, j, page, offset, elt;
 670
 671         mtx_lock(&dev_priv->error_lock);
 672         error = dev_priv->first_error;
 673         if (error != NULL)
 674                 refcount_acquire(&error->ref);
 675         mtx_unlock(&dev_priv->error_lock);
 676         if (!error) {
 677                 sbuf_printf(m, "no error state collected\n");
 678                 return 0;
 679         }
 680
 681         error = dev_priv->first_error;
 682
 683         sbuf_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
 684             (intmax_t)error->time.tv_usec);
 685         sbuf_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
 686         sbuf_printf(m, "EIR: 0x%08x\n", error->eir);
 687         sbuf_printf(m, "IER: 0x%08x\n", error->ier);
 688         sbuf_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 689
 690         for (i = 0; i < dev_priv->num_fence_regs; i++)
 691                 sbuf_printf(m, "  fence[%d] = %08jx\n", i,
 692                     (uintmax_t)error->fence[i]);
 693
 694         if (INTEL_INFO(dev)->gen >= 6) {
 695                 sbuf_printf(m, "ERROR: 0x%08x\n", error->error);
 696                 sbuf_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 697         }
 698
 699         for_each_ring(ring, dev_priv, i)
 700                 i915_ring_error_state(m, dev, error, i);
 701
 702         if (error->active_bo)
 703                 print_error_buffers(m, "Active",
 704                                     error->active_bo,
 705                                     error->active_bo_count);
 706
 707         if (error->pinned_bo)
 708                 print_error_buffers(m, "Pinned",
 709                                     error->pinned_bo,
 710                                     error->pinned_bo_count);
 711
 712         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 713                 struct drm_i915_error_object *obj;
 714
 715                 if ((obj = error->ring[i].batchbuffer)) {
 716                         sbuf_printf(m, "%s --- gtt_offset = 0x%08x\n",
 717                                    dev_priv->rings[i].name,
 718                                    obj->gtt_offset);
 719                         offset = 0;
 720                         for (page = 0; page < obj->page_count; page++) {
 721                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 722                                         sbuf_printf(m, "%08x :  %08x\n",
 723                                             offset, obj->pages[page][elt]);
 724                                         offset += 4;
 725                                 }
 726                         }
 727                 }
 728
 729                 if (error->ring[i].num_requests) {
 730                         sbuf_printf(m, "%s --- %d requests\n",
 731                                    dev_priv->rings[i].name,
 732                                    error->ring[i].num_requests);
 733                         for (j = 0; j < error->ring[i].num_requests; j++) {
 734                                 sbuf_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 735                                            error->ring[i].requests[j].seqno,
 736                                            error->ring[i].requests[j].jiffies,
 737                                            error->ring[i].requests[j].tail);
 738                         }
 739                 }
 740
 741                 if ((obj = error->ring[i].ringbuffer)) {
 742                         sbuf_printf(m, "%s --- ringbuffer = 0x%08x\n",
 743                                    dev_priv->rings[i].name,
 744                                    obj->gtt_offset);
 745                         offset = 0;
 746                         for (page = 0; page < obj->page_count; page++) {
 747                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 748                                         sbuf_printf(m, "%08x :  %08x\n",
 749                                                    offset,
 750                                                    obj->pages[page][elt]);
 751                                         offset += 4;
 752                                 }
 753                         }
 754                 }
 755         }
 756
 757         if (error->overlay)
 758                 intel_overlay_print_error_state(m, error->overlay);
 759
 760         if (error->display)
 761                 intel_display_print_error_state(m, dev, error->display);
 762
 763         if (refcount_release(&error->ref))
 764                 i915_error_state_free(error);
 765
 766         return 0;
 767 }
 768
 769 static int
 770 i915_error_state_w(struct drm_device *dev, const char *str, void *unused)
 771 {
 772         drm_i915_private_t *dev_priv = dev->dev_private;
 773         struct drm_i915_error_state *error;
 774
 775         DRM_DEBUG_DRIVER("Resetting error state\n");
 776         mtx_lock(&dev_priv->error_lock);
 777         error = dev_priv->first_error;
 778         dev_priv->first_error = NULL;
 779         mtx_unlock(&dev_priv->error_lock);
 780         if (error != NULL && refcount_release(&error->ref))
 781                 i915_error_state_free(error);
 782         return (0);
 783 }
 784
 785 static int
 786 i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused)
 787 {
 788         drm_i915_private_t *dev_priv = dev->dev_private;
 789         u16 crstanddelay;
 790
 791         if (sx_xlock_sig(&dev->dev_struct_lock))
 792                 return -EINTR;
 793
 794         crstanddelay = I915_READ16(CRSTANDVID);
 795
 796         DRM_UNLOCK(dev);
 797
 798         sbuf_printf(m, "w/ctx: %d, w/o ctx: %d\n",
 799             (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 800
 801         return 0;
 802 }
 803
 804 static int i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused)
 805 {
 806         drm_i915_private_t *dev_priv = dev->dev_private;
 807
 808         if (IS_GEN5(dev)) {
 809                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 810                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 811
 812                 sbuf_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 813                 sbuf_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 814                 sbuf_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 815                            MEMSTAT_VID_SHIFT);
 816                 sbuf_printf(m, "Current P-state: %d\n",
 817                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 818         } else if (IS_GEN6(dev)) {
 819                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 820                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 821                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 822                 u32 rpstat;
 823                 u32 rpupei, rpcurup, rpprevup;
 824                 u32 rpdownei, rpcurdown, rpprevdown;
 825                 int max_freq;
 826
 827                 /* RPSTAT1 is in the GT power well */
 828                 if (sx_xlock_sig(&dev->dev_struct_lock))
 829                         return -EINTR;
 830                 gen6_gt_force_wake_get(dev_priv);
 831
 832                 rpstat = I915_READ(GEN6_RPSTAT1);
 833                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 834                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 835                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 836                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 837                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 838                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 839
 840                 gen6_gt_force_wake_put(dev_priv);
 841                 DRM_UNLOCK(dev);
 842
 843                 sbuf_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 844                 sbuf_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 845                 sbuf_printf(m, "Render p-state ratio: %d\n",
 846                            (gt_perf_status & 0xff00) >> 8);
 847                 sbuf_printf(m, "Render p-state VID: %d\n",
 848                            gt_perf_status & 0xff);
 849                 sbuf_printf(m, "Render p-state limit: %d\n",
 850                            rp_state_limits & 0xff);
 851                 sbuf_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
 852                                                 GEN6_CAGF_SHIFT) * 50);
 853                 sbuf_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 854                            GEN6_CURICONT_MASK);
 855                 sbuf_printf(m, "RP CUR UP: %dus\n", rpcurup &
 856                            GEN6_CURBSYTAVG_MASK);
 857                 sbuf_printf(m, "RP PREV UP: %dus\n", rpprevup &
 858                            GEN6_CURBSYTAVG_MASK);
 859                 sbuf_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 860                            GEN6_CURIAVG_MASK);
 861                 sbuf_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 862                            GEN6_CURBSYTAVG_MASK);
 863                 sbuf_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 864                            GEN6_CURBSYTAVG_MASK);
 865
 866                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 867                 sbuf_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 868                            max_freq * 50);
 869
 870                 max_freq = (rp_state_cap & 0xff00) >> 8;
 871                 sbuf_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 872                            max_freq * 50);
 873
 874                 max_freq = rp_state_cap & 0xff;
 875                 sbuf_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 876                            max_freq * 50);
 877         } else {
 878                 sbuf_printf(m, "no P-state info available\n");
 879         }
 880
 881         return 0;
 882 }
 883
 884 static int i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused)
 885 {
 886         drm_i915_private_t *dev_priv = dev->dev_private;
 887         u32 delayfreq;
 888         int i;
 889
 890         if (sx_xlock_sig(&dev->dev_struct_lock))
 891                 return -EINTR;
 892
 893         for (i = 0; i < 16; i++) {
 894                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 895                 sbuf_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 896                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 897         }
 898
 899         DRM_UNLOCK(dev);
 900
 901         return 0;
 902 }
 903
 904 static inline int MAP_TO_MV(int map)
 905 {
 906         return 1250 - (map * 25);
 907 }
 908
 909 static int i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused)
 910 {
 911         drm_i915_private_t *dev_priv = dev->dev_private;
 912         u32 inttoext;
 913         int i;
 914
 915         if (sx_xlock_sig(&dev->dev_struct_lock))
 916                 return -EINTR;
 917
 918         for (i = 1; i <= 32; i++) {
 919                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 920                 sbuf_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 921         }
 922
 923         DRM_UNLOCK(dev);
 924
 925         return 0;
 926 }
 927
 928 static int ironlake_drpc_info(struct drm_device *dev, struct sbuf *m)
 929 {
 930         drm_i915_private_t *dev_priv = dev->dev_private;
 931         u32 rgvmodectl;
 932         u32 rstdbyctl;
 933         u16 crstandvid;
 934
 935         if (sx_xlock_sig(&dev->dev_struct_lock))
 936                 return -EINTR;
 937
 938         rgvmodectl = I915_READ(MEMMODECTL);
 939         rstdbyctl = I915_READ(RSTDBYCTL);
 940         crstandvid = I915_READ16(CRSTANDVID);
 941
 942         DRM_UNLOCK(dev);
 943
 944         sbuf_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 945                    "yes" : "no");
 946         sbuf_printf(m, "Boost freq: %d\n",
 947                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 948                    MEMMODE_BOOST_FREQ_SHIFT);
 949         sbuf_printf(m, "HW control enabled: %s\n",
 950                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 951         sbuf_printf(m, "SW control enabled: %s\n",
 952                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 953         sbuf_printf(m, "Gated voltage change: %s\n",
 954                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 955         sbuf_printf(m, "Starting frequency: P%d\n",
 956                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 957         sbuf_printf(m, "Max P-state: P%d\n",
 958                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 959         sbuf_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 960         sbuf_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 961         sbuf_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 962         sbuf_printf(m, "Render standby enabled: %s\n",
 963                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 964         sbuf_printf(m, "Current RS state: ");
 965         switch (rstdbyctl & RSX_STATUS_MASK) {
 966         case RSX_STATUS_ON:
 967                 sbuf_printf(m, "on\n");
 968                 break;
 969         case RSX_STATUS_RC1:
 970                 sbuf_printf(m, "RC1\n");
 971                 break;
 972         case RSX_STATUS_RC1E:
 973                 sbuf_printf(m, "RC1E\n");
 974                 break;
 975         case RSX_STATUS_RS1:
 976                 sbuf_printf(m, "RS1\n");
 977                 break;
 978         case RSX_STATUS_RS2:
 979                 sbuf_printf(m, "RS2 (RC6)\n");
 980                 break;
 981         case RSX_STATUS_RS3:
 982                 sbuf_printf(m, "RC3 (RC6+)\n");
 983                 break;
 984         default:
 985                 sbuf_printf(m, "unknown\n");
 986                 break;
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int gen6_drpc_info(struct drm_device *dev, struct sbuf *m)
 993 {
 994         drm_i915_private_t *dev_priv = dev->dev_private;
 995         u32 rpmodectl1, gt_core_status, rcctl1;
 996         unsigned forcewake_count;
 997         int count=0;
 998
 999
1000         if (sx_xlock_sig(&dev->dev_struct_lock))
1001                 return -EINTR;
1002
1003         mtx_lock(&dev_priv->gt_lock);
1004         forcewake_count = dev_priv->forcewake_count;
1005         mtx_unlock(&dev_priv->gt_lock);
1006
1007         if (forcewake_count) {
1008                 sbuf_printf(m, "RC information inaccurate because userspace "
1009                               "holds a reference \n");
1010         } else {
1011                 /* NB: we cannot use forcewake, else we read the wrong values */
1012                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1013                         udelay(10);
1014                 sbuf_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1015         }
1016
1017         gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS);
1018         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1019
1020         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1021         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1022         DRM_UNLOCK(dev);
1023
1024         sbuf_printf(m, "Video Turbo Mode: %s\n",
1025                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1026         sbuf_printf(m, "HW control enabled: %s\n",
1027                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1028         sbuf_printf(m, "SW control enabled: %s\n",
1029                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1030                           GEN6_RP_MEDIA_SW_MODE));
1031         sbuf_printf(m, "RC1e Enabled: %s\n",
1032                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1033         sbuf_printf(m, "RC6 Enabled: %s\n",
1034                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1035         sbuf_printf(m, "Deep RC6 Enabled: %s\n",
1036                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1037         sbuf_printf(m, "Deepest RC6 Enabled: %s\n",
1038                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1039         sbuf_printf(m, "Current RC state: ");
1040         switch (gt_core_status & GEN6_RCn_MASK) {
1041         case GEN6_RC0:
1042                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1043                         sbuf_printf(m, "Core Power Down\n");
1044                 else
1045                         sbuf_printf(m, "on\n");
1046                 break;
1047         case GEN6_RC3:
1048                 sbuf_printf(m, "RC3\n");
1049                 break;
1050         case GEN6_RC6:
1051                 sbuf_printf(m, "RC6\n");
1052                 break;
1053         case GEN6_RC7:
1054                 sbuf_printf(m, "RC7\n");
1055                 break;
1056         default:
1057                 sbuf_printf(m, "Unknown\n");
1058                 break;
1059         }
1060
1061         sbuf_printf(m, "Core Power Down: %s\n",
1062                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1063
1064         /* Not exactly sure what this is */
1065         sbuf_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1066                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1067         sbuf_printf(m, "RC6 residency since boot: %u\n",
1068                    I915_READ(GEN6_GT_GFX_RC6));
1069         sbuf_printf(m, "RC6+ residency since boot: %u\n",
1070                    I915_READ(GEN6_GT_GFX_RC6p));
1071         sbuf_printf(m, "RC6++ residency since boot: %u\n",
1072                    I915_READ(GEN6_GT_GFX_RC6pp));
1073
1074         return 0;
1075 }
1076
1077 static int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused)
1078 {
1079
1080         if (IS_GEN6(dev) || IS_GEN7(dev))
1081                 return gen6_drpc_info(dev, m);
1082         else
1083                 return ironlake_drpc_info(dev, m);
1084 }
1085
1086 static int i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused)
1087 {
1088         drm_i915_private_t *dev_priv = dev->dev_private;
1089
1090         if (!I915_HAS_FBC(dev)) {
1091                 sbuf_printf(m, "FBC unsupported on this chipset");
1092                 return 0;
1093         }
1094
1095         if (intel_fbc_enabled(dev)) {
1096                 sbuf_printf(m, "FBC enabled");
1097         } else {
1098                 sbuf_printf(m, "FBC disabled: ");
1099                 switch (dev_priv->no_fbc_reason) {
1100                 case FBC_NO_OUTPUT:
1101                         sbuf_printf(m, "no outputs");
1102                         break;
1103                 case FBC_STOLEN_TOO_SMALL:
1104                         sbuf_printf(m, "not enough stolen memory");
1105                         break;
1106                 case FBC_UNSUPPORTED_MODE:
1107                         sbuf_printf(m, "mode not supported");
1108                         break;
1109                 case FBC_MODE_TOO_LARGE:
1110                         sbuf_printf(m, "mode too large");
1111                         break;
1112                 case FBC_BAD_PLANE:
1113                         sbuf_printf(m, "FBC unsupported on plane");
1114                         break;
1115                 case FBC_NOT_TILED:
1116                         sbuf_printf(m, "scanout buffer not tiled");
1117                         break;
1118                 case FBC_MULTIPLE_PIPES:
1119                         sbuf_printf(m, "multiple pipes are enabled");
1120                         break;
1121                 default:
1122                         sbuf_printf(m, "unknown reason");
1123                 }
1124         }
1125         return 0;
1126 }
1127
1128 static int i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused)
1129 {
1130         drm_i915_private_t *dev_priv = dev->dev_private;
1131         bool sr_enabled = false;
1132
1133         if (HAS_PCH_SPLIT(dev))
1134                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1135         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1136                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1137         else if (IS_I915GM(dev))
1138                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1139         else if (IS_PINEVIEW(dev))
1140                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1141
1142         sbuf_printf(m, "self-refresh: %s",
1143                    sr_enabled ? "enabled" : "disabled");
1144
1145         return 0;
1146 }
1147
1148 static int i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused)
1149 {
1150         drm_i915_private_t *dev_priv = dev->dev_private;
1151         unsigned long temp, chipset, gfx;
1152
1153         if (!IS_GEN5(dev))
1154                 return -ENODEV;
1155
1156         if (sx_xlock_sig(&dev->dev_struct_lock))
1157                 return -EINTR;
1158
1159         temp = i915_mch_val(dev_priv);
1160         chipset = i915_chipset_val(dev_priv);
1161         gfx = i915_gfx_val(dev_priv);
1162         DRM_UNLOCK(dev);
1163
1164         sbuf_printf(m, "GMCH temp: %ld\n", temp);
1165         sbuf_printf(m, "Chipset power: %ld\n", chipset);
1166         sbuf_printf(m, "GFX power: %ld\n", gfx);
1167         sbuf_printf(m, "Total power: %ld\n", chipset + gfx);
1168
1169         return 0;
1170 }
1171
1172 static int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m,
1173     void *unused)
1174 {
1175         drm_i915_private_t *dev_priv = dev->dev_private;
1176         int gpu_freq, ia_freq;
1177
1178         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1179                 sbuf_printf(m, "unsupported on this chipset");
1180                 return 0;
1181         }
1182
1183         if (sx_xlock_sig(&dev->dev_struct_lock))
1184                 return -EINTR;
1185
1186         sbuf_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1187
1188         for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1189              gpu_freq++) {
1190                 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1191                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1192                            GEN6_PCODE_READ_MIN_FREQ_TABLE);
1193                 if (_intel_wait_for(dev,
1194                     (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1195                     10, 1, "915frq")) {
1196                         DRM_ERROR("pcode read of freq table timed out\n");
1197                         continue;
1198                 }
1199                 ia_freq = I915_READ(GEN6_PCODE_DATA);
1200                 sbuf_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1201         }
1202
1203         DRM_UNLOCK(dev);
1204
1205         return 0;
1206 }
1207
1208 static int i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused)
1209 {
1210         drm_i915_private_t *dev_priv = dev->dev_private;
1211
1212         if (sx_xlock_sig(&dev->dev_struct_lock))
1213                 return -EINTR;
1214
1215         sbuf_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1216
1217         DRM_UNLOCK(dev);
1218
1219         return 0;
1220 }
1221
1222 #if 0
1223 static int i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused)
1224 {
1225         drm_i915_private_t *dev_priv = dev->dev_private;
1226         struct intel_opregion *opregion = &dev_priv->opregion;
1227
1228         if (sx_xlock_sig(&dev->dev_struct_lock))
1229                 return -EINTR;
1230
1231         if (opregion->header)
1232                 seq_write(m, opregion->header, OPREGION_SIZE);
1233
1234         DRM_UNLOCK(dev);
1235
1236         return 0;
1237 }
1238 #endif
1239
1240 static int i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
1241 {
1242         drm_i915_private_t *dev_priv = dev->dev_private;
1243         struct intel_fbdev *ifbdev;
1244         struct intel_framebuffer *fb;
1245
1246         if (sx_xlock_sig(&dev->dev_struct_lock))
1247                 return -EINTR;
1248
1249         ifbdev = dev_priv->fbdev;
1250         if (ifbdev == NULL) {
1251                 DRM_UNLOCK(dev);
1252                 return 0;
1253         }
1254         fb = to_intel_framebuffer(ifbdev->helper.fb);
1255
1256         sbuf_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1257                    fb->base.width,
1258                    fb->base.height,
1259                    fb->base.depth,
1260                    fb->base.bits_per_pixel);
1261         describe_obj(m, fb->obj);
1262         sbuf_printf(m, "\n");
1263
1264         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1265                 if (&fb->base == ifbdev->helper.fb)
1266                         continue;
1267
1268                 sbuf_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1269                            fb->base.width,
1270                            fb->base.height,
1271                            fb->base.depth,
1272                            fb->base.bits_per_pixel);
1273                 describe_obj(m, fb->obj);
1274                 sbuf_printf(m, "\n");
1275         }
1276
1277         DRM_UNLOCK(dev);
1278
1279         return 0;
1280 }
1281
1282 static int i915_context_status(struct drm_device *dev, struct sbuf *m, void *data)
1283 {
1284         drm_i915_private_t *dev_priv;
1285         int ret;
1286
1287         dev_priv = dev->dev_private;
1288         ret = sx_xlock_sig(&dev->mode_config.mutex);
1289         if (ret != 0)
1290                 return -EINTR;
1291
1292         if (dev_priv->pwrctx != NULL) {
1293                 sbuf_printf(m, "power context ");
1294                 describe_obj(m, dev_priv->pwrctx);
1295                 sbuf_printf(m, "\n");
1296         }
1297
1298         if (dev_priv->renderctx != NULL) {
1299                 sbuf_printf(m, "render context ");
1300                 describe_obj(m, dev_priv->renderctx);
1301                 sbuf_printf(m, "\n");
1302         }
1303
1304         sx_xunlock(&dev->mode_config.mutex);
1305
1306         return 0;
1307 }
1308
1309 static int i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m,
1310     void *data)
1311 {
1312         struct drm_i915_private *dev_priv;
1313         unsigned forcewake_count;
1314
1315         dev_priv = dev->dev_private;
1316         mtx_lock(&dev_priv->gt_lock);
1317         forcewake_count = dev_priv->forcewake_count;
1318         mtx_unlock(&dev_priv->gt_lock);
1319
1320         sbuf_printf(m, "forcewake count = %u\n", forcewake_count);
1321
1322         return 0;
1323 }
1324
1325 static const char *swizzle_string(unsigned swizzle)
1326 {
1327
1328         switch(swizzle) {
1329         case I915_BIT_6_SWIZZLE_NONE:
1330                 return "none";
1331         case I915_BIT_6_SWIZZLE_9:
1332                 return "bit9";
1333         case I915_BIT_6_SWIZZLE_9_10:
1334                 return "bit9/bit10";
1335         case I915_BIT_6_SWIZZLE_9_11:
1336                 return "bit9/bit11";
1337         case I915_BIT_6_SWIZZLE_9_10_11:
1338                 return "bit9/bit10/bit11";
1339         case I915_BIT_6_SWIZZLE_9_17:
1340                 return "bit9/bit17";
1341         case I915_BIT_6_SWIZZLE_9_10_17:
1342                 return "bit9/bit10/bit17";
1343         case I915_BIT_6_SWIZZLE_UNKNOWN:
1344                 return "unknown";
1345         }
1346
1347         return "bug";
1348 }
1349
1350 static int i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data)
1351 {
1352         struct drm_i915_private *dev_priv;
1353         int ret;
1354
1355         dev_priv = dev->dev_private;
1356         ret = sx_xlock_sig(&dev->dev_struct_lock);
1357         if (ret != 0)
1358                 return -EINTR;
1359
1360         sbuf_printf(m, "bit6 swizzle for X-tiling = %s\n",
1361                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1362         sbuf_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1363                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1364
1365         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1366                 sbuf_printf(m, "DDC = 0x%08x\n",
1367                            I915_READ(DCC));
1368                 sbuf_printf(m, "C0DRB3 = 0x%04x\n",
1369                            I915_READ16(C0DRB3));
1370                 sbuf_printf(m, "C1DRB3 = 0x%04x\n",
1371                            I915_READ16(C1DRB3));
1372         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1373                 sbuf_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1374                            I915_READ(MAD_DIMM_C0));
1375                 sbuf_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1376                            I915_READ(MAD_DIMM_C1));
1377                 sbuf_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1378                            I915_READ(MAD_DIMM_C2));
1379                 sbuf_printf(m, "TILECTL = 0x%08x\n",
1380                            I915_READ(TILECTL));
1381                 sbuf_printf(m, "ARB_MODE = 0x%08x\n",
1382                            I915_READ(ARB_MODE));
1383                 sbuf_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1384                            I915_READ(DISP_ARB_CTL));
1385         }
1386         DRM_UNLOCK(dev);
1387
1388         return 0;
1389 }
1390
1391 static int i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data)
1392 {
1393         struct drm_i915_private *dev_priv;
1394         struct intel_ring_buffer *ring;
1395         int i, ret;
1396
1397         dev_priv = dev->dev_private;
1398
1399         ret = sx_xlock_sig(&dev->dev_struct_lock);
1400         if (ret != 0)
1401                 return -EINTR;
1402         if (INTEL_INFO(dev)->gen == 6)
1403                 sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1404
1405         for (i = 0; i < I915_NUM_RINGS; i++) {
1406                 ring = &dev_priv->rings[i];
1407
1408                 sbuf_printf(m, "%s\n", ring->name);
1409                 if (INTEL_INFO(dev)->gen == 7)
1410                         sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1411                 sbuf_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1412                 sbuf_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1413                 sbuf_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1414         }
1415         if (dev_priv->mm.aliasing_ppgtt) {
1416                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1417
1418                 sbuf_printf(m, "aliasing PPGTT:\n");
1419                 sbuf_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1420         }
1421         sbuf_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1422         DRM_UNLOCK(dev);
1423
1424         return 0;
1425 }
1426
1427 static int i915_dpio_info(struct drm_device *dev, struct sbuf *m, void *data)
1428 {
1429         struct drm_i915_private *dev_priv;
1430         int ret;
1431
1432         if (!IS_VALLEYVIEW(dev)) {
1433                 sbuf_printf(m, "unsupported\n");
1434                 return 0;
1435         }
1436
1437         dev_priv = dev->dev_private;
1438
1439         ret = sx_xlock_sig(&dev->mode_config.mutex);
1440         if (ret != 0)
1441                 return -EINTR;
1442
1443         sbuf_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1444
1445         sbuf_printf(m, "DPIO_DIV_A: 0x%08x\n",
1446                    intel_dpio_read(dev_priv, _DPIO_DIV_A));
1447         sbuf_printf(m, "DPIO_DIV_B: 0x%08x\n",
1448                    intel_dpio_read(dev_priv, _DPIO_DIV_B));
1449
1450         sbuf_printf(m, "DPIO_REFSFR_A: 0x%08x\n",
1451                    intel_dpio_read(dev_priv, _DPIO_REFSFR_A));
1452         sbuf_printf(m, "DPIO_REFSFR_B: 0x%08x\n",
1453                    intel_dpio_read(dev_priv, _DPIO_REFSFR_B));
1454
1455         sbuf_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n",
1456                    intel_dpio_read(dev_priv, _DPIO_CORE_CLK_A));
1457         sbuf_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n",
1458                    intel_dpio_read(dev_priv, _DPIO_CORE_CLK_B));
1459
1460         sbuf_printf(m, "DPIO_LFP_COEFF_A: 0x%08x\n",
1461                    intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_A));
1462         sbuf_printf(m, "DPIO_LFP_COEFF_B: 0x%08x\n",
1463                    intel_dpio_read(dev_priv, _DPIO_LFP_COEFF_B));
1464
1465         sbuf_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1466                    intel_dpio_read(dev_priv, DPIO_FASTCLK_DISABLE));
1467
1468         sx_xunlock(&dev->mode_config.mutex);
1469
1470         return 0;
1471 }
1472
1473 static int
1474 i915_debug_set_wedged(SYSCTL_HANDLER_ARGS)
1475 {
1476         struct drm_device *dev;
1477         drm_i915_private_t *dev_priv;
1478         int error, wedged;
1479
1480         dev = arg1;
1481         dev_priv = dev->dev_private;
1482         if (dev_priv == NULL)
1483                 return (EBUSY);
1484         wedged = dev_priv->mm.wedged;
1485         error = sysctl_handle_int(oidp, &wedged, 0, req);
1486         if (error || !req->newptr)
1487                 return (error);
1488         DRM_INFO("Manually setting wedged to %d\n", wedged);
1489         i915_handle_error(dev, wedged);
1490         return (error);
1491 }
1492
1493 static int
1494 i915_max_freq(SYSCTL_HANDLER_ARGS)
1495 {
1496         struct drm_device *dev;
1497         drm_i915_private_t *dev_priv;
1498         int error, max_freq;
1499
1500         dev = arg1;
1501         dev_priv = dev->dev_private;
1502         if (dev_priv == NULL)
1503                 return (EBUSY);
1504         max_freq = dev_priv->max_delay * 50;
1505         error = sysctl_handle_int(oidp, &max_freq, 0, req);
1506         if (error || !req->newptr)
1507                 return (error);
1508         DRM_DEBUG("Manually setting max freq to %d\n", max_freq);
1509         /*
1510          * Turbo will still be enabled, but won't go above the set value.
1511          */
1512         dev_priv->max_delay = max_freq / 50;
1513         gen6_set_rps(dev, max_freq / 50);
1514         return (error);
1515 }
1516
1517 static int
1518 i915_cache_sharing(SYSCTL_HANDLER_ARGS)
1519 {
1520         struct drm_device *dev;
1521         drm_i915_private_t *dev_priv;
1522         int error, snpcr, cache_sharing;
1523
1524         dev = arg1;
1525         dev_priv = dev->dev_private;
1526         if (dev_priv == NULL)
1527                 return (EBUSY);
1528         DRM_LOCK(dev);
1529         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1530         DRM_UNLOCK(dev);
1531         cache_sharing = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1532         error = sysctl_handle_int(oidp, &cache_sharing, 0, req);
1533         if (error || !req->newptr)
1534                 return (error);
1535         if (cache_sharing < 0 || cache_sharing > 3)
1536                 return (EINVAL);
1537         DRM_DEBUG("Manually setting uncore sharing to %d\n", cache_sharing);
1538
1539         DRM_LOCK(dev);
1540         /* Update the cache sharing policy here as well */
1541         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1542         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1543         snpcr |= (cache_sharing << GEN6_MBC_SNPCR_SHIFT);
1544         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1545         DRM_UNLOCK(dev);
1546         return (0);
1547 }
1548
1549 static int
1550 i915_stop_rings(SYSCTL_HANDLER_ARGS)
1551 {
1552         struct drm_device *dev;
1553         drm_i915_private_t *dev_priv;
1554         int error, val;
1555
1556         dev = arg1;
1557         dev_priv = dev->dev_private;
1558         if (dev_priv == NULL)
1559                 return (EBUSY);
1560         DRM_LOCK(dev);
1561         val = dev_priv->stop_rings;
1562         DRM_UNLOCK(dev);
1563         error = sysctl_handle_int(oidp, &val, 0, req);
1564         if (error || !req->newptr)
1565                 return (error);
1566         DRM_DEBUG("Stopping rings 0x%08x\n", val);
1567
1568         DRM_LOCK(dev);
1569         dev_priv->stop_rings = val;
1570         DRM_UNLOCK(dev);
1571         return (0);
1572 }
1573
1574 static struct i915_info_sysctl_list {
1575         const char *name;
1576         int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data);
1577         int (*ptr_w)(struct drm_device *dev, const char *str, void *data);
1578         int flags;
1579         void *data;
1580 } i915_info_sysctl_list[] = {
1581         {"i915_capabilities", i915_capabilities, NULL, 0},
1582         {"i915_gem_objects", i915_gem_object_info, NULL, 0},
1583         {"i915_gem_gtt", i915_gem_gtt_info, NULL, 0},
1584         {"i915_gem_pinned", i915_gem_gtt_info, NULL, 0, (void *)PINNED_LIST},
1585         {"i915_gem_active", i915_gem_object_list_info, NULL, 0,
1586             (void *)ACTIVE_LIST},
1587         {"i915_gem_flushing", i915_gem_object_list_info, NULL, 0,
1588             (void *)FLUSHING_LIST},
1589         {"i915_gem_inactive", i915_gem_object_list_info, NULL, 0,
1590             (void *)INACTIVE_LIST},
1591         {"i915_gem_pageflip", i915_gem_pageflip_info, NULL, 0},
1592         {"i915_gem_request", i915_gem_request_info, NULL, 0},
1593         {"i915_gem_seqno", i915_gem_seqno_info, NULL, 0},
1594         {"i915_gem_fence_regs", i915_gem_fence_regs_info, NULL, 0},
1595         {"i915_gem_interrupt", i915_interrupt_info, NULL, 0},
1596         {"i915_gem_hws", i915_hws_info, NULL, 0, (void *)RCS},
1597         {"i915_gem_hws_blt", i915_hws_info, NULL, 0, (void *)BCS},
1598         {"i915_gem_hws_bsd", i915_hws_info, NULL, 0, (void *)VCS},
1599         {"i915_error_state", i915_error_state, i915_error_state_w, 0},
1600         {"i915_rstdby_delays", i915_rstdby_delays, NULL, 0},
1601         {"i915_cur_delayinfo", i915_cur_delayinfo, NULL, 0},
1602         {"i915_delayfreq_table", i915_delayfreq_table, NULL, 0},
1603         {"i915_inttoext_table", i915_inttoext_table, NULL, 0},
1604         {"i915_drpc_info", i915_drpc_info, NULL, 0},
1605         {"i915_emon_status", i915_emon_status, NULL, 0},
1606         {"i915_ring_freq_table", i915_ring_freq_table, NULL, 0},
1607         {"i915_gfxec", i915_gfxec, NULL, 0},
1608         {"i915_fbc_status", i915_fbc_status, NULL, 0},
1609         {"i915_sr_status", i915_sr_status, NULL, 0},
1610 #if 0
1611         {"i915_opregion", i915_opregion, NULL, 0},
1612 #endif
1613         {"i915_gem_framebuffer", i915_gem_framebuffer_info, NULL, 0},
1614         {"i915_context_status", i915_context_status, NULL, 0},
1615         {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info,
1616             NULL, 0},
1617         {"i915_swizzle_info", i915_swizzle_info, NULL, 0},
1618         {"i915_ppgtt_info", i915_ppgtt_info, NULL, 0},
1619         {"i915_dpio", i915_dpio_info, NULL, 0},
1620 };
1621
1622 struct i915_info_sysctl_thunk {
1623         struct drm_device *dev;
1624         int idx;
1625         void *arg;
1626 };
1627
1628 static int
1629 i915_info_sysctl_handler(SYSCTL_HANDLER_ARGS)
1630 {
1631         struct sbuf m;
1632         struct i915_info_sysctl_thunk *thunk;
1633         struct drm_device *dev;
1634         drm_i915_private_t *dev_priv;
1635         char *p;
1636         int error;
1637
1638         thunk = arg1;
1639         dev = thunk->dev;
1640         dev_priv = dev->dev_private;
1641         if (dev_priv == NULL)
1642                 return (EBUSY);
1643         error = sysctl_wire_old_buffer(req, 0);
1644         if (error != 0)
1645                 return (error);
1646         sbuf_new_for_sysctl(&m, NULL, 128, req);
1647         error = -i915_info_sysctl_list[thunk->idx].ptr(dev, &m,
1648             thunk->arg);
1649         if (error == 0)
1650                 error = sbuf_finish(&m);
1651         sbuf_delete(&m);
1652         if (error != 0 || req->newptr == NULL)
1653                 return (error);
1654         if (req->newlen > 2048)
1655                 return (E2BIG);
1656         p = malloc(req->newlen + 1, M_TEMP, M_WAITOK);
1657         error = SYSCTL_IN(req, p, req->newlen);
1658         if (error != 0)
1659                 goto out;
1660         p[req->newlen] = '\0';
1661         error = i915_info_sysctl_list[thunk->idx].ptr_w(dev, p,
1662             thunk->arg);
1663 out:
1664         free(p, M_TEMP);
1665         return (error);
1666 }
1667
1668 extern int i915_gem_sync_exec_requests;
1669 extern int i915_fix_mi_batchbuffer_end;
1670 extern int i915_intr_pf;
1671 extern long i915_gem_wired_pages_cnt;
1672
1673 int
1674 i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1675     struct sysctl_oid *top)
1676 {
1677         struct sysctl_oid *oid, *info;
1678         struct i915_info_sysctl_thunk *thunks;
1679         int i, error;
1680
1681         thunks = malloc(sizeof(*thunks) * ARRAY_SIZE(i915_info_sysctl_list),
1682             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1683         for (i = 0; i < ARRAY_SIZE(i915_info_sysctl_list); i++) {
1684                 thunks[i].dev = dev;
1685                 thunks[i].idx = i;
1686                 thunks[i].arg = i915_info_sysctl_list[i].data;
1687         }
1688         dev->sysctl_private = thunks;
1689         info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info",
1690             CTLFLAG_RW, NULL, NULL);
1691         if (info == NULL)
1692                 return (-ENOMEM);
1693         for (i = 0; i < ARRAY_SIZE(i915_info_sysctl_list); i++) {
1694                 oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1695                     i915_info_sysctl_list[i].name, CTLTYPE_STRING |
1696                     (i915_info_sysctl_list[i].ptr_w != NULL ? CTLFLAG_RW :
1697                     CTLFLAG_RD),
1698                     &thunks[i], 0, i915_info_sysctl_handler, "A", NULL);
1699                 if (oid == NULL)
1700                         return (-ENOMEM);
1701         }
1702         oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1703             "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt,
1704             NULL);
1705         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "wedged",
1706             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0,
1707             i915_debug_set_wedged, "I", NULL);
1708         if (oid == NULL)
1709                 return (-ENOMEM);
1710         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq",
1711             CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, i915_max_freq,
1712             "I", NULL);
1713         if (oid == NULL)
1714                 return (-ENOMEM);
1715         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1716             "cache_sharing", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev,
1717             0, i915_cache_sharing, "I", NULL);
1718         if (oid == NULL)
1719                 return (-ENOMEM);
1720         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1721             "stop_rings", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev,
1722             0, i915_stop_rings, "I", NULL);
1723         if (oid == NULL)
1724                 return (-ENOMEM);
1725         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "sync_exec",
1726             CTLFLAG_RW, &i915_gem_sync_exec_requests, 0, NULL);
1727         if (oid == NULL)
1728                 return (-ENOMEM);
1729         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "fix_mi",
1730             CTLFLAG_RW, &i915_fix_mi_batchbuffer_end, 0, NULL);
1731         if (oid == NULL)
1732                 return (-ENOMEM);
1733         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf",
1734             CTLFLAG_RW, &i915_intr_pf, 0, NULL);
1735         if (oid == NULL)
1736                 return (-ENOMEM);
1737
1738         error = drm_add_busid_modesetting(dev, ctx, top);
1739         if (error != 0)
1740                 return (error);
1741
1742         return (0);
1743 }
1744
1745 void
1746 i915_sysctl_cleanup(struct drm_device *dev)
1747 {
1748
1749         free(dev->sysctl_private, DRM_MEM_DRIVER);
1750 }