sys/dev/drm2/radeon/r600_cs.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <dev/drm2/drmP.h>
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r600d.h"
  36 #include "r600_reg_safe.h"
  37 #include "r600_cp.h"
  38 #include "r600_cs.h"
  39
  40 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
  41                                         struct radeon_cs_reloc **cs_reloc);
  42 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
  43                                         struct radeon_cs_reloc **cs_reloc);
  44 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
  45 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
  46 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
  47 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
  48 #endif
  49
  50
  51 struct r600_cs_track {
  52         /* configuration we miror so that we use same code btw kms/ums */
  53         u32                     group_size;
  54         u32                     nbanks;
  55         u32                     npipes;
  56         /* value we track */
  57         u32                     sq_config;
  58         u32                     log_nsamples;
  59         u32                     nsamples;
  60         u32                     cb_color_base_last[8];
  61         struct radeon_bo        *cb_color_bo[8];
  62         u64                     cb_color_bo_mc[8];
  63         u64                     cb_color_bo_offset[8];
  64         struct radeon_bo        *cb_color_frag_bo[8];
  65         u64                     cb_color_frag_offset[8];
  66         struct radeon_bo        *cb_color_tile_bo[8];
  67         u64                     cb_color_tile_offset[8];
  68         u32                     cb_color_mask[8];
  69         u32                     cb_color_info[8];
  70         u32                     cb_color_view[8];
  71         u32                     cb_color_size_idx[8]; /* unused */
  72         u32                     cb_target_mask;
  73         u32                     cb_shader_mask;  /* unused */
  74         bool                    is_resolve;
  75         u32                     cb_color_size[8];
  76         u32                     vgt_strmout_en;
  77         u32                     vgt_strmout_buffer_en;
  78         struct radeon_bo        *vgt_strmout_bo[4];
  79         u64                     vgt_strmout_bo_mc[4]; /* unused */
  80         u32                     vgt_strmout_bo_offset[4];
  81         u32                     vgt_strmout_size[4];
  82         u32                     db_depth_control;
  83         u32                     db_depth_info;
  84         u32                     db_depth_size_idx;
  85         u32                     db_depth_view;
  86         u32                     db_depth_size;
  87         u32                     db_offset;
  88         struct radeon_bo        *db_bo;
  89         u64                     db_bo_mc;
  90         bool                    sx_misc_kill_all_prims;
  91         bool                    cb_dirty;
  92         bool                    db_dirty;
  93         bool                    streamout_dirty;
  94         struct radeon_bo        *htile_bo;
  95         u64                     htile_offset;
  96         u32                     htile_surface;
  97 };
  98
  99 #define FMT_8_BIT(fmt, vc)   [fmt] = { 1, 1, 1, vc, CHIP_R600 }
 100 #define FMT_16_BIT(fmt, vc)  [fmt] = { 1, 1, 2, vc, CHIP_R600 }
 101 #define FMT_24_BIT(fmt)      [fmt] = { 1, 1, 4,  0, CHIP_R600 }
 102 #define FMT_32_BIT(fmt, vc)  [fmt] = { 1, 1, 4, vc, CHIP_R600 }
 103 #define FMT_48_BIT(fmt)      [fmt] = { 1, 1, 8,  0, CHIP_R600 }
 104 #define FMT_64_BIT(fmt, vc)  [fmt] = { 1, 1, 8, vc, CHIP_R600 }
 105 #define FMT_96_BIT(fmt)      [fmt] = { 1, 1, 12, 0, CHIP_R600 }
 106 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
 107
 108 struct gpu_formats {
 109         unsigned blockwidth;
 110         unsigned blockheight;
 111         unsigned blocksize;
 112         unsigned valid_color;
 113         enum radeon_family min_family;
 114 };
 115
 116 static const struct gpu_formats color_formats_table[] = {
 117         /* 8 bit */
 118         FMT_8_BIT(V_038004_COLOR_8, 1),
 119         FMT_8_BIT(V_038004_COLOR_4_4, 1),
 120         FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
 121         FMT_8_BIT(V_038004_FMT_1, 0),
 122
 123         /* 16-bit */
 124         FMT_16_BIT(V_038004_COLOR_16, 1),
 125         FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
 126         FMT_16_BIT(V_038004_COLOR_8_8, 1),
 127         FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
 128         FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
 129         FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
 130         FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
 131         FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
 132
 133         /* 24-bit */
 134         FMT_24_BIT(V_038004_FMT_8_8_8),
 135
 136         /* 32-bit */
 137         FMT_32_BIT(V_038004_COLOR_32, 1),
 138         FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
 139         FMT_32_BIT(V_038004_COLOR_16_16, 1),
 140         FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
 141         FMT_32_BIT(V_038004_COLOR_8_24, 1),
 142         FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
 143         FMT_32_BIT(V_038004_COLOR_24_8, 1),
 144         FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
 145         FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
 146         FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
 147         FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
 148         FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
 149         FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
 150         FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
 151         FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
 152         FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
 153         FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
 154         FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
 155
 156         /* 48-bit */
 157         FMT_48_BIT(V_038004_FMT_16_16_16),
 158         FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
 159
 160         /* 64-bit */
 161         FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
 162         FMT_64_BIT(V_038004_COLOR_32_32, 1),
 163         FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
 164         FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
 165         FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
 166
 167         FMT_96_BIT(V_038004_FMT_32_32_32),
 168         FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
 169
 170         /* 128-bit */
 171         FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
 172         FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
 173
 174         [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
 175         [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
 176
 177         /* block compressed formats */
 178         [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
 179         [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
 180         [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
 181         [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
 182         [V_038004_FMT_BC5] = { 4, 4, 16, 0},
 183         [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 184         [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
 185
 186         /* The other Evergreen formats */
 187         [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
 188 };
 189
 190 bool r600_fmt_is_valid_color(u32 format)
 191 {
 192         if (format >= ARRAY_SIZE(color_formats_table))
 193                 return false;
 194
 195         if (color_formats_table[format].valid_color)
 196                 return true;
 197
 198         return false;
 199 }
 200
 201 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 202 {
 203         if (format >= ARRAY_SIZE(color_formats_table))
 204                 return false;
 205
 206         if (family < color_formats_table[format].min_family)
 207                 return false;
 208
 209         if (color_formats_table[format].blockwidth > 0)
 210                 return true;
 211
 212         return false;
 213 }
 214
 215 int r600_fmt_get_blocksize(u32 format)
 216 {
 217         if (format >= ARRAY_SIZE(color_formats_table))
 218                 return 0;
 219
 220         return color_formats_table[format].blocksize;
 221 }
 222
 223 int r600_fmt_get_nblocksx(u32 format, u32 w)
 224 {
 225         unsigned bw;
 226
 227         if (format >= ARRAY_SIZE(color_formats_table))
 228                 return 0;
 229
 230         bw = color_formats_table[format].blockwidth;
 231         if (bw == 0)
 232                 return 0;
 233
 234         return (w + bw - 1) / bw;
 235 }
 236
 237 int r600_fmt_get_nblocksy(u32 format, u32 h)
 238 {
 239         unsigned bh;
 240
 241         if (format >= ARRAY_SIZE(color_formats_table))
 242                 return 0;
 243
 244         bh = color_formats_table[format].blockheight;
 245         if (bh == 0)
 246                 return 0;
 247
 248         return (h + bh - 1) / bh;
 249 }
 250
 251 struct array_mode_checker {
 252         int array_mode;
 253         u32 group_size;
 254         u32 nbanks;
 255         u32 npipes;
 256         u32 nsamples;
 257         u32 blocksize;
 258 };
 259
 260 /* returns alignment in pixels for pitch/height/depth and bytes for base */
 261 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
 262                                                 u32 *pitch_align,
 263                                                 u32 *height_align,
 264                                                 u32 *depth_align,
 265                                                 u64 *base_align)
 266 {
 267         u32 tile_width = 8;
 268         u32 tile_height = 8;
 269         u32 macro_tile_width = values->nbanks;
 270         u32 macro_tile_height = values->npipes;
 271         u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
 272         u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
 273
 274         switch (values->array_mode) {
 275         case ARRAY_LINEAR_GENERAL:
 276                 /* technically tile_width/_height for pitch/height */
 277                 *pitch_align = 1; /* tile_width */
 278                 *height_align = 1; /* tile_height */
 279                 *depth_align = 1;
 280                 *base_align = 1;
 281                 break;
 282         case ARRAY_LINEAR_ALIGNED:
 283                 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
 284                 *height_align = 1;
 285                 *depth_align = 1;
 286                 *base_align = values->group_size;
 287                 break;
 288         case ARRAY_1D_TILED_THIN1:
 289                 *pitch_align = max((u32)tile_width,
 290                                    (u32)(values->group_size /
 291                                          (tile_height * values->blocksize * values->nsamples)));
 292                 *height_align = tile_height;
 293                 *depth_align = 1;
 294                 *base_align = values->group_size;
 295                 break;
 296         case ARRAY_2D_TILED_THIN1:
 297                 *pitch_align = max((u32)macro_tile_width * tile_width,
 298                                 (u32)((values->group_size * values->nbanks) /
 299                                 (values->blocksize * values->nsamples * tile_width)));
 300                 *height_align = macro_tile_height * tile_height;
 301                 *depth_align = 1;
 302                 *base_align = max(macro_tile_bytes,
 303                                   (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
 304                 break;
 305         default:
 306                 return -EINVAL;
 307         }
 308
 309         return 0;
 310 }
 311
 312 static void r600_cs_track_init(struct r600_cs_track *track)
 313 {
 314         int i;
 315
 316         /* assume DX9 mode */
 317         track->sq_config = DX9_CONSTS;
 318         for (i = 0; i < 8; i++) {
 319                 track->cb_color_base_last[i] = 0;
 320                 track->cb_color_size[i] = 0;
 321                 track->cb_color_size_idx[i] = 0;
 322                 track->cb_color_info[i] = 0;
 323                 track->cb_color_view[i] = 0xFFFFFFFF;
 324                 track->cb_color_bo[i] = NULL;
 325                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 326                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
 327                 track->cb_color_frag_bo[i] = NULL;
 328                 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
 329                 track->cb_color_tile_bo[i] = NULL;
 330                 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
 331                 track->cb_color_mask[i] = 0xFFFFFFFF;
 332         }
 333         track->is_resolve = false;
 334         track->nsamples = 16;
 335         track->log_nsamples = 4;
 336         track->cb_target_mask = 0xFFFFFFFF;
 337         track->cb_shader_mask = 0xFFFFFFFF;
 338         track->cb_dirty = true;
 339         track->db_bo = NULL;
 340         track->db_bo_mc = 0xFFFFFFFF;
 341         /* assume the biggest format and that htile is enabled */
 342         track->db_depth_info = 7 | (1 << 25);
 343         track->db_depth_view = 0xFFFFC000;
 344         track->db_depth_size = 0xFFFFFFFF;
 345         track->db_depth_size_idx = 0;
 346         track->db_depth_control = 0xFFFFFFFF;
 347         track->db_dirty = true;
 348         track->htile_bo = NULL;
 349         track->htile_offset = 0xFFFFFFFF;
 350         track->htile_surface = 0;
 351
 352         for (i = 0; i < 4; i++) {
 353                 track->vgt_strmout_size[i] = 0;
 354                 track->vgt_strmout_bo[i] = NULL;
 355                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 356                 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
 357         }
 358         track->streamout_dirty = true;
 359         track->sx_misc_kill_all_prims = false;
 360 }
 361
 362 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 363 {
 364         struct r600_cs_track *track = p->track;
 365         u32 slice_tile_max, size, tmp;
 366         u32 height, height_align, pitch, pitch_align, depth_align;
 367         u64 base_offset, base_align;
 368         struct array_mode_checker array_check;
 369         volatile u32 *ib = p->ib.ptr;
 370         unsigned array_mode;
 371         u32 format;
 372         /* When resolve is used, the second colorbuffer has always 1 sample. */
 373         unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
 374
 375         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
 376         format = G_0280A0_FORMAT(track->cb_color_info[i]);
 377         if (!r600_fmt_is_valid_color(format)) {
 378                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
 379                          __func__, __LINE__, format,
 380                         i, track->cb_color_info[i]);
 381                 return -EINVAL;
 382         }
 383         /* pitch in pixels */
 384         pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
 385         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
 386         slice_tile_max *= 64;
 387         height = slice_tile_max / pitch;
 388         if (height > 8192)
 389                 height = 8192;
 390         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
 391
 392         base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
 393         array_check.array_mode = array_mode;
 394         array_check.group_size = track->group_size;
 395         array_check.nbanks = track->nbanks;
 396         array_check.npipes = track->npipes;
 397         array_check.nsamples = nsamples;
 398         array_check.blocksize = r600_fmt_get_blocksize(format);
 399         if (r600_get_array_mode_alignment(&array_check,
 400                                           &pitch_align, &height_align, &depth_align, &base_align)) {
 401                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 402                          G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 403                          track->cb_color_info[i]);
 404                 return -EINVAL;
 405         }
 406         switch (array_mode) {
 407         case V_0280A0_ARRAY_LINEAR_GENERAL:
 408                 break;
 409         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 410                 break;
 411         case V_0280A0_ARRAY_1D_TILED_THIN1:
 412                 /* avoid breaking userspace */
 413                 if (height > 7)
 414                         height &= ~0x7;
 415                 break;
 416         case V_0280A0_ARRAY_2D_TILED_THIN1:
 417                 break;
 418         default:
 419                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
 420                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
 421                         track->cb_color_info[i]);
 422                 return -EINVAL;
 423         }
 424
 425         if (!IS_ALIGNED(pitch, pitch_align)) {
 426                 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
 427                          __func__, __LINE__, pitch, pitch_align, array_mode);
 428                 return -EINVAL;
 429         }
 430         if (!IS_ALIGNED(height, height_align)) {
 431                 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
 432                          __func__, __LINE__, height, height_align, array_mode);
 433                 return -EINVAL;
 434         }
 435         if (!IS_ALIGNED(base_offset, base_align)) {
 436                 dev_warn(p->dev, "%s offset[%d] 0x%jx 0x%jx, %d not aligned\n", __func__, i,
 437                          (uintmax_t)base_offset, (uintmax_t)base_align, array_mode);
 438                 return -EINVAL;
 439         }
 440
 441         /* check offset */
 442         tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
 443               r600_fmt_get_blocksize(format) * nsamples;
 444         switch (array_mode) {
 445         default:
 446         case V_0280A0_ARRAY_LINEAR_GENERAL:
 447         case V_0280A0_ARRAY_LINEAR_ALIGNED:
 448                 tmp += track->cb_color_view[i] & 0xFF;
 449                 break;
 450         case V_0280A0_ARRAY_1D_TILED_THIN1:
 451         case V_0280A0_ARRAY_2D_TILED_THIN1:
 452                 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
 453                 break;
 454         }
 455         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
 456                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
 457                         /* the initial DDX does bad things with the CB size occasionally */
 458                         /* it rounds up height too far for slice tile max but the BO is smaller */
 459                         /* r600c,g also seem to flush at bad times in some apps resulting in
 460                          * bogus values here. So for linear just allow anything to avoid breaking
 461                          * broken userspace.
 462                          */
 463                 } else {
 464                         dev_warn(p->dev, "%s offset[%d] %d %ju %d %lu too big (%d %d) (%d %d %d)\n",
 465                                  __func__, i, array_mode,
 466                                  (uintmax_t)track->cb_color_bo_offset[i], tmp,
 467                                  radeon_bo_size(track->cb_color_bo[i]),
 468                                  pitch, height, r600_fmt_get_nblocksx(format, pitch),
 469                                  r600_fmt_get_nblocksy(format, height),
 470                                  r600_fmt_get_blocksize(format));
 471                         return -EINVAL;
 472                 }
 473         }
 474         /* limit max tile */
 475         tmp = (height * pitch) >> 6;
 476         if (tmp < slice_tile_max)
 477                 slice_tile_max = tmp;
 478         tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
 479                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
 480         ib[track->cb_color_size_idx[i]] = tmp;
 481
 482         /* FMASK/CMASK */
 483         switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
 484         case V_0280A0_TILE_DISABLE:
 485                 break;
 486         case V_0280A0_FRAG_ENABLE:
 487                 if (track->nsamples > 1) {
 488                         uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
 489                         /* the tile size is 8x8, but the size is in units of bits.
 490                          * for bytes, do just * 8. */
 491                         uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
 492
 493                         if (bytes + track->cb_color_frag_offset[i] >
 494                             radeon_bo_size(track->cb_color_frag_bo[i])) {
 495                                 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
 496                                          "(tile_max=%u, bytes=%u, offset=%ju, bo_size=%lu)\n",
 497                                          __func__, tile_max, bytes,
 498                                          (uintmax_t)track->cb_color_frag_offset[i],
 499                                          radeon_bo_size(track->cb_color_frag_bo[i]));
 500                                 return -EINVAL;
 501                         }
 502                 }
 503                 /* fall through */
 504         case V_0280A0_CLEAR_ENABLE:
 505         {
 506                 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
 507                 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
 508                  * (128*128) / (8*8) / 2 = 128 bytes per block. */
 509                 uint32_t bytes = (block_max + 1) * 128;
 510
 511                 if (bytes + track->cb_color_tile_offset[i] >
 512                     radeon_bo_size(track->cb_color_tile_bo[i])) {
 513                         dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
 514                                  "(block_max=%u, bytes=%u, offset=%ju, bo_size=%lu)\n",
 515                                  __func__, block_max, bytes,
 516                                  (uintmax_t)track->cb_color_tile_offset[i],
 517                                  radeon_bo_size(track->cb_color_tile_bo[i]));
 518                         return -EINVAL;
 519                 }
 520                 break;
 521         }
 522         default:
 523                 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
 524                 return -EINVAL;
 525         }
 526         return 0;
 527 }
 528
 529 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
 530 {
 531         struct r600_cs_track *track = p->track;
 532         u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
 533         u32 height_align, pitch_align, depth_align;
 534         u32 pitch = 8192;
 535         u32 height = 8192;
 536         u64 base_offset, base_align;
 537         struct array_mode_checker array_check;
 538         int array_mode;
 539         volatile u32 *ib = p->ib.ptr;
 540
 541
 542         if (track->db_bo == NULL) {
 543                 dev_warn(p->dev, "z/stencil with no depth buffer\n");
 544                 return -EINVAL;
 545         }
 546         switch (G_028010_FORMAT(track->db_depth_info)) {
 547         case V_028010_DEPTH_16:
 548                 bpe = 2;
 549                 break;
 550         case V_028010_DEPTH_X8_24:
 551         case V_028010_DEPTH_8_24:
 552         case V_028010_DEPTH_X8_24_FLOAT:
 553         case V_028010_DEPTH_8_24_FLOAT:
 554         case V_028010_DEPTH_32_FLOAT:
 555                 bpe = 4;
 556                 break;
 557         case V_028010_DEPTH_X24_8_32_FLOAT:
 558                 bpe = 8;
 559                 break;
 560         default:
 561                 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
 562                 return -EINVAL;
 563         }
 564         if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 565                 if (!track->db_depth_size_idx) {
 566                         dev_warn(p->dev, "z/stencil buffer size not set\n");
 567                         return -EINVAL;
 568                 }
 569                 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
 570                 tmp = (tmp / bpe) >> 6;
 571                 if (!tmp) {
 572                         dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
 573                                         track->db_depth_size, bpe, track->db_offset,
 574                                         radeon_bo_size(track->db_bo));
 575                         return -EINVAL;
 576                 }
 577                 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
 578         } else {
 579                 size = radeon_bo_size(track->db_bo);
 580                 /* pitch in pixels */
 581                 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
 582                 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 583                 slice_tile_max *= 64;
 584                 height = slice_tile_max / pitch;
 585                 if (height > 8192)
 586                         height = 8192;
 587                 base_offset = track->db_bo_mc + track->db_offset;
 588                 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
 589                 array_check.array_mode = array_mode;
 590                 array_check.group_size = track->group_size;
 591                 array_check.nbanks = track->nbanks;
 592                 array_check.npipes = track->npipes;
 593                 array_check.nsamples = track->nsamples;
 594                 array_check.blocksize = bpe;
 595                 if (r600_get_array_mode_alignment(&array_check,
 596                                         &pitch_align, &height_align, &depth_align, &base_align)) {
 597                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 598                                         G_028010_ARRAY_MODE(track->db_depth_info),
 599                                         track->db_depth_info);
 600                         return -EINVAL;
 601                 }
 602                 switch (array_mode) {
 603                 case V_028010_ARRAY_1D_TILED_THIN1:
 604                         /* don't break userspace */
 605                         height &= ~0x7;
 606                         break;
 607                 case V_028010_ARRAY_2D_TILED_THIN1:
 608                         break;
 609                 default:
 610                         dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
 611                                         G_028010_ARRAY_MODE(track->db_depth_info),
 612                                         track->db_depth_info);
 613                         return -EINVAL;
 614                 }
 615
 616                 if (!IS_ALIGNED(pitch, pitch_align)) {
 617                         dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
 618                                         __func__, __LINE__, pitch, pitch_align, array_mode);
 619                         return -EINVAL;
 620                 }
 621                 if (!IS_ALIGNED(height, height_align)) {
 622                         dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
 623                                         __func__, __LINE__, height, height_align, array_mode);
 624                         return -EINVAL;
 625                 }
 626                 if (!IS_ALIGNED(base_offset, base_align)) {
 627                         dev_warn(p->dev, "%s offset 0x%jx, 0x%jx, %d not aligned\n", __func__,
 628                                         (uintmax_t)base_offset, (uintmax_t)base_align, array_mode);
 629                         return -EINVAL;
 630                 }
 631
 632                 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
 633                 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
 634                 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
 635                 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
 636                         dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
 637                                         array_mode,
 638                                         track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
 639                                         radeon_bo_size(track->db_bo));
 640                         return -EINVAL;
 641                 }
 642         }
 643
 644         /* hyperz */
 645         if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
 646                 unsigned long size;
 647                 unsigned nbx, nby;
 648
 649                 if (track->htile_bo == NULL) {
 650                         dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
 651                                  __func__, __LINE__, track->db_depth_info);
 652                         return -EINVAL;
 653                 }
 654                 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
 655                         dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
 656                                  __func__, __LINE__, track->db_depth_size);
 657                         return -EINVAL;
 658                 }
 659
 660                 nbx = pitch;
 661                 nby = height;
 662                 if (G_028D24_LINEAR(track->htile_surface)) {
 663                         /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
 664                         nbx = roundup2(nbx, 16 * 8);
 665                         /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
 666                         nby = roundup(nby, track->npipes * 8);
 667                 } else {
 668                         /* always assume 8x8 htile */
 669                         /* align is htile align * 8, htile align vary according to
 670                          * number of pipe and tile width and nby
 671                          */
 672                         switch (track->npipes) {
 673                         case 8:
 674                                 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 675                                 nbx = roundup2(nbx, 64 * 8);
 676                                 nby = roundup2(nby, 64 * 8);
 677                                 break;
 678                         case 4:
 679                                 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 680                                 nbx = roundup2(nbx, 64 * 8);
 681                                 nby = roundup2(nby, 32 * 8);
 682                                 break;
 683                         case 2:
 684                                 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 685                                 nbx = roundup2(nbx, 32 * 8);
 686                                 nby = roundup2(nby, 32 * 8);
 687                                 break;
 688                         case 1:
 689                                 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 690                                 nbx = roundup2(nbx, 32 * 8);
 691                                 nby = roundup2(nby, 16 * 8);
 692                                 break;
 693                         default:
 694                                 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
 695                                          __func__, __LINE__, track->npipes);
 696                                 return -EINVAL;
 697                         }
 698                 }
 699                 /* compute number of htile */
 700                 nbx = nbx >> 3;
 701                 nby = nby >> 3;
 702                 /* size must be aligned on npipes * 2K boundary */
 703                 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
 704                 size += track->htile_offset;
 705
 706                 if (size > radeon_bo_size(track->htile_bo)) {
 707                         dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
 708                                  __func__, __LINE__, radeon_bo_size(track->htile_bo),
 709                                  size, nbx, nby);
 710                         return -EINVAL;
 711                 }
 712         }
 713
 714         track->db_dirty = false;
 715         return 0;
 716 }
 717
 718 static int r600_cs_track_check(struct radeon_cs_parser *p)
 719 {
 720         struct r600_cs_track *track = p->track;
 721         u32 tmp;
 722         int r, i;
 723
 724         /* on legacy kernel we don't perform advanced check */
 725         if (p->rdev == NULL)
 726                 return 0;
 727
 728         /* check streamout */
 729         if (track->streamout_dirty && track->vgt_strmout_en) {
 730                 for (i = 0; i < 4; i++) {
 731                         if (track->vgt_strmout_buffer_en & (1 << i)) {
 732                                 if (track->vgt_strmout_bo[i]) {
 733                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 734                                                 (u64)track->vgt_strmout_size[i];
 735                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 736                                                 DRM_ERROR("streamout %d bo too small: 0x%jx, 0x%lx\n",
 737                                                           i, (uintmax_t)offset,
 738                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
 739                                                 return -EINVAL;
 740                                         }
 741                                 } else {
 742                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
 743                                         return -EINVAL;
 744                                 }
 745                         }
 746                 }
 747                 track->streamout_dirty = false;
 748         }
 749
 750         if (track->sx_misc_kill_all_prims)
 751                 return 0;
 752
 753         /* check that we have a cb for each enabled target, we don't check
 754          * shader_mask because it seems mesa isn't always setting it :(
 755          */
 756         if (track->cb_dirty) {
 757                 tmp = track->cb_target_mask;
 758
 759                 /* We must check both colorbuffers for RESOLVE. */
 760                 if (track->is_resolve) {
 761                         tmp |= 0xff;
 762                 }
 763
 764                 for (i = 0; i < 8; i++) {
 765                         if ((tmp >> (i * 4)) & 0xF) {
 766                                 /* at least one component is enabled */
 767                                 if (track->cb_color_bo[i] == NULL) {
 768                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 769                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 770                                         return -EINVAL;
 771                                 }
 772                                 /* perform rewrite of CB_COLOR[0-7]_SIZE */
 773                                 r = r600_cs_track_validate_cb(p, i);
 774                                 if (r)
 775                                         return r;
 776                         }
 777                 }
 778                 track->cb_dirty = false;
 779         }
 780
 781         /* Check depth buffer */
 782         if (track->db_dirty &&
 783             G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
 784             (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
 785              G_028800_Z_ENABLE(track->db_depth_control))) {
 786                 r = r600_cs_track_validate_db(p);
 787                 if (r)
 788                         return r;
 789         }
 790
 791         return 0;
 792 }
 793
 794 /**
 795  * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
 796  * @parser:     parser structure holding parsing context.
 797  * @pkt:        where to store packet informations
 798  *
 799  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 800  * if packet is bigger than remaining ib size. or if packets is unknown.
 801  **/
 802 static int r600_cs_packet_parse(struct radeon_cs_parser *p,
 803                         struct radeon_cs_packet *pkt,
 804                         unsigned idx)
 805 {
 806         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 807         uint32_t header;
 808
 809         if (idx >= ib_chunk->length_dw) {
 810                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 811                           idx, ib_chunk->length_dw);
 812                 return -EINVAL;
 813         }
 814         header = radeon_get_ib_value(p, idx);
 815         pkt->idx = idx;
 816         pkt->type = CP_PACKET_GET_TYPE(header);
 817         pkt->count = CP_PACKET_GET_COUNT(header);
 818         pkt->one_reg_wr = 0;
 819         switch (pkt->type) {
 820         case PACKET_TYPE0:
 821                 pkt->reg = CP_PACKET0_GET_REG(header);
 822                 break;
 823         case PACKET_TYPE3:
 824                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 825                 break;
 826         case PACKET_TYPE2:
 827                 pkt->count = -1;
 828                 break;
 829         default:
 830                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 831                 return -EINVAL;
 832         }
 833         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 834                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 835                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 836                 return -EINVAL;
 837         }
 838         return 0;
 839 }
 840
 841 /**
 842  * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
 843  * @parser:             parser structure holding parsing context.
 844  * @data:               pointer to relocation data
 845  * @offset_start:       starting offset
 846  * @offset_mask:        offset mask (to align start offset on)
 847  * @reloc:              reloc informations
 848  *
 849  * Check next packet is relocation packet3, do bo validation and compute
 850  * GPU offset using the provided start.
 851  **/
 852 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
 853                                         struct radeon_cs_reloc **cs_reloc)
 854 {
 855         struct radeon_cs_chunk *relocs_chunk;
 856         struct radeon_cs_packet p3reloc;
 857         unsigned idx;
 858         int r;
 859
 860         if (p->chunk_relocs_idx == -1) {
 861                 DRM_ERROR("No relocation chunk !\n");
 862                 return -EINVAL;
 863         }
 864         *cs_reloc = NULL;
 865         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 866         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 867         if (r) {
 868                 return r;
 869         }
 870         p->idx += p3reloc.count + 2;
 871         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 872                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 873                           p3reloc.idx);
 874                 return -EINVAL;
 875         }
 876         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 877         if (idx >= relocs_chunk->length_dw) {
 878                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 879                           idx, relocs_chunk->length_dw);
 880                 return -EINVAL;
 881         }
 882         /* FIXME: we assume reloc size is 4 dwords */
 883         *cs_reloc = p->relocs_ptr[(idx / 4)];
 884         return 0;
 885 }
 886
 887 /**
 888  * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
 889  * @parser:             parser structure holding parsing context.
 890  * @data:               pointer to relocation data
 891  * @offset_start:       starting offset
 892  * @offset_mask:        offset mask (to align start offset on)
 893  * @reloc:              reloc informations
 894  *
 895  * Check next packet is relocation packet3, do bo validation and compute
 896  * GPU offset using the provided start.
 897  **/
 898 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
 899                                         struct radeon_cs_reloc **cs_reloc)
 900 {
 901         struct radeon_cs_chunk *relocs_chunk;
 902         struct radeon_cs_packet p3reloc;
 903         unsigned idx;
 904         int r;
 905
 906         if (p->chunk_relocs_idx == -1) {
 907                 DRM_ERROR("No relocation chunk !\n");
 908                 return -EINVAL;
 909         }
 910         *cs_reloc = NULL;
 911         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 912         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 913         if (r) {
 914                 return r;
 915         }
 916         p->idx += p3reloc.count + 2;
 917         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 918                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 919                           p3reloc.idx);
 920                 return -EINVAL;
 921         }
 922         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 923         if (idx >= relocs_chunk->length_dw) {
 924                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 925                           idx, relocs_chunk->length_dw);
 926                 return -EINVAL;
 927         }
 928         *cs_reloc = p->relocs;
 929         (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
 930         (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 931         return 0;
 932 }
 933
 934 /**
 935  * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
 936  * @parser:             parser structure holding parsing context.
 937  *
 938  * Check next packet is relocation packet3, do bo validation and compute
 939  * GPU offset using the provided start.
 940  **/
 941 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 942 {
 943         struct radeon_cs_packet p3reloc;
 944         int r;
 945
 946         r = r600_cs_packet_parse(p, &p3reloc, p->idx);
 947         if (r) {
 948                 return 0;
 949         }
 950         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 951                 return 0;
 952         }
 953         return 1;
 954 }
 955
 956 /**
 957  * r600_cs_packet_next_vline() - parse userspace VLINE packet
 958  * @parser:             parser structure holding parsing context.
 959  *
 960  * Userspace sends a special sequence for VLINE waits.
 961  * PACKET0 - VLINE_START_END + value
 962  * PACKET3 - WAIT_REG_MEM poll vline status reg
 963  * RELOC (P3) - crtc_id in reloc.
 964  *
 965  * This function parses this and relocates the VLINE START END
 966  * and WAIT_REG_MEM packets to the correct crtc.
 967  * It also detects a switched off crtc and nulls out the
 968  * wait in that case.
 969  */
 970 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
 971 {
 972         struct drm_mode_object *obj;
 973         struct drm_crtc *crtc;
 974         struct radeon_crtc *radeon_crtc;
 975         struct radeon_cs_packet p3reloc, wait_reg_mem;
 976         int crtc_id;
 977         int r;
 978         uint32_t header, h_idx, reg, wait_reg_mem_info;
 979         volatile uint32_t *ib;
 980
 981         ib = p->ib.ptr;
 982
 983         /* parse the WAIT_REG_MEM */
 984         r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
 985         if (r)
 986                 return r;
 987
 988         /* check its a WAIT_REG_MEM */
 989         if (wait_reg_mem.type != PACKET_TYPE3 ||
 990             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 991                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 992                 return -EINVAL;
 993         }
 994
 995         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 996         /* bit 4 is reg (0) or mem (1) */
 997         if (wait_reg_mem_info & 0x10) {
 998                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
 999                 return -EINVAL;
1000         }
1001         /* waiting for value to be equal */
1002         if ((wait_reg_mem_info & 0x7) != 0x3) {
1003                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1004                 return -EINVAL;
1005         }
1006         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
1007                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1008                 return -EINVAL;
1009         }
1010
1011         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
1012                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1013                 return -EINVAL;
1014         }
1015
1016         /* jump over the NOP */
1017         r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1018         if (r)
1019                 return r;
1020
1021         h_idx = p->idx - 2;
1022         p->idx += wait_reg_mem.count + 2;
1023         p->idx += p3reloc.count + 2;
1024
1025         header = radeon_get_ib_value(p, h_idx);
1026         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1027         reg = CP_PACKET0_GET_REG(header);
1028
1029         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1030         if (!obj) {
1031                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1032                 return -EINVAL;
1033         }
1034         crtc = obj_to_crtc(obj);
1035         radeon_crtc = to_radeon_crtc(crtc);
1036         crtc_id = radeon_crtc->crtc_id;
1037
1038         if (!crtc->enabled) {
1039                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1040                 ib[h_idx + 2] = PACKET2(0);
1041                 ib[h_idx + 3] = PACKET2(0);
1042                 ib[h_idx + 4] = PACKET2(0);
1043                 ib[h_idx + 5] = PACKET2(0);
1044                 ib[h_idx + 6] = PACKET2(0);
1045                 ib[h_idx + 7] = PACKET2(0);
1046                 ib[h_idx + 8] = PACKET2(0);
1047         } else if (crtc_id == 1) {
1048                 switch (reg) {
1049                 case AVIVO_D1MODE_VLINE_START_END:
1050                         header &= ~R600_CP_PACKET0_REG_MASK;
1051                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1052                         break;
1053                 default:
1054                         DRM_ERROR("unknown crtc reloc\n");
1055                         return -EINVAL;
1056                 }
1057                 ib[h_idx] = header;
1058                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int r600_packet0_check(struct radeon_cs_parser *p,
1065                                 struct radeon_cs_packet *pkt,
1066                                 unsigned idx, unsigned reg)
1067 {
1068         int r;
1069
1070         switch (reg) {
1071         case AVIVO_D1MODE_VLINE_START_END:
1072                 r = r600_cs_packet_parse_vline(p);
1073                 if (r) {
1074                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1075                                         idx, reg);
1076                         return r;
1077                 }
1078                 break;
1079         default:
1080                 DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
1081                        reg, idx);
1082                 return -EINVAL;
1083         }
1084         return 0;
1085 }
1086
1087 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1088                                 struct radeon_cs_packet *pkt)
1089 {
1090         unsigned reg, i;
1091         unsigned idx;
1092         int r;
1093
1094         idx = pkt->idx + 1;
1095         reg = pkt->reg;
1096         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1097                 r = r600_packet0_check(p, pkt, idx, reg);
1098                 if (r) {
1099                         return r;
1100                 }
1101         }
1102         return 0;
1103 }
1104
1105 /**
1106  * r600_cs_check_reg() - check if register is authorized or not
1107  * @parser: parser structure holding parsing context
1108  * @reg: register we are testing
1109  * @idx: index into the cs buffer
1110  *
1111  * This function will test against r600_reg_safe_bm and return 0
1112  * if register is safe. If register is not flag as safe this function
1113  * will test it against a list of register needind special handling.
1114  */
1115 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1116 {
1117         struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1118         struct radeon_cs_reloc *reloc;
1119         u32 m, i, tmp, *ib;
1120         int r;
1121
1122         i = (reg >> 7);
1123         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1124                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1125                 return -EINVAL;
1126         }
1127         m = 1 << ((reg >> 2) & 31);
1128         if (!(r600_reg_safe_bm[i] & m))
1129                 return 0;
1130         ib = p->ib.ptr;
1131         switch (reg) {
1132         /* force following reg to 0 in an attempt to disable out buffer
1133          * which will need us to better understand how it works to perform
1134          * security check on it (Jerome)
1135          */
1136         case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1137         case R_008C44_SQ_ESGS_RING_SIZE:
1138         case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1139         case R_008C54_SQ_ESTMP_RING_SIZE:
1140         case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1141         case R_008C74_SQ_FBUF_RING_SIZE:
1142         case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1143         case R_008C5C_SQ_GSTMP_RING_SIZE:
1144         case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1145         case R_008C4C_SQ_GSVS_RING_SIZE:
1146         case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1147         case R_008C6C_SQ_PSTMP_RING_SIZE:
1148         case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1149         case R_008C7C_SQ_REDUC_RING_SIZE:
1150         case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1151         case R_008C64_SQ_VSTMP_RING_SIZE:
1152         case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1153                 /* get value to populate the IB don't remove */
1154                 tmp =radeon_get_ib_value(p, idx);
1155                 ib[idx] = 0;
1156                 break;
1157         case SQ_CONFIG:
1158                 track->sq_config = radeon_get_ib_value(p, idx);
1159                 break;
1160         case R_028800_DB_DEPTH_CONTROL:
1161                 track->db_depth_control = radeon_get_ib_value(p, idx);
1162                 track->db_dirty = true;
1163                 break;
1164         case R_028010_DB_DEPTH_INFO:
1165                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1166                     r600_cs_packet_next_is_pkt3_nop(p)) {
1167                         r = r600_cs_packet_next_reloc(p, &reloc);
1168                         if (r) {
1169                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1170                                          "0x%04X\n", reg);
1171                                 return -EINVAL;
1172                         }
1173                         track->db_depth_info = radeon_get_ib_value(p, idx);
1174                         ib[idx] &= C_028010_ARRAY_MODE;
1175                         track->db_depth_info &= C_028010_ARRAY_MODE;
1176                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1177                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1178                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1179                         } else {
1180                                 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1181                                 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1182                         }
1183                 } else {
1184                         track->db_depth_info = radeon_get_ib_value(p, idx);
1185                 }
1186                 track->db_dirty = true;
1187                 break;
1188         case R_028004_DB_DEPTH_VIEW:
1189                 track->db_depth_view = radeon_get_ib_value(p, idx);
1190                 track->db_dirty = true;
1191                 break;
1192         case R_028000_DB_DEPTH_SIZE:
1193                 track->db_depth_size = radeon_get_ib_value(p, idx);
1194                 track->db_depth_size_idx = idx;
1195                 track->db_dirty = true;
1196                 break;
1197         case R_028AB0_VGT_STRMOUT_EN:
1198                 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1199                 track->streamout_dirty = true;
1200                 break;
1201         case R_028B20_VGT_STRMOUT_BUFFER_EN:
1202                 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1203                 track->streamout_dirty = true;
1204                 break;
1205         case VGT_STRMOUT_BUFFER_BASE_0:
1206         case VGT_STRMOUT_BUFFER_BASE_1:
1207         case VGT_STRMOUT_BUFFER_BASE_2:
1208         case VGT_STRMOUT_BUFFER_BASE_3:
1209                 r = r600_cs_packet_next_reloc(p, &reloc);
1210                 if (r) {
1211                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1212                                         "0x%04X\n", reg);
1213                         return -EINVAL;
1214                 }
1215                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1216                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1217                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1218                 track->vgt_strmout_bo[tmp] = reloc->robj;
1219                 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1220                 track->streamout_dirty = true;
1221                 break;
1222         case VGT_STRMOUT_BUFFER_SIZE_0:
1223         case VGT_STRMOUT_BUFFER_SIZE_1:
1224         case VGT_STRMOUT_BUFFER_SIZE_2:
1225         case VGT_STRMOUT_BUFFER_SIZE_3:
1226                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1227                 /* size in register is DWs, convert to bytes */
1228                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1229                 track->streamout_dirty = true;
1230                 break;
1231         case CP_COHER_BASE:
1232                 r = r600_cs_packet_next_reloc(p, &reloc);
1233                 if (r) {
1234                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1235                                         "0x%04X\n", reg);
1236                         return -EINVAL;
1237                 }
1238                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1239                 break;
1240         case R_028238_CB_TARGET_MASK:
1241                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1242                 track->cb_dirty = true;
1243                 break;
1244         case R_02823C_CB_SHADER_MASK:
1245                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1246                 break;
1247         case R_028C04_PA_SC_AA_CONFIG:
1248                 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1249                 track->log_nsamples = tmp;
1250                 track->nsamples = 1 << tmp;
1251                 track->cb_dirty = true;
1252                 break;
1253         case R_028808_CB_COLOR_CONTROL:
1254                 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
1255                 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
1256                 track->cb_dirty = true;
1257                 break;
1258         case R_0280A0_CB_COLOR0_INFO:
1259         case R_0280A4_CB_COLOR1_INFO:
1260         case R_0280A8_CB_COLOR2_INFO:
1261         case R_0280AC_CB_COLOR3_INFO:
1262         case R_0280B0_CB_COLOR4_INFO:
1263         case R_0280B4_CB_COLOR5_INFO:
1264         case R_0280B8_CB_COLOR6_INFO:
1265         case R_0280BC_CB_COLOR7_INFO:
1266                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1267                      r600_cs_packet_next_is_pkt3_nop(p)) {
1268                         r = r600_cs_packet_next_reloc(p, &reloc);
1269                         if (r) {
1270                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1271                                 return -EINVAL;
1272                         }
1273                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1274                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1275                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1276                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1277                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1278                         } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1279                                 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1280                                 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1281                         }
1282                 } else {
1283                         tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1284                         track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1285                 }
1286                 track->cb_dirty = true;
1287                 break;
1288         case R_028080_CB_COLOR0_VIEW:
1289         case R_028084_CB_COLOR1_VIEW:
1290         case R_028088_CB_COLOR2_VIEW:
1291         case R_02808C_CB_COLOR3_VIEW:
1292         case R_028090_CB_COLOR4_VIEW:
1293         case R_028094_CB_COLOR5_VIEW:
1294         case R_028098_CB_COLOR6_VIEW:
1295         case R_02809C_CB_COLOR7_VIEW:
1296                 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1297                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1298                 track->cb_dirty = true;
1299                 break;
1300         case R_028060_CB_COLOR0_SIZE:
1301         case R_028064_CB_COLOR1_SIZE:
1302         case R_028068_CB_COLOR2_SIZE:
1303         case R_02806C_CB_COLOR3_SIZE:
1304         case R_028070_CB_COLOR4_SIZE:
1305         case R_028074_CB_COLOR5_SIZE:
1306         case R_028078_CB_COLOR6_SIZE:
1307         case R_02807C_CB_COLOR7_SIZE:
1308                 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1309                 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1310                 track->cb_color_size_idx[tmp] = idx;
1311                 track->cb_dirty = true;
1312                 break;
1313                 /* This register were added late, there is userspace
1314                  * which does provide relocation for those but set
1315                  * 0 offset. In order to avoid breaking old userspace
1316                  * we detect this and set address to point to last
1317                  * CB_COLOR0_BASE, note that if userspace doesn't set
1318                  * CB_COLOR0_BASE before this register we will report
1319                  * error. Old userspace always set CB_COLOR0_BASE
1320                  * before any of this.
1321                  */
1322         case R_0280E0_CB_COLOR0_FRAG:
1323         case R_0280E4_CB_COLOR1_FRAG:
1324         case R_0280E8_CB_COLOR2_FRAG:
1325         case R_0280EC_CB_COLOR3_FRAG:
1326         case R_0280F0_CB_COLOR4_FRAG:
1327         case R_0280F4_CB_COLOR5_FRAG:
1328         case R_0280F8_CB_COLOR6_FRAG:
1329         case R_0280FC_CB_COLOR7_FRAG:
1330                 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1331                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1332                         if (!track->cb_color_base_last[tmp]) {
1333                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1334                                 return -EINVAL;
1335                         }
1336                         track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1337                         track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1338                         ib[idx] = track->cb_color_base_last[tmp];
1339                 } else {
1340                         r = r600_cs_packet_next_reloc(p, &reloc);
1341                         if (r) {
1342                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1343                                 return -EINVAL;
1344                         }
1345                         track->cb_color_frag_bo[tmp] = reloc->robj;
1346                         track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1347                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1348                 }
1349                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1350                         track->cb_dirty = true;
1351                 }
1352                 break;
1353         case R_0280C0_CB_COLOR0_TILE:
1354         case R_0280C4_CB_COLOR1_TILE:
1355         case R_0280C8_CB_COLOR2_TILE:
1356         case R_0280CC_CB_COLOR3_TILE:
1357         case R_0280D0_CB_COLOR4_TILE:
1358         case R_0280D4_CB_COLOR5_TILE:
1359         case R_0280D8_CB_COLOR6_TILE:
1360         case R_0280DC_CB_COLOR7_TILE:
1361                 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1362                 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1363                         if (!track->cb_color_base_last[tmp]) {
1364                                 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1365                                 return -EINVAL;
1366                         }
1367                         track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1368                         track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1369                         ib[idx] = track->cb_color_base_last[tmp];
1370                 } else {
1371                         r = r600_cs_packet_next_reloc(p, &reloc);
1372                         if (r) {
1373                                 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1374                                 return -EINVAL;
1375                         }
1376                         track->cb_color_tile_bo[tmp] = reloc->robj;
1377                         track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1378                         ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1379                 }
1380                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1381                         track->cb_dirty = true;
1382                 }
1383                 break;
1384         case R_028100_CB_COLOR0_MASK:
1385         case R_028104_CB_COLOR1_MASK:
1386         case R_028108_CB_COLOR2_MASK:
1387         case R_02810C_CB_COLOR3_MASK:
1388         case R_028110_CB_COLOR4_MASK:
1389         case R_028114_CB_COLOR5_MASK:
1390         case R_028118_CB_COLOR6_MASK:
1391         case R_02811C_CB_COLOR7_MASK:
1392                 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1393                 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1394                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1395                         track->cb_dirty = true;
1396                 }
1397                 break;
1398         case CB_COLOR0_BASE:
1399         case CB_COLOR1_BASE:
1400         case CB_COLOR2_BASE:
1401         case CB_COLOR3_BASE:
1402         case CB_COLOR4_BASE:
1403         case CB_COLOR5_BASE:
1404         case CB_COLOR6_BASE:
1405         case CB_COLOR7_BASE:
1406                 r = r600_cs_packet_next_reloc(p, &reloc);
1407                 if (r) {
1408                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1409                                         "0x%04X\n", reg);
1410                         return -EINVAL;
1411                 }
1412                 tmp = (reg - CB_COLOR0_BASE) / 4;
1413                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1414                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1415                 track->cb_color_base_last[tmp] = ib[idx];
1416                 track->cb_color_bo[tmp] = reloc->robj;
1417                 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1418                 track->cb_dirty = true;
1419                 break;
1420         case DB_DEPTH_BASE:
1421                 r = r600_cs_packet_next_reloc(p, &reloc);
1422                 if (r) {
1423                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1424                                         "0x%04X\n", reg);
1425                         return -EINVAL;
1426                 }
1427                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1428                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1429                 track->db_bo = reloc->robj;
1430                 track->db_bo_mc = reloc->lobj.gpu_offset;
1431                 track->db_dirty = true;
1432                 break;
1433         case DB_HTILE_DATA_BASE:
1434                 r = r600_cs_packet_next_reloc(p, &reloc);
1435                 if (r) {
1436                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1437                                         "0x%04X\n", reg);
1438                         return -EINVAL;
1439                 }
1440                 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1441                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1442                 track->htile_bo = reloc->robj;
1443                 track->db_dirty = true;
1444                 break;
1445         case DB_HTILE_SURFACE:
1446                 track->htile_surface = radeon_get_ib_value(p, idx);
1447                 /* force 8x8 htile width and height */
1448                 ib[idx] |= 3;
1449                 track->db_dirty = true;
1450                 break;
1451         case SQ_PGM_START_FS:
1452         case SQ_PGM_START_ES:
1453         case SQ_PGM_START_VS:
1454         case SQ_PGM_START_GS:
1455         case SQ_PGM_START_PS:
1456         case SQ_ALU_CONST_CACHE_GS_0:
1457         case SQ_ALU_CONST_CACHE_GS_1:
1458         case SQ_ALU_CONST_CACHE_GS_2:
1459         case SQ_ALU_CONST_CACHE_GS_3:
1460         case SQ_ALU_CONST_CACHE_GS_4:
1461         case SQ_ALU_CONST_CACHE_GS_5:
1462         case SQ_ALU_CONST_CACHE_GS_6:
1463         case SQ_ALU_CONST_CACHE_GS_7:
1464         case SQ_ALU_CONST_CACHE_GS_8:
1465         case SQ_ALU_CONST_CACHE_GS_9:
1466         case SQ_ALU_CONST_CACHE_GS_10:
1467         case SQ_ALU_CONST_CACHE_GS_11:
1468         case SQ_ALU_CONST_CACHE_GS_12:
1469         case SQ_ALU_CONST_CACHE_GS_13:
1470         case SQ_ALU_CONST_CACHE_GS_14:
1471         case SQ_ALU_CONST_CACHE_GS_15:
1472         case SQ_ALU_CONST_CACHE_PS_0:
1473         case SQ_ALU_CONST_CACHE_PS_1:
1474         case SQ_ALU_CONST_CACHE_PS_2:
1475         case SQ_ALU_CONST_CACHE_PS_3:
1476         case SQ_ALU_CONST_CACHE_PS_4:
1477         case SQ_ALU_CONST_CACHE_PS_5:
1478         case SQ_ALU_CONST_CACHE_PS_6:
1479         case SQ_ALU_CONST_CACHE_PS_7:
1480         case SQ_ALU_CONST_CACHE_PS_8:
1481         case SQ_ALU_CONST_CACHE_PS_9:
1482         case SQ_ALU_CONST_CACHE_PS_10:
1483         case SQ_ALU_CONST_CACHE_PS_11:
1484         case SQ_ALU_CONST_CACHE_PS_12:
1485         case SQ_ALU_CONST_CACHE_PS_13:
1486         case SQ_ALU_CONST_CACHE_PS_14:
1487         case SQ_ALU_CONST_CACHE_PS_15:
1488         case SQ_ALU_CONST_CACHE_VS_0:
1489         case SQ_ALU_CONST_CACHE_VS_1:
1490         case SQ_ALU_CONST_CACHE_VS_2:
1491         case SQ_ALU_CONST_CACHE_VS_3:
1492         case SQ_ALU_CONST_CACHE_VS_4:
1493         case SQ_ALU_CONST_CACHE_VS_5:
1494         case SQ_ALU_CONST_CACHE_VS_6:
1495         case SQ_ALU_CONST_CACHE_VS_7:
1496         case SQ_ALU_CONST_CACHE_VS_8:
1497         case SQ_ALU_CONST_CACHE_VS_9:
1498         case SQ_ALU_CONST_CACHE_VS_10:
1499         case SQ_ALU_CONST_CACHE_VS_11:
1500         case SQ_ALU_CONST_CACHE_VS_12:
1501         case SQ_ALU_CONST_CACHE_VS_13:
1502         case SQ_ALU_CONST_CACHE_VS_14:
1503         case SQ_ALU_CONST_CACHE_VS_15:
1504                 r = r600_cs_packet_next_reloc(p, &reloc);
1505                 if (r) {
1506                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1507                                         "0x%04X\n", reg);
1508                         return -EINVAL;
1509                 }
1510                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1511                 break;
1512         case SX_MEMORY_EXPORT_BASE:
1513                 r = r600_cs_packet_next_reloc(p, &reloc);
1514                 if (r) {
1515                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1516                                         "0x%04X\n", reg);
1517                         return -EINVAL;
1518                 }
1519                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1520                 break;
1521         case SX_MISC:
1522                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1523                 break;
1524         default:
1525                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1526                 return -EINVAL;
1527         }
1528         return 0;
1529 }
1530
1531 unsigned r600_mip_minify(unsigned size, unsigned level)
1532 {
1533         unsigned val;
1534
1535         val = max(1U, size >> level);
1536         if (level > 0)
1537                 val = roundup_pow_of_two(val);
1538         return val;
1539 }
1540
1541 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1542                               unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1543                               unsigned block_align, unsigned height_align, unsigned base_align,
1544                               unsigned *l0_size, unsigned *mipmap_size)
1545 {
1546         unsigned offset, i, level;
1547         unsigned width, height, depth, size;
1548         unsigned blocksize;
1549         unsigned nbx, nby;
1550         unsigned nlevels = llevel - blevel + 1;
1551
1552         *l0_size = -1;
1553         blocksize = r600_fmt_get_blocksize(format);
1554
1555         w0 = r600_mip_minify(w0, 0);
1556         h0 = r600_mip_minify(h0, 0);
1557         d0 = r600_mip_minify(d0, 0);
1558         for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1559                 width = r600_mip_minify(w0, i);
1560                 nbx = r600_fmt_get_nblocksx(format, width);
1561
1562                 nbx = roundup(nbx, block_align);
1563
1564                 height = r600_mip_minify(h0, i);
1565                 nby = r600_fmt_get_nblocksy(format, height);
1566                 nby = roundup(nby, height_align);
1567
1568                 depth = r600_mip_minify(d0, i);
1569
1570                 size = nbx * nby * blocksize * nsamples;
1571                 if (nfaces)
1572                         size *= nfaces;
1573                 else
1574                         size *= depth;
1575
1576                 if (i == 0)
1577                         *l0_size = size;
1578
1579                 if (i == 0 || i == 1)
1580                         offset = roundup(offset, base_align);
1581
1582                 offset += size;
1583         }
1584         *mipmap_size = offset;
1585         if (llevel == 0)
1586                 *mipmap_size = *l0_size;
1587         if (!blevel)
1588                 *mipmap_size -= *l0_size;
1589 }
1590
1591 /**
1592  * r600_check_texture_resource() - check if register is authorized or not
1593  * @p: parser structure holding parsing context
1594  * @idx: index into the cs buffer
1595  * @texture: texture's bo structure
1596  * @mipmap: mipmap's bo structure
1597  *
1598  * This function will check that the resource has valid field and that
1599  * the texture and mipmap bo object are big enough to cover this resource.
1600  */
1601 static int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
1602                                               struct radeon_bo *texture,
1603                                               struct radeon_bo *mipmap,
1604                                               u64 base_offset,
1605                                               u64 mip_offset,
1606                                               u32 tiling_flags)
1607 {
1608         struct r600_cs_track *track = p->track;
1609         u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1610         u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1611         u32 height_align, pitch, pitch_align, depth_align;
1612         u32 barray, larray;
1613         u64 base_align;
1614         struct array_mode_checker array_check;
1615         u32 format;
1616         bool is_array;
1617
1618         /* on legacy kernel we don't perform advanced check */
1619         if (p->rdev == NULL)
1620                 return 0;
1621
1622         /* convert to bytes */
1623         base_offset <<= 8;
1624         mip_offset <<= 8;
1625
1626         word0 = radeon_get_ib_value(p, idx + 0);
1627         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1628                 if (tiling_flags & RADEON_TILING_MACRO)
1629                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1630                 else if (tiling_flags & RADEON_TILING_MICRO)
1631                         word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1632         }
1633         word1 = radeon_get_ib_value(p, idx + 1);
1634         word2 = radeon_get_ib_value(p, idx + 2) << 8;
1635         word3 = radeon_get_ib_value(p, idx + 3) << 8;
1636         word4 = radeon_get_ib_value(p, idx + 4);
1637         word5 = radeon_get_ib_value(p, idx + 5);
1638         dim = G_038000_DIM(word0);
1639         w0 = G_038000_TEX_WIDTH(word0) + 1;
1640         pitch = (G_038000_PITCH(word0) + 1) * 8;
1641         h0 = G_038004_TEX_HEIGHT(word1) + 1;
1642         d0 = G_038004_TEX_DEPTH(word1);
1643         format = G_038004_DATA_FORMAT(word1);
1644         blevel = G_038010_BASE_LEVEL(word4);
1645         llevel = G_038014_LAST_LEVEL(word5);
1646         /* pitch in texels */
1647         array_check.array_mode = G_038000_TILE_MODE(word0);
1648         array_check.group_size = track->group_size;
1649         array_check.nbanks = track->nbanks;
1650         array_check.npipes = track->npipes;
1651         array_check.nsamples = 1;
1652         array_check.blocksize = r600_fmt_get_blocksize(format);
1653         nfaces = 1;
1654         is_array = false;
1655         switch (dim) {
1656         case V_038000_SQ_TEX_DIM_1D:
1657         case V_038000_SQ_TEX_DIM_2D:
1658         case V_038000_SQ_TEX_DIM_3D:
1659                 break;
1660         case V_038000_SQ_TEX_DIM_CUBEMAP:
1661                 if (p->family >= CHIP_RV770)
1662                         nfaces = 8;
1663                 else
1664                         nfaces = 6;
1665                 break;
1666         case V_038000_SQ_TEX_DIM_1D_ARRAY:
1667         case V_038000_SQ_TEX_DIM_2D_ARRAY:
1668                 is_array = true;
1669                 break;
1670         case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1671                 is_array = true;
1672                 /* fall through */
1673         case V_038000_SQ_TEX_DIM_2D_MSAA:
1674                 array_check.nsamples = 1 << llevel;
1675                 llevel = 0;
1676                 break;
1677         default:
1678                 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1679                 return -EINVAL;
1680         }
1681         if (!r600_fmt_is_valid_texture(format, p->family)) {
1682                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1683                          __func__, __LINE__, format);
1684                 return -EINVAL;
1685         }
1686
1687         if (r600_get_array_mode_alignment(&array_check,
1688                                           &pitch_align, &height_align, &depth_align, &base_align)) {
1689                 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1690                          __func__, __LINE__, G_038000_TILE_MODE(word0));
1691                 return -EINVAL;
1692         }
1693
1694         /* XXX check height as well... */
1695
1696         if (!IS_ALIGNED(pitch, pitch_align)) {
1697                 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1698                          __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1699                 return -EINVAL;
1700         }
1701         if (!IS_ALIGNED(base_offset, base_align)) {
1702                 dev_warn(p->dev, "%s:%d tex base offset (0x%jx, 0x%jx, %d) invalid\n",
1703                          __func__, __LINE__, (uintmax_t)base_offset, (uintmax_t)base_align, G_038000_TILE_MODE(word0));
1704                 return -EINVAL;
1705         }
1706         if (!IS_ALIGNED(mip_offset, base_align)) {
1707                 dev_warn(p->dev, "%s:%d tex mip offset (0x%jx, 0x%jx, %d) invalid\n",
1708                          __func__, __LINE__, (uintmax_t)mip_offset, (uintmax_t)base_align, G_038000_TILE_MODE(word0));
1709                 return -EINVAL;
1710         }
1711
1712         if (blevel > llevel) {
1713                 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1714                          blevel, llevel);
1715         }
1716         if (is_array) {
1717                 barray = G_038014_BASE_ARRAY(word5);
1718                 larray = G_038014_LAST_ARRAY(word5);
1719
1720                 nfaces = larray - barray + 1;
1721         }
1722         r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1723                           pitch_align, height_align, base_align,
1724                           &l0_size, &mipmap_size);
1725         /* using get ib will give us the offset into the texture bo */
1726         if ((l0_size + word2) > radeon_bo_size(texture)) {
1727                 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1728                          w0, h0, pitch_align, height_align,
1729                          array_check.array_mode, format, word2,
1730                          l0_size, radeon_bo_size(texture));
1731                 dev_warn(p->dev, "alignments %d %d %d %jd\n", pitch, pitch_align, height_align, (uintmax_t)base_align);
1732                 return -EINVAL;
1733         }
1734         /* using get ib will give us the offset into the mipmap bo */
1735         if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1736                 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1737                   w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1738         }
1739         return 0;
1740 }
1741
1742 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1743 {
1744         u32 m, i;
1745
1746         i = (reg >> 7);
1747         if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1748                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1749                 return false;
1750         }
1751         m = 1 << ((reg >> 2) & 31);
1752         if (!(r600_reg_safe_bm[i] & m))
1753                 return true;
1754         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1755         return false;
1756 }
1757
1758 static int r600_packet3_check(struct radeon_cs_parser *p,
1759                                 struct radeon_cs_packet *pkt)
1760 {
1761         struct radeon_cs_reloc *reloc;
1762         struct r600_cs_track *track;
1763         volatile u32 *ib;
1764         unsigned idx;
1765         unsigned i;
1766         unsigned start_reg, end_reg, reg;
1767         int r;
1768         u32 idx_value;
1769
1770         track = (struct r600_cs_track *)p->track;
1771         ib = p->ib.ptr;
1772         idx = pkt->idx + 1;
1773         idx_value = radeon_get_ib_value(p, idx);
1774
1775         switch (pkt->opcode) {
1776         case PACKET3_SET_PREDICATION:
1777         {
1778                 int pred_op;
1779                 int tmp;
1780                 uint64_t offset;
1781
1782                 if (pkt->count != 1) {
1783                         DRM_ERROR("bad SET PREDICATION\n");
1784                         return -EINVAL;
1785                 }
1786
1787                 tmp = radeon_get_ib_value(p, idx + 1);
1788                 pred_op = (tmp >> 16) & 0x7;
1789
1790                 /* for the clear predicate operation */
1791                 if (pred_op == 0)
1792                         return 0;
1793
1794                 if (pred_op > 2) {
1795                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1796                         return -EINVAL;
1797                 }
1798
1799                 r = r600_cs_packet_next_reloc(p, &reloc);
1800                 if (r) {
1801                         DRM_ERROR("bad SET PREDICATION\n");
1802                         return -EINVAL;
1803                 }
1804
1805                 offset = reloc->lobj.gpu_offset +
1806                          (idx_value & 0xfffffff0) +
1807                          ((u64)(tmp & 0xff) << 32);
1808
1809                 ib[idx + 0] = offset;
1810                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1811         }
1812         break;
1813
1814         case PACKET3_START_3D_CMDBUF:
1815                 if (p->family >= CHIP_RV770 || pkt->count) {
1816                         DRM_ERROR("bad START_3D\n");
1817                         return -EINVAL;
1818                 }
1819                 break;
1820         case PACKET3_CONTEXT_CONTROL:
1821                 if (pkt->count != 1) {
1822                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1823                         return -EINVAL;
1824                 }
1825                 break;
1826         case PACKET3_INDEX_TYPE:
1827         case PACKET3_NUM_INSTANCES:
1828                 if (pkt->count) {
1829                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1830                         return -EINVAL;
1831                 }
1832                 break;
1833         case PACKET3_DRAW_INDEX:
1834         {
1835                 uint64_t offset;
1836                 if (pkt->count != 3) {
1837                         DRM_ERROR("bad DRAW_INDEX\n");
1838                         return -EINVAL;
1839                 }
1840                 r = r600_cs_packet_next_reloc(p, &reloc);
1841                 if (r) {
1842                         DRM_ERROR("bad DRAW_INDEX\n");
1843                         return -EINVAL;
1844                 }
1845
1846                 offset = reloc->lobj.gpu_offset +
1847                          idx_value +
1848                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1849
1850                 ib[idx+0] = offset;
1851                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1852
1853                 r = r600_cs_track_check(p);
1854                 if (r) {
1855                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1856                         return r;
1857                 }
1858                 break;
1859         }
1860         case PACKET3_DRAW_INDEX_AUTO:
1861                 if (pkt->count != 1) {
1862                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1863                         return -EINVAL;
1864                 }
1865                 r = r600_cs_track_check(p);
1866                 if (r) {
1867                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1868                         return r;
1869                 }
1870                 break;
1871         case PACKET3_DRAW_INDEX_IMMD_BE:
1872         case PACKET3_DRAW_INDEX_IMMD:
1873                 if (pkt->count < 2) {
1874                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1875                         return -EINVAL;
1876                 }
1877                 r = r600_cs_track_check(p);
1878                 if (r) {
1879                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1880                         return r;
1881                 }
1882                 break;
1883         case PACKET3_WAIT_REG_MEM:
1884                 if (pkt->count != 5) {
1885                         DRM_ERROR("bad WAIT_REG_MEM\n");
1886                         return -EINVAL;
1887                 }
1888                 /* bit 4 is reg (0) or mem (1) */
1889                 if (idx_value & 0x10) {
1890                         uint64_t offset;
1891
1892                         r = r600_cs_packet_next_reloc(p, &reloc);
1893                         if (r) {
1894                                 DRM_ERROR("bad WAIT_REG_MEM\n");
1895                                 return -EINVAL;
1896                         }
1897
1898                         offset = reloc->lobj.gpu_offset +
1899                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1900                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1901
1902                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1903                         ib[idx+2] = upper_32_bits(offset) & 0xff;
1904                 }
1905                 break;
1906         case PACKET3_CP_DMA:
1907         {
1908                 u32 command, size;
1909                 u64 offset, tmp;
1910                 if (pkt->count != 4) {
1911                         DRM_ERROR("bad CP DMA\n");
1912                         return -EINVAL;
1913                 }
1914                 command = radeon_get_ib_value(p, idx+4);
1915                 size = command & 0x1fffff;
1916                 if (command & PACKET3_CP_DMA_CMD_SAS) {
1917                         /* src address space is register */
1918                         DRM_ERROR("CP DMA SAS not supported\n");
1919                         return -EINVAL;
1920                 } else {
1921                         if (command & PACKET3_CP_DMA_CMD_SAIC) {
1922                                 DRM_ERROR("CP DMA SAIC only supported for registers\n");
1923                                 return -EINVAL;
1924                         }
1925                         /* src address space is memory */
1926                         r = r600_cs_packet_next_reloc(p, &reloc);
1927                         if (r) {
1928                                 DRM_ERROR("bad CP DMA SRC\n");
1929                                 return -EINVAL;
1930                         }
1931
1932                         tmp = radeon_get_ib_value(p, idx) +
1933                                 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1934
1935                         offset = reloc->lobj.gpu_offset + tmp;
1936
1937                         if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1938                                 dev_warn(p->dev, "CP DMA src buffer too small (%ju %lu)\n",
1939                                          (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
1940                                 return -EINVAL;
1941                         }
1942
1943                         ib[idx] = offset;
1944                         ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1945                 }
1946                 if (command & PACKET3_CP_DMA_CMD_DAS) {
1947                         /* dst address space is register */
1948                         DRM_ERROR("CP DMA DAS not supported\n");
1949                         return -EINVAL;
1950                 } else {
1951                         /* dst address space is memory */
1952                         if (command & PACKET3_CP_DMA_CMD_DAIC) {
1953                                 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1954                                 return -EINVAL;
1955                         }
1956                         r = r600_cs_packet_next_reloc(p, &reloc);
1957                         if (r) {
1958                                 DRM_ERROR("bad CP DMA DST\n");
1959                                 return -EINVAL;
1960                         }
1961
1962                         tmp = radeon_get_ib_value(p, idx+2) +
1963                                 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
1964
1965                         offset = reloc->lobj.gpu_offset + tmp;
1966
1967                         if ((tmp + size) > radeon_bo_size(reloc->robj)) {
1968                                 dev_warn(p->dev, "CP DMA dst buffer too small (%ju %lu)\n",
1969                                          (uintmax_t)tmp + size, radeon_bo_size(reloc->robj));
1970                                 return -EINVAL;
1971                         }
1972
1973                         ib[idx+2] = offset;
1974                         ib[idx+3] = upper_32_bits(offset) & 0xff;
1975                 }
1976                 break;
1977         }
1978         case PACKET3_SURFACE_SYNC:
1979                 if (pkt->count != 3) {
1980                         DRM_ERROR("bad SURFACE_SYNC\n");
1981                         return -EINVAL;
1982                 }
1983                 /* 0xffffffff/0x0 is flush all cache flag */
1984                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1985                     radeon_get_ib_value(p, idx + 2) != 0) {
1986                         r = r600_cs_packet_next_reloc(p, &reloc);
1987                         if (r) {
1988                                 DRM_ERROR("bad SURFACE_SYNC\n");
1989                                 return -EINVAL;
1990                         }
1991                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1992                 }
1993                 break;
1994         case PACKET3_EVENT_WRITE:
1995                 if (pkt->count != 2 && pkt->count != 0) {
1996                         DRM_ERROR("bad EVENT_WRITE\n");
1997                         return -EINVAL;
1998                 }
1999                 if (pkt->count) {
2000                         uint64_t offset;
2001
2002                         r = r600_cs_packet_next_reloc(p, &reloc);
2003                         if (r) {
2004                                 DRM_ERROR("bad EVENT_WRITE\n");
2005                                 return -EINVAL;
2006                         }
2007                         offset = reloc->lobj.gpu_offset +
2008                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2009                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2010
2011                         ib[idx+1] = offset & 0xfffffff8;
2012                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2013                 }
2014                 break;
2015         case PACKET3_EVENT_WRITE_EOP:
2016         {
2017                 uint64_t offset;
2018
2019                 if (pkt->count != 4) {
2020                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
2021                         return -EINVAL;
2022                 }
2023                 r = r600_cs_packet_next_reloc(p, &reloc);
2024                 if (r) {
2025                         DRM_ERROR("bad EVENT_WRITE\n");
2026                         return -EINVAL;
2027                 }
2028
2029                 offset = reloc->lobj.gpu_offset +
2030                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2031                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2032
2033                 ib[idx+1] = offset & 0xfffffffc;
2034                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2035                 break;
2036         }
2037         case PACKET3_SET_CONFIG_REG:
2038                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
2039                 end_reg = 4 * pkt->count + start_reg - 4;
2040                 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
2041                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2042                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2043                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2044                         return -EINVAL;
2045                 }
2046                 for (i = 0; i < pkt->count; i++) {
2047                         reg = start_reg + (4 * i);
2048                         r = r600_cs_check_reg(p, reg, idx+1+i);
2049                         if (r)
2050                                 return r;
2051                 }
2052                 break;
2053         case PACKET3_SET_CONTEXT_REG:
2054                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
2055                 end_reg = 4 * pkt->count + start_reg - 4;
2056                 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2057                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2058                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2059                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2060                         return -EINVAL;
2061                 }
2062                 for (i = 0; i < pkt->count; i++) {
2063                         reg = start_reg + (4 * i);
2064                         r = r600_cs_check_reg(p, reg, idx+1+i);
2065                         if (r)
2066                                 return r;
2067                 }
2068                 break;
2069         case PACKET3_SET_RESOURCE:
2070                 if (pkt->count % 7) {
2071                         DRM_ERROR("bad SET_RESOURCE\n");
2072                         return -EINVAL;
2073                 }
2074                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
2075                 end_reg = 4 * pkt->count + start_reg - 4;
2076                 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2077                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
2078                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
2079                         DRM_ERROR("bad SET_RESOURCE\n");
2080                         return -EINVAL;
2081                 }
2082                 for (i = 0; i < (pkt->count / 7); i++) {
2083                         struct radeon_bo *texture, *mipmap;
2084                         u32 size, offset, base_offset, mip_offset;
2085
2086                         switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
2087                         case SQ_TEX_VTX_VALID_TEXTURE:
2088                                 /* tex base */
2089                                 r = r600_cs_packet_next_reloc(p, &reloc);
2090                                 if (r) {
2091                                         DRM_ERROR("bad SET_RESOURCE\n");
2092                                         return -EINVAL;
2093                                 }
2094                                 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2095                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2096                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2097                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2098                                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2099                                                 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2100                                 }
2101                                 texture = reloc->robj;
2102                                 /* tex mip base */
2103                                 r = r600_cs_packet_next_reloc(p, &reloc);
2104                                 if (r) {
2105                                         DRM_ERROR("bad SET_RESOURCE\n");
2106                                         return -EINVAL;
2107                                 }
2108                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2109                                 mipmap = reloc->robj;
2110                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
2111                                                                 texture, mipmap,
2112                                                                 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2113                                                                 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2114                                                                 reloc->lobj.tiling_flags);
2115                                 if (r)
2116                                         return r;
2117                                 ib[idx+1+(i*7)+2] += base_offset;
2118                                 ib[idx+1+(i*7)+3] += mip_offset;
2119                                 break;
2120                         case SQ_TEX_VTX_VALID_BUFFER:
2121                         {
2122                                 uint64_t offset64;
2123                                 /* vtx base */
2124                                 r = r600_cs_packet_next_reloc(p, &reloc);
2125                                 if (r) {
2126                                         DRM_ERROR("bad SET_RESOURCE\n");
2127                                         return -EINVAL;
2128                                 }
2129                                 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2130                                 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2131                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2132                                         /* force size to size of the buffer */
2133                                         dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2134                                                  size + offset, radeon_bo_size(reloc->robj));
2135                                         ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2136                                 }
2137
2138                                 offset64 = reloc->lobj.gpu_offset + offset;
2139                                 ib[idx+1+(i*8)+0] = offset64;
2140                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2141                                                     (upper_32_bits(offset64) & 0xff);
2142                                 break;
2143                         }
2144                         case SQ_TEX_VTX_INVALID_TEXTURE:
2145                         case SQ_TEX_VTX_INVALID_BUFFER:
2146                         default:
2147                                 DRM_ERROR("bad SET_RESOURCE\n");
2148                                 return -EINVAL;
2149                         }
2150                 }
2151                 break;
2152         case PACKET3_SET_ALU_CONST:
2153                 if (track->sq_config & DX9_CONSTS) {
2154                         start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2155                         end_reg = 4 * pkt->count + start_reg - 4;
2156                         if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2157                             (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2158                             (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2159                                 DRM_ERROR("bad SET_ALU_CONST\n");
2160                                 return -EINVAL;
2161                         }
2162                 }
2163                 break;
2164         case PACKET3_SET_BOOL_CONST:
2165                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2166                 end_reg = 4 * pkt->count + start_reg - 4;
2167                 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2168                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2169                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2170                         DRM_ERROR("bad SET_BOOL_CONST\n");
2171                         return -EINVAL;
2172                 }
2173                 break;
2174         case PACKET3_SET_LOOP_CONST:
2175                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2176                 end_reg = 4 * pkt->count + start_reg - 4;
2177                 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2178                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2179                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2180                         DRM_ERROR("bad SET_LOOP_CONST\n");
2181                         return -EINVAL;
2182                 }
2183                 break;
2184         case PACKET3_SET_CTL_CONST:
2185                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2186                 end_reg = 4 * pkt->count + start_reg - 4;
2187                 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2188                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2189                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2190                         DRM_ERROR("bad SET_CTL_CONST\n");
2191                         return -EINVAL;
2192                 }
2193                 break;
2194         case PACKET3_SET_SAMPLER:
2195                 if (pkt->count % 3) {
2196                         DRM_ERROR("bad SET_SAMPLER\n");
2197                         return -EINVAL;
2198                 }
2199                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2200                 end_reg = 4 * pkt->count + start_reg - 4;
2201                 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2202                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
2203                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
2204                         DRM_ERROR("bad SET_SAMPLER\n");
2205                         return -EINVAL;
2206                 }
2207                 break;
2208         case PACKET3_STRMOUT_BASE_UPDATE:
2209                 /* RS780 and RS880 also need this */
2210                 if (p->family < CHIP_RS780) {
2211                         DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2212                         return -EINVAL;
2213                 }
2214                 if (pkt->count != 1) {
2215                         DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2216                         return -EINVAL;
2217                 }
2218                 if (idx_value > 3) {
2219                         DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2220                         return -EINVAL;
2221                 }
2222                 {
2223                         u64 offset;
2224
2225                         r = r600_cs_packet_next_reloc(p, &reloc);
2226                         if (r) {
2227                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2228                                 return -EINVAL;
2229                         }
2230
2231                         if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2232                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2233                                 return -EINVAL;
2234                         }
2235
2236                         offset = radeon_get_ib_value(p, idx+1) << 8;
2237                         if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2238                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%jx, 0x%x\n",
2239                                           (uintmax_t)offset, track->vgt_strmout_bo_offset[idx_value]);
2240                                 return -EINVAL;
2241                         }
2242
2243                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2244                                 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%jx, 0x%lx\n",
2245                                           (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2246                                 return -EINVAL;
2247                         }
2248                         ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2249                 }
2250                 break;
2251         case PACKET3_SURFACE_BASE_UPDATE:
2252                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2253                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2254                         return -EINVAL;
2255                 }
2256                 if (pkt->count) {
2257                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2258                         return -EINVAL;
2259                 }
2260                 break;
2261         case PACKET3_STRMOUT_BUFFER_UPDATE:
2262                 if (pkt->count != 4) {
2263                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2264                         return -EINVAL;
2265                 }
2266                 /* Updating memory at DST_ADDRESS. */
2267                 if (idx_value & 0x1) {
2268                         u64 offset;
2269                         r = r600_cs_packet_next_reloc(p, &reloc);
2270                         if (r) {
2271                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2272                                 return -EINVAL;
2273                         }
2274                         offset = radeon_get_ib_value(p, idx+1);
2275                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2276                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2277                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%jx, 0x%lx\n",
2278                                           (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2279                                 return -EINVAL;
2280                         }
2281                         offset += reloc->lobj.gpu_offset;
2282                         ib[idx+1] = offset;
2283                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2284                 }
2285                 /* Reading data from SRC_ADDRESS. */
2286                 if (((idx_value >> 1) & 0x3) == 2) {
2287                         u64 offset;
2288                         r = r600_cs_packet_next_reloc(p, &reloc);
2289                         if (r) {
2290                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2291                                 return -EINVAL;
2292                         }
2293                         offset = radeon_get_ib_value(p, idx+3);
2294                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2295                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2296                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%jx, 0x%lx\n",
2297                                           (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2298                                 return -EINVAL;
2299                         }
2300                         offset += reloc->lobj.gpu_offset;
2301                         ib[idx+3] = offset;
2302                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2303                 }
2304                 break;
2305         case PACKET3_MEM_WRITE:
2306         {
2307                 u64 offset;
2308
2309                 if (pkt->count != 3) {
2310                         DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2311                         return -EINVAL;
2312                 }
2313                 r = r600_cs_packet_next_reloc(p, &reloc);
2314                 if (r) {
2315                         DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2316                         return -EINVAL;
2317                 }
2318                 offset = radeon_get_ib_value(p, idx+0);
2319                 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;
2320                 if (offset & 0x7) {
2321                         DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");
2322                         return -EINVAL;
2323                 }
2324                 if ((offset + 8) > radeon_bo_size(reloc->robj)) {
2325                         DRM_ERROR("bad MEM_WRITE bo too small: 0x%jx, 0x%lx\n",
2326                                   (uintmax_t)offset + 8, radeon_bo_size(reloc->robj));
2327                         return -EINVAL;
2328                 }
2329                 offset += reloc->lobj.gpu_offset;
2330                 ib[idx+0] = offset;
2331                 ib[idx+1] = upper_32_bits(offset) & 0xff;
2332                 break;
2333         }
2334         case PACKET3_COPY_DW:
2335                 if (pkt->count != 4) {
2336                         DRM_ERROR("bad COPY_DW (invalid count)\n");
2337                         return -EINVAL;
2338                 }
2339                 if (idx_value & 0x1) {
2340                         u64 offset;
2341                         /* SRC is memory. */
2342                         r = r600_cs_packet_next_reloc(p, &reloc);
2343                         if (r) {
2344                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2345                                 return -EINVAL;
2346                         }
2347                         offset = radeon_get_ib_value(p, idx+1);
2348                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2349                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2350                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%jx, 0x%lx\n",
2351                                           (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2352                                 return -EINVAL;
2353                         }
2354                         offset += reloc->lobj.gpu_offset;
2355                         ib[idx+1] = offset;
2356                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2357                 } else {
2358                         /* SRC is a reg. */
2359                         reg = radeon_get_ib_value(p, idx+1) << 2;
2360                         if (!r600_is_safe_reg(p, reg, idx+1))
2361                                 return -EINVAL;
2362                 }
2363                 if (idx_value & 0x2) {
2364                         u64 offset;
2365                         /* DST is memory. */
2366                         r = r600_cs_packet_next_reloc(p, &reloc);
2367                         if (r) {
2368                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2369                                 return -EINVAL;
2370                         }
2371                         offset = radeon_get_ib_value(p, idx+3);
2372                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2373                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2374                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%jx, 0x%lx\n",
2375                                           (uintmax_t)offset + 4, radeon_bo_size(reloc->robj));
2376                                 return -EINVAL;
2377                         }
2378                         offset += reloc->lobj.gpu_offset;
2379                         ib[idx+3] = offset;
2380                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2381                 } else {
2382                         /* DST is a reg. */
2383                         reg = radeon_get_ib_value(p, idx+3) << 2;
2384                         if (!r600_is_safe_reg(p, reg, idx+3))
2385                                 return -EINVAL;
2386                 }
2387                 break;
2388         case PACKET3_NOP:
2389                 break;
2390         default:
2391                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2392                 return -EINVAL;
2393         }
2394         return 0;
2395 }
2396
2397 int r600_cs_parse(struct radeon_cs_parser *p)
2398 {
2399         struct radeon_cs_packet pkt;
2400         struct r600_cs_track *track;
2401         int r;
2402
2403         if (p->track == NULL) {
2404                 /* initialize tracker, we are in kms */
2405                 track = malloc(sizeof(*track),
2406                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2407                 if (track == NULL)
2408                         return -ENOMEM;
2409                 r600_cs_track_init(track);
2410                 if (p->rdev->family < CHIP_RV770) {
2411                         track->npipes = p->rdev->config.r600.tiling_npipes;
2412                         track->nbanks = p->rdev->config.r600.tiling_nbanks;
2413                         track->group_size = p->rdev->config.r600.tiling_group_size;
2414                 } else if (p->rdev->family <= CHIP_RV740) {
2415                         track->npipes = p->rdev->config.rv770.tiling_npipes;
2416                         track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2417                         track->group_size = p->rdev->config.rv770.tiling_group_size;
2418                 }
2419                 p->track = track;
2420         }
2421         do {
2422                 r = r600_cs_packet_parse(p, &pkt, p->idx);
2423                 if (r) {
2424                         free(p->track, DRM_MEM_DRIVER);
2425                         p->track = NULL;
2426                         return r;
2427                 }
2428                 p->idx += pkt.count + 2;
2429                 switch (pkt.type) {
2430                 case PACKET_TYPE0:
2431                         r = r600_cs_parse_packet0(p, &pkt);
2432                         break;
2433                 case PACKET_TYPE2:
2434                         break;
2435                 case PACKET_TYPE3:
2436                         r = r600_packet3_check(p, &pkt);
2437                         break;
2438                 default:
2439                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2440                         free(p->track, DRM_MEM_DRIVER);
2441                         p->track = NULL;
2442                         return -EINVAL;
2443                 }
2444                 if (r) {
2445                         free(p->track, DRM_MEM_DRIVER);
2446                         p->track = NULL;
2447                         return r;
2448                 }
2449         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2450 #if 0
2451         for (r = 0; r < p->ib.length_dw; r++) {
2452                 DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
2453                 mdelay(1);
2454         }
2455 #endif
2456         free(p->track, DRM_MEM_DRIVER);
2457         p->track = NULL;
2458         return 0;
2459 }
2460
2461 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2462 {
2463         if (p->chunk_relocs_idx == -1) {
2464                 return 0;
2465         }
2466         p->relocs = malloc(sizeof(struct radeon_cs_reloc),
2467             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2468         if (p->relocs == NULL) {
2469                 return -ENOMEM;
2470         }
2471         return 0;
2472 }
2473
2474 /**
2475  * cs_parser_fini() - clean parser states
2476  * @parser:     parser structure holding parsing context.
2477  * @error:      error number
2478  *
2479  * If error is set than unvalidate buffer, otherwise just free memory
2480  * used by parsing context.
2481  **/
2482 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2483 {
2484         unsigned i;
2485
2486         free(parser->relocs, DRM_MEM_DRIVER);
2487         for (i = 0; i < parser->nchunks; i++) {
2488                 free(parser->chunks[i].kdata, DRM_MEM_DRIVER);
2489                 if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
2490                         free(parser->chunks[i].kpage[0], DRM_MEM_DRIVER);
2491                         free(parser->chunks[i].kpage[1], DRM_MEM_DRIVER);
2492                 }
2493         }
2494         free(parser->chunks, DRM_MEM_DRIVER);
2495         free(parser->chunks_array, DRM_MEM_DRIVER);
2496         free(parser->track, DRM_MEM_DRIVER);
2497 }
2498
2499 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2500                         unsigned family, u32 *ib, int *l)
2501 {
2502         struct radeon_cs_parser parser;
2503         struct radeon_cs_chunk *ib_chunk;
2504         struct r600_cs_track *track;
2505         int r;
2506
2507         /* initialize tracker */
2508         track = malloc(sizeof(*track), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2509         if (track == NULL)
2510                 return -ENOMEM;
2511         r600_cs_track_init(track);
2512         r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2513         /* initialize parser */
2514         memset(&parser, 0, sizeof(struct radeon_cs_parser));
2515         parser.filp = filp;
2516         parser.dev = dev->dev;
2517         parser.rdev = NULL;
2518         parser.family = family;
2519         parser.track = track;
2520         parser.ib.ptr = ib;
2521         r = radeon_cs_parser_init(&parser, data);
2522         if (r) {
2523                 DRM_ERROR("Failed to initialize parser !\n");
2524                 r600_cs_parser_fini(&parser, r);
2525                 return r;
2526         }
2527         r = r600_cs_parser_relocs_legacy(&parser);
2528         if (r) {
2529                 DRM_ERROR("Failed to parse relocation !\n");
2530                 r600_cs_parser_fini(&parser, r);
2531                 return r;
2532         }
2533         /* Copy the packet into the IB, the parser will read from the
2534          * input memory (cached) and write to the IB (which can be
2535          * uncached). */
2536         ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2537         parser.ib.length_dw = ib_chunk->length_dw;
2538         *l = parser.ib.length_dw;
2539         r = r600_cs_parse(&parser);
2540         if (r) {
2541                 DRM_ERROR("Invalid command stream !\n");
2542                 r600_cs_parser_fini(&parser, r);
2543                 return r;
2544         }
2545         r = radeon_cs_finish_pages(&parser);
2546         if (r) {
2547                 DRM_ERROR("Invalid command stream !\n");
2548                 r600_cs_parser_fini(&parser, r);
2549                 return r;
2550         }
2551         r600_cs_parser_fini(&parser, r);
2552         return r;
2553 }
2554
2555 void r600_cs_legacy_init(void)
2556 {
2557         r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2558 }
2559
2560 /*
2561  *  DMA
2562  */
2563 /**
2564  * r600_dma_cs_next_reloc() - parse next reloc
2565  * @p:          parser structure holding parsing context.
2566  * @cs_reloc:           reloc informations
2567  *
2568  * Return the next reloc, do bo validation and compute
2569  * GPU offset using the provided start.
2570  **/
2571 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
2572                            struct radeon_cs_reloc **cs_reloc)
2573 {
2574         struct radeon_cs_chunk *relocs_chunk;
2575         unsigned idx;
2576
2577         *cs_reloc = NULL;
2578         if (p->chunk_relocs_idx == -1) {
2579                 DRM_ERROR("No relocation chunk !\n");
2580                 return -EINVAL;
2581         }
2582         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
2583         idx = p->dma_reloc_idx;
2584         if (idx >= p->nrelocs) {
2585                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
2586                           idx, p->nrelocs);
2587                 return -EINVAL;
2588         }
2589         *cs_reloc = p->relocs_ptr[idx];
2590         p->dma_reloc_idx++;
2591         return 0;
2592 }
2593
2594 #define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2595 #define GET_DMA_COUNT(h) ((h) & 0x0000ffff)
2596 #define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2597
2598 /**
2599  * r600_dma_cs_parse() - parse the DMA IB
2600  * @p:          parser structure holding parsing context.
2601  *
2602  * Parses the DMA IB from the CS ioctl and updates
2603  * the GPU addresses based on the reloc information and
2604  * checks for errors. (R6xx-R7xx)
2605  * Returns 0 for success and an error on failure.
2606  **/
2607 int r600_dma_cs_parse(struct radeon_cs_parser *p)
2608 {
2609         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2610         struct radeon_cs_reloc *src_reloc, *dst_reloc;
2611         u32 header, cmd, count, tiled;
2612         volatile u32 *ib = p->ib.ptr;
2613         u32 idx, idx_value;
2614         u64 src_offset, dst_offset;
2615         int r;
2616
2617         do {
2618                 if (p->idx >= ib_chunk->length_dw) {
2619                         DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
2620                                   p->idx, ib_chunk->length_dw);
2621                         return -EINVAL;
2622                 }
2623                 idx = p->idx;
2624                 header = radeon_get_ib_value(p, idx);
2625                 cmd = GET_DMA_CMD(header);
2626                 count = GET_DMA_COUNT(header);
2627                 tiled = GET_DMA_T(header);
2628
2629                 switch (cmd) {
2630                 case DMA_PACKET_WRITE:
2631                         r = r600_dma_cs_next_reloc(p, &dst_reloc);
2632                         if (r) {
2633                                 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2634                                 return -EINVAL;
2635                         }
2636                         if (tiled) {
2637                                 dst_offset = radeon_get_ib_value(p, idx+1);
2638                                 dst_offset <<= 8;
2639
2640                                 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2641                                 p->idx += count + 5;
2642                         } else {
2643                                 dst_offset = radeon_get_ib_value(p, idx+1);
2644                                 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2645
2646                                 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2647                                 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2648                                 p->idx += count + 3;
2649                         }
2650                         if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2651                                 dev_warn(p->dev, "DMA write buffer too small (%ju %lu)\n",
2652                                          (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2653                                 return -EINVAL;
2654                         }
2655                         break;
2656                 case DMA_PACKET_COPY:
2657                         r = r600_dma_cs_next_reloc(p, &src_reloc);
2658                         if (r) {
2659                                 DRM_ERROR("bad DMA_PACKET_COPY\n");
2660                                 return -EINVAL;
2661                         }
2662                         r = r600_dma_cs_next_reloc(p, &dst_reloc);
2663                         if (r) {
2664                                 DRM_ERROR("bad DMA_PACKET_COPY\n");
2665                                 return -EINVAL;
2666                         }
2667                         if (tiled) {
2668                                 idx_value = radeon_get_ib_value(p, idx + 2);
2669                                 /* detile bit */
2670                                 if (idx_value & (1U << 31)) {
2671                                         /* tiled src, linear dst */
2672                                         src_offset = radeon_get_ib_value(p, idx+1);
2673                                         src_offset <<= 8;
2674                                         ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2675
2676                                         dst_offset = radeon_get_ib_value(p, idx+5);
2677                                         dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2678                                         ib[idx+5] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2679                                         ib[idx+6] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2680                                 } else {
2681                                         /* linear src, tiled dst */
2682                                         src_offset = radeon_get_ib_value(p, idx+5);
2683                                         src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;
2684                                         ib[idx+5] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2685                                         ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2686
2687                                         dst_offset = radeon_get_ib_value(p, idx+1);
2688                                         dst_offset <<= 8;
2689                                         ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2690                                 }
2691                                 p->idx += 7;
2692                         } else {
2693                                 if (p->family >= CHIP_RV770) {
2694                                         src_offset = radeon_get_ib_value(p, idx+2);
2695                                         src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2696                                         dst_offset = radeon_get_ib_value(p, idx+1);
2697                                         dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2698
2699                                         ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2700                                         ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2701                                         ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2702                                         ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2703                                         p->idx += 5;
2704                                 } else {
2705                                         src_offset = radeon_get_ib_value(p, idx+2);
2706                                         src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;
2707                                         dst_offset = radeon_get_ib_value(p, idx+1);
2708                                         dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;
2709
2710                                         ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2711                                         ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2712                                         ib[idx+3] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2713                                         ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff) << 16;
2714                                         p->idx += 4;
2715                                 }
2716                         }
2717                         if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2718                                 dev_warn(p->dev, "DMA copy src buffer too small (%ju %lu)\n",
2719                                          (uintmax_t)src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2720                                 return -EINVAL;
2721                         }
2722                         if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2723                                 dev_warn(p->dev, "DMA write dst buffer too small (%ju %lu)\n",
2724                                          (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2725                                 return -EINVAL;
2726                         }
2727                         break;
2728                 case DMA_PACKET_CONSTANT_FILL:
2729                         if (p->family < CHIP_RV770) {
2730                                 DRM_ERROR("Constant Fill is 7xx only !\n");
2731                                 return -EINVAL;
2732                         }
2733                         r = r600_dma_cs_next_reloc(p, &dst_reloc);
2734                         if (r) {
2735                                 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2736                                 return -EINVAL;
2737                         }
2738                         dst_offset = radeon_get_ib_value(p, idx+1);
2739                         dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;
2740                         if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2741                                 dev_warn(p->dev, "DMA constant fill buffer too small (%ju %lu)\n",
2742                                          (uintmax_t)dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2743                                 return -EINVAL;
2744                         }
2745                         ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2746                         ib[idx+3] += (upper_32_bits(dst_reloc->lobj.gpu_offset) << 16) & 0x00ff0000;
2747                         p->idx += 4;
2748                         break;
2749                 case DMA_PACKET_NOP:
2750                         p->idx += 1;
2751                         break;
2752                 default:
2753                         DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);
2754                         return -EINVAL;
2755                 }
2756         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2757 #if 0
2758         for (r = 0; r < p->ib->length_dw; r++) {
2759                 DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
2760                 mdelay(1);
2761         }
2762 #endif
2763         return 0;
2764 }