sys/dev/drm2/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <dev/drm2/drmP.h>
  31 #include <dev/drm2/radeon/radeon_drm.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
  34
  35 #include "atom.h"
  36 #include "atom-bits.h"
  37
  38 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
  39 /* from radeon_encoder.c */
  40 extern uint32_t
  41 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  42                         uint8_t dac);
  43 extern void radeon_link_encoder_connector(struct drm_device *dev);
  44 extern void
  45 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  46                         uint32_t supported_device, u16 caps);
  47
  48 /* from radeon_connector.c */
  49 extern void
  50 radeon_add_atom_connector(struct drm_device *dev,
  51                           uint32_t connector_id,
  52                           uint32_t supported_device,
  53                           int connector_type,
  54                           struct radeon_i2c_bus_rec *i2c_bus,
  55                           uint32_t igp_lane_info,
  56                           uint16_t connector_object_id,
  57                           struct radeon_hpd *hpd,
  58                           struct radeon_router *router);
  59
  60 /* from radeon_legacy_encoder.c */
  61 extern void
  62 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  63                           uint32_t supported_device);
  64 #endif
  65
  66 /* local */
  67 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  68                                     u16 voltage_id, u16 *voltage);
  69
  70 union atom_supported_devices {
  71         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  72         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  73         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  74 };
  75
  76 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
  77                                           ATOM_GPIO_I2C_ASSIGMENT *gpio,
  78                                           u8 index)
  79 {
  80         /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
  81         if ((rdev->family == CHIP_R420) ||
  82             (rdev->family == CHIP_R423) ||
  83             (rdev->family == CHIP_RV410)) {
  84                 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
  85                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
  86                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
  87                         gpio->ucClkMaskShift = 0x19;
  88                         gpio->ucDataMaskShift = 0x18;
  89                 }
  90         }
  91
  92         /* some evergreen boards have bad data for this entry */
  93         if (ASIC_IS_DCE4(rdev)) {
  94                 if ((index == 7) &&
  95                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
  96                     (gpio->sucI2cId.ucAccess == 0)) {
  97                         gpio->sucI2cId.ucAccess = 0x97;
  98                         gpio->ucDataMaskShift = 8;
  99                         gpio->ucDataEnShift = 8;
 100                         gpio->ucDataY_Shift = 8;
 101                         gpio->ucDataA_Shift = 8;
 102                 }
 103         }
 104
 105         /* some DCE3 boards have bad data for this entry */
 106         if (ASIC_IS_DCE3(rdev)) {
 107                 if ((index == 4) &&
 108                     (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
 109                     (gpio->sucI2cId.ucAccess == 0x94))
 110                         gpio->sucI2cId.ucAccess = 0x14;
 111         }
 112 }
 113
 114 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
 115 {
 116         struct radeon_i2c_bus_rec i2c;
 117
 118         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 119
 120         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 121         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 122         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 123         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 124         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 125         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 126         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 127         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 128         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 129         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 130         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 131         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 132         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 133         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 134         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 135         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 136
 137         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 138                 i2c.hw_capable = true;
 139         else
 140                 i2c.hw_capable = false;
 141
 142         if (gpio->sucI2cId.ucAccess == 0xa0)
 143                 i2c.mm_i2c = true;
 144         else
 145                 i2c.mm_i2c = false;
 146
 147         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 148
 149         if (i2c.mask_clk_reg)
 150                 i2c.valid = true;
 151         else
 152                 i2c.valid = false;
 153
 154         return i2c;
 155 }
 156
 157 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
 158                                                                uint8_t id)
 159 {
 160         struct atom_context *ctx = rdev->mode_info.atom_context;
 161         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 162         struct radeon_i2c_bus_rec i2c;
 163         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 164         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 165         uint16_t data_offset, size;
 166         int i, num_indices;
 167
 168         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 169         i2c.valid = false;
 170
 171         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 172                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
 173
 174                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 175                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 176
 177                 for (i = 0; i < num_indices; i++) {
 178                         gpio = &i2c_info->asGPIO_Info[i];
 179
 180                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 181
 182                         if (gpio->sucI2cId.ucAccess == id) {
 183                                 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 184                                 break;
 185                         }
 186                 }
 187         }
 188
 189         return i2c;
 190 }
 191
 192 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 193 {
 194         struct atom_context *ctx = rdev->mode_info.atom_context;
 195         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 196         struct radeon_i2c_bus_rec i2c;
 197         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 198         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 199         uint16_t data_offset, size;
 200         int i, num_indices;
 201         char stmp[32];
 202
 203         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 204                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)((char *)ctx->bios + data_offset);
 205
 206                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 207                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 208
 209                 for (i = 0; i < num_indices; i++) {
 210                         gpio = &i2c_info->asGPIO_Info[i];
 211
 212                         radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
 213
 214                         i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
 215
 216                         if (i2c.valid) {
 217                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 218                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 219                         }
 220                 }
 221         }
 222 }
 223
 224 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 225                                                         u8 id)
 226 {
 227         struct atom_context *ctx = rdev->mode_info.atom_context;
 228         struct radeon_gpio_rec gpio;
 229         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 230         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 231         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 232         u16 data_offset, size;
 233         int i, num_indices;
 234
 235         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 236         gpio.valid = false;
 237
 238         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 239                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)((char *)ctx->bios + data_offset);
 240
 241                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 242                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 243
 244                 for (i = 0; i < num_indices; i++) {
 245                         pin = &gpio_info->asGPIO_Pin[i];
 246                         if (id == pin->ucGPIO_ID) {
 247                                 gpio.id = pin->ucGPIO_ID;
 248                                 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
 249                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 250                                 gpio.valid = true;
 251                                 break;
 252                         }
 253                 }
 254         }
 255
 256         return gpio;
 257 }
 258
 259 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 260                                                             struct radeon_gpio_rec *gpio)
 261 {
 262         struct radeon_hpd hpd;
 263         u32 reg;
 264
 265         memset(&hpd, 0, sizeof(struct radeon_hpd));
 266
 267         if (ASIC_IS_DCE6(rdev))
 268                 reg = SI_DC_GPIO_HPD_A;
 269         else if (ASIC_IS_DCE4(rdev))
 270                 reg = EVERGREEN_DC_GPIO_HPD_A;
 271         else
 272                 reg = AVIVO_DC_GPIO_HPD_A;
 273
 274         hpd.gpio = *gpio;
 275         if (gpio->reg == reg) {
 276                 switch(gpio->mask) {
 277                 case (1 << 0):
 278                         hpd.hpd = RADEON_HPD_1;
 279                         break;
 280                 case (1 << 8):
 281                         hpd.hpd = RADEON_HPD_2;
 282                         break;
 283                 case (1 << 16):
 284                         hpd.hpd = RADEON_HPD_3;
 285                         break;
 286                 case (1 << 24):
 287                         hpd.hpd = RADEON_HPD_4;
 288                         break;
 289                 case (1 << 26):
 290                         hpd.hpd = RADEON_HPD_5;
 291                         break;
 292                 case (1 << 28):
 293                         hpd.hpd = RADEON_HPD_6;
 294                         break;
 295                 default:
 296                         hpd.hpd = RADEON_HPD_NONE;
 297                         break;
 298                 }
 299         } else
 300                 hpd.hpd = RADEON_HPD_NONE;
 301         return hpd;
 302 }
 303
 304 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 305                                      uint32_t supported_device,
 306                                      int *connector_type,
 307                                      struct radeon_i2c_bus_rec *i2c_bus,
 308                                      uint16_t *line_mux,
 309                                      struct radeon_hpd *hpd)
 310 {
 311
 312         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 313         if ((dev->pci_device == 0x791e) &&
 314             (dev->pci_subvendor == 0x1043) &&
 315             (dev->pci_subdevice == 0x826d)) {
 316                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 317                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 318                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 319         }
 320
 321         /* Asrock RS600 board lists the DVI port as HDMI */
 322         if ((dev->pci_device == 0x7941) &&
 323             (dev->pci_subvendor == 0x1849) &&
 324             (dev->pci_subdevice == 0x7941)) {
 325                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 326                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 327                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 328         }
 329
 330         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 331         if ((dev->pci_device == 0x796e) &&
 332             (dev->pci_subvendor == 0x1462) &&
 333             (dev->pci_subdevice == 0x7302)) {
 334                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 335                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 336                         return false;
 337         }
 338
 339         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 340         if ((dev->pci_device == 0x7941) &&
 341             (dev->pci_subvendor == 0x147b) &&
 342             (dev->pci_subdevice == 0x2412)) {
 343                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 344                         return false;
 345         }
 346
 347         /* Falcon NW laptop lists vga ddc line for LVDS */
 348         if ((dev->pci_device == 0x5653) &&
 349             (dev->pci_subvendor == 0x1462) &&
 350             (dev->pci_subdevice == 0x0291)) {
 351                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 352                         i2c_bus->valid = false;
 353                         *line_mux = 53;
 354                 }
 355         }
 356
 357         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 358         if ((dev->pci_device == 0x7146) &&
 359             (dev->pci_subvendor == 0x17af) &&
 360             (dev->pci_subdevice == 0x2058)) {
 361                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 362                         return false;
 363         }
 364
 365         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 366         if ((dev->pci_device == 0x7142) &&
 367             (dev->pci_subvendor == 0x1458) &&
 368             (dev->pci_subdevice == 0x2134)) {
 369                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 370                         return false;
 371         }
 372
 373
 374         /* Funky macbooks */
 375         if ((dev->pci_device == 0x71C5) &&
 376             (dev->pci_subvendor == 0x106b) &&
 377             (dev->pci_subdevice == 0x0080)) {
 378                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 379                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 380                         return false;
 381                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 382                         *line_mux = 0x90;
 383         }
 384
 385         /* mac rv630, rv730, others */
 386         if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 387             (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 388                 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 389                 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 390         }
 391
 392         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 393         if ((dev->pci_device == 0x9598) &&
 394             (dev->pci_subvendor == 0x1043) &&
 395             (dev->pci_subdevice == 0x01da)) {
 396                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 397                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 398                 }
 399         }
 400
 401         /* ASUS HD 3600 board lists the DVI port as HDMI */
 402         if ((dev->pci_device == 0x9598) &&
 403             (dev->pci_subvendor == 0x1043) &&
 404             (dev->pci_subdevice == 0x01e4)) {
 405                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 406                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 407                 }
 408         }
 409
 410         /* ASUS HD 3450 board lists the DVI port as HDMI */
 411         if ((dev->pci_device == 0x95C5) &&
 412             (dev->pci_subvendor == 0x1043) &&
 413             (dev->pci_subdevice == 0x01e2)) {
 414                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 415                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 416                 }
 417         }
 418
 419         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 420          * HDMI + VGA reporting as HDMI
 421          */
 422         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 423                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 424                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 425                         *line_mux = 0;
 426                 }
 427         }
 428
 429         /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
 430          * on the laptop and a DVI port on the docking station and
 431          * both share the same encoder, hpd pin, and ddc line.
 432          * So while the bios table is technically correct,
 433          * we drop the DVI port here since xrandr has no concept of
 434          * encoders and will try and drive both connectors
 435          * with different crtcs which isn't possible on the hardware
 436          * side and leaves no crtcs for LVDS or VGA.
 437          */
 438         if (((dev->pci_device == 0x95c4) || (dev->pci_device == 0x9591)) &&
 439             (dev->pci_subvendor == 0x1025) &&
 440             (dev->pci_subdevice == 0x013c)) {
 441                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 442                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 443                         /* actually it's a DVI-D port not DVI-I */
 444                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 445                         return false;
 446                 }
 447         }
 448
 449         /* XFX Pine Group device rv730 reports no VGA DDC lines
 450          * even though they are wired up to record 0x93
 451          */
 452         if ((dev->pci_device == 0x9498) &&
 453             (dev->pci_subvendor == 0x1682) &&
 454             (dev->pci_subdevice == 0x2452) &&
 455             (i2c_bus->valid == false) &&
 456             !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
 457                 struct radeon_device *rdev = dev->dev_private;
 458                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 459         }
 460
 461         /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
 462         if (((dev->pci_device == 0x9802) || (dev->pci_device == 0x9806)) &&
 463             (dev->pci_subvendor == 0x1734) &&
 464             (dev->pci_subdevice == 0x11bd)) {
 465                 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
 466                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 467                         *line_mux = 0x3103;
 468                 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
 469                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 470                 }
 471         }
 472
 473
 474         return true;
 475 }
 476
 477 const int supported_devices_connector_convert[] = {
 478         DRM_MODE_CONNECTOR_Unknown,
 479         DRM_MODE_CONNECTOR_VGA,
 480         DRM_MODE_CONNECTOR_DVII,
 481         DRM_MODE_CONNECTOR_DVID,
 482         DRM_MODE_CONNECTOR_DVIA,
 483         DRM_MODE_CONNECTOR_SVIDEO,
 484         DRM_MODE_CONNECTOR_Composite,
 485         DRM_MODE_CONNECTOR_LVDS,
 486         DRM_MODE_CONNECTOR_Unknown,
 487         DRM_MODE_CONNECTOR_Unknown,
 488         DRM_MODE_CONNECTOR_HDMIA,
 489         DRM_MODE_CONNECTOR_HDMIB,
 490         DRM_MODE_CONNECTOR_Unknown,
 491         DRM_MODE_CONNECTOR_Unknown,
 492         DRM_MODE_CONNECTOR_9PinDIN,
 493         DRM_MODE_CONNECTOR_DisplayPort
 494 };
 495
 496 const uint16_t supported_devices_connector_object_id_convert[] = {
 497         CONNECTOR_OBJECT_ID_NONE,
 498         CONNECTOR_OBJECT_ID_VGA,
 499         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 500         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 501         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 502         CONNECTOR_OBJECT_ID_COMPOSITE,
 503         CONNECTOR_OBJECT_ID_SVIDEO,
 504         CONNECTOR_OBJECT_ID_LVDS,
 505         CONNECTOR_OBJECT_ID_9PIN_DIN,
 506         CONNECTOR_OBJECT_ID_9PIN_DIN,
 507         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 508         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 509         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 510         CONNECTOR_OBJECT_ID_SVIDEO
 511 };
 512
 513 const int object_connector_convert[] = {
 514         DRM_MODE_CONNECTOR_Unknown,
 515         DRM_MODE_CONNECTOR_DVII,
 516         DRM_MODE_CONNECTOR_DVII,
 517         DRM_MODE_CONNECTOR_DVID,
 518         DRM_MODE_CONNECTOR_DVID,
 519         DRM_MODE_CONNECTOR_VGA,
 520         DRM_MODE_CONNECTOR_Composite,
 521         DRM_MODE_CONNECTOR_SVIDEO,
 522         DRM_MODE_CONNECTOR_Unknown,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_9PinDIN,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_HDMIA,
 527         DRM_MODE_CONNECTOR_HDMIB,
 528         DRM_MODE_CONNECTOR_LVDS,
 529         DRM_MODE_CONNECTOR_9PinDIN,
 530         DRM_MODE_CONNECTOR_Unknown,
 531         DRM_MODE_CONNECTOR_Unknown,
 532         DRM_MODE_CONNECTOR_Unknown,
 533         DRM_MODE_CONNECTOR_DisplayPort,
 534         DRM_MODE_CONNECTOR_eDP,
 535         DRM_MODE_CONNECTOR_Unknown
 536 };
 537
 538 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 539 {
 540         struct radeon_device *rdev = dev->dev_private;
 541         struct radeon_mode_info *mode_info = &rdev->mode_info;
 542         struct atom_context *ctx = mode_info->atom_context;
 543         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 544         u16 size, data_offset;
 545         u8 frev, crev;
 546         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 547         ATOM_ENCODER_OBJECT_TABLE *enc_obj;
 548         ATOM_OBJECT_TABLE *router_obj;
 549         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 550         ATOM_OBJECT_HEADER *obj_header;
 551         int i, j, k, path_size, device_support;
 552         int connector_type;
 553         u16 igp_lane_info, conn_id, connector_object_id;
 554         struct radeon_i2c_bus_rec ddc_bus;
 555         struct radeon_router router;
 556         struct radeon_gpio_rec gpio;
 557         struct radeon_hpd hpd;
 558
 559         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 560                 return false;
 561
 562         if (crev < 2)
 563                 return false;
 564
 565         obj_header = (ATOM_OBJECT_HEADER *) ((char *)ctx->bios + data_offset);
 566         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 567             ((char *)ctx->bios + data_offset +
 568              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 569         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 570             ((char *)ctx->bios + data_offset +
 571              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 572         enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
 573             ((char *)ctx->bios + data_offset +
 574              le16_to_cpu(obj_header->usEncoderObjectTableOffset));
 575         router_obj = (ATOM_OBJECT_TABLE *)
 576                 ((char *)ctx->bios + data_offset +
 577                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 578         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 579
 580         path_size = 0;
 581         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 582                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 583                 ATOM_DISPLAY_OBJECT_PATH *path;
 584                 addr += path_size;
 585                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 586                 path_size += le16_to_cpu(path->usSize);
 587
 588                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 589                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 590
 591                         con_obj_id =
 592                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 593                             >> OBJECT_ID_SHIFT;
 594                         con_obj_num =
 595                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 596                             >> ENUM_ID_SHIFT;
 597                         con_obj_type =
 598                             (le16_to_cpu(path->usConnObjectId) &
 599                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 600
 601                         /* TODO CV support */
 602                         if (le16_to_cpu(path->usDeviceTag) ==
 603                                 ATOM_DEVICE_CV_SUPPORT)
 604                                 continue;
 605
 606                         /* IGP chips */
 607                         if ((rdev->flags & RADEON_IS_IGP) &&
 608                             (con_obj_id ==
 609                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 610                                 uint16_t igp_offset = 0;
 611                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 612
 613                                 index =
 614                                     GetIndexIntoMasterTable(DATA,
 615                                                             IntegratedSystemInfo);
 616
 617                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 618                                                            &crev, &igp_offset)) {
 619
 620                                         if (crev >= 2) {
 621                                                 igp_obj =
 622                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 623                                                          *) ((char *)ctx->bios + igp_offset);
 624
 625                                                 if (igp_obj) {
 626                                                         uint32_t slot_config, ct;
 627
 628                                                         if (con_obj_num == 1)
 629                                                                 slot_config =
 630                                                                         igp_obj->
 631                                                                         ulDDISlot1Config;
 632                                                         else
 633                                                                 slot_config =
 634                                                                         igp_obj->
 635                                                                         ulDDISlot2Config;
 636
 637                                                         ct = (slot_config >> 16) & 0xff;
 638                                                         connector_type =
 639                                                                 object_connector_convert
 640                                                                 [ct];
 641                                                         connector_object_id = ct;
 642                                                         igp_lane_info =
 643                                                                 slot_config & 0xffff;
 644                                                 } else
 645                                                         continue;
 646                                         } else
 647                                                 continue;
 648                                 } else {
 649                                         igp_lane_info = 0;
 650                                         connector_type =
 651                                                 object_connector_convert[con_obj_id];
 652                                         connector_object_id = con_obj_id;
 653                                 }
 654                         } else {
 655                                 igp_lane_info = 0;
 656                                 connector_type =
 657                                     object_connector_convert[con_obj_id];
 658                                 connector_object_id = con_obj_id;
 659                         }
 660
 661                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 662                                 continue;
 663
 664                         router.ddc_valid = false;
 665                         router.cd_valid = false;
 666                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 667                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 668
 669                                 grph_obj_id =
 670                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 671                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 672                                 grph_obj_num =
 673                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 674                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 675                                 grph_obj_type =
 676                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 677                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 678
 679                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 680                                         for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
 681                                                 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
 682                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
 683                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 684                                                                 ((char *)ctx->bios + data_offset +
 685                                                                  le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
 686                                                         ATOM_ENCODER_CAP_RECORD *cap_record;
 687                                                         u16 caps = 0;
 688
 689                                                         while (record->ucRecordSize > 0 &&
 690                                                                record->ucRecordType > 0 &&
 691                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 692                                                                 switch (record->ucRecordType) {
 693                                                                 case ATOM_ENCODER_CAP_RECORD_TYPE:
 694                                                                         cap_record =(ATOM_ENCODER_CAP_RECORD *)
 695                                                                                 record;
 696                                                                         caps = le16_to_cpu(cap_record->usEncoderCap);
 697                                                                         break;
 698                                                                 }
 699                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 700                                                                         ((char *)record + record->ucRecordSize);
 701                                                         }
 702                                                         radeon_add_atom_encoder(dev,
 703                                                                                 encoder_obj,
 704                                                                                 le16_to_cpu
 705                                                                                 (path->
 706                                                                                  usDeviceTag),
 707                                                                                 caps);
 708                                                 }
 709                                         }
 710                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 711                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 712                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 713                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 714                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 715                                                                 ((char *)ctx->bios + data_offset +
 716                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 717                                                         ATOM_I2C_RECORD *i2c_record;
 718                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 719                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 720                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 721                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 722                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 723                                                                 ((char *)ctx->bios + data_offset +
 724                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 725                                                         int enum_id;
 726
 727                                                         router.router_id = router_obj_id;
 728                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 729                                                              enum_id++) {
 730                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 731                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 732                                                                         break;
 733                                                         }
 734
 735                                                         while (record->ucRecordSize > 0 &&
 736                                                                record->ucRecordType > 0 &&
 737                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 738                                                                 switch (record->ucRecordType) {
 739                                                                 case ATOM_I2C_RECORD_TYPE:
 740                                                                         i2c_record =
 741                                                                                 (ATOM_I2C_RECORD *)
 742                                                                                 record;
 743                                                                         i2c_config =
 744                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 745                                                                                 &i2c_record->sucI2cId;
 746                                                                         router.i2c_info =
 747                                                                                 radeon_lookup_i2c_gpio(rdev,
 748                                                                                                        i2c_config->
 749                                                                                                        ucAccess);
 750                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 751                                                                         break;
 752                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 753                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 754                                                                                 record;
 755                                                                         router.ddc_valid = true;
 756                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 757                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 758                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 759                                                                         break;
 760                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 761                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 762                                                                                 record;
 763                                                                         router.cd_valid = true;
 764                                                                         router.cd_mux_type = cd_path->ucMuxType;
 765                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 766                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 767                                                                         break;
 768                                                                 }
 769                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 770                                                                         ((char *)record + record->ucRecordSize);
 771                                                         }
 772                                                 }
 773                                         }
 774                                 }
 775                         }
 776
 777                         /* look up gpio for ddc, hpd */
 778                         ddc_bus.valid = false;
 779                         hpd.hpd = RADEON_HPD_NONE;
 780                         if ((le16_to_cpu(path->usDeviceTag) &
 781                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 782                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 783                                         if (le16_to_cpu(path->usConnObjectId) ==
 784                                             le16_to_cpu(con_obj->asObjects[j].
 785                                                         usObjectID)) {
 786                                                 ATOM_COMMON_RECORD_HEADER
 787                                                     *record =
 788                                                     (ATOM_COMMON_RECORD_HEADER
 789                                                      *)
 790                                                     ((char *)ctx->bios + data_offset +
 791                                                      le16_to_cpu(con_obj->
 792                                                                  asObjects[j].
 793                                                                  usRecordOffset));
 794                                                 ATOM_I2C_RECORD *i2c_record;
 795                                                 ATOM_HPD_INT_RECORD *hpd_record;
 796                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 797
 798                                                 while (record->ucRecordSize > 0 &&
 799                                                        record->ucRecordType > 0 &&
 800                                                        record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 801                                                         switch (record->ucRecordType) {
 802                                                         case ATOM_I2C_RECORD_TYPE:
 803                                                                 i2c_record =
 804                                                                     (ATOM_I2C_RECORD *)
 805                                                                         record;
 806                                                                 i2c_config =
 807                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 808                                                                         &i2c_record->sucI2cId;
 809                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 810                                                                                                  i2c_config->
 811                                                                                                  ucAccess);
 812                                                                 break;
 813                                                         case ATOM_HPD_INT_RECORD_TYPE:
 814                                                                 hpd_record =
 815                                                                         (ATOM_HPD_INT_RECORD *)
 816                                                                         record;
 817                                                                 gpio = radeon_lookup_gpio(rdev,
 818                                                                                           hpd_record->ucHPDIntGPIOID);
 819                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 820                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 821                                                                 break;
 822                                                         }
 823                                                         record =
 824                                                             (ATOM_COMMON_RECORD_HEADER
 825                                                              *) ((char *)record
 826                                                                  +
 827                                                                  record->
 828                                                                  ucRecordSize);
 829                                                 }
 830                                                 break;
 831                                         }
 832                                 }
 833                         }
 834
 835                         /* needed for aux chan transactions */
 836                         ddc_bus.hpd = hpd.hpd;
 837
 838                         conn_id = le16_to_cpu(path->usConnObjectId);
 839
 840                         if (!radeon_atom_apply_quirks
 841                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 842                              &ddc_bus, &conn_id, &hpd))
 843                                 continue;
 844
 845                         radeon_add_atom_connector(dev,
 846                                                   conn_id,
 847                                                   le16_to_cpu(path->
 848                                                               usDeviceTag),
 849                                                   connector_type, &ddc_bus,
 850                                                   igp_lane_info,
 851                                                   connector_object_id,
 852                                                   &hpd,
 853                                                   &router);
 854
 855                 }
 856         }
 857
 858         radeon_link_encoder_connector(dev);
 859
 860         return true;
 861 }
 862
 863 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 864                                                  int connector_type,
 865                                                  uint16_t devices)
 866 {
 867         struct radeon_device *rdev = dev->dev_private;
 868
 869         if (rdev->flags & RADEON_IS_IGP) {
 870                 return supported_devices_connector_object_id_convert
 871                         [connector_type];
 872         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 873                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 874                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 875                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 876                 struct atom_context *ctx = mode_info->atom_context;
 877                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 878                 uint16_t size, data_offset;
 879                 uint8_t frev, crev;
 880                 ATOM_XTMDS_INFO *xtmds;
 881
 882                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 883                         xtmds = (ATOM_XTMDS_INFO *)((char *)ctx->bios + data_offset);
 884
 885                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 886                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 887                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 888                                 else
 889                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 890                         } else {
 891                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 892                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 893                                 else
 894                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 895                         }
 896                 } else
 897                         return supported_devices_connector_object_id_convert
 898                                 [connector_type];
 899         } else {
 900                 return supported_devices_connector_object_id_convert
 901                         [connector_type];
 902         }
 903 }
 904
 905 struct bios_connector {
 906         bool valid;
 907         uint16_t line_mux;
 908         uint16_t devices;
 909         int connector_type;
 910         struct radeon_i2c_bus_rec ddc_bus;
 911         struct radeon_hpd hpd;
 912 };
 913
 914 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 915                                                                  drm_device
 916                                                                  *dev)
 917 {
 918         struct radeon_device *rdev = dev->dev_private;
 919         struct radeon_mode_info *mode_info = &rdev->mode_info;
 920         struct atom_context *ctx = mode_info->atom_context;
 921         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 922         uint16_t size, data_offset;
 923         uint8_t frev, crev;
 924         uint16_t device_support;
 925         uint8_t dac;
 926         union atom_supported_devices *supported_devices;
 927         int i, j, max_device;
 928         struct bios_connector *bios_connectors;
 929         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 930         struct radeon_router router;
 931
 932         router.ddc_valid = false;
 933         router.cd_valid = false;
 934
 935         bios_connectors = malloc(bc_size, DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
 936         if (!bios_connectors)
 937                 return false;
 938
 939         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 940                                     &data_offset)) {
 941                 free(bios_connectors, DRM_MEM_DRIVER);
 942                 return false;
 943         }
 944
 945         supported_devices =
 946             (union atom_supported_devices *)((char *)ctx->bios + data_offset);
 947
 948         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 949
 950         if (frev > 1)
 951                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 952         else
 953                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 954
 955         for (i = 0; i < max_device; i++) {
 956                 ATOM_CONNECTOR_INFO_I2C ci =
 957                     supported_devices->info.asConnInfo[i];
 958
 959                 bios_connectors[i].valid = false;
 960
 961                 if (!(device_support & (1 << i))) {
 962                         continue;
 963                 }
 964
 965                 if (i == ATOM_DEVICE_CV_INDEX) {
 966                         DRM_DEBUG_KMS("Skipping Component Video\n");
 967                         continue;
 968                 }
 969
 970                 bios_connectors[i].connector_type =
 971                     supported_devices_connector_convert[ci.sucConnectorInfo.
 972                                                         sbfAccess.
 973                                                         bfConnectorType];
 974
 975                 if (bios_connectors[i].connector_type ==
 976                     DRM_MODE_CONNECTOR_Unknown)
 977                         continue;
 978
 979                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 980
 981                 bios_connectors[i].line_mux =
 982                         ci.sucI2cId.ucAccess;
 983
 984                 /* give tv unique connector ids */
 985                 if (i == ATOM_DEVICE_TV1_INDEX) {
 986                         bios_connectors[i].ddc_bus.valid = false;
 987                         bios_connectors[i].line_mux = 50;
 988                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 989                         bios_connectors[i].ddc_bus.valid = false;
 990                         bios_connectors[i].line_mux = 51;
 991                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 992                         bios_connectors[i].ddc_bus.valid = false;
 993                         bios_connectors[i].line_mux = 52;
 994                 } else
 995                         bios_connectors[i].ddc_bus =
 996                             radeon_lookup_i2c_gpio(rdev,
 997                                                    bios_connectors[i].line_mux);
 998
 999                 if ((crev > 1) && (frev > 1)) {
1000                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
1001                         switch (isb) {
1002                         case 0x4:
1003                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1004                                 break;
1005                         case 0xa:
1006                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1007                                 break;
1008                         default:
1009                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1010                                 break;
1011                         }
1012                 } else {
1013                         if (i == ATOM_DEVICE_DFP1_INDEX)
1014                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
1015                         else if (i == ATOM_DEVICE_DFP2_INDEX)
1016                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
1017                         else
1018                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
1019                 }
1020
1021                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
1022                  * shared with a DVI port, we'll pick up the DVI connector when we
1023                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
1024                  */
1025                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
1026                         bios_connectors[i].connector_type =
1027                             DRM_MODE_CONNECTOR_VGA;
1028
1029                 if (!radeon_atom_apply_quirks
1030                     (dev, (1 << i), &bios_connectors[i].connector_type,
1031                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1032                      &bios_connectors[i].hpd))
1033                         continue;
1034
1035                 bios_connectors[i].valid = true;
1036                 bios_connectors[i].devices = (1 << i);
1037
1038                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1039                         radeon_add_atom_encoder(dev,
1040                                                 radeon_get_encoder_enum(dev,
1041                                                                       (1 << i),
1042                                                                       dac),
1043                                                 (1 << i),
1044                                                 0);
1045                 else
1046                         radeon_add_legacy_encoder(dev,
1047                                                   radeon_get_encoder_enum(dev,
1048                                                                         (1 << i),
1049                                                                         dac),
1050                                                   (1 << i));
1051         }
1052
1053         /* combine shared connectors */
1054         for (i = 0; i < max_device; i++) {
1055                 if (bios_connectors[i].valid) {
1056                         for (j = 0; j < max_device; j++) {
1057                                 if (bios_connectors[j].valid && (i != j)) {
1058                                         if (bios_connectors[i].line_mux ==
1059                                             bios_connectors[j].line_mux) {
1060                                                 /* make sure not to combine LVDS */
1061                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1062                                                         bios_connectors[i].line_mux = 53;
1063                                                         bios_connectors[i].ddc_bus.valid = false;
1064                                                         continue;
1065                                                 }
1066                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1067                                                         bios_connectors[j].line_mux = 53;
1068                                                         bios_connectors[j].ddc_bus.valid = false;
1069                                                         continue;
1070                                                 }
1071                                                 /* combine analog and digital for DVI-I */
1072                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1073                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1074                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1075                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1076                                                         bios_connectors[i].devices |=
1077                                                                 bios_connectors[j].devices;
1078                                                         bios_connectors[i].connector_type =
1079                                                                 DRM_MODE_CONNECTOR_DVII;
1080                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1081                                                                 bios_connectors[i].hpd =
1082                                                                         bios_connectors[j].hpd;
1083                                                         bios_connectors[j].valid = false;
1084                                                 }
1085                                         }
1086                                 }
1087                         }
1088                 }
1089         }
1090
1091         /* add the connectors */
1092         for (i = 0; i < max_device; i++) {
1093                 if (bios_connectors[i].valid) {
1094                         uint16_t connector_object_id =
1095                                 atombios_get_connector_object_id(dev,
1096                                                       bios_connectors[i].connector_type,
1097                                                       bios_connectors[i].devices);
1098                         radeon_add_atom_connector(dev,
1099                                                   bios_connectors[i].line_mux,
1100                                                   bios_connectors[i].devices,
1101                                                   bios_connectors[i].
1102                                                   connector_type,
1103                                                   &bios_connectors[i].ddc_bus,
1104                                                   0,
1105                                                   connector_object_id,
1106                                                   &bios_connectors[i].hpd,
1107                                                   &router);
1108                 }
1109         }
1110
1111         radeon_link_encoder_connector(dev);
1112
1113         free(bios_connectors, DRM_MEM_DRIVER);
1114         return true;
1115 }
1116
1117 union firmware_info {
1118         ATOM_FIRMWARE_INFO info;
1119         ATOM_FIRMWARE_INFO_V1_2 info_12;
1120         ATOM_FIRMWARE_INFO_V1_3 info_13;
1121         ATOM_FIRMWARE_INFO_V1_4 info_14;
1122         ATOM_FIRMWARE_INFO_V2_1 info_21;
1123         ATOM_FIRMWARE_INFO_V2_2 info_22;
1124 };
1125
1126 bool radeon_atom_get_clock_info(struct drm_device *dev)
1127 {
1128         struct radeon_device *rdev = dev->dev_private;
1129         struct radeon_mode_info *mode_info = &rdev->mode_info;
1130         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1131         union firmware_info *firmware_info;
1132         uint8_t frev, crev;
1133         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1134         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1135         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1136         struct radeon_pll *spll = &rdev->clock.spll;
1137         struct radeon_pll *mpll = &rdev->clock.mpll;
1138         uint16_t data_offset;
1139
1140         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1141                                    &frev, &crev, &data_offset)) {
1142                 firmware_info =
1143                         (union firmware_info *)((char *)mode_info->atom_context->bios +
1144                                                 data_offset);
1145                 /* pixel clocks */
1146                 p1pll->reference_freq =
1147                     le16_to_cpu(firmware_info->info.usReferenceClock);
1148                 p1pll->reference_div = 0;
1149
1150                 if (crev < 2)
1151                         p1pll->pll_out_min =
1152                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1153                 else
1154                         p1pll->pll_out_min =
1155                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1156                 p1pll->pll_out_max =
1157                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1158
1159                 if (crev >= 4) {
1160                         p1pll->lcd_pll_out_min =
1161                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1162                         if (p1pll->lcd_pll_out_min == 0)
1163                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1164                         p1pll->lcd_pll_out_max =
1165                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1166                         if (p1pll->lcd_pll_out_max == 0)
1167                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1168                 } else {
1169                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1170                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1171                 }
1172
1173                 if (p1pll->pll_out_min == 0) {
1174                         if (ASIC_IS_AVIVO(rdev))
1175                                 p1pll->pll_out_min = 64800;
1176                         else
1177                                 p1pll->pll_out_min = 20000;
1178                 }
1179
1180                 p1pll->pll_in_min =
1181                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1182                 p1pll->pll_in_max =
1183                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1184
1185                 *p2pll = *p1pll;
1186
1187                 /* system clock */
1188                 if (ASIC_IS_DCE4(rdev))
1189                         spll->reference_freq =
1190                                 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1191                 else
1192                         spll->reference_freq =
1193                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1194                 spll->reference_div = 0;
1195
1196                 spll->pll_out_min =
1197                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1198                 spll->pll_out_max =
1199                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1200
1201                 /* ??? */
1202                 if (spll->pll_out_min == 0) {
1203                         if (ASIC_IS_AVIVO(rdev))
1204                                 spll->pll_out_min = 64800;
1205                         else
1206                                 spll->pll_out_min = 20000;
1207                 }
1208
1209                 spll->pll_in_min =
1210                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1211                 spll->pll_in_max =
1212                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1213
1214                 /* memory clock */
1215                 if (ASIC_IS_DCE4(rdev))
1216                         mpll->reference_freq =
1217                                 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1218                 else
1219                         mpll->reference_freq =
1220                                 le16_to_cpu(firmware_info->info.usReferenceClock);
1221                 mpll->reference_div = 0;
1222
1223                 mpll->pll_out_min =
1224                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1225                 mpll->pll_out_max =
1226                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1227
1228                 /* ??? */
1229                 if (mpll->pll_out_min == 0) {
1230                         if (ASIC_IS_AVIVO(rdev))
1231                                 mpll->pll_out_min = 64800;
1232                         else
1233                                 mpll->pll_out_min = 20000;
1234                 }
1235
1236                 mpll->pll_in_min =
1237                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1238                 mpll->pll_in_max =
1239                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1240
1241                 rdev->clock.default_sclk =
1242                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1243                 rdev->clock.default_mclk =
1244                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1245
1246                 if (ASIC_IS_DCE4(rdev)) {
1247                         rdev->clock.default_dispclk =
1248                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1249                         if (rdev->clock.default_dispclk == 0) {
1250                                 if (ASIC_IS_DCE5(rdev))
1251                                         rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1252                                 else
1253                                         rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1254                         }
1255                         rdev->clock.dp_extclk =
1256                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1257                 }
1258                 *dcpll = *p1pll;
1259
1260                 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1261                 if (rdev->clock.max_pixel_clock == 0)
1262                         rdev->clock.max_pixel_clock = 40000;
1263
1264                 /* not technically a clock, but... */
1265                 rdev->mode_info.firmware_flags =
1266                         le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1267
1268                 return true;
1269         }
1270
1271         return false;
1272 }
1273
1274 union igp_info {
1275         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1276         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1277         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1278         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1279 };
1280
1281 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1282 {
1283         struct radeon_mode_info *mode_info = &rdev->mode_info;
1284         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1285         union igp_info *igp_info;
1286         u8 frev, crev;
1287         u16 data_offset;
1288
1289         /* sideport is AMD only */
1290         if (rdev->family == CHIP_RS600)
1291                 return false;
1292
1293         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1294                                    &frev, &crev, &data_offset)) {
1295                 igp_info = (union igp_info *)((char *)mode_info->atom_context->bios +
1296                                       data_offset);
1297                 switch (crev) {
1298                 case 1:
1299                         if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1300                                 return true;
1301                         break;
1302                 case 2:
1303                         if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1304                                 return true;
1305                         break;
1306                 default:
1307                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1308                         break;
1309                 }
1310         }
1311         return false;
1312 }
1313
1314 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1315                                    struct radeon_encoder_int_tmds *tmds)
1316 {
1317         struct drm_device *dev = encoder->base.dev;
1318         struct radeon_device *rdev = dev->dev_private;
1319         struct radeon_mode_info *mode_info = &rdev->mode_info;
1320         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1321         uint16_t data_offset;
1322         struct _ATOM_TMDS_INFO *tmds_info;
1323         uint8_t frev, crev;
1324         uint16_t maxfreq;
1325         int i;
1326
1327         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1328                                    &frev, &crev, &data_offset)) {
1329                 tmds_info =
1330                         (struct _ATOM_TMDS_INFO *)((char *)mode_info->atom_context->bios +
1331                                                    data_offset);
1332
1333                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1334                 for (i = 0; i < 4; i++) {
1335                         tmds->tmds_pll[i].freq =
1336                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1337                         tmds->tmds_pll[i].value =
1338                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1339                         tmds->tmds_pll[i].value |=
1340                             (tmds_info->asMiscInfo[i].
1341                              ucPLL_VCO_Gain & 0x3f) << 6;
1342                         tmds->tmds_pll[i].value |=
1343                             (tmds_info->asMiscInfo[i].
1344                              ucPLL_DutyCycle & 0xf) << 12;
1345                         tmds->tmds_pll[i].value |=
1346                             (tmds_info->asMiscInfo[i].
1347                              ucPLL_VoltageSwing & 0xf) << 16;
1348
1349                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1350                                   tmds->tmds_pll[i].freq,
1351                                   tmds->tmds_pll[i].value);
1352
1353                         if (maxfreq == tmds->tmds_pll[i].freq) {
1354                                 tmds->tmds_pll[i].freq = 0xffffffff;
1355                                 break;
1356                         }
1357                 }
1358                 return true;
1359         }
1360         return false;
1361 }
1362
1363 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1364                                       struct radeon_atom_ss *ss,
1365                                       int id)
1366 {
1367         struct radeon_mode_info *mode_info = &rdev->mode_info;
1368         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1369         uint16_t data_offset, size;
1370         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1371         uint8_t frev, crev;
1372         int i, num_indices;
1373
1374         memset(ss, 0, sizeof(struct radeon_atom_ss));
1375         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1376                                    &frev, &crev, &data_offset)) {
1377                 ss_info =
1378                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1379
1380                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1381                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1382
1383                 for (i = 0; i < num_indices; i++) {
1384                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1385                                 ss->percentage =
1386                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1387                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1388                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1389                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1390                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1391                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1392                                 return true;
1393                         }
1394                 }
1395         }
1396         return false;
1397 }
1398
1399 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1400                                                  struct radeon_atom_ss *ss,
1401                                                  int id)
1402 {
1403         struct radeon_mode_info *mode_info = &rdev->mode_info;
1404         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1405         u16 data_offset, size;
1406         union igp_info *igp_info;
1407         u8 frev, crev;
1408         u16 percentage = 0, rate = 0;
1409
1410         /* get any igp specific overrides */
1411         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1412                                    &frev, &crev, &data_offset)) {
1413                 igp_info = (union igp_info *)
1414                         ((char *)mode_info->atom_context->bios + data_offset);
1415                 switch (crev) {
1416                 case 6:
1417                         switch (id) {
1418                         case ASIC_INTERNAL_SS_ON_TMDS:
1419                                 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1420                                 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1421                                 break;
1422                         case ASIC_INTERNAL_SS_ON_HDMI:
1423                                 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1424                                 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1425                                 break;
1426                         case ASIC_INTERNAL_SS_ON_LVDS:
1427                                 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1428                                 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1429                                 break;
1430                         }
1431                         break;
1432                 case 7:
1433                         switch (id) {
1434                         case ASIC_INTERNAL_SS_ON_TMDS:
1435                                 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1436                                 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1437                                 break;
1438                         case ASIC_INTERNAL_SS_ON_HDMI:
1439                                 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1440                                 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1441                                 break;
1442                         case ASIC_INTERNAL_SS_ON_LVDS:
1443                                 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1444                                 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1445                                 break;
1446                         }
1447                         break;
1448                 default:
1449                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1450                         break;
1451                 }
1452                 if (percentage)
1453                         ss->percentage = percentage;
1454                 if (rate)
1455                         ss->rate = rate;
1456         }
1457 }
1458
1459 union asic_ss_info {
1460         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1461         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1462         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1463 };
1464
1465 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1466                                       struct radeon_atom_ss *ss,
1467                                       int id, u32 clock)
1468 {
1469         struct radeon_mode_info *mode_info = &rdev->mode_info;
1470         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1471         uint16_t data_offset, size;
1472         union asic_ss_info *ss_info;
1473         uint8_t frev, crev;
1474         int i, num_indices;
1475
1476         memset(ss, 0, sizeof(struct radeon_atom_ss));
1477         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1478                                    &frev, &crev, &data_offset)) {
1479
1480                 ss_info =
1481                         (union asic_ss_info *)((char *)mode_info->atom_context->bios + data_offset);
1482
1483                 switch (frev) {
1484                 case 1:
1485                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1486                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1487
1488                         for (i = 0; i < num_indices; i++) {
1489                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1490                                     (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) {
1491                                         ss->percentage =
1492                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1493                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1494                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1495                                         return true;
1496                                 }
1497                         }
1498                         break;
1499                 case 2:
1500                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1501                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1502                         for (i = 0; i < num_indices; i++) {
1503                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1504                                     (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) {
1505                                         ss->percentage =
1506                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1507                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1508                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1509                                         return true;
1510                                 }
1511                         }
1512                         break;
1513                 case 3:
1514                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1515                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1516                         for (i = 0; i < num_indices; i++) {
1517                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1518                                     (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) {
1519                                         ss->percentage =
1520                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1521                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1522                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1523                                         if (rdev->flags & RADEON_IS_IGP)
1524                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1525                                         return true;
1526                                 }
1527                         }
1528                         break;
1529                 default:
1530                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1531                         break;
1532                 }
1533
1534         }
1535         return false;
1536 }
1537
1538 union lvds_info {
1539         struct _ATOM_LVDS_INFO info;
1540         struct _ATOM_LVDS_INFO_V12 info_12;
1541 };
1542
1543 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1544                                                               radeon_encoder
1545                                                               *encoder)
1546 {
1547         struct drm_device *dev = encoder->base.dev;
1548         struct radeon_device *rdev = dev->dev_private;
1549         struct radeon_mode_info *mode_info = &rdev->mode_info;
1550         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1551         uint16_t data_offset, misc;
1552         union lvds_info *lvds_info;
1553         uint8_t frev, crev;
1554         struct radeon_encoder_atom_dig *lvds = NULL;
1555         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1556
1557         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1558                                    &frev, &crev, &data_offset)) {
1559                 lvds_info =
1560                         (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
1561                 lvds =
1562                     malloc(sizeof(struct radeon_encoder_atom_dig),
1563                         DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1564
1565                 if (!lvds)
1566                         return NULL;
1567
1568                 lvds->native_mode.clock =
1569                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1570                 lvds->native_mode.hdisplay =
1571                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1572                 lvds->native_mode.vdisplay =
1573                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1574                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1575                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1576                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1577                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1578                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1579                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1580                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1581                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1582                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1583                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1584                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1585                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1586                 lvds->panel_pwr_delay =
1587                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1588                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1589
1590                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1591                 if (misc & ATOM_VSYNC_POLARITY)
1592                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1593                 if (misc & ATOM_HSYNC_POLARITY)
1594                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1595                 if (misc & ATOM_COMPOSITESYNC)
1596                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1597                 if (misc & ATOM_INTERLACE)
1598                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1599                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1600                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1601
1602                 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1603                 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1604
1605                 /* set crtc values */
1606                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1607
1608                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1609
1610                 encoder->native_mode = lvds->native_mode;
1611
1612                 if (encoder_enum == 2)
1613                         lvds->linkb = true;
1614                 else
1615                         lvds->linkb = false;
1616
1617                 /* parse the lcd record table */
1618                 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1619                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1620                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1621                         bool bad_record = false;
1622                         u8 *record;
1623
1624                         if ((frev == 1) && (crev < 2))
1625                                 /* absolute */
1626                                 record = (u8 *)((char *)mode_info->atom_context->bios +
1627                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1628                         else
1629                                 /* relative */
1630                                 record = (u8 *)((char *)mode_info->atom_context->bios +
1631                                                 data_offset +
1632                                                 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1633                         while (*record != ATOM_RECORD_END_TYPE) {
1634                                 switch (*record) {
1635                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1636                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1637                                         break;
1638                                 case LCD_RTS_RECORD_TYPE:
1639                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1640                                         break;
1641                                 case LCD_CAP_RECORD_TYPE:
1642                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1643                                         break;
1644                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1645                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1646                                         if (fake_edid_record->ucFakeEDIDLength) {
1647                                                 struct edid *edid;
1648                                                 int edid_size =
1649                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1650                                                 edid = malloc(edid_size, DRM_MEM_KMS, M_NOWAIT);
1651                                                 if (edid) {
1652                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1653                                                                fake_edid_record->ucFakeEDIDLength);
1654
1655                                                         if (drm_edid_is_valid(edid)) {
1656                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1657                                                                 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1658                                                         } else
1659                                                                 free(edid, DRM_MEM_KMS);
1660                                                 }
1661                                         }
1662                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1663                                         break;
1664                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1665                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1666                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1667                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1668                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1669                                         break;
1670                                 default:
1671                                         DRM_ERROR("Bad LCD record %d\n", *record);
1672                                         bad_record = true;
1673                                         break;
1674                                 }
1675                                 if (bad_record)
1676                                         break;
1677                         }
1678                 }
1679         }
1680         return lvds;
1681 }
1682
1683 struct radeon_encoder_primary_dac *
1684 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1685 {
1686         struct drm_device *dev = encoder->base.dev;
1687         struct radeon_device *rdev = dev->dev_private;
1688         struct radeon_mode_info *mode_info = &rdev->mode_info;
1689         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1690         uint16_t data_offset;
1691         struct _COMPASSIONATE_DATA *dac_info;
1692         uint8_t frev, crev;
1693         uint8_t bg, dac;
1694         struct radeon_encoder_primary_dac *p_dac = NULL;
1695
1696         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1697                                    &frev, &crev, &data_offset)) {
1698                 dac_info = (struct _COMPASSIONATE_DATA *)
1699                         ((char *)mode_info->atom_context->bios + data_offset);
1700
1701                 p_dac = malloc(sizeof(struct radeon_encoder_primary_dac),
1702                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1703
1704                 if (!p_dac)
1705                         return NULL;
1706
1707                 bg = dac_info->ucDAC1_BG_Adjustment;
1708                 dac = dac_info->ucDAC1_DAC_Adjustment;
1709                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1710
1711         }
1712         return p_dac;
1713 }
1714
1715 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1716                                 struct drm_display_mode *mode)
1717 {
1718         struct radeon_mode_info *mode_info = &rdev->mode_info;
1719         ATOM_ANALOG_TV_INFO *tv_info;
1720         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1721         ATOM_DTD_FORMAT *dtd_timings;
1722         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1723         u8 frev, crev;
1724         u16 data_offset, misc;
1725
1726         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1727                                     &frev, &crev, &data_offset))
1728                 return false;
1729
1730         switch (crev) {
1731         case 1:
1732                 tv_info = (ATOM_ANALOG_TV_INFO *)((char *)mode_info->atom_context->bios + data_offset);
1733                 if (index >= MAX_SUPPORTED_TV_TIMING)
1734                         return false;
1735
1736                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1737                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1738                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1739                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1740                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1741
1742                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1743                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1744                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1745                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1746                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1747
1748                 mode->flags = 0;
1749                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1750                 if (misc & ATOM_VSYNC_POLARITY)
1751                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1752                 if (misc & ATOM_HSYNC_POLARITY)
1753                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1754                 if (misc & ATOM_COMPOSITESYNC)
1755                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1756                 if (misc & ATOM_INTERLACE)
1757                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1758                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1759                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1760
1761                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1762
1763                 if (index == 1) {
1764                         /* PAL timings appear to have wrong values for totals */
1765                         mode->crtc_htotal -= 1;
1766                         mode->crtc_vtotal -= 1;
1767                 }
1768                 break;
1769         case 2:
1770                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)((char *)mode_info->atom_context->bios + data_offset);
1771                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1772                         return false;
1773
1774                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1775                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1776                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1777                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1778                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1779                         le16_to_cpu(dtd_timings->usHSyncOffset);
1780                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1781                         le16_to_cpu(dtd_timings->usHSyncWidth);
1782
1783                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1784                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1785                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1786                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1787                         le16_to_cpu(dtd_timings->usVSyncOffset);
1788                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1789                         le16_to_cpu(dtd_timings->usVSyncWidth);
1790
1791                 mode->flags = 0;
1792                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1793                 if (misc & ATOM_VSYNC_POLARITY)
1794                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1795                 if (misc & ATOM_HSYNC_POLARITY)
1796                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1797                 if (misc & ATOM_COMPOSITESYNC)
1798                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1799                 if (misc & ATOM_INTERLACE)
1800                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1801                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1802                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1803
1804                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1805                 break;
1806         }
1807         return true;
1808 }
1809
1810 enum radeon_tv_std
1811 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1812 {
1813         struct radeon_mode_info *mode_info = &rdev->mode_info;
1814         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1815         uint16_t data_offset;
1816         uint8_t frev, crev;
1817         struct _ATOM_ANALOG_TV_INFO *tv_info;
1818         enum radeon_tv_std tv_std = TV_STD_NTSC;
1819
1820         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1821                                    &frev, &crev, &data_offset)) {
1822
1823                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1824                         ((char *)mode_info->atom_context->bios + data_offset);
1825
1826                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1827                 case ATOM_TV_NTSC:
1828                         tv_std = TV_STD_NTSC;
1829                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1830                         break;
1831                 case ATOM_TV_NTSCJ:
1832                         tv_std = TV_STD_NTSC_J;
1833                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1834                         break;
1835                 case ATOM_TV_PAL:
1836                         tv_std = TV_STD_PAL;
1837                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1838                         break;
1839                 case ATOM_TV_PALM:
1840                         tv_std = TV_STD_PAL_M;
1841                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1842                         break;
1843                 case ATOM_TV_PALN:
1844                         tv_std = TV_STD_PAL_N;
1845                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1846                         break;
1847                 case ATOM_TV_PALCN:
1848                         tv_std = TV_STD_PAL_CN;
1849                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1850                         break;
1851                 case ATOM_TV_PAL60:
1852                         tv_std = TV_STD_PAL_60;
1853                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1854                         break;
1855                 case ATOM_TV_SECAM:
1856                         tv_std = TV_STD_SECAM;
1857                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1858                         break;
1859                 default:
1860                         tv_std = TV_STD_NTSC;
1861                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1862                         break;
1863                 }
1864         }
1865         return tv_std;
1866 }
1867
1868 struct radeon_encoder_tv_dac *
1869 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1870 {
1871         struct drm_device *dev = encoder->base.dev;
1872         struct radeon_device *rdev = dev->dev_private;
1873         struct radeon_mode_info *mode_info = &rdev->mode_info;
1874         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1875         uint16_t data_offset;
1876         struct _COMPASSIONATE_DATA *dac_info;
1877         uint8_t frev, crev;
1878         uint8_t bg, dac;
1879         struct radeon_encoder_tv_dac *tv_dac = NULL;
1880
1881         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1882                                    &frev, &crev, &data_offset)) {
1883
1884                 dac_info = (struct _COMPASSIONATE_DATA *)
1885                         ((char *)mode_info->atom_context->bios + data_offset);
1886
1887                 tv_dac = malloc(sizeof(struct radeon_encoder_tv_dac),
1888                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1889
1890                 if (!tv_dac)
1891                         return NULL;
1892
1893                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1894                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1895                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1896
1897                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1898                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1899                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1900
1901                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1902                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1903                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1904
1905                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1906         }
1907         return tv_dac;
1908 }
1909
1910 static const char *thermal_controller_names[] = {
1911         "NONE",
1912         "lm63",
1913         "adm1032",
1914         "adm1030",
1915         "max6649",
1916         "lm64",
1917         "f75375",
1918         "asc7xxx",
1919 };
1920
1921 static const char *pp_lib_thermal_controller_names[] = {
1922         "NONE",
1923         "lm63",
1924         "adm1032",
1925         "adm1030",
1926         "max6649",
1927         "lm64",
1928         "f75375",
1929         "RV6xx",
1930         "RV770",
1931         "adt7473",
1932         "NONE",
1933         "External GPIO",
1934         "Evergreen",
1935         "emc2103",
1936         "Sumo",
1937         "Northern Islands",
1938         "Southern Islands",
1939         "lm96163",
1940 };
1941
1942 union power_info {
1943         struct _ATOM_POWERPLAY_INFO info;
1944         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1945         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1946         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1947         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1948         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1949 };
1950
1951 union pplib_clock_info {
1952         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1953         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1954         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1955         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1956         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
1957 };
1958
1959 union pplib_power_state {
1960         struct _ATOM_PPLIB_STATE v1;
1961         struct _ATOM_PPLIB_STATE_V2 v2;
1962 };
1963
1964 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1965                                                  int state_index,
1966                                                  u32 misc, u32 misc2)
1967 {
1968         rdev->pm.power_state[state_index].misc = misc;
1969         rdev->pm.power_state[state_index].misc2 = misc2;
1970         /* order matters! */
1971         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1972                 rdev->pm.power_state[state_index].type =
1973                         POWER_STATE_TYPE_POWERSAVE;
1974         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1975                 rdev->pm.power_state[state_index].type =
1976                         POWER_STATE_TYPE_BATTERY;
1977         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1978                 rdev->pm.power_state[state_index].type =
1979                         POWER_STATE_TYPE_BATTERY;
1980         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1981                 rdev->pm.power_state[state_index].type =
1982                         POWER_STATE_TYPE_BALANCED;
1983         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1984                 rdev->pm.power_state[state_index].type =
1985                         POWER_STATE_TYPE_PERFORMANCE;
1986                 rdev->pm.power_state[state_index].flags &=
1987                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1988         }
1989         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1990                 rdev->pm.power_state[state_index].type =
1991                         POWER_STATE_TYPE_BALANCED;
1992         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1993                 rdev->pm.power_state[state_index].type =
1994                         POWER_STATE_TYPE_DEFAULT;
1995                 rdev->pm.default_power_state_index = state_index;
1996                 rdev->pm.power_state[state_index].default_clock_mode =
1997                         &rdev->pm.power_state[state_index].clock_info[0];
1998         } else if (state_index == 0) {
1999                 rdev->pm.power_state[state_index].clock_info[0].flags |=
2000                         RADEON_PM_MODE_NO_DISPLAY;
2001         }
2002 }
2003
2004 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2005 {
2006         struct radeon_mode_info *mode_info = &rdev->mode_info;
2007         u32 misc, misc2 = 0;
2008         int num_modes = 0, i;
2009         int state_index = 0;
2010         struct radeon_i2c_bus_rec i2c_bus;
2011         union power_info *power_info;
2012         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2013         u16 data_offset;
2014         u8 frev, crev;
2015
2016         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2017                                    &frev, &crev, &data_offset))
2018                 return state_index;
2019         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2020
2021         /* add the i2c bus for thermal/fan chip */
2022         if ((power_info->info.ucOverdriveThermalController > 0) &&
2023             (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2024                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2025                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
2026                          power_info->info.ucOverdriveControllerAddress >> 1);
2027                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2028                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2029 #ifdef FREEBSD_WIP
2030                 if (rdev->pm.i2c_bus) {
2031                         struct i2c_board_info info = { };
2032                         const char *name = thermal_controller_names[power_info->info.
2033                                                                     ucOverdriveThermalController];
2034                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2035                         strlcpy(info.type, name, sizeof(info.type));
2036                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2037                 }
2038 #endif /* FREEBSD_WIP */
2039         }
2040         num_modes = power_info->info.ucNumOfPowerModeEntries;
2041         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2042                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2043         if (num_modes == 0)
2044                 return state_index;
2045         rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) * num_modes,
2046             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2047         if (!rdev->pm.power_state)
2048                 return state_index;
2049         /* last mode is usually default, array is low to high */
2050         for (i = 0; i < num_modes; i++) {
2051                 rdev->pm.power_state[state_index].clock_info =
2052                         malloc(sizeof(struct radeon_pm_clock_info) * 1,
2053                             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2054                 if (!rdev->pm.power_state[state_index].clock_info)
2055                         return state_index;
2056                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2057                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2058                 switch (frev) {
2059                 case 1:
2060                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2061                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2062                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2063                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2064                         /* skip invalid modes */
2065                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2066                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2067                                 continue;
2068                         rdev->pm.power_state[state_index].pcie_lanes =
2069                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2070                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2071                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2072                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2073                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2074                                         VOLTAGE_GPIO;
2075                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2076                                         radeon_lookup_gpio(rdev,
2077                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2078                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2079                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2080                                                 true;
2081                                 else
2082                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2083                                                 false;
2084                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2085                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2086                                         VOLTAGE_VDDC;
2087                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2088                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2089                         }
2090                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2091                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2092                         state_index++;
2093                         break;
2094                 case 2:
2095                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2096                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2097                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2098                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2099                         /* skip invalid modes */
2100                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2101                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2102                                 continue;
2103                         rdev->pm.power_state[state_index].pcie_lanes =
2104                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2105                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2106                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2107                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2108                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2109                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2110                                         VOLTAGE_GPIO;
2111                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2112                                         radeon_lookup_gpio(rdev,
2113                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2114                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2115                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2116                                                 true;
2117                                 else
2118                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2119                                                 false;
2120                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2121                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2122                                         VOLTAGE_VDDC;
2123                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2124                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2125                         }
2126                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2127                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2128                         state_index++;
2129                         break;
2130                 case 3:
2131                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2132                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2133                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2134                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2135                         /* skip invalid modes */
2136                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2137                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2138                                 continue;
2139                         rdev->pm.power_state[state_index].pcie_lanes =
2140                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2141                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2142                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2143                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2144                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2145                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2146                                         VOLTAGE_GPIO;
2147                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2148                                         radeon_lookup_gpio(rdev,
2149                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2150                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2151                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2152                                                 true;
2153                                 else
2154                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2155                                                 false;
2156                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2157                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2158                                         VOLTAGE_VDDC;
2159                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2160                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2161                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2162                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2163                                                 true;
2164                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2165                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2166                                 }
2167                         }
2168                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2169                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2170                         state_index++;
2171                         break;
2172                 }
2173         }
2174         /* last mode is usually default */
2175         if (rdev->pm.default_power_state_index == -1) {
2176                 rdev->pm.power_state[state_index - 1].type =
2177                         POWER_STATE_TYPE_DEFAULT;
2178                 rdev->pm.default_power_state_index = state_index - 1;
2179                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2180                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2181                 rdev->pm.power_state[state_index].flags &=
2182                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2183                 rdev->pm.power_state[state_index].misc = 0;
2184                 rdev->pm.power_state[state_index].misc2 = 0;
2185         }
2186         return state_index;
2187 }
2188
2189 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2190                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2191 {
2192         struct radeon_i2c_bus_rec i2c_bus;
2193
2194         /* add the i2c bus for thermal/fan chip */
2195         if (controller->ucType > 0) {
2196                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2197                         DRM_INFO("Internal thermal controller %s fan control\n",
2198                                  (controller->ucFanParameters &
2199                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2200                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2201                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2202                         DRM_INFO("Internal thermal controller %s fan control\n",
2203                                  (controller->ucFanParameters &
2204                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2205                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2206                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2207                         DRM_INFO("Internal thermal controller %s fan control\n",
2208                                  (controller->ucFanParameters &
2209                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2210                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2211                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2212                         DRM_INFO("Internal thermal controller %s fan control\n",
2213                                  (controller->ucFanParameters &
2214                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2215                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2216                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2217                         DRM_INFO("Internal thermal controller %s fan control\n",
2218                                  (controller->ucFanParameters &
2219                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2220                         rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2221                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2222                         DRM_INFO("Internal thermal controller %s fan control\n",
2223                                  (controller->ucFanParameters &
2224                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2225                         rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2226                 } else if ((controller->ucType ==
2227                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2228                            (controller->ucType ==
2229                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2230                            (controller->ucType ==
2231                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2232                         DRM_INFO("Special thermal controller config\n");
2233                 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2234                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2235                                  pp_lib_thermal_controller_names[controller->ucType],
2236                                  controller->ucI2cAddress >> 1,
2237                                  (controller->ucFanParameters &
2238                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2239                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2240                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2241 #ifdef FREEBSD_WIP
2242                         if (rdev->pm.i2c_bus) {
2243                                 struct i2c_board_info info = { };
2244                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2245                                 info.addr = controller->ucI2cAddress >> 1;
2246                                 strlcpy(info.type, name, sizeof(info.type));
2247                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2248                         }
2249 #endif /* FREEBSD_WIP */
2250                 } else {
2251                         DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2252                                  controller->ucType,
2253                                  controller->ucI2cAddress >> 1,
2254                                  (controller->ucFanParameters &
2255                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2256                 }
2257         }
2258 }
2259
2260 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2261                                                  u16 *vddc, u16 *vddci)
2262 {
2263         struct radeon_mode_info *mode_info = &rdev->mode_info;
2264         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2265         u8 frev, crev;
2266         u16 data_offset;
2267         union firmware_info *firmware_info;
2268
2269         *vddc = 0;
2270         *vddci = 0;
2271
2272         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2273                                    &frev, &crev, &data_offset)) {
2274                 firmware_info =
2275                         (union firmware_info *)((char *)mode_info->atom_context->bios +
2276                                                 data_offset);
2277                 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2278                 if ((frev == 2) && (crev >= 2))
2279                         *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2280         }
2281 }
2282
2283 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2284                                                        int state_index, int mode_index,
2285                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2286 {
2287         int j;
2288         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2289         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2290         u16 vddc, vddci;
2291
2292         radeon_atombios_get_default_voltages(rdev, &vddc, &vddci);
2293
2294         rdev->pm.power_state[state_index].misc = misc;
2295         rdev->pm.power_state[state_index].misc2 = misc2;
2296         rdev->pm.power_state[state_index].pcie_lanes =
2297                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2298                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2299         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2300         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2301                 rdev->pm.power_state[state_index].type =
2302                         POWER_STATE_TYPE_BATTERY;
2303                 break;
2304         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2305                 rdev->pm.power_state[state_index].type =
2306                         POWER_STATE_TYPE_BALANCED;
2307                 break;
2308         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2309                 rdev->pm.power_state[state_index].type =
2310                         POWER_STATE_TYPE_PERFORMANCE;
2311                 break;
2312         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2313                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2314                         rdev->pm.power_state[state_index].type =
2315                                 POWER_STATE_TYPE_PERFORMANCE;
2316                 break;
2317         }
2318         rdev->pm.power_state[state_index].flags = 0;
2319         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2320                 rdev->pm.power_state[state_index].flags |=
2321                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2322         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2323                 rdev->pm.power_state[state_index].type =
2324                         POWER_STATE_TYPE_DEFAULT;
2325                 rdev->pm.default_power_state_index = state_index;
2326                 rdev->pm.power_state[state_index].default_clock_mode =
2327                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2328                 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2329                         /* NI chips post without MC ucode, so default clocks are strobe mode only */
2330                         rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2331                         rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2332                         rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2333                         rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2334                 } else {
2335                         /* patch the table values with the default slck/mclk from firmware info */
2336                         for (j = 0; j < mode_index; j++) {
2337                                 rdev->pm.power_state[state_index].clock_info[j].mclk =
2338                                         rdev->clock.default_mclk;
2339                                 rdev->pm.power_state[state_index].clock_info[j].sclk =
2340                                         rdev->clock.default_sclk;
2341                                 if (vddc)
2342                                         rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2343                                                 vddc;
2344                         }
2345                 }
2346         }
2347 }
2348
2349 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2350                                                    int state_index, int mode_index,
2351                                                    union pplib_clock_info *clock_info)
2352 {
2353         u32 sclk, mclk;
2354         u16 vddc;
2355
2356         if (rdev->flags & RADEON_IS_IGP) {
2357                 if (rdev->family >= CHIP_PALM) {
2358                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2359                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2360                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2361                 } else {
2362                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2363                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2364                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2365                 }
2366         } else if (ASIC_IS_DCE6(rdev)) {
2367                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2368                 sclk |= clock_info->si.ucEngineClockHigh << 16;
2369                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2370                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2371                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2372                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2373                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2374                         VOLTAGE_SW;
2375                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2376                         le16_to_cpu(clock_info->si.usVDDC);
2377                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2378                         le16_to_cpu(clock_info->si.usVDDCI);
2379         } else if (ASIC_IS_DCE4(rdev)) {
2380                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2381                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2382                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2383                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2384                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2385                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2386                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2387                         VOLTAGE_SW;
2388                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2389                         le16_to_cpu(clock_info->evergreen.usVDDC);
2390                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2391                         le16_to_cpu(clock_info->evergreen.usVDDCI);
2392         } else {
2393                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2394                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2395                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2396                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2397                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2398                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2399                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2400                         VOLTAGE_SW;
2401                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2402                         le16_to_cpu(clock_info->r600.usVDDC);
2403         }
2404
2405         /* patch up vddc if necessary */
2406         switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2407         case ATOM_VIRTUAL_VOLTAGE_ID0:
2408         case ATOM_VIRTUAL_VOLTAGE_ID1:
2409         case ATOM_VIRTUAL_VOLTAGE_ID2:
2410         case ATOM_VIRTUAL_VOLTAGE_ID3:
2411                 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2412                                              rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2413                                              &vddc) == 0)
2414                         rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2415                 break;
2416         default:
2417                 break;
2418         }
2419
2420         if (rdev->flags & RADEON_IS_IGP) {
2421                 /* skip invalid modes */
2422                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2423                         return false;
2424         } else {
2425                 /* skip invalid modes */
2426                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2427                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2428                         return false;
2429         }
2430         return true;
2431 }
2432
2433 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2434 {
2435         struct radeon_mode_info *mode_info = &rdev->mode_info;
2436         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2437         union pplib_power_state *power_state;
2438         int i, j;
2439         int state_index = 0, mode_index = 0;
2440         union pplib_clock_info *clock_info;
2441         bool valid;
2442         union power_info *power_info;
2443         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2444         u16 data_offset;
2445         u8 frev, crev;
2446
2447         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2448                                    &frev, &crev, &data_offset))
2449                 return state_index;
2450         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2451
2452         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2453         if (power_info->pplib.ucNumStates == 0)
2454                 return state_index;
2455         rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2456                                        power_info->pplib.ucNumStates,
2457                                        DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2458         if (!rdev->pm.power_state)
2459                 return state_index;
2460         /* first mode is usually default, followed by low to high */
2461         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2462                 mode_index = 0;
2463                 power_state = (union pplib_power_state *)
2464                         ((char *)mode_info->atom_context->bios + data_offset +
2465                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2466                          i * power_info->pplib.ucStateEntrySize);
2467                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2468                         ((char *)mode_info->atom_context->bios + data_offset +
2469                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2470                          (power_state->v1.ucNonClockStateIndex *
2471                           power_info->pplib.ucNonClockSize));
2472                 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2473                                                              ((power_info->pplib.ucStateEntrySize - 1) ?
2474                                                               (power_info->pplib.ucStateEntrySize - 1) : 1),
2475                                                              DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2476                 if (!rdev->pm.power_state[i].clock_info)
2477                         return state_index;
2478                 if (power_info->pplib.ucStateEntrySize - 1) {
2479                         for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2480                                 clock_info = (union pplib_clock_info *)
2481                                         ((char *)mode_info->atom_context->bios + data_offset +
2482                                          le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2483                                          (power_state->v1.ucClockStateIndices[j] *
2484                                           power_info->pplib.ucClockInfoSize));
2485                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2486                                                                                state_index, mode_index,
2487                                                                                clock_info);
2488                                 if (valid)
2489                                         mode_index++;
2490                         }
2491                 } else {
2492                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2493                                 rdev->clock.default_mclk;
2494                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2495                                 rdev->clock.default_sclk;
2496                         mode_index++;
2497                 }
2498                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2499                 if (mode_index) {
2500                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2501                                                                    non_clock_info);
2502                         state_index++;
2503                 }
2504         }
2505         /* if multiple clock modes, mark the lowest as no display */
2506         for (i = 0; i < state_index; i++) {
2507                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2508                         rdev->pm.power_state[i].clock_info[0].flags |=
2509                                 RADEON_PM_MODE_NO_DISPLAY;
2510         }
2511         /* first mode is usually default */
2512         if (rdev->pm.default_power_state_index == -1) {
2513                 rdev->pm.power_state[0].type =
2514                         POWER_STATE_TYPE_DEFAULT;
2515                 rdev->pm.default_power_state_index = 0;
2516                 rdev->pm.power_state[0].default_clock_mode =
2517                         &rdev->pm.power_state[0].clock_info[0];
2518         }
2519         return state_index;
2520 }
2521
2522 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2523 {
2524         struct radeon_mode_info *mode_info = &rdev->mode_info;
2525         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2526         union pplib_power_state *power_state;
2527         int i, j, non_clock_array_index, clock_array_index;
2528         int state_index = 0, mode_index = 0;
2529         union pplib_clock_info *clock_info;
2530         struct _StateArray *state_array;
2531         struct _ClockInfoArray *clock_info_array;
2532         struct _NonClockInfoArray *non_clock_info_array;
2533         bool valid;
2534         union power_info *power_info;
2535         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2536         u16 data_offset;
2537         u8 frev, crev;
2538         u8 *power_state_offset;
2539
2540         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2541                                    &frev, &crev, &data_offset))
2542                 return state_index;
2543         power_info = (union power_info *)((char *)mode_info->atom_context->bios + data_offset);
2544
2545         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2546         state_array = (struct _StateArray *)
2547                 ((char *)mode_info->atom_context->bios + data_offset +
2548                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2549         clock_info_array = (struct _ClockInfoArray *)
2550                 ((char *)mode_info->atom_context->bios + data_offset +
2551                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2552         non_clock_info_array = (struct _NonClockInfoArray *)
2553                 ((char *)mode_info->atom_context->bios + data_offset +
2554                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2555         if (state_array->ucNumEntries == 0)
2556                 return state_index;
2557         rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) *
2558                                        state_array->ucNumEntries,
2559                                        DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2560         if (!rdev->pm.power_state)
2561                 return state_index;
2562         power_state_offset = (u8 *)state_array->states;
2563         for (i = 0; i < state_array->ucNumEntries; i++) {
2564                 mode_index = 0;
2565                 power_state = (union pplib_power_state *)power_state_offset;
2566                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2567                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2568                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2569                 rdev->pm.power_state[i].clock_info = malloc(sizeof(struct radeon_pm_clock_info) *
2570                                                              (power_state->v2.ucNumDPMLevels ?
2571                                                               power_state->v2.ucNumDPMLevels : 1),
2572                                                              DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2573                 if (!rdev->pm.power_state[i].clock_info)
2574                         return state_index;
2575                 if (power_state->v2.ucNumDPMLevels) {
2576                         for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2577                                 clock_array_index = power_state->v2.clockInfoIndex[j];
2578                                 clock_info = (union pplib_clock_info *)
2579                                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2580                                 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2581                                                                                state_index, mode_index,
2582                                                                                clock_info);
2583                                 if (valid)
2584                                         mode_index++;
2585                         }
2586                 } else {
2587                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2588                                 rdev->clock.default_mclk;
2589                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2590                                 rdev->clock.default_sclk;
2591                         mode_index++;
2592                 }
2593                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2594                 if (mode_index) {
2595                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2596                                                                    non_clock_info);
2597                         state_index++;
2598                 }
2599                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2600         }
2601         /* if multiple clock modes, mark the lowest as no display */
2602         for (i = 0; i < state_index; i++) {
2603                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2604                         rdev->pm.power_state[i].clock_info[0].flags |=
2605                                 RADEON_PM_MODE_NO_DISPLAY;
2606         }
2607         /* first mode is usually default */
2608         if (rdev->pm.default_power_state_index == -1) {
2609                 rdev->pm.power_state[0].type =
2610                         POWER_STATE_TYPE_DEFAULT;
2611                 rdev->pm.default_power_state_index = 0;
2612                 rdev->pm.power_state[0].default_clock_mode =
2613                         &rdev->pm.power_state[0].clock_info[0];
2614         }
2615         return state_index;
2616 }
2617
2618 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2619 {
2620         struct radeon_mode_info *mode_info = &rdev->mode_info;
2621         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2622         u16 data_offset;
2623         u8 frev, crev;
2624         int state_index = 0;
2625
2626         rdev->pm.default_power_state_index = -1;
2627
2628         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2629                                    &frev, &crev, &data_offset)) {
2630                 switch (frev) {
2631                 case 1:
2632                 case 2:
2633                 case 3:
2634                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2635                         break;
2636                 case 4:
2637                 case 5:
2638                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2639                         break;
2640                 case 6:
2641                         state_index = radeon_atombios_parse_power_table_6(rdev);
2642                         break;
2643                 default:
2644                         break;
2645                 }
2646         }
2647
2648         if (state_index == 0) {
2649                 rdev->pm.power_state = malloc(sizeof(struct radeon_power_state),
2650                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2651                 if (rdev->pm.power_state) {
2652                         rdev->pm.power_state[0].clock_info =
2653                                 malloc(sizeof(struct radeon_pm_clock_info) * 1,
2654                                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2655                         if (rdev->pm.power_state[0].clock_info) {
2656                                 /* add the default mode */
2657                                 rdev->pm.power_state[state_index].type =
2658                                         POWER_STATE_TYPE_DEFAULT;
2659                                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2660                                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2661                                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2662                                 rdev->pm.power_state[state_index].default_clock_mode =
2663                                         &rdev->pm.power_state[state_index].clock_info[0];
2664                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2665                                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2666                                 rdev->pm.default_power_state_index = state_index;
2667                                 rdev->pm.power_state[state_index].flags = 0;
2668                                 state_index++;
2669                         }
2670                 }
2671         }
2672
2673         rdev->pm.num_power_states = state_index;
2674
2675         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2676         rdev->pm.current_clock_mode_index = 0;
2677         if (rdev->pm.default_power_state_index >= 0)
2678                 rdev->pm.current_vddc =
2679                         rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2680         else
2681                 rdev->pm.current_vddc = 0;
2682 }
2683
2684 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2685 {
2686         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2687         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2688
2689         args.ucEnable = enable;
2690
2691         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2692 }
2693
2694 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2695 {
2696         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2697         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2698
2699         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2700         return le32_to_cpu(args.ulReturnEngineClock);
2701 }
2702
2703 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2704 {
2705         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2706         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2707
2708         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2709         return le32_to_cpu(args.ulReturnMemoryClock);
2710 }
2711
2712 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2713                                   uint32_t eng_clock)
2714 {
2715         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2716         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2717
2718         args.ulTargetEngineClock = cpu_to_le32(eng_clock);      /* 10 khz */
2719
2720         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2721 }
2722
2723 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2724                                   uint32_t mem_clock)
2725 {
2726         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2727         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2728
2729         if (rdev->flags & RADEON_IS_IGP)
2730                 return;
2731
2732         args.ulTargetMemoryClock = cpu_to_le32(mem_clock);      /* 10 khz */
2733
2734         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2735 }
2736
2737 union set_voltage {
2738         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2739         struct _SET_VOLTAGE_PARAMETERS v1;
2740         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2741         struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
2742 };
2743
2744 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
2745 {
2746         union set_voltage args;
2747         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2748         u8 frev, crev, volt_index = voltage_level;
2749
2750         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2751                 return;
2752
2753         /* 0xff01 is a flag rather then an actual voltage */
2754         if (voltage_level == 0xff01)
2755                 return;
2756
2757         switch (crev) {
2758         case 1:
2759                 args.v1.ucVoltageType = voltage_type;
2760                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2761                 args.v1.ucVoltageIndex = volt_index;
2762                 break;
2763         case 2:
2764                 args.v2.ucVoltageType = voltage_type;
2765                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2766                 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
2767                 break;
2768         case 3:
2769                 args.v3.ucVoltageType = voltage_type;
2770                 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
2771                 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
2772                 break;
2773         default:
2774                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2775                 return;
2776         }
2777
2778         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2779 }
2780
2781 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
2782                                     u16 voltage_id, u16 *voltage)
2783 {
2784         union set_voltage args;
2785         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2786         u8 frev, crev;
2787
2788         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2789                 return -EINVAL;
2790
2791         switch (crev) {
2792         case 1:
2793                 return -EINVAL;
2794         case 2:
2795                 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
2796                 args.v2.ucVoltageMode = 0;
2797                 args.v2.usVoltageLevel = 0;
2798
2799                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2800
2801                 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
2802                 break;
2803         case 3:
2804                 args.v3.ucVoltageType = voltage_type;
2805                 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
2806                 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
2807
2808                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2809
2810                 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
2811                 break;
2812         default:
2813                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2814                 return -EINVAL;
2815         }
2816
2817         return 0;
2818 }
2819
2820 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2821 {
2822         struct radeon_device *rdev = dev->dev_private;
2823         uint32_t bios_2_scratch, bios_6_scratch;
2824
2825         if (rdev->family >= CHIP_R600) {
2826                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2827                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2828         } else {
2829                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2830                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2831         }
2832
2833         /* let the bios control the backlight */
2834         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2835
2836         /* tell the bios not to handle mode switching */
2837         bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
2838
2839         if (rdev->family >= CHIP_R600) {
2840                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2841                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2842         } else {
2843                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2844                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2845         }
2846
2847 }
2848
2849 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2850 {
2851         uint32_t scratch_reg;
2852         int i;
2853
2854         if (rdev->family >= CHIP_R600)
2855                 scratch_reg = R600_BIOS_0_SCRATCH;
2856         else
2857                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2858
2859         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2860                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2861 }
2862
2863 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2864 {
2865         uint32_t scratch_reg;
2866         int i;
2867
2868         if (rdev->family >= CHIP_R600)
2869                 scratch_reg = R600_BIOS_0_SCRATCH;
2870         else
2871                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2872
2873         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2874                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2875 }
2876
2877 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2878 {
2879         struct drm_device *dev = encoder->dev;
2880         struct radeon_device *rdev = dev->dev_private;
2881         uint32_t bios_6_scratch;
2882
2883         if (rdev->family >= CHIP_R600)
2884                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2885         else
2886                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2887
2888         if (lock) {
2889                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2890                 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
2891         } else {
2892                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2893                 bios_6_scratch |= ATOM_S6_ACC_MODE;
2894         }
2895
2896         if (rdev->family >= CHIP_R600)
2897                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2898         else
2899                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2900 }
2901
2902 /* at some point we may want to break this out into individual functions */
2903 void
2904 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2905                                        struct drm_encoder *encoder,
2906                                        bool connected)
2907 {
2908         struct drm_device *dev = connector->dev;
2909         struct radeon_device *rdev = dev->dev_private;
2910         struct radeon_connector *radeon_connector =
2911             to_radeon_connector(connector);
2912         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2913         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2914
2915         if (rdev->family >= CHIP_R600) {
2916                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2917                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2918                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2919         } else {
2920                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2921                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2922                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2923         }
2924
2925         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2926             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2927                 if (connected) {
2928                         DRM_DEBUG_KMS("TV1 connected\n");
2929                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2930                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2931                 } else {
2932                         DRM_DEBUG_KMS("TV1 disconnected\n");
2933                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2934                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2935                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2936                 }
2937         }
2938         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2939             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2940                 if (connected) {
2941                         DRM_DEBUG_KMS("CV connected\n");
2942                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2943                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2944                 } else {
2945                         DRM_DEBUG_KMS("CV disconnected\n");
2946                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2947                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2948                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2949                 }
2950         }
2951         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2952             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2953                 if (connected) {
2954                         DRM_DEBUG_KMS("LCD1 connected\n");
2955                         bios_0_scratch |= ATOM_S0_LCD1;
2956                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2957                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2958                 } else {
2959                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2960                         bios_0_scratch &= ~ATOM_S0_LCD1;
2961                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2962                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2963                 }
2964         }
2965         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2966             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2967                 if (connected) {
2968                         DRM_DEBUG_KMS("CRT1 connected\n");
2969                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2970                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2971                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2972                 } else {
2973                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2974                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2975                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2976                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2977                 }
2978         }
2979         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2980             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2981                 if (connected) {
2982                         DRM_DEBUG_KMS("CRT2 connected\n");
2983                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2984                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2985                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2986                 } else {
2987                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2988                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2989                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2990                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2991                 }
2992         }
2993         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2994             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2995                 if (connected) {
2996                         DRM_DEBUG_KMS("DFP1 connected\n");
2997                         bios_0_scratch |= ATOM_S0_DFP1;
2998                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2999                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
3000                 } else {
3001                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3002                         bios_0_scratch &= ~ATOM_S0_DFP1;
3003                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
3004                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
3005                 }
3006         }
3007         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3008             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3009                 if (connected) {
3010                         DRM_DEBUG_KMS("DFP2 connected\n");
3011                         bios_0_scratch |= ATOM_S0_DFP2;
3012                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
3013                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
3014                 } else {
3015                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3016                         bios_0_scratch &= ~ATOM_S0_DFP2;
3017                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
3018                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
3019                 }
3020         }
3021         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
3022             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
3023                 if (connected) {
3024                         DRM_DEBUG_KMS("DFP3 connected\n");
3025                         bios_0_scratch |= ATOM_S0_DFP3;
3026                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
3027                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
3028                 } else {
3029                         DRM_DEBUG_KMS("DFP3 disconnected\n");
3030                         bios_0_scratch &= ~ATOM_S0_DFP3;
3031                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
3032                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
3033                 }
3034         }
3035         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
3036             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
3037                 if (connected) {
3038                         DRM_DEBUG_KMS("DFP4 connected\n");
3039                         bios_0_scratch |= ATOM_S0_DFP4;
3040                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
3041                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
3042                 } else {
3043                         DRM_DEBUG_KMS("DFP4 disconnected\n");
3044                         bios_0_scratch &= ~ATOM_S0_DFP4;
3045                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
3046                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
3047                 }
3048         }
3049         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
3050             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
3051                 if (connected) {
3052                         DRM_DEBUG_KMS("DFP5 connected\n");
3053                         bios_0_scratch |= ATOM_S0_DFP5;
3054                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
3055                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
3056                 } else {
3057                         DRM_DEBUG_KMS("DFP5 disconnected\n");
3058                         bios_0_scratch &= ~ATOM_S0_DFP5;
3059                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
3060                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
3061                 }
3062         }
3063         if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
3064             (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
3065                 if (connected) {
3066                         DRM_DEBUG_KMS("DFP6 connected\n");
3067                         bios_0_scratch |= ATOM_S0_DFP6;
3068                         bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
3069                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
3070                 } else {
3071                         DRM_DEBUG_KMS("DFP6 disconnected\n");
3072                         bios_0_scratch &= ~ATOM_S0_DFP6;
3073                         bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
3074                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
3075                 }
3076         }
3077
3078         if (rdev->family >= CHIP_R600) {
3079                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
3080                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3081                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
3082         } else {
3083                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3084                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3085                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3086         }
3087 }
3088
3089 void
3090 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3091 {
3092         struct drm_device *dev = encoder->dev;
3093         struct radeon_device *rdev = dev->dev_private;
3094         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3095         uint32_t bios_3_scratch;
3096
3097         if (ASIC_IS_DCE4(rdev))
3098                 return;
3099
3100         if (rdev->family >= CHIP_R600)
3101                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
3102         else
3103                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
3104
3105         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3106                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
3107                 bios_3_scratch |= (crtc << 18);
3108         }
3109         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3110                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
3111                 bios_3_scratch |= (crtc << 24);
3112         }
3113         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3114                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
3115                 bios_3_scratch |= (crtc << 16);
3116         }
3117         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3118                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
3119                 bios_3_scratch |= (crtc << 20);
3120         }
3121         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3122                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
3123                 bios_3_scratch |= (crtc << 17);
3124         }
3125         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3126                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
3127                 bios_3_scratch |= (crtc << 19);
3128         }
3129         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3130                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
3131                 bios_3_scratch |= (crtc << 23);
3132         }
3133         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3134                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
3135                 bios_3_scratch |= (crtc << 25);
3136         }
3137
3138         if (rdev->family >= CHIP_R600)
3139                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
3140         else
3141                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
3142 }
3143
3144 void
3145 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3146 {
3147         struct drm_device *dev = encoder->dev;
3148         struct radeon_device *rdev = dev->dev_private;
3149         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3150         uint32_t bios_2_scratch;
3151
3152         if (ASIC_IS_DCE4(rdev))
3153                 return;
3154
3155         if (rdev->family >= CHIP_R600)
3156                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
3157         else
3158                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
3159
3160         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3161                 if (on)
3162                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
3163                 else
3164                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
3165         }
3166         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
3167                 if (on)
3168                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
3169                 else
3170                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
3171         }
3172         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3173                 if (on)
3174                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
3175                 else
3176                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
3177         }
3178         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3179                 if (on)
3180                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
3181                 else
3182                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
3183         }
3184         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3185                 if (on)
3186                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
3187                 else
3188                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
3189         }
3190         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3191                 if (on)
3192                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
3193                 else
3194                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
3195         }
3196         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3197                 if (on)
3198                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
3199                 else
3200                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
3201         }
3202         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
3203                 if (on)
3204                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
3205                 else
3206                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
3207         }
3208         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
3209                 if (on)
3210                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
3211                 else
3212                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
3213         }
3214         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
3215                 if (on)
3216                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
3217                 else
3218                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
3219         }
3220
3221         if (rdev->family >= CHIP_R600)
3222                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
3223         else
3224                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
3225 }