sys/dev/drm2/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include <dev/drm2/drmP.h>
  32 #include <dev/drm2/radeon/radeon_drm.h>
  33 #include "radeon.h"
  34 #include "atom.h"
  35
  36 #ifdef CONFIG_PPC_PMAC
  37 /* not sure which of these are needed */
  38 #include <asm/machdep.h>
  39 #include <asm/pmac_feature.h>
  40 #include <asm/prom.h>
  41 #include <asm/pci-bridge.h>
  42 #endif /* CONFIG_PPC_PMAC */
  43
  44 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
  45 /* from radeon_encoder.c */
  46 extern uint32_t
  47 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  48                         uint8_t dac);
  49 extern void radeon_link_encoder_connector(struct drm_device *dev);
  50
  51 /* from radeon_connector.c */
  52 extern void
  53 radeon_add_legacy_connector(struct drm_device *dev,
  54                             uint32_t connector_id,
  55                             uint32_t supported_device,
  56                             int connector_type,
  57                             struct radeon_i2c_bus_rec *i2c_bus,
  58                             uint16_t connector_object_id,
  59                             struct radeon_hpd *hpd);
  60
  61 /* from radeon_legacy_encoder.c */
  62 extern void
  63 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  64                           uint32_t supported_device);
  65 #endif
  66
  67 /* old legacy ATI BIOS routines */
  68
  69 /* COMBIOS table offsets */
  70 enum radeon_combios_table_offset {
  71         /* absolute offset tables */
  72         COMBIOS_ASIC_INIT_1_TABLE,
  73         COMBIOS_BIOS_SUPPORT_TABLE,
  74         COMBIOS_DAC_PROGRAMMING_TABLE,
  75         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  76         COMBIOS_CRTC_INFO_TABLE,
  77         COMBIOS_PLL_INFO_TABLE,
  78         COMBIOS_TV_INFO_TABLE,
  79         COMBIOS_DFP_INFO_TABLE,
  80         COMBIOS_HW_CONFIG_INFO_TABLE,
  81         COMBIOS_MULTIMEDIA_INFO_TABLE,
  82         COMBIOS_TV_STD_PATCH_TABLE,
  83         COMBIOS_LCD_INFO_TABLE,
  84         COMBIOS_MOBILE_INFO_TABLE,
  85         COMBIOS_PLL_INIT_TABLE,
  86         COMBIOS_MEM_CONFIG_TABLE,
  87         COMBIOS_SAVE_MASK_TABLE,
  88         COMBIOS_HARDCODED_EDID_TABLE,
  89         COMBIOS_ASIC_INIT_2_TABLE,
  90         COMBIOS_CONNECTOR_INFO_TABLE,
  91         COMBIOS_DYN_CLK_1_TABLE,
  92         COMBIOS_RESERVED_MEM_TABLE,
  93         COMBIOS_EXT_TMDS_INFO_TABLE,
  94         COMBIOS_MEM_CLK_INFO_TABLE,
  95         COMBIOS_EXT_DAC_INFO_TABLE,
  96         COMBIOS_MISC_INFO_TABLE,
  97         COMBIOS_CRT_INFO_TABLE,
  98         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  99         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
 100         COMBIOS_FAN_SPEED_INFO_TABLE,
 101         COMBIOS_OVERDRIVE_INFO_TABLE,
 102         COMBIOS_OEM_INFO_TABLE,
 103         COMBIOS_DYN_CLK_2_TABLE,
 104         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
 105         COMBIOS_I2C_INFO_TABLE,
 106         /* relative offset tables */
 107         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 108         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 109         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 110         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 111         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 112         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 113         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 114         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 115         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 116         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 117         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 118 };
 119
 120 enum radeon_combios_ddc {
 121         DDC_NONE_DETECTED,
 122         DDC_MONID,
 123         DDC_DVI,
 124         DDC_VGA,
 125         DDC_CRT2,
 126         DDC_LCD,
 127         DDC_GPIO,
 128 };
 129
 130 enum radeon_combios_connector {
 131         CONNECTOR_NONE_LEGACY,
 132         CONNECTOR_PROPRIETARY_LEGACY,
 133         CONNECTOR_CRT_LEGACY,
 134         CONNECTOR_DVI_I_LEGACY,
 135         CONNECTOR_DVI_D_LEGACY,
 136         CONNECTOR_CTV_LEGACY,
 137         CONNECTOR_STV_LEGACY,
 138         CONNECTOR_UNSUPPORTED_LEGACY
 139 };
 140
 141 const int legacy_connector_convert[] = {
 142         DRM_MODE_CONNECTOR_Unknown,
 143         DRM_MODE_CONNECTOR_DVID,
 144         DRM_MODE_CONNECTOR_VGA,
 145         DRM_MODE_CONNECTOR_DVII,
 146         DRM_MODE_CONNECTOR_DVID,
 147         DRM_MODE_CONNECTOR_Composite,
 148         DRM_MODE_CONNECTOR_SVIDEO,
 149         DRM_MODE_CONNECTOR_Unknown,
 150 };
 151
 152 static uint16_t combios_get_table_offset(struct drm_device *dev,
 153                                          enum radeon_combios_table_offset table)
 154 {
 155         struct radeon_device *rdev = dev->dev_private;
 156         int rev;
 157         uint16_t offset = 0, check_offset;
 158
 159         if (!rdev->bios)
 160                 return 0;
 161
 162         switch (table) {
 163                 /* absolute offset tables */
 164         case COMBIOS_ASIC_INIT_1_TABLE:
 165                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 166                 if (check_offset)
 167                         offset = check_offset;
 168                 break;
 169         case COMBIOS_BIOS_SUPPORT_TABLE:
 170                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 171                 if (check_offset)
 172                         offset = check_offset;
 173                 break;
 174         case COMBIOS_DAC_PROGRAMMING_TABLE:
 175                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 176                 if (check_offset)
 177                         offset = check_offset;
 178                 break;
 179         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 180                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 181                 if (check_offset)
 182                         offset = check_offset;
 183                 break;
 184         case COMBIOS_CRTC_INFO_TABLE:
 185                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 186                 if (check_offset)
 187                         offset = check_offset;
 188                 break;
 189         case COMBIOS_PLL_INFO_TABLE:
 190                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 191                 if (check_offset)
 192                         offset = check_offset;
 193                 break;
 194         case COMBIOS_TV_INFO_TABLE:
 195                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 196                 if (check_offset)
 197                         offset = check_offset;
 198                 break;
 199         case COMBIOS_DFP_INFO_TABLE:
 200                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 201                 if (check_offset)
 202                         offset = check_offset;
 203                 break;
 204         case COMBIOS_HW_CONFIG_INFO_TABLE:
 205                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 206                 if (check_offset)
 207                         offset = check_offset;
 208                 break;
 209         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 210                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 211                 if (check_offset)
 212                         offset = check_offset;
 213                 break;
 214         case COMBIOS_TV_STD_PATCH_TABLE:
 215                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 216                 if (check_offset)
 217                         offset = check_offset;
 218                 break;
 219         case COMBIOS_LCD_INFO_TABLE:
 220                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 221                 if (check_offset)
 222                         offset = check_offset;
 223                 break;
 224         case COMBIOS_MOBILE_INFO_TABLE:
 225                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 226                 if (check_offset)
 227                         offset = check_offset;
 228                 break;
 229         case COMBIOS_PLL_INIT_TABLE:
 230                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 231                 if (check_offset)
 232                         offset = check_offset;
 233                 break;
 234         case COMBIOS_MEM_CONFIG_TABLE:
 235                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 236                 if (check_offset)
 237                         offset = check_offset;
 238                 break;
 239         case COMBIOS_SAVE_MASK_TABLE:
 240                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 241                 if (check_offset)
 242                         offset = check_offset;
 243                 break;
 244         case COMBIOS_HARDCODED_EDID_TABLE:
 245                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 246                 if (check_offset)
 247                         offset = check_offset;
 248                 break;
 249         case COMBIOS_ASIC_INIT_2_TABLE:
 250                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 251                 if (check_offset)
 252                         offset = check_offset;
 253                 break;
 254         case COMBIOS_CONNECTOR_INFO_TABLE:
 255                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 256                 if (check_offset)
 257                         offset = check_offset;
 258                 break;
 259         case COMBIOS_DYN_CLK_1_TABLE:
 260                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 261                 if (check_offset)
 262                         offset = check_offset;
 263                 break;
 264         case COMBIOS_RESERVED_MEM_TABLE:
 265                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 266                 if (check_offset)
 267                         offset = check_offset;
 268                 break;
 269         case COMBIOS_EXT_TMDS_INFO_TABLE:
 270                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 271                 if (check_offset)
 272                         offset = check_offset;
 273                 break;
 274         case COMBIOS_MEM_CLK_INFO_TABLE:
 275                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 276                 if (check_offset)
 277                         offset = check_offset;
 278                 break;
 279         case COMBIOS_EXT_DAC_INFO_TABLE:
 280                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 281                 if (check_offset)
 282                         offset = check_offset;
 283                 break;
 284         case COMBIOS_MISC_INFO_TABLE:
 285                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 286                 if (check_offset)
 287                         offset = check_offset;
 288                 break;
 289         case COMBIOS_CRT_INFO_TABLE:
 290                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 291                 if (check_offset)
 292                         offset = check_offset;
 293                 break;
 294         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 295                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 296                 if (check_offset)
 297                         offset = check_offset;
 298                 break;
 299         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 300                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 301                 if (check_offset)
 302                         offset = check_offset;
 303                 break;
 304         case COMBIOS_FAN_SPEED_INFO_TABLE:
 305                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 306                 if (check_offset)
 307                         offset = check_offset;
 308                 break;
 309         case COMBIOS_OVERDRIVE_INFO_TABLE:
 310                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 311                 if (check_offset)
 312                         offset = check_offset;
 313                 break;
 314         case COMBIOS_OEM_INFO_TABLE:
 315                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 316                 if (check_offset)
 317                         offset = check_offset;
 318                 break;
 319         case COMBIOS_DYN_CLK_2_TABLE:
 320                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 321                 if (check_offset)
 322                         offset = check_offset;
 323                 break;
 324         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 325                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 326                 if (check_offset)
 327                         offset = check_offset;
 328                 break;
 329         case COMBIOS_I2C_INFO_TABLE:
 330                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 331                 if (check_offset)
 332                         offset = check_offset;
 333                 break;
 334                 /* relative offset tables */
 335         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 336                 check_offset =
 337                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 338                 if (check_offset) {
 339                         rev = RBIOS8(check_offset);
 340                         if (rev > 0) {
 341                                 check_offset = RBIOS16(check_offset + 0x3);
 342                                 if (check_offset)
 343                                         offset = check_offset;
 344                         }
 345                 }
 346                 break;
 347         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 348                 check_offset =
 349                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 350                 if (check_offset) {
 351                         rev = RBIOS8(check_offset);
 352                         if (rev > 0) {
 353                                 check_offset = RBIOS16(check_offset + 0x5);
 354                                 if (check_offset)
 355                                         offset = check_offset;
 356                         }
 357                 }
 358                 break;
 359         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 360                 check_offset =
 361                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 362                 if (check_offset) {
 363                         rev = RBIOS8(check_offset);
 364                         if (rev > 0) {
 365                                 check_offset = RBIOS16(check_offset + 0x7);
 366                                 if (check_offset)
 367                                         offset = check_offset;
 368                         }
 369                 }
 370                 break;
 371         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 372                 check_offset =
 373                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 374                 if (check_offset) {
 375                         rev = RBIOS8(check_offset);
 376                         if (rev == 2) {
 377                                 check_offset = RBIOS16(check_offset + 0x9);
 378                                 if (check_offset)
 379                                         offset = check_offset;
 380                         }
 381                 }
 382                 break;
 383         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 384                 check_offset =
 385                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 386                 if (check_offset) {
 387                         while (RBIOS8(check_offset++));
 388                         check_offset += 2;
 389                         if (check_offset)
 390                                 offset = check_offset;
 391                 }
 392                 break;
 393         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 394                 check_offset =
 395                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 396                 if (check_offset) {
 397                         check_offset = RBIOS16(check_offset + 0x11);
 398                         if (check_offset)
 399                                 offset = check_offset;
 400                 }
 401                 break;
 402         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 403                 check_offset =
 404                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 405                 if (check_offset) {
 406                         check_offset = RBIOS16(check_offset + 0x13);
 407                         if (check_offset)
 408                                 offset = check_offset;
 409                 }
 410                 break;
 411         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 412                 check_offset =
 413                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 414                 if (check_offset) {
 415                         check_offset = RBIOS16(check_offset + 0x15);
 416                         if (check_offset)
 417                                 offset = check_offset;
 418                 }
 419                 break;
 420         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 421                 check_offset =
 422                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 423                 if (check_offset) {
 424                         check_offset = RBIOS16(check_offset + 0x17);
 425                         if (check_offset)
 426                                 offset = check_offset;
 427                 }
 428                 break;
 429         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 430                 check_offset =
 431                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 432                 if (check_offset) {
 433                         check_offset = RBIOS16(check_offset + 0x2);
 434                         if (check_offset)
 435                                 offset = check_offset;
 436                 }
 437                 break;
 438         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 439                 check_offset =
 440                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 441                 if (check_offset) {
 442                         check_offset = RBIOS16(check_offset + 0x4);
 443                         if (check_offset)
 444                                 offset = check_offset;
 445                 }
 446                 break;
 447         default:
 448                 break;
 449         }
 450
 451         return offset;
 452
 453 }
 454
 455 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 456 {
 457         int edid_info, size;
 458         struct edid *edid;
 459         unsigned char *raw;
 460         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 461         if (!edid_info)
 462                 return false;
 463
 464         raw = rdev->bios + edid_info;
 465         size = EDID_LENGTH * (raw[0x7e] + 1);
 466         edid = malloc(size, DRM_MEM_KMS, M_NOWAIT);
 467         if (edid == NULL)
 468                 return false;
 469
 470         memcpy((unsigned char *)edid, raw, size);
 471
 472         if (!drm_edid_is_valid(edid)) {
 473                 free(edid, DRM_MEM_KMS);
 474                 return false;
 475         }
 476
 477         rdev->mode_info.bios_hardcoded_edid = edid;
 478         rdev->mode_info.bios_hardcoded_edid_size = size;
 479         return true;
 480 }
 481
 482 /* this is used for atom LCDs as well */
 483 struct edid *
 484 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 485 {
 486         struct edid *edid;
 487
 488         if (rdev->mode_info.bios_hardcoded_edid) {
 489                 edid = malloc(rdev->mode_info.bios_hardcoded_edid_size,
 490                     DRM_MEM_KMS, M_NOWAIT);
 491                 if (edid) {
 492                         memcpy((unsigned char *)edid,
 493                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 494                                rdev->mode_info.bios_hardcoded_edid_size);
 495                         return edid;
 496                 }
 497         }
 498         return NULL;
 499 }
 500
 501 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 502                                                        enum radeon_combios_ddc ddc,
 503                                                        u32 clk_mask,
 504                                                        u32 data_mask)
 505 {
 506         struct radeon_i2c_bus_rec i2c;
 507         int ddc_line = 0;
 508
 509         /* ddc id            = mask reg
 510          * DDC_NONE_DETECTED = none
 511          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 512          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 513          * DDC_LCD           = RADEON_GPIOPAD_MASK
 514          * DDC_GPIO          = RADEON_MDGPIO_MASK
 515          * r1xx
 516          * DDC_MONID         = RADEON_GPIO_MONID
 517          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 518          * r200
 519          * DDC_MONID         = RADEON_GPIO_MONID
 520          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 521          * r300/r350
 522          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 523          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 524          * rv2xx/rv3xx
 525          * DDC_MONID         = RADEON_GPIO_MONID
 526          * DDC_CRT2          = RADEON_GPIO_MONID
 527          * rs3xx/rs4xx
 528          * DDC_MONID         = RADEON_GPIOPAD_MASK
 529          * DDC_CRT2          = RADEON_GPIO_MONID
 530          */
 531         switch (ddc) {
 532         case DDC_NONE_DETECTED:
 533         default:
 534                 ddc_line = 0;
 535                 break;
 536         case DDC_DVI:
 537                 ddc_line = RADEON_GPIO_DVI_DDC;
 538                 break;
 539         case DDC_VGA:
 540                 ddc_line = RADEON_GPIO_VGA_DDC;
 541                 break;
 542         case DDC_LCD:
 543                 ddc_line = RADEON_GPIOPAD_MASK;
 544                 break;
 545         case DDC_GPIO:
 546                 ddc_line = RADEON_MDGPIO_MASK;
 547                 break;
 548         case DDC_MONID:
 549                 if (rdev->family == CHIP_RS300 ||
 550                     rdev->family == CHIP_RS400 ||
 551                     rdev->family == CHIP_RS480)
 552                         ddc_line = RADEON_GPIOPAD_MASK;
 553                 else if (rdev->family == CHIP_R300 ||
 554                          rdev->family == CHIP_R350) {
 555                         ddc_line = RADEON_GPIO_DVI_DDC;
 556                         ddc = DDC_DVI;
 557                 } else
 558                         ddc_line = RADEON_GPIO_MONID;
 559                 break;
 560         case DDC_CRT2:
 561                 if (rdev->family == CHIP_R200 ||
 562                     rdev->family == CHIP_R300 ||
 563                     rdev->family == CHIP_R350) {
 564                         ddc_line = RADEON_GPIO_DVI_DDC;
 565                         ddc = DDC_DVI;
 566                 } else if (rdev->family == CHIP_RS300 ||
 567                            rdev->family == CHIP_RS400 ||
 568                            rdev->family == CHIP_RS480)
 569                         ddc_line = RADEON_GPIO_MONID;
 570                 else if (rdev->family >= CHIP_RV350) {
 571                         ddc_line = RADEON_GPIO_MONID;
 572                         ddc = DDC_MONID;
 573                 } else
 574                         ddc_line = RADEON_GPIO_CRT2_DDC;
 575                 break;
 576         }
 577
 578         if (ddc_line == RADEON_GPIOPAD_MASK) {
 579                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 580                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 581                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 582                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 583                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 584                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 585                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 586                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 587         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 588                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 589                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 590                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 591                 i2c.a_data_reg = RADEON_MDGPIO_A;
 592                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 593                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 594                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 595                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 596         } else {
 597                 i2c.mask_clk_reg = ddc_line;
 598                 i2c.mask_data_reg = ddc_line;
 599                 i2c.a_clk_reg = ddc_line;
 600                 i2c.a_data_reg = ddc_line;
 601                 i2c.en_clk_reg = ddc_line;
 602                 i2c.en_data_reg = ddc_line;
 603                 i2c.y_clk_reg = ddc_line;
 604                 i2c.y_data_reg = ddc_line;
 605         }
 606
 607         if (clk_mask && data_mask) {
 608                 /* system specific masks */
 609                 i2c.mask_clk_mask = clk_mask;
 610                 i2c.mask_data_mask = data_mask;
 611                 i2c.a_clk_mask = clk_mask;
 612                 i2c.a_data_mask = data_mask;
 613                 i2c.en_clk_mask = clk_mask;
 614                 i2c.en_data_mask = data_mask;
 615                 i2c.y_clk_mask = clk_mask;
 616                 i2c.y_data_mask = data_mask;
 617         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 618                    (ddc_line == RADEON_MDGPIO_MASK)) {
 619                 /* default gpiopad masks */
 620                 i2c.mask_clk_mask = (0x20 << 8);
 621                 i2c.mask_data_mask = 0x80;
 622                 i2c.a_clk_mask = (0x20 << 8);
 623                 i2c.a_data_mask = 0x80;
 624                 i2c.en_clk_mask = (0x20 << 8);
 625                 i2c.en_data_mask = 0x80;
 626                 i2c.y_clk_mask = (0x20 << 8);
 627                 i2c.y_data_mask = 0x80;
 628         } else {
 629                 /* default masks for ddc pads */
 630                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 631                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 632                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 633                 i2c.a_data_mask = RADEON_GPIO_A_0;
 634                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 635                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 636                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 637                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 638         }
 639
 640         switch (rdev->family) {
 641         case CHIP_R100:
 642         case CHIP_RV100:
 643         case CHIP_RS100:
 644         case CHIP_RV200:
 645         case CHIP_RS200:
 646         case CHIP_RS300:
 647                 switch (ddc_line) {
 648                 case RADEON_GPIO_DVI_DDC:
 649                         i2c.hw_capable = true;
 650                         break;
 651                 default:
 652                         i2c.hw_capable = false;
 653                         break;
 654                 }
 655                 break;
 656         case CHIP_R200:
 657                 switch (ddc_line) {
 658                 case RADEON_GPIO_DVI_DDC:
 659                 case RADEON_GPIO_MONID:
 660                         i2c.hw_capable = true;
 661                         break;
 662                 default:
 663                         i2c.hw_capable = false;
 664                         break;
 665                 }
 666                 break;
 667         case CHIP_RV250:
 668         case CHIP_RV280:
 669                 switch (ddc_line) {
 670                 case RADEON_GPIO_VGA_DDC:
 671                 case RADEON_GPIO_DVI_DDC:
 672                 case RADEON_GPIO_CRT2_DDC:
 673                         i2c.hw_capable = true;
 674                         break;
 675                 default:
 676                         i2c.hw_capable = false;
 677                         break;
 678                 }
 679                 break;
 680         case CHIP_R300:
 681         case CHIP_R350:
 682                 switch (ddc_line) {
 683                 case RADEON_GPIO_VGA_DDC:
 684                 case RADEON_GPIO_DVI_DDC:
 685                         i2c.hw_capable = true;
 686                         break;
 687                 default:
 688                         i2c.hw_capable = false;
 689                         break;
 690                 }
 691                 break;
 692         case CHIP_RV350:
 693         case CHIP_RV380:
 694         case CHIP_RS400:
 695         case CHIP_RS480:
 696                 switch (ddc_line) {
 697                 case RADEON_GPIO_VGA_DDC:
 698                 case RADEON_GPIO_DVI_DDC:
 699                         i2c.hw_capable = true;
 700                         break;
 701                 case RADEON_GPIO_MONID:
 702                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 703                          * reliably on some pre-r4xx hardware; not sure why.
 704                          */
 705                         i2c.hw_capable = false;
 706                         break;
 707                 default:
 708                         i2c.hw_capable = false;
 709                         break;
 710                 }
 711                 break;
 712         default:
 713                 i2c.hw_capable = false;
 714                 break;
 715         }
 716         i2c.mm_i2c = false;
 717
 718         i2c.i2c_id = ddc;
 719         i2c.hpd = RADEON_HPD_NONE;
 720
 721         if (ddc_line)
 722                 i2c.valid = true;
 723         else
 724                 i2c.valid = false;
 725
 726         return i2c;
 727 }
 728
 729 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 730 {
 731         struct drm_device *dev = rdev->ddev;
 732         struct radeon_i2c_bus_rec i2c;
 733         u16 offset;
 734         u8 id, blocks, clk, data;
 735         int i;
 736
 737         i2c.valid = false;
 738
 739         offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 740         if (offset) {
 741                 blocks = RBIOS8(offset + 2);
 742                 for (i = 0; i < blocks; i++) {
 743                         id = RBIOS8(offset + 3 + (i * 5) + 0);
 744                         if (id == 136) {
 745                                 clk = RBIOS8(offset + 3 + (i * 5) + 3);
 746                                 data = RBIOS8(offset + 3 + (i * 5) + 4);
 747                                 /* gpiopad */
 748                                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 749                                                             (1 << clk), (1 << data));
 750                                 break;
 751                         }
 752                 }
 753         }
 754         return i2c;
 755 }
 756
 757 void radeon_combios_i2c_init(struct radeon_device *rdev)
 758 {
 759         struct drm_device *dev = rdev->ddev;
 760         struct radeon_i2c_bus_rec i2c;
 761
 762         /* actual hw pads
 763          * r1xx/rs2xx/rs3xx
 764          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 765          * r200
 766          * 0x60, 0x64, 0x68, mm
 767          * r300/r350
 768          * 0x60, 0x64, mm
 769          * rv2xx/rv3xx/rs4xx
 770          * 0x60, 0x64, 0x68, gpiopads, mm
 771          */
 772
 773         /* 0x60 */
 774         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 775         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 776         /* 0x64 */
 777         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 778         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 779
 780         /* mm i2c */
 781         i2c.valid = true;
 782         i2c.hw_capable = true;
 783         i2c.mm_i2c = true;
 784         i2c.i2c_id = 0xa0;
 785         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 786
 787         if (rdev->family == CHIP_R300 ||
 788             rdev->family == CHIP_R350) {
 789                 /* only 2 sw i2c pads */
 790         } else if (rdev->family == CHIP_RS300 ||
 791                    rdev->family == CHIP_RS400 ||
 792                    rdev->family == CHIP_RS480) {
 793                 /* 0x68 */
 794                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 795                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 796
 797                 /* gpiopad */
 798                 i2c = radeon_combios_get_i2c_info_from_table(rdev);
 799                 if (i2c.valid)
 800                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 801         } else if ((rdev->family == CHIP_R200) ||
 802                    (rdev->family >= CHIP_R300)) {
 803                 /* 0x68 */
 804                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 805                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 806         } else {
 807                 /* 0x68 */
 808                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 809                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 810                 /* 0x6c */
 811                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 812                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 813         }
 814 }
 815
 816 bool radeon_combios_get_clock_info(struct drm_device *dev)
 817 {
 818         struct radeon_device *rdev = dev->dev_private;
 819         uint16_t pll_info;
 820         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 821         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 822         struct radeon_pll *spll = &rdev->clock.spll;
 823         struct radeon_pll *mpll = &rdev->clock.mpll;
 824         int8_t rev;
 825         uint16_t sclk, mclk;
 826
 827         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 828         if (pll_info) {
 829                 rev = RBIOS8(pll_info);
 830
 831                 /* pixel clocks */
 832                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 833                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 834                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 835                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 836                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 837                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 838
 839                 if (rev > 9) {
 840                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 841                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 842                 } else {
 843                         p1pll->pll_in_min = 40;
 844                         p1pll->pll_in_max = 500;
 845                 }
 846                 *p2pll = *p1pll;
 847
 848                 /* system clock */
 849                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 850                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 851                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 852                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 853
 854                 if (rev > 10) {
 855                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 856                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 857                 } else {
 858                         /* ??? */
 859                         spll->pll_in_min = 40;
 860                         spll->pll_in_max = 500;
 861                 }
 862
 863                 /* memory clock */
 864                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 865                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 866                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 867                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 868
 869                 if (rev > 10) {
 870                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 871                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 872                 } else {
 873                         /* ??? */
 874                         mpll->pll_in_min = 40;
 875                         mpll->pll_in_max = 500;
 876                 }
 877
 878                 /* default sclk/mclk */
 879                 sclk = RBIOS16(pll_info + 0xa);
 880                 mclk = RBIOS16(pll_info + 0x8);
 881                 if (sclk == 0)
 882                         sclk = 200 * 100;
 883                 if (mclk == 0)
 884                         mclk = 200 * 100;
 885
 886                 rdev->clock.default_sclk = sclk;
 887                 rdev->clock.default_mclk = mclk;
 888
 889                 if (RBIOS32(pll_info + 0x16))
 890                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 891                 else
 892                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 893
 894                 return true;
 895         }
 896         return false;
 897 }
 898
 899 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 900 {
 901         struct drm_device *dev = rdev->ddev;
 902         u16 igp_info;
 903
 904         /* sideport is AMD only */
 905         if (rdev->family == CHIP_RS400)
 906                 return false;
 907
 908         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 909
 910         if (igp_info) {
 911                 if (RBIOS16(igp_info + 0x4))
 912                         return true;
 913         }
 914         return false;
 915 }
 916
 917 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 918         0x00000808,             /* r100  */
 919         0x00000808,             /* rv100 */
 920         0x00000808,             /* rs100 */
 921         0x00000808,             /* rv200 */
 922         0x00000808,             /* rs200 */
 923         0x00000808,             /* r200  */
 924         0x00000808,             /* rv250 */
 925         0x00000000,             /* rs300 */
 926         0x00000808,             /* rv280 */
 927         0x00000808,             /* r300  */
 928         0x00000808,             /* r350  */
 929         0x00000808,             /* rv350 */
 930         0x00000808,             /* rv380 */
 931         0x00000808,             /* r420  */
 932         0x00000808,             /* r423  */
 933         0x00000808,             /* rv410 */
 934         0x00000000,             /* rs400 */
 935         0x00000000,             /* rs480 */
 936 };
 937
 938 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 939                                                           struct radeon_encoder_primary_dac *p_dac)
 940 {
 941         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 942         return;
 943 }
 944
 945 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 946                                                                        radeon_encoder
 947                                                                        *encoder)
 948 {
 949         struct drm_device *dev = encoder->base.dev;
 950         struct radeon_device *rdev = dev->dev_private;
 951         uint16_t dac_info;
 952         uint8_t rev, bg, dac;
 953         struct radeon_encoder_primary_dac *p_dac = NULL;
 954         int found = 0;
 955
 956         p_dac = malloc(sizeof(struct radeon_encoder_primary_dac),
 957                         DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
 958
 959         if (!p_dac)
 960                 return NULL;
 961
 962         /* check CRT table */
 963         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 964         if (dac_info) {
 965                 rev = RBIOS8(dac_info) & 0x3;
 966                 if (rev < 2) {
 967                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 968                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 969                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 970                 } else {
 971                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 972                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 973                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 974                 }
 975                 /* if the values are all zeros, use the table */
 976                 if (p_dac->ps2_pdac_adj)
 977                         found = 1;
 978         }
 979
 980         /* quirks */
 981         /* Radeon 9100 (R200) */
 982         if ((dev->pci_device == 0x514D) &&
 983             (dev->pci_subvendor == 0x174B) &&
 984             (dev->pci_subdevice == 0x7149)) {
 985                 /* vbios value is bad, use the default */
 986                 found = 0;
 987         }
 988
 989         if (!found) /* fallback to defaults */
 990                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 991
 992         return p_dac;
 993 }
 994
 995 enum radeon_tv_std
 996 radeon_combios_get_tv_info(struct radeon_device *rdev)
 997 {
 998         struct drm_device *dev = rdev->ddev;
 999         uint16_t tv_info;
1000         enum radeon_tv_std tv_std = TV_STD_NTSC;
1001
1002         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1003         if (tv_info) {
1004                 if (RBIOS8(tv_info + 6) == 'T') {
1005                         switch (RBIOS8(tv_info + 7) & 0xf) {
1006                         case 1:
1007                                 tv_std = TV_STD_NTSC;
1008                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1009                                 break;
1010                         case 2:
1011                                 tv_std = TV_STD_PAL;
1012                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1013                                 break;
1014                         case 3:
1015                                 tv_std = TV_STD_PAL_M;
1016                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1017                                 break;
1018                         case 4:
1019                                 tv_std = TV_STD_PAL_60;
1020                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1021                                 break;
1022                         case 5:
1023                                 tv_std = TV_STD_NTSC_J;
1024                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1025                                 break;
1026                         case 6:
1027                                 tv_std = TV_STD_SCART_PAL;
1028                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1029                                 break;
1030                         default:
1031                                 tv_std = TV_STD_NTSC;
1032                                 DRM_DEBUG_KMS
1033                                     ("Unknown TV standard; defaulting to NTSC\n");
1034                                 break;
1035                         }
1036
1037                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1038                         case 0:
1039                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1040                                 break;
1041                         case 1:
1042                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1043                                 break;
1044                         case 2:
1045                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1046                                 break;
1047                         case 3:
1048                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1049                                 break;
1050                         default:
1051                                 break;
1052                         }
1053                 }
1054         }
1055         return tv_std;
1056 }
1057
1058 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1059         0x00000000,             /* r100  */
1060         0x00280000,             /* rv100 */
1061         0x00000000,             /* rs100 */
1062         0x00880000,             /* rv200 */
1063         0x00000000,             /* rs200 */
1064         0x00000000,             /* r200  */
1065         0x00770000,             /* rv250 */
1066         0x00290000,             /* rs300 */
1067         0x00560000,             /* rv280 */
1068         0x00780000,             /* r300  */
1069         0x00770000,             /* r350  */
1070         0x00780000,             /* rv350 */
1071         0x00780000,             /* rv380 */
1072         0x01080000,             /* r420  */
1073         0x01080000,             /* r423  */
1074         0x01080000,             /* rv410 */
1075         0x00780000,             /* rs400 */
1076         0x00780000,             /* rs480 */
1077 };
1078
1079 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1080                                                      struct radeon_encoder_tv_dac *tv_dac)
1081 {
1082         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1083         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1084                 tv_dac->ps2_tvdac_adj = 0x00880000;
1085         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1086         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1087         return;
1088 }
1089
1090 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1091                                                              radeon_encoder
1092                                                              *encoder)
1093 {
1094         struct drm_device *dev = encoder->base.dev;
1095         struct radeon_device *rdev = dev->dev_private;
1096         uint16_t dac_info;
1097         uint8_t rev, bg, dac;
1098         struct radeon_encoder_tv_dac *tv_dac = NULL;
1099         int found = 0;
1100
1101         tv_dac = malloc(sizeof(struct radeon_encoder_tv_dac),
1102             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1103         if (!tv_dac)
1104                 return NULL;
1105
1106         /* first check TV table */
1107         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1108         if (dac_info) {
1109                 rev = RBIOS8(dac_info + 0x3);
1110                 if (rev > 4) {
1111                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1112                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1113                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1114
1115                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1116                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1117                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1118
1119                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1120                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1121                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1122                         /* if the values are all zeros, use the table */
1123                         if (tv_dac->ps2_tvdac_adj)
1124                                 found = 1;
1125                 } else if (rev > 1) {
1126                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1127                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1128                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1129
1130                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1131                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1132                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1133
1134                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1135                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1136                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1137                         /* if the values are all zeros, use the table */
1138                         if (tv_dac->ps2_tvdac_adj)
1139                                 found = 1;
1140                 }
1141                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1142         }
1143         if (!found) {
1144                 /* then check CRT table */
1145                 dac_info =
1146                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1147                 if (dac_info) {
1148                         rev = RBIOS8(dac_info) & 0x3;
1149                         if (rev < 2) {
1150                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1151                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1152                                 tv_dac->ps2_tvdac_adj =
1153                                     (bg << 16) | (dac << 20);
1154                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1155                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1156                                 /* if the values are all zeros, use the table */
1157                                 if (tv_dac->ps2_tvdac_adj)
1158                                         found = 1;
1159                         } else {
1160                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1161                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1162                                 tv_dac->ps2_tvdac_adj =
1163                                     (bg << 16) | (dac << 20);
1164                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1165                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1166                                 /* if the values are all zeros, use the table */
1167                                 if (tv_dac->ps2_tvdac_adj)
1168                                         found = 1;
1169                         }
1170                 } else {
1171                         DRM_INFO("No TV DAC info found in BIOS\n");
1172                 }
1173         }
1174
1175         if (!found) /* fallback to defaults */
1176                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1177
1178         return tv_dac;
1179 }
1180
1181 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1182                                                                          radeon_device
1183                                                                          *rdev)
1184 {
1185         struct radeon_encoder_lvds *lvds = NULL;
1186         uint32_t fp_vert_stretch, fp_horz_stretch;
1187         uint32_t ppll_div_sel, ppll_val;
1188         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1189
1190         lvds = malloc(sizeof(struct radeon_encoder_lvds),
1191             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1192
1193         if (!lvds)
1194                 return NULL;
1195
1196         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1197         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1198
1199         /* These should be fail-safe defaults, fingers crossed */
1200         lvds->panel_pwr_delay = 200;
1201         lvds->panel_vcc_delay = 2000;
1202
1203         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1204         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1205         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1206
1207         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1208                 lvds->native_mode.vdisplay =
1209                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1210                      RADEON_VERT_PANEL_SHIFT) + 1;
1211         else
1212                 lvds->native_mode.vdisplay =
1213                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1214
1215         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1216                 lvds->native_mode.hdisplay =
1217                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1218                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1219         else
1220                 lvds->native_mode.hdisplay =
1221                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1222
1223         if ((lvds->native_mode.hdisplay < 640) ||
1224             (lvds->native_mode.vdisplay < 480)) {
1225                 lvds->native_mode.hdisplay = 640;
1226                 lvds->native_mode.vdisplay = 480;
1227         }
1228
1229         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1230         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1231         if ((ppll_val & 0x000707ff) == 0x1bb)
1232                 lvds->use_bios_dividers = false;
1233         else {
1234                 lvds->panel_ref_divider =
1235                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1236                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1237                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1238
1239                 if ((lvds->panel_ref_divider != 0) &&
1240                     (lvds->panel_fb_divider > 3))
1241                         lvds->use_bios_dividers = true;
1242         }
1243         lvds->panel_vcc_delay = 200;
1244
1245         DRM_INFO("Panel info derived from registers\n");
1246         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1247                  lvds->native_mode.vdisplay);
1248
1249         return lvds;
1250 }
1251
1252 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1253                                                          *encoder)
1254 {
1255         struct drm_device *dev = encoder->base.dev;
1256         struct radeon_device *rdev = dev->dev_private;
1257         uint16_t lcd_info;
1258         uint32_t panel_setup;
1259         char stmp[30];
1260         int tmp, i;
1261         struct radeon_encoder_lvds *lvds = NULL;
1262
1263         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1264
1265         if (lcd_info) {
1266                 lvds = malloc(sizeof(struct radeon_encoder_lvds),
1267                     DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1268
1269                 if (!lvds)
1270                         return NULL;
1271
1272                 for (i = 0; i < 24; i++)
1273                         stmp[i] = RBIOS8(lcd_info + i + 1);
1274                 stmp[24] = 0;
1275
1276                 DRM_INFO("Panel ID String: %s\n", stmp);
1277
1278                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1279                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1280
1281                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1282                          lvds->native_mode.vdisplay);
1283
1284                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1285                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1286
1287                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1288                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1289                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1290
1291                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1292                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1293                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1294                 if ((lvds->panel_ref_divider != 0) &&
1295                     (lvds->panel_fb_divider > 3))
1296                         lvds->use_bios_dividers = true;
1297
1298                 panel_setup = RBIOS32(lcd_info + 0x39);
1299                 lvds->lvds_gen_cntl = 0xff00;
1300                 if (panel_setup & 0x1)
1301                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1302
1303                 if ((panel_setup >> 4) & 0x1)
1304                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1305
1306                 switch ((panel_setup >> 8) & 0x7) {
1307                 case 0:
1308                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1309                         break;
1310                 case 1:
1311                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1312                         break;
1313                 case 2:
1314                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1315                         break;
1316                 default:
1317                         break;
1318                 }
1319
1320                 if ((panel_setup >> 16) & 0x1)
1321                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1322
1323                 if ((panel_setup >> 17) & 0x1)
1324                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1325
1326                 if ((panel_setup >> 18) & 0x1)
1327                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1328
1329                 if ((panel_setup >> 23) & 0x1)
1330                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1331
1332                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1333
1334                 for (i = 0; i < 32; i++) {
1335                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1336                         if (tmp == 0)
1337                                 break;
1338
1339                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1340                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1341                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1342                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1343                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1344                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1345                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1346                                         (RBIOS8(tmp + 23) * 8);
1347
1348                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1349                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1350                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1351                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1352                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1353                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1354
1355                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1356                                 lvds->native_mode.flags = 0;
1357                                 /* set crtc values */
1358                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1359
1360                         }
1361                 }
1362         } else {
1363                 DRM_INFO("No panel info found in BIOS\n");
1364                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1365         }
1366
1367         if (lvds)
1368                 encoder->native_mode = lvds->native_mode;
1369         return lvds;
1370 }
1371
1372 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1373         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1374         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1375         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1376         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1377         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1378         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1379         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1380         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1381         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1382         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1383         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1384         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1385         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1386         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1387         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1388         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1389         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1390         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1391 };
1392
1393 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1394                                             struct radeon_encoder_int_tmds *tmds)
1395 {
1396         struct drm_device *dev = encoder->base.dev;
1397         struct radeon_device *rdev = dev->dev_private;
1398         int i;
1399
1400         for (i = 0; i < 4; i++) {
1401                 tmds->tmds_pll[i].value =
1402                         default_tmds_pll[rdev->family][i].value;
1403                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1404         }
1405
1406         return true;
1407 }
1408
1409 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1410                                               struct radeon_encoder_int_tmds *tmds)
1411 {
1412         struct drm_device *dev = encoder->base.dev;
1413         struct radeon_device *rdev = dev->dev_private;
1414         uint16_t tmds_info;
1415         int i, n;
1416         uint8_t ver;
1417
1418         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1419
1420         if (tmds_info) {
1421                 ver = RBIOS8(tmds_info);
1422                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1423                 if (ver == 3) {
1424                         n = RBIOS8(tmds_info + 5) + 1;
1425                         if (n > 4)
1426                                 n = 4;
1427                         for (i = 0; i < n; i++) {
1428                                 tmds->tmds_pll[i].value =
1429                                     RBIOS32(tmds_info + i * 10 + 0x08);
1430                                 tmds->tmds_pll[i].freq =
1431                                     RBIOS16(tmds_info + i * 10 + 0x10);
1432                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1433                                           tmds->tmds_pll[i].freq,
1434                                           tmds->tmds_pll[i].value);
1435                         }
1436                 } else if (ver == 4) {
1437                         int stride = 0;
1438                         n = RBIOS8(tmds_info + 5) + 1;
1439                         if (n > 4)
1440                                 n = 4;
1441                         for (i = 0; i < n; i++) {
1442                                 tmds->tmds_pll[i].value =
1443                                     RBIOS32(tmds_info + stride + 0x08);
1444                                 tmds->tmds_pll[i].freq =
1445                                     RBIOS16(tmds_info + stride + 0x10);
1446                                 if (i == 0)
1447                                         stride += 10;
1448                                 else
1449                                         stride += 6;
1450                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1451                                           tmds->tmds_pll[i].freq,
1452                                           tmds->tmds_pll[i].value);
1453                         }
1454                 }
1455         } else {
1456                 DRM_INFO("No TMDS info found in BIOS\n");
1457                 return false;
1458         }
1459         return true;
1460 }
1461
1462 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1463                                                 struct radeon_encoder_ext_tmds *tmds)
1464 {
1465         struct drm_device *dev = encoder->base.dev;
1466         struct radeon_device *rdev = dev->dev_private;
1467         struct radeon_i2c_bus_rec i2c_bus;
1468
1469         /* default for macs */
1470         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1471         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1472
1473         /* XXX some macs have duallink chips */
1474         switch (rdev->mode_info.connector_table) {
1475         case CT_POWERBOOK_EXTERNAL:
1476         case CT_MINI_EXTERNAL:
1477         default:
1478                 tmds->dvo_chip = DVO_SIL164;
1479                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1480                 break;
1481         }
1482
1483         return true;
1484 }
1485
1486 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1487                                                   struct radeon_encoder_ext_tmds *tmds)
1488 {
1489         struct drm_device *dev = encoder->base.dev;
1490         struct radeon_device *rdev = dev->dev_private;
1491         uint16_t offset;
1492         uint8_t ver;
1493         enum radeon_combios_ddc gpio;
1494         struct radeon_i2c_bus_rec i2c_bus;
1495
1496         tmds->i2c_bus = NULL;
1497         if (rdev->flags & RADEON_IS_IGP) {
1498                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1499                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1500                 tmds->dvo_chip = DVO_SIL164;
1501                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1502         } else {
1503                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1504                 if (offset) {
1505                         ver = RBIOS8(offset);
1506                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1507                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1508                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1509                         gpio = RBIOS8(offset + 4 + 3);
1510                         if (gpio == DDC_LCD) {
1511                                 /* MM i2c */
1512                                 i2c_bus.valid = true;
1513                                 i2c_bus.hw_capable = true;
1514                                 i2c_bus.mm_i2c = true;
1515                                 i2c_bus.i2c_id = 0xa0;
1516                         } else
1517                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1518                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1519                 }
1520         }
1521
1522         if (!tmds->i2c_bus) {
1523                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1524                 return false;
1525         }
1526
1527         return true;
1528 }
1529
1530 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1531 {
1532         struct radeon_device *rdev = dev->dev_private;
1533         struct radeon_i2c_bus_rec ddc_i2c;
1534         struct radeon_hpd hpd;
1535
1536         rdev->mode_info.connector_table = radeon_connector_table;
1537         if (rdev->mode_info.connector_table == CT_NONE) {
1538 #ifdef CONFIG_PPC_PMAC
1539                 if (of_machine_is_compatible("PowerBook3,3")) {
1540                         /* powerbook with VGA */
1541                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1542                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1543                            of_machine_is_compatible("PowerBook3,5")) {
1544                         /* powerbook with internal tmds */
1545                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1546                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1547                            of_machine_is_compatible("PowerBook5,2") ||
1548                            of_machine_is_compatible("PowerBook5,3") ||
1549                            of_machine_is_compatible("PowerBook5,4") ||
1550                            of_machine_is_compatible("PowerBook5,5")) {
1551                         /* powerbook with external single link tmds (sil164) */
1552                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1553                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1554                         /* powerbook with external dual or single link tmds */
1555                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1556                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1557                            of_machine_is_compatible("PowerBook5,8") ||
1558                            of_machine_is_compatible("PowerBook5,9")) {
1559                         /* PowerBook6,2 ? */
1560                         /* powerbook with external dual link tmds (sil1178?) */
1561                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1562                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1563                            of_machine_is_compatible("PowerBook4,2") ||
1564                            of_machine_is_compatible("PowerBook4,3") ||
1565                            of_machine_is_compatible("PowerBook6,3") ||
1566                            of_machine_is_compatible("PowerBook6,5") ||
1567                            of_machine_is_compatible("PowerBook6,7")) {
1568                         /* ibook */
1569                         rdev->mode_info.connector_table = CT_IBOOK;
1570                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1571                         /* PowerMac G4 Silver radeon 7500 */
1572                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1573                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1574                         /* emac */
1575                         rdev->mode_info.connector_table = CT_EMAC;
1576                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1577                         /* mini with internal tmds */
1578                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1579                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1580                         /* mini with external tmds */
1581                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1582                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1583                         /* PowerMac8,1 ? */
1584                         /* imac g5 isight */
1585                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1586                 } else if ((dev->pci_device == 0x4a48) &&
1587                            (dev->pci_subvendor == 0x1002) &&
1588                            (dev->pci_subdevice == 0x4a48)) {
1589                         /* Mac X800 */
1590                         rdev->mode_info.connector_table = CT_MAC_X800;
1591                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1592                             of_machine_is_compatible("PowerMac7,3")) &&
1593                            (dev->pci_device == 0x4150) &&
1594                            (dev->pci_subvendor == 0x1002) &&
1595                            (dev->pci_subdevice == 0x4150)) {
1596                         /* Mac G5 tower 9600 */
1597                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1598                 } else if ((dev->pci_device == 0x4c66) &&
1599                            (dev->pci_subvendor == 0x1002) &&
1600                            (dev->pci_subdevice == 0x4c66)) {
1601                         /* SAM440ep RV250 embedded board */
1602                         rdev->mode_info.connector_table = CT_SAM440EP;
1603                 } else
1604 #endif /* CONFIG_PPC_PMAC */
1605 #ifdef CONFIG_PPC64
1606                 if (ASIC_IS_RN50(rdev))
1607                         rdev->mode_info.connector_table = CT_RN50_POWER;
1608                 else
1609 #endif
1610                         rdev->mode_info.connector_table = CT_GENERIC;
1611         }
1612
1613         switch (rdev->mode_info.connector_table) {
1614         case CT_GENERIC:
1615                 DRM_INFO("Connector Table: %d (generic)\n",
1616                          rdev->mode_info.connector_table);
1617                 /* these are the most common settings */
1618                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1619                         /* VGA - primary dac */
1620                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1621                         hpd.hpd = RADEON_HPD_NONE;
1622                         radeon_add_legacy_encoder(dev,
1623                                                   radeon_get_encoder_enum(dev,
1624                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1625                                                                         1),
1626                                                   ATOM_DEVICE_CRT1_SUPPORT);
1627                         radeon_add_legacy_connector(dev, 0,
1628                                                     ATOM_DEVICE_CRT1_SUPPORT,
1629                                                     DRM_MODE_CONNECTOR_VGA,
1630                                                     &ddc_i2c,
1631                                                     CONNECTOR_OBJECT_ID_VGA,
1632                                                     &hpd);
1633                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1634                         /* LVDS */
1635                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1636                         hpd.hpd = RADEON_HPD_NONE;
1637                         radeon_add_legacy_encoder(dev,
1638                                                   radeon_get_encoder_enum(dev,
1639                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1640                                                                         0),
1641                                                   ATOM_DEVICE_LCD1_SUPPORT);
1642                         radeon_add_legacy_connector(dev, 0,
1643                                                     ATOM_DEVICE_LCD1_SUPPORT,
1644                                                     DRM_MODE_CONNECTOR_LVDS,
1645                                                     &ddc_i2c,
1646                                                     CONNECTOR_OBJECT_ID_LVDS,
1647                                                     &hpd);
1648
1649                         /* VGA - primary dac */
1650                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1651                         hpd.hpd = RADEON_HPD_NONE;
1652                         radeon_add_legacy_encoder(dev,
1653                                                   radeon_get_encoder_enum(dev,
1654                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1655                                                                         1),
1656                                                   ATOM_DEVICE_CRT1_SUPPORT);
1657                         radeon_add_legacy_connector(dev, 1,
1658                                                     ATOM_DEVICE_CRT1_SUPPORT,
1659                                                     DRM_MODE_CONNECTOR_VGA,
1660                                                     &ddc_i2c,
1661                                                     CONNECTOR_OBJECT_ID_VGA,
1662                                                     &hpd);
1663                 } else {
1664                         /* DVI-I - tv dac, int tmds */
1665                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1666                         hpd.hpd = RADEON_HPD_1;
1667                         radeon_add_legacy_encoder(dev,
1668                                                   radeon_get_encoder_enum(dev,
1669                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1670                                                                         0),
1671                                                   ATOM_DEVICE_DFP1_SUPPORT);
1672                         radeon_add_legacy_encoder(dev,
1673                                                   radeon_get_encoder_enum(dev,
1674                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1675                                                                         2),
1676                                                   ATOM_DEVICE_CRT2_SUPPORT);
1677                         radeon_add_legacy_connector(dev, 0,
1678                                                     ATOM_DEVICE_DFP1_SUPPORT |
1679                                                     ATOM_DEVICE_CRT2_SUPPORT,
1680                                                     DRM_MODE_CONNECTOR_DVII,
1681                                                     &ddc_i2c,
1682                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1683                                                     &hpd);
1684
1685                         /* VGA - primary dac */
1686                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1687                         hpd.hpd = RADEON_HPD_NONE;
1688                         radeon_add_legacy_encoder(dev,
1689                                                   radeon_get_encoder_enum(dev,
1690                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1691                                                                         1),
1692                                                   ATOM_DEVICE_CRT1_SUPPORT);
1693                         radeon_add_legacy_connector(dev, 1,
1694                                                     ATOM_DEVICE_CRT1_SUPPORT,
1695                                                     DRM_MODE_CONNECTOR_VGA,
1696                                                     &ddc_i2c,
1697                                                     CONNECTOR_OBJECT_ID_VGA,
1698                                                     &hpd);
1699                 }
1700
1701                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1702                         /* TV - tv dac */
1703                         ddc_i2c.valid = false;
1704                         hpd.hpd = RADEON_HPD_NONE;
1705                         radeon_add_legacy_encoder(dev,
1706                                                   radeon_get_encoder_enum(dev,
1707                                                                         ATOM_DEVICE_TV1_SUPPORT,
1708                                                                         2),
1709                                                   ATOM_DEVICE_TV1_SUPPORT);
1710                         radeon_add_legacy_connector(dev, 2,
1711                                                     ATOM_DEVICE_TV1_SUPPORT,
1712                                                     DRM_MODE_CONNECTOR_SVIDEO,
1713                                                     &ddc_i2c,
1714                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1715                                                     &hpd);
1716                 }
1717                 break;
1718         case CT_IBOOK:
1719                 DRM_INFO("Connector Table: %d (ibook)\n",
1720                          rdev->mode_info.connector_table);
1721                 /* LVDS */
1722                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1723                 hpd.hpd = RADEON_HPD_NONE;
1724                 radeon_add_legacy_encoder(dev,
1725                                           radeon_get_encoder_enum(dev,
1726                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1727                                                                 0),
1728                                           ATOM_DEVICE_LCD1_SUPPORT);
1729                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1730                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1731                                             CONNECTOR_OBJECT_ID_LVDS,
1732                                             &hpd);
1733                 /* VGA - TV DAC */
1734                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1735                 hpd.hpd = RADEON_HPD_NONE;
1736                 radeon_add_legacy_encoder(dev,
1737                                           radeon_get_encoder_enum(dev,
1738                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1739                                                                 2),
1740                                           ATOM_DEVICE_CRT2_SUPPORT);
1741                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1742                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1743                                             CONNECTOR_OBJECT_ID_VGA,
1744                                             &hpd);
1745                 /* TV - TV DAC */
1746                 ddc_i2c.valid = false;
1747                 hpd.hpd = RADEON_HPD_NONE;
1748                 radeon_add_legacy_encoder(dev,
1749                                           radeon_get_encoder_enum(dev,
1750                                                                 ATOM_DEVICE_TV1_SUPPORT,
1751                                                                 2),
1752                                           ATOM_DEVICE_TV1_SUPPORT);
1753                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1754                                             DRM_MODE_CONNECTOR_SVIDEO,
1755                                             &ddc_i2c,
1756                                             CONNECTOR_OBJECT_ID_SVIDEO,
1757                                             &hpd);
1758                 break;
1759         case CT_POWERBOOK_EXTERNAL:
1760                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1761                          rdev->mode_info.connector_table);
1762                 /* LVDS */
1763                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1764                 hpd.hpd = RADEON_HPD_NONE;
1765                 radeon_add_legacy_encoder(dev,
1766                                           radeon_get_encoder_enum(dev,
1767                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1768                                                                 0),
1769                                           ATOM_DEVICE_LCD1_SUPPORT);
1770                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1771                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1772                                             CONNECTOR_OBJECT_ID_LVDS,
1773                                             &hpd);
1774                 /* DVI-I - primary dac, ext tmds */
1775                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1776                 hpd.hpd = RADEON_HPD_2; /* ??? */
1777                 radeon_add_legacy_encoder(dev,
1778                                           radeon_get_encoder_enum(dev,
1779                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1780                                                                 0),
1781                                           ATOM_DEVICE_DFP2_SUPPORT);
1782                 radeon_add_legacy_encoder(dev,
1783                                           radeon_get_encoder_enum(dev,
1784                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1785                                                                 1),
1786                                           ATOM_DEVICE_CRT1_SUPPORT);
1787                 /* XXX some are SL */
1788                 radeon_add_legacy_connector(dev, 1,
1789                                             ATOM_DEVICE_DFP2_SUPPORT |
1790                                             ATOM_DEVICE_CRT1_SUPPORT,
1791                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1792                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1793                                             &hpd);
1794                 /* TV - TV DAC */
1795                 ddc_i2c.valid = false;
1796                 hpd.hpd = RADEON_HPD_NONE;
1797                 radeon_add_legacy_encoder(dev,
1798                                           radeon_get_encoder_enum(dev,
1799                                                                 ATOM_DEVICE_TV1_SUPPORT,
1800                                                                 2),
1801                                           ATOM_DEVICE_TV1_SUPPORT);
1802                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1803                                             DRM_MODE_CONNECTOR_SVIDEO,
1804                                             &ddc_i2c,
1805                                             CONNECTOR_OBJECT_ID_SVIDEO,
1806                                             &hpd);
1807                 break;
1808         case CT_POWERBOOK_INTERNAL:
1809                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1810                          rdev->mode_info.connector_table);
1811                 /* LVDS */
1812                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1813                 hpd.hpd = RADEON_HPD_NONE;
1814                 radeon_add_legacy_encoder(dev,
1815                                           radeon_get_encoder_enum(dev,
1816                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1817                                                                 0),
1818                                           ATOM_DEVICE_LCD1_SUPPORT);
1819                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1820                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1821                                             CONNECTOR_OBJECT_ID_LVDS,
1822                                             &hpd);
1823                 /* DVI-I - primary dac, int tmds */
1824                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1825                 hpd.hpd = RADEON_HPD_1; /* ??? */
1826                 radeon_add_legacy_encoder(dev,
1827                                           radeon_get_encoder_enum(dev,
1828                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1829                                                                 0),
1830                                           ATOM_DEVICE_DFP1_SUPPORT);
1831                 radeon_add_legacy_encoder(dev,
1832                                           radeon_get_encoder_enum(dev,
1833                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1834                                                                 1),
1835                                           ATOM_DEVICE_CRT1_SUPPORT);
1836                 radeon_add_legacy_connector(dev, 1,
1837                                             ATOM_DEVICE_DFP1_SUPPORT |
1838                                             ATOM_DEVICE_CRT1_SUPPORT,
1839                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1840                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1841                                             &hpd);
1842                 /* TV - TV DAC */
1843                 ddc_i2c.valid = false;
1844                 hpd.hpd = RADEON_HPD_NONE;
1845                 radeon_add_legacy_encoder(dev,
1846                                           radeon_get_encoder_enum(dev,
1847                                                                 ATOM_DEVICE_TV1_SUPPORT,
1848                                                                 2),
1849                                           ATOM_DEVICE_TV1_SUPPORT);
1850                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1851                                             DRM_MODE_CONNECTOR_SVIDEO,
1852                                             &ddc_i2c,
1853                                             CONNECTOR_OBJECT_ID_SVIDEO,
1854                                             &hpd);
1855                 break;
1856         case CT_POWERBOOK_VGA:
1857                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1858                          rdev->mode_info.connector_table);
1859                 /* LVDS */
1860                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1861                 hpd.hpd = RADEON_HPD_NONE;
1862                 radeon_add_legacy_encoder(dev,
1863                                           radeon_get_encoder_enum(dev,
1864                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1865                                                                 0),
1866                                           ATOM_DEVICE_LCD1_SUPPORT);
1867                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1868                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1869                                             CONNECTOR_OBJECT_ID_LVDS,
1870                                             &hpd);
1871                 /* VGA - primary dac */
1872                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1873                 hpd.hpd = RADEON_HPD_NONE;
1874                 radeon_add_legacy_encoder(dev,
1875                                           radeon_get_encoder_enum(dev,
1876                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1877                                                                 1),
1878                                           ATOM_DEVICE_CRT1_SUPPORT);
1879                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1880                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1881                                             CONNECTOR_OBJECT_ID_VGA,
1882                                             &hpd);
1883                 /* TV - TV DAC */
1884                 ddc_i2c.valid = false;
1885                 hpd.hpd = RADEON_HPD_NONE;
1886                 radeon_add_legacy_encoder(dev,
1887                                           radeon_get_encoder_enum(dev,
1888                                                                 ATOM_DEVICE_TV1_SUPPORT,
1889                                                                 2),
1890                                           ATOM_DEVICE_TV1_SUPPORT);
1891                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1892                                             DRM_MODE_CONNECTOR_SVIDEO,
1893                                             &ddc_i2c,
1894                                             CONNECTOR_OBJECT_ID_SVIDEO,
1895                                             &hpd);
1896                 break;
1897         case CT_MINI_EXTERNAL:
1898                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1899                          rdev->mode_info.connector_table);
1900                 /* DVI-I - tv dac, ext tmds */
1901                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1902                 hpd.hpd = RADEON_HPD_2; /* ??? */
1903                 radeon_add_legacy_encoder(dev,
1904                                           radeon_get_encoder_enum(dev,
1905                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1906                                                                 0),
1907                                           ATOM_DEVICE_DFP2_SUPPORT);
1908                 radeon_add_legacy_encoder(dev,
1909                                           radeon_get_encoder_enum(dev,
1910                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1911                                                                 2),
1912                                           ATOM_DEVICE_CRT2_SUPPORT);
1913                 /* XXX are any DL? */
1914                 radeon_add_legacy_connector(dev, 0,
1915                                             ATOM_DEVICE_DFP2_SUPPORT |
1916                                             ATOM_DEVICE_CRT2_SUPPORT,
1917                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1918                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1919                                             &hpd);
1920                 /* TV - TV DAC */
1921                 ddc_i2c.valid = false;
1922                 hpd.hpd = RADEON_HPD_NONE;
1923                 radeon_add_legacy_encoder(dev,
1924                                           radeon_get_encoder_enum(dev,
1925                                                                 ATOM_DEVICE_TV1_SUPPORT,
1926                                                                 2),
1927                                           ATOM_DEVICE_TV1_SUPPORT);
1928                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1929                                             DRM_MODE_CONNECTOR_SVIDEO,
1930                                             &ddc_i2c,
1931                                             CONNECTOR_OBJECT_ID_SVIDEO,
1932                                             &hpd);
1933                 break;
1934         case CT_MINI_INTERNAL:
1935                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1936                          rdev->mode_info.connector_table);
1937                 /* DVI-I - tv dac, int tmds */
1938                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1939                 hpd.hpd = RADEON_HPD_1; /* ??? */
1940                 radeon_add_legacy_encoder(dev,
1941                                           radeon_get_encoder_enum(dev,
1942                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1943                                                                 0),
1944                                           ATOM_DEVICE_DFP1_SUPPORT);
1945                 radeon_add_legacy_encoder(dev,
1946                                           radeon_get_encoder_enum(dev,
1947                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1948                                                                 2),
1949                                           ATOM_DEVICE_CRT2_SUPPORT);
1950                 radeon_add_legacy_connector(dev, 0,
1951                                             ATOM_DEVICE_DFP1_SUPPORT |
1952                                             ATOM_DEVICE_CRT2_SUPPORT,
1953                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1954                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1955                                             &hpd);
1956                 /* TV - TV DAC */
1957                 ddc_i2c.valid = false;
1958                 hpd.hpd = RADEON_HPD_NONE;
1959                 radeon_add_legacy_encoder(dev,
1960                                           radeon_get_encoder_enum(dev,
1961                                                                 ATOM_DEVICE_TV1_SUPPORT,
1962                                                                 2),
1963                                           ATOM_DEVICE_TV1_SUPPORT);
1964                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1965                                             DRM_MODE_CONNECTOR_SVIDEO,
1966                                             &ddc_i2c,
1967                                             CONNECTOR_OBJECT_ID_SVIDEO,
1968                                             &hpd);
1969                 break;
1970         case CT_IMAC_G5_ISIGHT:
1971                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1972                          rdev->mode_info.connector_table);
1973                 /* DVI-D - int tmds */
1974                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1975                 hpd.hpd = RADEON_HPD_1; /* ??? */
1976                 radeon_add_legacy_encoder(dev,
1977                                           radeon_get_encoder_enum(dev,
1978                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1979                                                                 0),
1980                                           ATOM_DEVICE_DFP1_SUPPORT);
1981                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1982                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1983                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1984                                             &hpd);
1985                 /* VGA - tv dac */
1986                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1987                 hpd.hpd = RADEON_HPD_NONE;
1988                 radeon_add_legacy_encoder(dev,
1989                                           radeon_get_encoder_enum(dev,
1990                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1991                                                                 2),
1992                                           ATOM_DEVICE_CRT2_SUPPORT);
1993                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1994                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1995                                             CONNECTOR_OBJECT_ID_VGA,
1996                                             &hpd);
1997                 /* TV - TV DAC */
1998                 ddc_i2c.valid = false;
1999                 hpd.hpd = RADEON_HPD_NONE;
2000                 radeon_add_legacy_encoder(dev,
2001                                           radeon_get_encoder_enum(dev,
2002                                                                 ATOM_DEVICE_TV1_SUPPORT,
2003                                                                 2),
2004                                           ATOM_DEVICE_TV1_SUPPORT);
2005                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2006                                             DRM_MODE_CONNECTOR_SVIDEO,
2007                                             &ddc_i2c,
2008                                             CONNECTOR_OBJECT_ID_SVIDEO,
2009                                             &hpd);
2010                 break;
2011         case CT_EMAC:
2012                 DRM_INFO("Connector Table: %d (emac)\n",
2013                          rdev->mode_info.connector_table);
2014                 /* VGA - primary dac */
2015                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2016                 hpd.hpd = RADEON_HPD_NONE;
2017                 radeon_add_legacy_encoder(dev,
2018                                           radeon_get_encoder_enum(dev,
2019                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2020                                                                 1),
2021                                           ATOM_DEVICE_CRT1_SUPPORT);
2022                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2023                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2024                                             CONNECTOR_OBJECT_ID_VGA,
2025                                             &hpd);
2026                 /* VGA - tv dac */
2027                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2028                 hpd.hpd = RADEON_HPD_NONE;
2029                 radeon_add_legacy_encoder(dev,
2030                                           radeon_get_encoder_enum(dev,
2031                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2032                                                                 2),
2033                                           ATOM_DEVICE_CRT2_SUPPORT);
2034                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2035                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2036                                             CONNECTOR_OBJECT_ID_VGA,
2037                                             &hpd);
2038                 /* TV - TV DAC */
2039                 ddc_i2c.valid = false;
2040                 hpd.hpd = RADEON_HPD_NONE;
2041                 radeon_add_legacy_encoder(dev,
2042                                           radeon_get_encoder_enum(dev,
2043                                                                 ATOM_DEVICE_TV1_SUPPORT,
2044                                                                 2),
2045                                           ATOM_DEVICE_TV1_SUPPORT);
2046                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2047                                             DRM_MODE_CONNECTOR_SVIDEO,
2048                                             &ddc_i2c,
2049                                             CONNECTOR_OBJECT_ID_SVIDEO,
2050                                             &hpd);
2051                 break;
2052         case CT_RN50_POWER:
2053                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2054                          rdev->mode_info.connector_table);
2055                 /* VGA - primary dac */
2056                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2057                 hpd.hpd = RADEON_HPD_NONE;
2058                 radeon_add_legacy_encoder(dev,
2059                                           radeon_get_encoder_enum(dev,
2060                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2061                                                                 1),
2062                                           ATOM_DEVICE_CRT1_SUPPORT);
2063                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2064                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2065                                             CONNECTOR_OBJECT_ID_VGA,
2066                                             &hpd);
2067                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2068                 hpd.hpd = RADEON_HPD_NONE;
2069                 radeon_add_legacy_encoder(dev,
2070                                           radeon_get_encoder_enum(dev,
2071                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2072                                                                 2),
2073                                           ATOM_DEVICE_CRT2_SUPPORT);
2074                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2075                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2076                                             CONNECTOR_OBJECT_ID_VGA,
2077                                             &hpd);
2078                 break;
2079         case CT_MAC_X800:
2080                 DRM_INFO("Connector Table: %d (mac x800)\n",
2081                          rdev->mode_info.connector_table);
2082                 /* DVI - primary dac, internal tmds */
2083                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2084                 hpd.hpd = RADEON_HPD_1; /* ??? */
2085                 radeon_add_legacy_encoder(dev,
2086                                           radeon_get_encoder_enum(dev,
2087                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2088                                                                   0),
2089                                           ATOM_DEVICE_DFP1_SUPPORT);
2090                 radeon_add_legacy_encoder(dev,
2091                                           radeon_get_encoder_enum(dev,
2092                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2093                                                                   1),
2094                                           ATOM_DEVICE_CRT1_SUPPORT);
2095                 radeon_add_legacy_connector(dev, 0,
2096                                             ATOM_DEVICE_DFP1_SUPPORT |
2097                                             ATOM_DEVICE_CRT1_SUPPORT,
2098                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2099                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2100                                             &hpd);
2101                 /* DVI - tv dac, dvo */
2102                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2103                 hpd.hpd = RADEON_HPD_2; /* ??? */
2104                 radeon_add_legacy_encoder(dev,
2105                                           radeon_get_encoder_enum(dev,
2106                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2107                                                                   0),
2108                                           ATOM_DEVICE_DFP2_SUPPORT);
2109                 radeon_add_legacy_encoder(dev,
2110                                           radeon_get_encoder_enum(dev,
2111                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2112                                                                   2),
2113                                           ATOM_DEVICE_CRT2_SUPPORT);
2114                 radeon_add_legacy_connector(dev, 1,
2115                                             ATOM_DEVICE_DFP2_SUPPORT |
2116                                             ATOM_DEVICE_CRT2_SUPPORT,
2117                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2118                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2119                                             &hpd);
2120                 break;
2121         case CT_MAC_G5_9600:
2122                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2123                          rdev->mode_info.connector_table);
2124                 /* DVI - tv dac, dvo */
2125                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2126                 hpd.hpd = RADEON_HPD_1; /* ??? */
2127                 radeon_add_legacy_encoder(dev,
2128                                           radeon_get_encoder_enum(dev,
2129                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2130                                                                   0),
2131                                           ATOM_DEVICE_DFP2_SUPPORT);
2132                 radeon_add_legacy_encoder(dev,
2133                                           radeon_get_encoder_enum(dev,
2134                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2135                                                                   2),
2136                                           ATOM_DEVICE_CRT2_SUPPORT);
2137                 radeon_add_legacy_connector(dev, 0,
2138                                             ATOM_DEVICE_DFP2_SUPPORT |
2139                                             ATOM_DEVICE_CRT2_SUPPORT,
2140                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2141                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2142                                             &hpd);
2143                 /* ADC - primary dac, internal tmds */
2144                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2145                 hpd.hpd = RADEON_HPD_2; /* ??? */
2146                 radeon_add_legacy_encoder(dev,
2147                                           radeon_get_encoder_enum(dev,
2148                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2149                                                                   0),
2150                                           ATOM_DEVICE_DFP1_SUPPORT);
2151                 radeon_add_legacy_encoder(dev,
2152                                           radeon_get_encoder_enum(dev,
2153                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2154                                                                   1),
2155                                           ATOM_DEVICE_CRT1_SUPPORT);
2156                 radeon_add_legacy_connector(dev, 1,
2157                                             ATOM_DEVICE_DFP1_SUPPORT |
2158                                             ATOM_DEVICE_CRT1_SUPPORT,
2159                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2160                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2161                                             &hpd);
2162                 /* TV - TV DAC */
2163                 ddc_i2c.valid = false;
2164                 hpd.hpd = RADEON_HPD_NONE;
2165                 radeon_add_legacy_encoder(dev,
2166                                           radeon_get_encoder_enum(dev,
2167                                                                 ATOM_DEVICE_TV1_SUPPORT,
2168                                                                 2),
2169                                           ATOM_DEVICE_TV1_SUPPORT);
2170                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2171                                             DRM_MODE_CONNECTOR_SVIDEO,
2172                                             &ddc_i2c,
2173                                             CONNECTOR_OBJECT_ID_SVIDEO,
2174                                             &hpd);
2175                 break;
2176         case CT_SAM440EP:
2177                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2178                          rdev->mode_info.connector_table);
2179                 /* LVDS */
2180                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2181                 hpd.hpd = RADEON_HPD_NONE;
2182                 radeon_add_legacy_encoder(dev,
2183                                           radeon_get_encoder_enum(dev,
2184                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2185                                                                 0),
2186                                           ATOM_DEVICE_LCD1_SUPPORT);
2187                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2188                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2189                                             CONNECTOR_OBJECT_ID_LVDS,
2190                                             &hpd);
2191                 /* DVI-I - secondary dac, int tmds */
2192                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2193                 hpd.hpd = RADEON_HPD_1; /* ??? */
2194                 radeon_add_legacy_encoder(dev,
2195                                           radeon_get_encoder_enum(dev,
2196                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2197                                                                 0),
2198                                           ATOM_DEVICE_DFP1_SUPPORT);
2199                 radeon_add_legacy_encoder(dev,
2200                                           radeon_get_encoder_enum(dev,
2201                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2202                                                                 2),
2203                                           ATOM_DEVICE_CRT2_SUPPORT);
2204                 radeon_add_legacy_connector(dev, 1,
2205                                             ATOM_DEVICE_DFP1_SUPPORT |
2206                                             ATOM_DEVICE_CRT2_SUPPORT,
2207                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2208                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2209                                             &hpd);
2210                 /* VGA - primary dac */
2211                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2212                 hpd.hpd = RADEON_HPD_NONE;
2213                 radeon_add_legacy_encoder(dev,
2214                                           radeon_get_encoder_enum(dev,
2215                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2216                                                                 1),
2217                                           ATOM_DEVICE_CRT1_SUPPORT);
2218                 radeon_add_legacy_connector(dev, 2,
2219                                             ATOM_DEVICE_CRT1_SUPPORT,
2220                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2221                                             CONNECTOR_OBJECT_ID_VGA,
2222                                             &hpd);
2223                 /* TV - TV DAC */
2224                 ddc_i2c.valid = false;
2225                 hpd.hpd = RADEON_HPD_NONE;
2226                 radeon_add_legacy_encoder(dev,
2227                                           radeon_get_encoder_enum(dev,
2228                                                                 ATOM_DEVICE_TV1_SUPPORT,
2229                                                                 2),
2230                                           ATOM_DEVICE_TV1_SUPPORT);
2231                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2232                                             DRM_MODE_CONNECTOR_SVIDEO,
2233                                             &ddc_i2c,
2234                                             CONNECTOR_OBJECT_ID_SVIDEO,
2235                                             &hpd);
2236                 break;
2237         case CT_MAC_G4_SILVER:
2238                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2239                          rdev->mode_info.connector_table);
2240                 /* DVI-I - tv dac, int tmds */
2241                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2242                 hpd.hpd = RADEON_HPD_1; /* ??? */
2243                 radeon_add_legacy_encoder(dev,
2244                                           radeon_get_encoder_enum(dev,
2245                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2246                                                                 0),
2247                                           ATOM_DEVICE_DFP1_SUPPORT);
2248                 radeon_add_legacy_encoder(dev,
2249                                           radeon_get_encoder_enum(dev,
2250                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2251                                                                 2),
2252                                           ATOM_DEVICE_CRT2_SUPPORT);
2253                 radeon_add_legacy_connector(dev, 0,
2254                                             ATOM_DEVICE_DFP1_SUPPORT |
2255                                             ATOM_DEVICE_CRT2_SUPPORT,
2256                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2257                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2258                                             &hpd);
2259                 /* VGA - primary dac */
2260                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2261                 hpd.hpd = RADEON_HPD_NONE;
2262                 radeon_add_legacy_encoder(dev,
2263                                           radeon_get_encoder_enum(dev,
2264                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2265                                                                 1),
2266                                           ATOM_DEVICE_CRT1_SUPPORT);
2267                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2268                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2269                                             CONNECTOR_OBJECT_ID_VGA,
2270                                             &hpd);
2271                 /* TV - TV DAC */
2272                 ddc_i2c.valid = false;
2273                 hpd.hpd = RADEON_HPD_NONE;
2274                 radeon_add_legacy_encoder(dev,
2275                                           radeon_get_encoder_enum(dev,
2276                                                                 ATOM_DEVICE_TV1_SUPPORT,
2277                                                                 2),
2278                                           ATOM_DEVICE_TV1_SUPPORT);
2279                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2280                                             DRM_MODE_CONNECTOR_SVIDEO,
2281                                             &ddc_i2c,
2282                                             CONNECTOR_OBJECT_ID_SVIDEO,
2283                                             &hpd);
2284                 break;
2285         default:
2286                 DRM_INFO("Connector table: %d (invalid)\n",
2287                          rdev->mode_info.connector_table);
2288                 return false;
2289         }
2290
2291         radeon_link_encoder_connector(dev);
2292
2293         return true;
2294 }
2295
2296 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2297                                        int bios_index,
2298                                        enum radeon_combios_connector
2299                                        *legacy_connector,
2300                                        struct radeon_i2c_bus_rec *ddc_i2c,
2301                                        struct radeon_hpd *hpd)
2302 {
2303
2304         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2305            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2306         if (dev->pci_device == 0x515e &&
2307             dev->pci_subvendor == 0x1014) {
2308                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2309                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2310                         return false;
2311         }
2312
2313         /* X300 card with extra non-existent DVI port */
2314         if (dev->pci_device == 0x5B60 &&
2315             dev->pci_subvendor == 0x17af &&
2316             dev->pci_subdevice == 0x201e && bios_index == 2) {
2317                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2318                         return false;
2319         }
2320
2321         return true;
2322 }
2323
2324 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2325 {
2326         /* Acer 5102 has non-existent TV port */
2327         if (dev->pci_device == 0x5975 &&
2328             dev->pci_subvendor == 0x1025 &&
2329             dev->pci_subdevice == 0x009f)
2330                 return false;
2331
2332         /* HP dc5750 has non-existent TV port */
2333         if (dev->pci_device == 0x5974 &&
2334             dev->pci_subvendor == 0x103c &&
2335             dev->pci_subdevice == 0x280a)
2336                 return false;
2337
2338         /* MSI S270 has non-existent TV port */
2339         if (dev->pci_device == 0x5955 &&
2340             dev->pci_subvendor == 0x1462 &&
2341             dev->pci_subdevice == 0x0131)
2342                 return false;
2343
2344         return true;
2345 }
2346
2347 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2348 {
2349         struct radeon_device *rdev = dev->dev_private;
2350         uint32_t ext_tmds_info;
2351
2352         if (rdev->flags & RADEON_IS_IGP) {
2353                 if (is_dvi_d)
2354                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2355                 else
2356                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2357         }
2358         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2359         if (ext_tmds_info) {
2360                 uint8_t rev = RBIOS8(ext_tmds_info);
2361                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2362                 if (rev >= 3) {
2363                         if (is_dvi_d)
2364                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2365                         else
2366                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2367                 } else {
2368                         if (flags & 1) {
2369                                 if (is_dvi_d)
2370                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2371                                 else
2372                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2373                         }
2374                 }
2375         }
2376         if (is_dvi_d)
2377                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2378         else
2379                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2380 }
2381
2382 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2383 {
2384         struct radeon_device *rdev = dev->dev_private;
2385         uint32_t conn_info, entry, devices;
2386         uint16_t tmp, connector_object_id;
2387         enum radeon_combios_ddc ddc_type;
2388         enum radeon_combios_connector connector;
2389         int i = 0;
2390         struct radeon_i2c_bus_rec ddc_i2c;
2391         struct radeon_hpd hpd;
2392
2393         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2394         if (conn_info) {
2395                 for (i = 0; i < 4; i++) {
2396                         entry = conn_info + 2 + i * 2;
2397
2398                         if (!RBIOS16(entry))
2399                                 break;
2400
2401                         tmp = RBIOS16(entry);
2402
2403                         connector = (tmp >> 12) & 0xf;
2404
2405                         ddc_type = (tmp >> 8) & 0xf;
2406                         if (ddc_type == 5)
2407                                 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2408                         else
2409                                 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2410
2411                         switch (connector) {
2412                         case CONNECTOR_PROPRIETARY_LEGACY:
2413                         case CONNECTOR_DVI_I_LEGACY:
2414                         case CONNECTOR_DVI_D_LEGACY:
2415                                 if ((tmp >> 4) & 0x1)
2416                                         hpd.hpd = RADEON_HPD_2;
2417                                 else
2418                                         hpd.hpd = RADEON_HPD_1;
2419                                 break;
2420                         default:
2421                                 hpd.hpd = RADEON_HPD_NONE;
2422                                 break;
2423                         }
2424
2425                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2426                                                         &ddc_i2c, &hpd))
2427                                 continue;
2428
2429                         switch (connector) {
2430                         case CONNECTOR_PROPRIETARY_LEGACY:
2431                                 if ((tmp >> 4) & 0x1)
2432                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2433                                 else
2434                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2435                                 radeon_add_legacy_encoder(dev,
2436                                                           radeon_get_encoder_enum
2437                                                           (dev, devices, 0),
2438                                                           devices);
2439                                 radeon_add_legacy_connector(dev, i, devices,
2440                                                             legacy_connector_convert
2441                                                             [connector],
2442                                                             &ddc_i2c,
2443                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2444                                                             &hpd);
2445                                 break;
2446                         case CONNECTOR_CRT_LEGACY:
2447                                 if (tmp & 0x1) {
2448                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2449                                         radeon_add_legacy_encoder(dev,
2450                                                                   radeon_get_encoder_enum
2451                                                                   (dev,
2452                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2453                                                                    2),
2454                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2455                                 } else {
2456                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2457                                         radeon_add_legacy_encoder(dev,
2458                                                                   radeon_get_encoder_enum
2459                                                                   (dev,
2460                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2461                                                                    1),
2462                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2463                                 }
2464                                 radeon_add_legacy_connector(dev,
2465                                                             i,
2466                                                             devices,
2467                                                             legacy_connector_convert
2468                                                             [connector],
2469                                                             &ddc_i2c,
2470                                                             CONNECTOR_OBJECT_ID_VGA,
2471                                                             &hpd);
2472                                 break;
2473                         case CONNECTOR_DVI_I_LEGACY:
2474                                 devices = 0;
2475                                 if (tmp & 0x1) {
2476                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2477                                         radeon_add_legacy_encoder(dev,
2478                                                                   radeon_get_encoder_enum
2479                                                                   (dev,
2480                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2481                                                                    2),
2482                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2483                                 } else {
2484                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2485                                         radeon_add_legacy_encoder(dev,
2486                                                                   radeon_get_encoder_enum
2487                                                                   (dev,
2488                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2489                                                                    1),
2490                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2491                                 }
2492                                 /* RV100 board with external TDMS bit mis-set.
2493                                  * Actually uses internal TMDS, clear the bit.
2494                                  */
2495                                 if (dev->pci_device == 0x5159 &&
2496                                     dev->pci_subvendor == 0x1014 &&
2497                                     dev->pci_subdevice == 0x029A) {
2498                                         tmp &= ~(1 << 4);
2499                                 }
2500                                 if ((tmp >> 4) & 0x1) {
2501                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2502                                         radeon_add_legacy_encoder(dev,
2503                                                                   radeon_get_encoder_enum
2504                                                                   (dev,
2505                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2506                                                                    0),
2507                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2508                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2509                                 } else {
2510                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2511                                         radeon_add_legacy_encoder(dev,
2512                                                                   radeon_get_encoder_enum
2513                                                                   (dev,
2514                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2515                                                                    0),
2516                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2517                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2518                                 }
2519                                 radeon_add_legacy_connector(dev,
2520                                                             i,
2521                                                             devices,
2522                                                             legacy_connector_convert
2523                                                             [connector],
2524                                                             &ddc_i2c,
2525                                                             connector_object_id,
2526                                                             &hpd);
2527                                 break;
2528                         case CONNECTOR_DVI_D_LEGACY:
2529                                 if ((tmp >> 4) & 0x1) {
2530                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2531                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2532                                 } else {
2533                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2534                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2535                                 }
2536                                 radeon_add_legacy_encoder(dev,
2537                                                           radeon_get_encoder_enum
2538                                                           (dev, devices, 0),
2539                                                           devices);
2540                                 radeon_add_legacy_connector(dev, i, devices,
2541                                                             legacy_connector_convert
2542                                                             [connector],
2543                                                             &ddc_i2c,
2544                                                             connector_object_id,
2545                                                             &hpd);
2546                                 break;
2547                         case CONNECTOR_CTV_LEGACY:
2548                         case CONNECTOR_STV_LEGACY:
2549                                 radeon_add_legacy_encoder(dev,
2550                                                           radeon_get_encoder_enum
2551                                                           (dev,
2552                                                            ATOM_DEVICE_TV1_SUPPORT,
2553                                                            2),
2554                                                           ATOM_DEVICE_TV1_SUPPORT);
2555                                 radeon_add_legacy_connector(dev, i,
2556                                                             ATOM_DEVICE_TV1_SUPPORT,
2557                                                             legacy_connector_convert
2558                                                             [connector],
2559                                                             &ddc_i2c,
2560                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2561                                                             &hpd);
2562                                 break;
2563                         default:
2564                                 DRM_ERROR("Unknown connector type: %d\n",
2565                                           connector);
2566                                 continue;
2567                         }
2568
2569                 }
2570         } else {
2571                 uint16_t tmds_info =
2572                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2573                 if (tmds_info) {
2574                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2575
2576                         radeon_add_legacy_encoder(dev,
2577                                                   radeon_get_encoder_enum(dev,
2578                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2579                                                                         1),
2580                                                   ATOM_DEVICE_CRT1_SUPPORT);
2581                         radeon_add_legacy_encoder(dev,
2582                                                   radeon_get_encoder_enum(dev,
2583                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2584                                                                         0),
2585                                                   ATOM_DEVICE_DFP1_SUPPORT);
2586
2587                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2588                         hpd.hpd = RADEON_HPD_1;
2589                         radeon_add_legacy_connector(dev,
2590                                                     0,
2591                                                     ATOM_DEVICE_CRT1_SUPPORT |
2592                                                     ATOM_DEVICE_DFP1_SUPPORT,
2593                                                     DRM_MODE_CONNECTOR_DVII,
2594                                                     &ddc_i2c,
2595                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2596                                                     &hpd);
2597                 } else {
2598                         uint16_t crt_info =
2599                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2600                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2601                         if (crt_info) {
2602                                 radeon_add_legacy_encoder(dev,
2603                                                           radeon_get_encoder_enum(dev,
2604                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2605                                                                                 1),
2606                                                           ATOM_DEVICE_CRT1_SUPPORT);
2607                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2608                                 hpd.hpd = RADEON_HPD_NONE;
2609                                 radeon_add_legacy_connector(dev,
2610                                                             0,
2611                                                             ATOM_DEVICE_CRT1_SUPPORT,
2612                                                             DRM_MODE_CONNECTOR_VGA,
2613                                                             &ddc_i2c,
2614                                                             CONNECTOR_OBJECT_ID_VGA,
2615                                                             &hpd);
2616                         } else {
2617                                 DRM_DEBUG_KMS("No connector info found\n");
2618                                 return false;
2619                         }
2620                 }
2621         }
2622
2623         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2624                 uint16_t lcd_info =
2625                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2626                 if (lcd_info) {
2627                         uint16_t lcd_ddc_info =
2628                             combios_get_table_offset(dev,
2629                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2630
2631                         radeon_add_legacy_encoder(dev,
2632                                                   radeon_get_encoder_enum(dev,
2633                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2634                                                                         0),
2635                                                   ATOM_DEVICE_LCD1_SUPPORT);
2636
2637                         if (lcd_ddc_info) {
2638                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2639                                 switch (ddc_type) {
2640                                 case DDC_LCD:
2641                                         ddc_i2c =
2642                                                 combios_setup_i2c_bus(rdev,
2643                                                                       DDC_LCD,
2644                                                                       RBIOS32(lcd_ddc_info + 3),
2645                                                                       RBIOS32(lcd_ddc_info + 7));
2646                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2647                                         break;
2648                                 case DDC_GPIO:
2649                                         ddc_i2c =
2650                                                 combios_setup_i2c_bus(rdev,
2651                                                                       DDC_GPIO,
2652                                                                       RBIOS32(lcd_ddc_info + 3),
2653                                                                       RBIOS32(lcd_ddc_info + 7));
2654                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2655                                         break;
2656                                 default:
2657                                         ddc_i2c =
2658                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2659                                         break;
2660                                 }
2661                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2662                         } else
2663                                 ddc_i2c.valid = false;
2664
2665                         hpd.hpd = RADEON_HPD_NONE;
2666                         radeon_add_legacy_connector(dev,
2667                                                     5,
2668                                                     ATOM_DEVICE_LCD1_SUPPORT,
2669                                                     DRM_MODE_CONNECTOR_LVDS,
2670                                                     &ddc_i2c,
2671                                                     CONNECTOR_OBJECT_ID_LVDS,
2672                                                     &hpd);
2673                 }
2674         }
2675
2676         /* check TV table */
2677         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2678                 uint32_t tv_info =
2679                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2680                 if (tv_info) {
2681                         if (RBIOS8(tv_info + 6) == 'T') {
2682                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2683                                         hpd.hpd = RADEON_HPD_NONE;
2684                                         ddc_i2c.valid = false;
2685                                         radeon_add_legacy_encoder(dev,
2686                                                                   radeon_get_encoder_enum
2687                                                                   (dev,
2688                                                                    ATOM_DEVICE_TV1_SUPPORT,
2689                                                                    2),
2690                                                                   ATOM_DEVICE_TV1_SUPPORT);
2691                                         radeon_add_legacy_connector(dev, 6,
2692                                                                     ATOM_DEVICE_TV1_SUPPORT,
2693                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2694                                                                     &ddc_i2c,
2695                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2696                                                                     &hpd);
2697                                 }
2698                         }
2699                 }
2700         }
2701
2702         radeon_link_encoder_connector(dev);
2703
2704         return true;
2705 }
2706
2707 static const char *thermal_controller_names[] = {
2708         "NONE",
2709         "lm63",
2710         "adm1032",
2711 };
2712
2713 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2714 {
2715         struct drm_device *dev = rdev->ddev;
2716         u16 offset, misc, misc2 = 0;
2717         u8 rev, blocks, tmp;
2718         int state_index = 0;
2719         struct radeon_i2c_bus_rec i2c_bus;
2720
2721         rdev->pm.default_power_state_index = -1;
2722
2723         /* allocate 2 power states */
2724         rdev->pm.power_state = malloc(sizeof(struct radeon_power_state) * 2,
2725             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2726         if (rdev->pm.power_state) {
2727                 /* allocate 1 clock mode per state */
2728                 rdev->pm.power_state[0].clock_info =
2729                         malloc(sizeof(struct radeon_pm_clock_info) * 1,
2730                             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2731                 rdev->pm.power_state[1].clock_info =
2732                         malloc(sizeof(struct radeon_pm_clock_info) * 1,
2733                             DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
2734                 if (!rdev->pm.power_state[0].clock_info ||
2735                     !rdev->pm.power_state[1].clock_info)
2736                         goto pm_failed;
2737         } else
2738                 goto pm_failed;
2739
2740         /* check for a thermal chip */
2741         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2742         if (offset) {
2743                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2744
2745                 rev = RBIOS8(offset);
2746
2747                 if (rev == 0) {
2748                         thermal_controller = RBIOS8(offset + 3);
2749                         gpio = RBIOS8(offset + 4) & 0x3f;
2750                         i2c_addr = RBIOS8(offset + 5);
2751                 } else if (rev == 1) {
2752                         thermal_controller = RBIOS8(offset + 4);
2753                         gpio = RBIOS8(offset + 5) & 0x3f;
2754                         i2c_addr = RBIOS8(offset + 6);
2755                 } else if (rev == 2) {
2756                         thermal_controller = RBIOS8(offset + 4);
2757                         gpio = RBIOS8(offset + 5) & 0x3f;
2758                         i2c_addr = RBIOS8(offset + 6);
2759                         clk_bit = RBIOS8(offset + 0xa);
2760                         data_bit = RBIOS8(offset + 0xb);
2761                 }
2762                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2763                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2764                                  thermal_controller_names[thermal_controller],
2765                                  i2c_addr >> 1);
2766                         if (gpio == DDC_LCD) {
2767                                 /* MM i2c */
2768                                 i2c_bus.valid = true;
2769                                 i2c_bus.hw_capable = true;
2770                                 i2c_bus.mm_i2c = true;
2771                                 i2c_bus.i2c_id = 0xa0;
2772                         } else if (gpio == DDC_GPIO)
2773                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2774                         else
2775                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2776                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2777                         if (rdev->pm.i2c_bus) {
2778 #ifdef FREEBSD_WIP
2779                                 struct i2c_board_info info = { };
2780                                 const char *name = thermal_controller_names[thermal_controller];
2781                                 info.addr = i2c_addr >> 1;
2782                                 strlcpy(info.type, name, sizeof(info.type));
2783                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2784 #endif /* FREEBSD_WIP */
2785                         }
2786                 }
2787         } else {
2788                 /* boards with a thermal chip, but no overdrive table */
2789
2790                 /* Asus 9600xt has an f75375 on the monid bus */
2791                 if ((dev->pci_device == 0x4152) &&
2792                     (dev->pci_subvendor == 0x1043) &&
2793                     (dev->pci_subdevice == 0xc002)) {
2794                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2795                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2796                         if (rdev->pm.i2c_bus) {
2797 #ifdef FREEBSD_WIP
2798                                 struct i2c_board_info info = { };
2799                                 const char *name = "f75375";
2800                                 info.addr = 0x28;
2801                                 strlcpy(info.type, name, sizeof(info.type));
2802                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2803                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2804                                          name, info.addr);
2805 #endif /* FREEBSD_WIP */
2806                         }
2807                 }
2808         }
2809
2810         if (rdev->flags & RADEON_IS_MOBILITY) {
2811                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2812                 if (offset) {
2813                         rev = RBIOS8(offset);
2814                         blocks = RBIOS8(offset + 0x2);
2815                         /* power mode 0 tends to be the only valid one */
2816                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2817                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2818                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2819                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2820                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2821                                 goto default_mode;
2822                         rdev->pm.power_state[state_index].type =
2823                                 POWER_STATE_TYPE_BATTERY;
2824                         misc = RBIOS16(offset + 0x5 + 0x0);
2825                         if (rev > 4)
2826                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2827                         rdev->pm.power_state[state_index].misc = misc;
2828                         rdev->pm.power_state[state_index].misc2 = misc2;
2829                         if (misc & 0x4) {
2830                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2831                                 if (misc & 0x8)
2832                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2833                                                 true;
2834                                 else
2835                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2836                                                 false;
2837                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2838                                 if (rev < 6) {
2839                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2840                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2841                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2842                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2843                                 } else {
2844                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2845                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2846                                         if (entries && voltage_table_offset) {
2847                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2848                                                         RBIOS16(voltage_table_offset) * 4;
2849                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2850                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2851                                         } else
2852                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2853                                 }
2854                                 switch ((misc2 & 0x700) >> 8) {
2855                                 case 0:
2856                                 default:
2857                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2858                                         break;
2859                                 case 1:
2860                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2861                                         break;
2862                                 case 2:
2863                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2864                                         break;
2865                                 case 3:
2866                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2867                                         break;
2868                                 case 4:
2869                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2870                                         break;
2871                                 }
2872                         } else
2873                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2874                         if (rev > 6)
2875                                 rdev->pm.power_state[state_index].pcie_lanes =
2876                                         RBIOS8(offset + 0x5 + 0x10);
2877                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2878                         state_index++;
2879                 } else {
2880                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2881                 }
2882         } else {
2883                 /* XXX figure out some good default low power mode for desktop cards */
2884         }
2885
2886 default_mode:
2887         /* add the default mode */
2888         rdev->pm.power_state[state_index].type =
2889                 POWER_STATE_TYPE_DEFAULT;
2890         rdev->pm.power_state[state_index].num_clock_modes = 1;
2891         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2892         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2893         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2894         if ((state_index > 0) &&
2895             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2896                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2897                         rdev->pm.power_state[0].clock_info[0].voltage;
2898         else
2899                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2900         rdev->pm.power_state[state_index].pcie_lanes = 16;
2901         rdev->pm.power_state[state_index].flags = 0;
2902         rdev->pm.default_power_state_index = state_index;
2903         rdev->pm.num_power_states = state_index + 1;
2904
2905         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2906         rdev->pm.current_clock_mode_index = 0;
2907         return;
2908
2909 pm_failed:
2910         rdev->pm.default_power_state_index = state_index;
2911         rdev->pm.num_power_states = 0;
2912
2913         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2914         rdev->pm.current_clock_mode_index = 0;
2915 }
2916
2917 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2918 {
2919         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2920         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2921
2922         if (!tmds)
2923                 return;
2924
2925         switch (tmds->dvo_chip) {
2926         case DVO_SIL164:
2927                 /* sil 164 */
2928                 radeon_i2c_put_byte(tmds->i2c_bus,
2929                                     tmds->slave_addr,
2930                                     0x08, 0x30);
2931                 radeon_i2c_put_byte(tmds->i2c_bus,
2932                                        tmds->slave_addr,
2933                                        0x09, 0x00);
2934                 radeon_i2c_put_byte(tmds->i2c_bus,
2935                                     tmds->slave_addr,
2936                                     0x0a, 0x90);
2937                 radeon_i2c_put_byte(tmds->i2c_bus,
2938                                     tmds->slave_addr,
2939                                     0x0c, 0x89);
2940                 radeon_i2c_put_byte(tmds->i2c_bus,
2941                                        tmds->slave_addr,
2942                                        0x08, 0x3b);
2943                 break;
2944         case DVO_SIL1178:
2945                 /* sil 1178 - untested */
2946                 /*
2947                  * 0x0f, 0x44
2948                  * 0x0f, 0x4c
2949                  * 0x0e, 0x01
2950                  * 0x0a, 0x80
2951                  * 0x09, 0x30
2952                  * 0x0c, 0xc9
2953                  * 0x0d, 0x70
2954                  * 0x08, 0x32
2955                  * 0x08, 0x33
2956                  */
2957                 break;
2958         default:
2959                 break;
2960         }
2961
2962 }
2963
2964 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2965 {
2966         struct drm_device *dev = encoder->dev;
2967         struct radeon_device *rdev = dev->dev_private;
2968         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2969         uint16_t offset;
2970         uint8_t blocks, slave_addr, rev;
2971         uint32_t index, id;
2972         uint32_t reg, val, and_mask, or_mask;
2973         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2974
2975         if (!tmds)
2976                 return false;
2977
2978         if (rdev->flags & RADEON_IS_IGP) {
2979                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2980                 rev = RBIOS8(offset);
2981                 if (offset) {
2982                         rev = RBIOS8(offset);
2983                         if (rev > 1) {
2984                                 blocks = RBIOS8(offset + 3);
2985                                 index = offset + 4;
2986                                 while (blocks > 0) {
2987                                         id = RBIOS16(index);
2988                                         index += 2;
2989                                         switch (id >> 13) {
2990                                         case 0:
2991                                                 reg = (id & 0x1fff) * 4;
2992                                                 val = RBIOS32(index);
2993                                                 index += 4;
2994                                                 WREG32(reg, val);
2995                                                 break;
2996                                         case 2:
2997                                                 reg = (id & 0x1fff) * 4;
2998                                                 and_mask = RBIOS32(index);
2999                                                 index += 4;
3000                                                 or_mask = RBIOS32(index);
3001                                                 index += 4;
3002                                                 val = RREG32(reg);
3003                                                 val = (val & and_mask) | or_mask;
3004                                                 WREG32(reg, val);
3005                                                 break;
3006                                         case 3:
3007                                                 val = RBIOS16(index);
3008                                                 index += 2;
3009                                                 udelay(val);
3010                                                 break;
3011                                         case 4:
3012                                                 val = RBIOS16(index);
3013                                                 index += 2;
3014                                                 mdelay(val);
3015                                                 break;
3016                                         case 6:
3017                                                 slave_addr = id & 0xff;
3018                                                 slave_addr >>= 1; /* 7 bit addressing */
3019                                                 index++;
3020                                                 reg = RBIOS8(index);
3021                                                 index++;
3022                                                 val = RBIOS8(index);
3023                                                 index++;
3024                                                 radeon_i2c_put_byte(tmds->i2c_bus,
3025                                                                     slave_addr,
3026                                                                     reg, val);
3027                                                 break;
3028                                         default:
3029                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
3030                                                 break;
3031                                         }
3032                                         blocks--;
3033                                 }
3034                                 return true;
3035                         }
3036                 }
3037         } else {
3038                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
3039                 if (offset) {
3040                         index = offset + 10;
3041                         id = RBIOS16(index);
3042                         while (id != 0xffff) {
3043                                 index += 2;
3044                                 switch (id >> 13) {
3045                                 case 0:
3046                                         reg = (id & 0x1fff) * 4;
3047                                         val = RBIOS32(index);
3048                                         WREG32(reg, val);
3049                                         break;
3050                                 case 2:
3051                                         reg = (id & 0x1fff) * 4;
3052                                         and_mask = RBIOS32(index);
3053                                         index += 4;
3054                                         or_mask = RBIOS32(index);
3055                                         index += 4;
3056                                         val = RREG32(reg);
3057                                         val = (val & and_mask) | or_mask;
3058                                         WREG32(reg, val);
3059                                         break;
3060                                 case 4:
3061                                         val = RBIOS16(index);
3062                                         index += 2;
3063                                         udelay(val);
3064                                         break;
3065                                 case 5:
3066                                         reg = id & 0x1fff;
3067                                         and_mask = RBIOS32(index);
3068                                         index += 4;
3069                                         or_mask = RBIOS32(index);
3070                                         index += 4;
3071                                         val = RREG32_PLL(reg);
3072                                         val = (val & and_mask) | or_mask;
3073                                         WREG32_PLL(reg, val);
3074                                         break;
3075                                 case 6:
3076                                         reg = id & 0x1fff;
3077                                         val = RBIOS8(index);
3078                                         index += 1;
3079                                         radeon_i2c_put_byte(tmds->i2c_bus,
3080                                                             tmds->slave_addr,
3081                                                             reg, val);
3082                                         break;
3083                                 default:
3084                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3085                                         break;
3086                                 }
3087                                 id = RBIOS16(index);
3088                         }
3089                         return true;
3090                 }
3091         }
3092         return false;
3093 }
3094
3095 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3096 {
3097         struct radeon_device *rdev = dev->dev_private;
3098
3099         if (offset) {
3100                 while (RBIOS16(offset)) {
3101                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3102                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3103                         uint32_t val, and_mask, or_mask;
3104                         uint32_t tmp;
3105
3106                         offset += 2;
3107                         switch (cmd) {
3108                         case 0:
3109                                 val = RBIOS32(offset);
3110                                 offset += 4;
3111                                 WREG32(addr, val);
3112                                 break;
3113                         case 1:
3114                                 val = RBIOS32(offset);
3115                                 offset += 4;
3116                                 WREG32(addr, val);
3117                                 break;
3118                         case 2:
3119                                 and_mask = RBIOS32(offset);
3120                                 offset += 4;
3121                                 or_mask = RBIOS32(offset);
3122                                 offset += 4;
3123                                 tmp = RREG32(addr);
3124                                 tmp &= and_mask;
3125                                 tmp |= or_mask;
3126                                 WREG32(addr, tmp);
3127                                 break;
3128                         case 3:
3129                                 and_mask = RBIOS32(offset);
3130                                 offset += 4;
3131                                 or_mask = RBIOS32(offset);
3132                                 offset += 4;
3133                                 tmp = RREG32(addr);
3134                                 tmp &= and_mask;
3135                                 tmp |= or_mask;
3136                                 WREG32(addr, tmp);
3137                                 break;
3138                         case 4:
3139                                 val = RBIOS16(offset);
3140                                 offset += 2;
3141                                 udelay(val);
3142                                 break;
3143                         case 5:
3144                                 val = RBIOS16(offset);
3145                                 offset += 2;
3146                                 switch (addr) {
3147                                 case 8:
3148                                         while (val--) {
3149                                                 if (!
3150                                                     (RREG32_PLL
3151                                                      (RADEON_CLK_PWRMGT_CNTL) &
3152                                                      RADEON_MC_BUSY))
3153                                                         break;
3154                                         }
3155                                         break;
3156                                 case 9:
3157                                         while (val--) {
3158                                                 if ((RREG32(RADEON_MC_STATUS) &
3159                                                      RADEON_MC_IDLE))
3160                                                         break;
3161                                         }
3162                                         break;
3163                                 default:
3164                                         break;
3165                                 }
3166                                 break;
3167                         default:
3168                                 break;
3169                         }
3170                 }
3171         }
3172 }
3173
3174 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3175 {
3176         struct radeon_device *rdev = dev->dev_private;
3177
3178         if (offset) {
3179                 while (RBIOS8(offset)) {
3180                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3181                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3182                         uint32_t val, shift, tmp;
3183                         uint32_t and_mask, or_mask;
3184
3185                         offset++;
3186                         switch (cmd) {
3187                         case 0:
3188                                 val = RBIOS32(offset);
3189                                 offset += 4;
3190                                 WREG32_PLL(addr, val);
3191                                 break;
3192                         case 1:
3193                                 shift = RBIOS8(offset) * 8;
3194                                 offset++;
3195                                 and_mask = RBIOS8(offset) << shift;
3196                                 and_mask |= ~(0xff << shift);
3197                                 offset++;
3198                                 or_mask = RBIOS8(offset) << shift;
3199                                 offset++;
3200                                 tmp = RREG32_PLL(addr);
3201                                 tmp &= and_mask;
3202                                 tmp |= or_mask;
3203                                 WREG32_PLL(addr, tmp);
3204                                 break;
3205                         case 2:
3206                         case 3:
3207                                 tmp = 1000;
3208                                 switch (addr) {
3209                                 case 1:
3210                                         udelay(150);
3211                                         break;
3212                                 case 2:
3213                                         mdelay(1);
3214                                         break;
3215                                 case 3:
3216                                         while (tmp--) {
3217                                                 if (!
3218                                                     (RREG32_PLL
3219                                                      (RADEON_CLK_PWRMGT_CNTL) &
3220                                                      RADEON_MC_BUSY))
3221                                                         break;
3222                                         }
3223                                         break;
3224                                 case 4:
3225                                         while (tmp--) {
3226                                                 if (RREG32_PLL
3227                                                     (RADEON_CLK_PWRMGT_CNTL) &
3228                                                     RADEON_DLL_READY)
3229                                                         break;
3230                                         }
3231                                         break;
3232                                 case 5:
3233                                         tmp =
3234                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3235                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3236 #if 0
3237                                                 uint32_t mclk_cntl =
3238                                                     RREG32_PLL
3239                                                     (RADEON_MCLK_CNTL);
3240                                                 mclk_cntl &= 0xffff0000;
3241                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3242                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3243                                                            mclk_cntl);
3244                                                 mdelay(10);
3245 #endif
3246                                                 WREG32_PLL
3247                                                     (RADEON_CLK_PWRMGT_CNTL,
3248                                                      tmp &
3249                                                      ~RADEON_CG_NO1_DEBUG_0);
3250                                                 mdelay(10);
3251                                         }
3252                                         break;
3253                                 default:
3254                                         break;
3255                                 }
3256                                 break;
3257                         default:
3258                                 break;
3259                         }
3260                 }
3261         }
3262 }
3263
3264 static void combios_parse_ram_reset_table(struct drm_device *dev,
3265                                           uint16_t offset)
3266 {
3267         struct radeon_device *rdev = dev->dev_private;
3268         uint32_t tmp;
3269
3270         if (offset) {
3271                 uint8_t val = RBIOS8(offset);
3272                 while (val != 0xff) {
3273                         offset++;
3274
3275                         if (val == 0x0f) {
3276                                 uint32_t channel_complete_mask;
3277
3278                                 if (ASIC_IS_R300(rdev))
3279                                         channel_complete_mask =
3280                                             R300_MEM_PWRUP_COMPLETE;
3281                                 else
3282                                         channel_complete_mask =
3283                                             RADEON_MEM_PWRUP_COMPLETE;
3284                                 tmp = 20000;
3285                                 while (tmp--) {
3286                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3287                                              channel_complete_mask) ==
3288                                             channel_complete_mask)
3289                                                 break;
3290                                 }
3291                         } else {
3292                                 uint32_t or_mask = RBIOS16(offset);
3293                                 offset += 2;
3294
3295                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3296                                 tmp &= RADEON_SDRAM_MODE_MASK;
3297                                 tmp |= or_mask;
3298                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3299
3300                                 or_mask = val << 24;
3301                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3302                                 tmp &= RADEON_B3MEM_RESET_MASK;
3303                                 tmp |= or_mask;
3304                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3305                         }
3306                         val = RBIOS8(offset);
3307                 }
3308         }
3309 }
3310
3311 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3312                                    int mem_addr_mapping)
3313 {
3314         struct radeon_device *rdev = dev->dev_private;
3315         uint32_t mem_cntl;
3316         uint32_t mem_size;
3317         uint32_t addr = 0;
3318
3319         mem_cntl = RREG32(RADEON_MEM_CNTL);
3320         if (mem_cntl & RV100_HALF_MODE)
3321                 ram /= 2;
3322         mem_size = ram;
3323         mem_cntl &= ~(0xff << 8);
3324         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3325         WREG32(RADEON_MEM_CNTL, mem_cntl);
3326         RREG32(RADEON_MEM_CNTL);
3327
3328         /* sdram reset ? */
3329
3330         /* something like this????  */
3331         while (ram--) {
3332                 addr = ram * 1024 * 1024;
3333                 /* write to each page */
3334                 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3335                 /* read back and verify */
3336                 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3337                         return 0;
3338         }
3339
3340         return mem_size;
3341 }
3342
3343 static void combios_write_ram_size(struct drm_device *dev)
3344 {
3345         struct radeon_device *rdev = dev->dev_private;
3346         uint8_t rev;
3347         uint16_t offset;
3348         uint32_t mem_size = 0;
3349         uint32_t mem_cntl = 0;
3350
3351         /* should do something smarter here I guess... */
3352         if (rdev->flags & RADEON_IS_IGP)
3353                 return;
3354
3355         /* first check detected mem table */
3356         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3357         if (offset) {
3358                 rev = RBIOS8(offset);
3359                 if (rev < 3) {
3360                         mem_cntl = RBIOS32(offset + 1);
3361                         mem_size = RBIOS16(offset + 5);
3362                         if ((rdev->family < CHIP_R200) &&
3363                             !ASIC_IS_RN50(rdev))
3364                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3365                 }
3366         }
3367
3368         if (!mem_size) {
3369                 offset =
3370                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3371                 if (offset) {
3372                         rev = RBIOS8(offset - 1);
3373                         if (rev < 1) {
3374                                 if ((rdev->family < CHIP_R200)
3375                                     && !ASIC_IS_RN50(rdev)) {
3376                                         int ram = 0;
3377                                         int mem_addr_mapping = 0;
3378
3379                                         while (RBIOS8(offset)) {
3380                                                 ram = RBIOS8(offset);
3381                                                 mem_addr_mapping =
3382                                                     RBIOS8(offset + 1);
3383                                                 if (mem_addr_mapping != 0x25)
3384                                                         ram *= 2;
3385                                                 mem_size =
3386                                                     combios_detect_ram(dev, ram,
3387                                                                        mem_addr_mapping);
3388                                                 if (mem_size)
3389                                                         break;
3390                                                 offset += 2;
3391                                         }
3392                                 } else
3393                                         mem_size = RBIOS8(offset);
3394                         } else {
3395                                 mem_size = RBIOS8(offset);
3396                                 mem_size *= 2;  /* convert to MB */
3397                         }
3398                 }
3399         }
3400
3401         mem_size *= (1024 * 1024);      /* convert to bytes */
3402         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3403 }
3404
3405 void radeon_combios_asic_init(struct drm_device *dev)
3406 {
3407         struct radeon_device *rdev = dev->dev_private;
3408         uint16_t table;
3409
3410         /* port hardcoded mac stuff from radeonfb */
3411         if (rdev->bios == NULL)
3412                 return;
3413
3414         /* ASIC INIT 1 */
3415         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3416         if (table)
3417                 combios_parse_mmio_table(dev, table);
3418
3419         /* PLL INIT */
3420         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3421         if (table)
3422                 combios_parse_pll_table(dev, table);
3423
3424         /* ASIC INIT 2 */
3425         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3426         if (table)
3427                 combios_parse_mmio_table(dev, table);
3428
3429         if (!(rdev->flags & RADEON_IS_IGP)) {
3430                 /* ASIC INIT 4 */
3431                 table =
3432                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3433                 if (table)
3434                         combios_parse_mmio_table(dev, table);
3435
3436                 /* RAM RESET */
3437                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3438                 if (table)
3439                         combios_parse_ram_reset_table(dev, table);
3440
3441                 /* ASIC INIT 3 */
3442                 table =
3443                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3444                 if (table)
3445                         combios_parse_mmio_table(dev, table);
3446
3447                 /* write CONFIG_MEMSIZE */
3448                 combios_write_ram_size(dev);
3449         }
3450
3451         /* quirk for rs4xx HP nx6125 laptop to make it resume
3452          * - it hangs on resume inside the dynclk 1 table.
3453          */
3454         if (rdev->family == CHIP_RS480 &&
3455             dev->pci_subvendor == 0x103c &&
3456             dev->pci_subdevice == 0x308b)
3457                 return;
3458
3459         /* quirk for rs4xx HP dv5000 laptop to make it resume
3460          * - it hangs on resume inside the dynclk 1 table.
3461          */
3462         if (rdev->family == CHIP_RS480 &&
3463             dev->pci_subvendor == 0x103c &&
3464             dev->pci_subdevice == 0x30a4)
3465                 return;
3466
3467         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3468          * - it hangs on resume inside the dynclk 1 table.
3469          */
3470         if (rdev->family == CHIP_RS480 &&
3471             dev->pci_subvendor == 0x103c &&
3472             dev->pci_subdevice == 0x30ae)
3473                 return;
3474
3475         /* DYN CLK 1 */
3476         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3477         if (table)
3478                 combios_parse_pll_table(dev, table);
3479
3480 }
3481
3482 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3483 {
3484         struct radeon_device *rdev = dev->dev_private;
3485         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3486
3487         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3488         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3489         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3490
3491         /* let the bios control the backlight */
3492         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3493
3494         /* tell the bios not to handle mode switching */
3495         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3496                            RADEON_ACC_MODE_CHANGE);
3497
3498         /* tell the bios a driver is loaded */
3499         bios_7_scratch |= RADEON_DRV_LOADED;
3500
3501         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3502         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3503         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3504 }
3505
3506 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3507 {
3508         struct drm_device *dev = encoder->dev;
3509         struct radeon_device *rdev = dev->dev_private;
3510         uint32_t bios_6_scratch;
3511
3512         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3513
3514         if (lock)
3515                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3516         else
3517                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3518
3519         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3520 }
3521
3522 void
3523 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3524                                       struct drm_encoder *encoder,
3525                                       bool connected)
3526 {
3527         struct drm_device *dev = connector->dev;
3528         struct radeon_device *rdev = dev->dev_private;
3529         struct radeon_connector *radeon_connector =
3530             to_radeon_connector(connector);
3531         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3532         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3533         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3534
3535         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3536             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3537                 if (connected) {
3538                         DRM_DEBUG_KMS("TV1 connected\n");
3539                         /* fix me */
3540                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3541                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3542                         bios_5_scratch |= RADEON_TV1_ON;
3543                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3544                 } else {
3545                         DRM_DEBUG_KMS("TV1 disconnected\n");
3546                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3547                         bios_5_scratch &= ~RADEON_TV1_ON;
3548                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3549                 }
3550         }
3551         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3552             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3553                 if (connected) {
3554                         DRM_DEBUG_KMS("LCD1 connected\n");
3555                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3556                         bios_5_scratch |= RADEON_LCD1_ON;
3557                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3558                 } else {
3559                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3560                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3561                         bios_5_scratch &= ~RADEON_LCD1_ON;
3562                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3563                 }
3564         }
3565         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3566             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3567                 if (connected) {
3568                         DRM_DEBUG_KMS("CRT1 connected\n");
3569                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3570                         bios_5_scratch |= RADEON_CRT1_ON;
3571                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3572                 } else {
3573                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3574                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3575                         bios_5_scratch &= ~RADEON_CRT1_ON;
3576                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3577                 }
3578         }
3579         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3580             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3581                 if (connected) {
3582                         DRM_DEBUG_KMS("CRT2 connected\n");
3583                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3584                         bios_5_scratch |= RADEON_CRT2_ON;
3585                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3586                 } else {
3587                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3588                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3589                         bios_5_scratch &= ~RADEON_CRT2_ON;
3590                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3591                 }
3592         }
3593         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3594             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3595                 if (connected) {
3596                         DRM_DEBUG_KMS("DFP1 connected\n");
3597                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3598                         bios_5_scratch |= RADEON_DFP1_ON;
3599                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3600                 } else {
3601                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3602                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3603                         bios_5_scratch &= ~RADEON_DFP1_ON;
3604                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3605                 }
3606         }
3607         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3608             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3609                 if (connected) {
3610                         DRM_DEBUG_KMS("DFP2 connected\n");
3611                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3612                         bios_5_scratch |= RADEON_DFP2_ON;
3613                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3614                 } else {
3615                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3616                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3617                         bios_5_scratch &= ~RADEON_DFP2_ON;
3618                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3619                 }
3620         }
3621         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3622         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3623 }
3624
3625 void
3626 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3627 {
3628         struct drm_device *dev = encoder->dev;
3629         struct radeon_device *rdev = dev->dev_private;
3630         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3631         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3632
3633         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3634                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3635                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3636         }
3637         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3638                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3639                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3640         }
3641         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3642                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3643                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3644         }
3645         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3646                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3647                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3648         }
3649         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3650                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3651                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3652         }
3653         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3654                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3655                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3656         }
3657         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3658 }
3659
3660 void
3661 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3662 {
3663         struct drm_device *dev = encoder->dev;
3664         struct radeon_device *rdev = dev->dev_private;
3665         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3666         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3667
3668         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3669                 if (on)
3670                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3671                 else
3672                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3673         }
3674         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3675                 if (on)
3676                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3677                 else
3678                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3679         }
3680         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3681                 if (on)
3682                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3683                 else
3684                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3685         }
3686         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3687                 if (on)
3688                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3689                 else
3690                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3691         }
3692         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3693 }