sys/dev/drm2/radeon/rs400.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <dev/drm2/drmP.h>
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "rs400d.h"
  36
  37 /* This files gather functions specifics to : rs400,rs480 */
  38 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  39
  40 void rs400_gart_adjust_size(struct radeon_device *rdev)
  41 {
  42         /* Check gart size */
  43         switch (rdev->mc.gtt_size/(1024*1024)) {
  44         case 32:
  45         case 64:
  46         case 128:
  47         case 256:
  48         case 512:
  49         case 1024:
  50         case 2048:
  51                 break;
  52         default:
  53                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  54                           (unsigned)(rdev->mc.gtt_size >> 20));
  55                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  56                 DRM_ERROR("Forcing to 32M GART size\n");
  57                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  58                 return;
  59         }
  60 }
  61
  62 void rs400_gart_tlb_flush(struct radeon_device *rdev)
  63 {
  64         uint32_t tmp;
  65         unsigned int timeout = rdev->usec_timeout;
  66
  67         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  68         do {
  69                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  70                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  71                         break;
  72                 DRM_UDELAY(1);
  73                 timeout--;
  74         } while (timeout > 0);
  75         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  76 }
  77
  78 int rs400_gart_init(struct radeon_device *rdev)
  79 {
  80         int r;
  81
  82         if (rdev->gart.ptr) {
  83                 DRM_ERROR("RS400 GART already initialized\n");
  84                 return 0;
  85         }
  86         /* Check gart size */
  87         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  88         case 32:
  89         case 64:
  90         case 128:
  91         case 256:
  92         case 512:
  93         case 1024:
  94         case 2048:
  95                 break;
  96         default:
  97                 return -EINVAL;
  98         }
  99         /* Initialize common gart structure */
 100         r = radeon_gart_init(rdev);
 101         if (r)
 102                 return r;
 103         if (rs400_debugfs_pcie_gart_info_init(rdev))
 104                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
 105         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 106         return radeon_gart_table_ram_alloc(rdev);
 107 }
 108
 109 int rs400_gart_enable(struct radeon_device *rdev)
 110 {
 111         uint32_t size_reg;
 112         uint32_t tmp;
 113
 114         radeon_gart_restore(rdev);
 115         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 116         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 117         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 118         /* Check gart size */
 119         switch(rdev->mc.gtt_size / (1024 * 1024)) {
 120         case 32:
 121                 size_reg = RS480_VA_SIZE_32MB;
 122                 break;
 123         case 64:
 124                 size_reg = RS480_VA_SIZE_64MB;
 125                 break;
 126         case 128:
 127                 size_reg = RS480_VA_SIZE_128MB;
 128                 break;
 129         case 256:
 130                 size_reg = RS480_VA_SIZE_256MB;
 131                 break;
 132         case 512:
 133                 size_reg = RS480_VA_SIZE_512MB;
 134                 break;
 135         case 1024:
 136                 size_reg = RS480_VA_SIZE_1GB;
 137                 break;
 138         case 2048:
 139                 size_reg = RS480_VA_SIZE_2GB;
 140                 break;
 141         default:
 142                 return -EINVAL;
 143         }
 144         /* It should be fine to program it to max value */
 145         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 146                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
 147                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
 148         } else {
 149                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
 150                 WREG32(RS480_AGP_BASE_2, 0);
 151         }
 152         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
 153         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
 154         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 155                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
 156                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 157                 WREG32(RADEON_BUS_CNTL, tmp);
 158         } else {
 159                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
 160                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 161                 WREG32(RADEON_BUS_CNTL, tmp);
 162         }
 163         /* Table should be in 32bits address space so ignore bits above. */
 164         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
 165         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
 166
 167         WREG32_MC(RS480_GART_BASE, tmp);
 168         /* TODO: more tweaking here */
 169         WREG32_MC(RS480_GART_FEATURE_ID,
 170                   (RS480_TLB_ENABLE |
 171                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
 172         /* Disable snooping */
 173         WREG32_MC(RS480_AGP_MODE_CNTL,
 174                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
 175         /* Disable AGP mode */
 176         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
 177          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
 178         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
 179                 WREG32_MC(RS480_MC_MISC_CNTL,
 180                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
 181         } else {
 182                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 183         }
 184         /* Enable gart */
 185         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
 186         rs400_gart_tlb_flush(rdev);
 187         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 188                  (unsigned)(rdev->mc.gtt_size >> 20),
 189                  (unsigned long long)rdev->gart.table_addr);
 190         rdev->gart.ready = true;
 191         return 0;
 192 }
 193
 194 void rs400_gart_disable(struct radeon_device *rdev)
 195 {
 196         uint32_t tmp;
 197
 198         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 199         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
 200         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
 201         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 202 }
 203
 204 void rs400_gart_fini(struct radeon_device *rdev)
 205 {
 206         radeon_gart_fini(rdev);
 207         rs400_gart_disable(rdev);
 208         radeon_gart_table_ram_free(rdev);
 209 }
 210
 211 #define RS400_PTE_WRITEABLE (1 << 2)
 212 #define RS400_PTE_READABLE  (1 << 3)
 213
 214 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 215 {
 216         uint32_t entry;
 217         u32 *gtt = rdev->gart.ptr;
 218
 219         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 220                 return -EINVAL;
 221         }
 222
 223         entry = (lower_32_bits(addr) & ~PAGE_MASK) |
 224                 ((upper_32_bits(addr) & 0xff) << 4) |
 225                 RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
 226         entry = cpu_to_le32(entry);
 227         gtt[i] = entry;
 228         return 0;
 229 }
 230
 231 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
 232 {
 233         unsigned i;
 234         uint32_t tmp;
 235
 236         for (i = 0; i < rdev->usec_timeout; i++) {
 237                 /* read MC_STATUS */
 238                 tmp = RREG32(RADEON_MC_STATUS);
 239                 if (tmp & RADEON_MC_IDLE) {
 240                         return 0;
 241                 }
 242                 DRM_UDELAY(1);
 243         }
 244         return -1;
 245 }
 246
 247 static void rs400_gpu_init(struct radeon_device *rdev)
 248 {
 249         /* FIXME: is this correct ? */
 250         r420_pipes_init(rdev);
 251         if (rs400_mc_wait_for_idle(rdev)) {
 252                 DRM_ERROR("rs400: Failed to wait MC idle while "
 253                        "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
 254         }
 255 }
 256
 257 static void rs400_mc_init(struct radeon_device *rdev)
 258 {
 259         u64 base;
 260
 261         rs400_gart_adjust_size(rdev);
 262         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
 263         /* DDR for all card after R300 & IGP */
 264         rdev->mc.vram_is_ddr = true;
 265         rdev->mc.vram_width = 128;
 266         r100_vram_init_sizes(rdev);
 267         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 268         radeon_vram_location(rdev, &rdev->mc, base);
 269         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
 270         radeon_gtt_location(rdev, &rdev->mc);
 271         radeon_update_bandwidth_info(rdev);
 272 }
 273
 274 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 275 {
 276         uint32_t r;
 277
 278         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
 279         r = RREG32(RS480_NB_MC_DATA);
 280         WREG32(RS480_NB_MC_INDEX, 0xff);
 281         return r;
 282 }
 283
 284 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 285 {
 286         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
 287         WREG32(RS480_NB_MC_DATA, (v));
 288         WREG32(RS480_NB_MC_INDEX, 0xff);
 289 }
 290
 291 #if defined(CONFIG_DEBUG_FS)
 292 static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
 293 {
 294         struct drm_info_node *node = (struct drm_info_node *) m->private;
 295         struct drm_device *dev = node->minor->dev;
 296         struct radeon_device *rdev = dev->dev_private;
 297         uint32_t tmp;
 298
 299         tmp = RREG32(RADEON_HOST_PATH_CNTL);
 300         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
 301         tmp = RREG32(RADEON_BUS_CNTL);
 302         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
 303         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
 304         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
 305         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
 306                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
 307                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
 308                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
 309                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
 310                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
 311                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
 312                 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
 313                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
 314                 tmp = RREG32(RS690_HDP_FB_LOCATION);
 315                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
 316         } else {
 317                 tmp = RREG32(RADEON_AGP_BASE);
 318                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
 319                 tmp = RREG32(RS480_AGP_BASE_2);
 320                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
 321                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
 322                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
 323         }
 324         tmp = RREG32_MC(RS480_GART_BASE);
 325         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
 326         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
 327         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
 328         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
 329         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
 330         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
 331         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
 332         tmp = RREG32_MC(0x5F);
 333         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
 334         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
 335         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
 336         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
 337         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
 338         tmp = RREG32_MC(0x3B);
 339         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
 340         tmp = RREG32_MC(0x3C);
 341         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
 342         tmp = RREG32_MC(0x30);
 343         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
 344         tmp = RREG32_MC(0x31);
 345         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
 346         tmp = RREG32_MC(0x32);
 347         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
 348         tmp = RREG32_MC(0x33);
 349         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
 350         tmp = RREG32_MC(0x34);
 351         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
 352         tmp = RREG32_MC(0x35);
 353         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
 354         tmp = RREG32_MC(0x36);
 355         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
 356         tmp = RREG32_MC(0x37);
 357         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
 358         return 0;
 359 }
 360
 361 static struct drm_info_list rs400_gart_info_list[] = {
 362         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
 363 };
 364 #endif
 365
 366 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 367 {
 368 #if defined(CONFIG_DEBUG_FS)
 369         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
 370 #else
 371         return 0;
 372 #endif
 373 }
 374
 375 static void rs400_mc_program(struct radeon_device *rdev)
 376 {
 377         struct r100_mc_save save;
 378
 379         /* Stops all mc clients */
 380         r100_mc_stop(rdev, &save);
 381
 382         /* Wait for mc idle */
 383         if (rs400_mc_wait_for_idle(rdev))
 384                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
 385         WREG32(R_000148_MC_FB_LOCATION,
 386                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
 387                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
 388
 389         r100_mc_resume(rdev, &save);
 390 }
 391
 392 static int rs400_startup(struct radeon_device *rdev)
 393 {
 394         int r;
 395
 396         r100_set_common_regs(rdev);
 397
 398         rs400_mc_program(rdev);
 399         /* Resume clock */
 400         r300_clock_startup(rdev);
 401         /* Initialize GPU configuration (# pipes, ...) */
 402         rs400_gpu_init(rdev);
 403         r100_enable_bm(rdev);
 404         /* Initialize GART (initialize after TTM so we can allocate
 405          * memory through TTM but finalize after TTM) */
 406         r = rs400_gart_enable(rdev);
 407         if (r)
 408                 return r;
 409
 410         /* allocate wb buffer */
 411         r = radeon_wb_init(rdev);
 412         if (r)
 413                 return r;
 414
 415         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 416         if (r) {
 417                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 418                 return r;
 419         }
 420
 421         /* Enable IRQ */
 422         r100_irq_set(rdev);
 423         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 424         /* 1M ring buffer */
 425         r = r100_cp_init(rdev, 1024 * 1024);
 426         if (r) {
 427                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 428                 return r;
 429         }
 430
 431         r = radeon_ib_pool_init(rdev);
 432         if (r) {
 433                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 434                 return r;
 435         }
 436
 437         return 0;
 438 }
 439
 440 int rs400_resume(struct radeon_device *rdev)
 441 {
 442         int r;
 443
 444         /* Make sur GART are not working */
 445         rs400_gart_disable(rdev);
 446         /* Resume clock before doing reset */
 447         r300_clock_startup(rdev);
 448         /* setup MC before calling post tables */
 449         rs400_mc_program(rdev);
 450         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 451         if (radeon_asic_reset(rdev)) {
 452                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 453                         RREG32(R_000E40_RBBM_STATUS),
 454                         RREG32(R_0007C0_CP_STAT));
 455         }
 456         /* post */
 457         radeon_combios_asic_init(rdev->ddev);
 458         /* Resume clock after posting */
 459         r300_clock_startup(rdev);
 460         /* Initialize surface registers */
 461         radeon_surface_init(rdev);
 462
 463         rdev->accel_working = true;
 464         r = rs400_startup(rdev);
 465         if (r) {
 466                 rdev->accel_working = false;
 467         }
 468         return r;
 469 }
 470
 471 int rs400_suspend(struct radeon_device *rdev)
 472 {
 473         r100_cp_disable(rdev);
 474         radeon_wb_disable(rdev);
 475         r100_irq_disable(rdev);
 476         rs400_gart_disable(rdev);
 477         return 0;
 478 }
 479
 480 void rs400_fini(struct radeon_device *rdev)
 481 {
 482         r100_cp_fini(rdev);
 483         radeon_wb_fini(rdev);
 484         radeon_ib_pool_fini(rdev);
 485         radeon_gem_fini(rdev);
 486         rs400_gart_fini(rdev);
 487         radeon_irq_kms_fini(rdev);
 488         radeon_fence_driver_fini(rdev);
 489         radeon_bo_fini(rdev);
 490         radeon_atombios_fini(rdev);
 491         free(rdev->bios, DRM_MEM_DRIVER);
 492         rdev->bios = NULL;
 493 }
 494
 495 int rs400_init(struct radeon_device *rdev)
 496 {
 497         int r;
 498
 499         /* Disable VGA */
 500         r100_vga_render_disable(rdev);
 501         /* Initialize scratch registers */
 502         radeon_scratch_init(rdev);
 503         /* Initialize surface registers */
 504         radeon_surface_init(rdev);
 505         /* TODO: disable VGA need to use VGA request */
 506         /* restore some register to sane defaults */
 507         r100_restore_sanity(rdev);
 508         /* BIOS*/
 509         if (!radeon_get_bios(rdev)) {
 510                 if (ASIC_IS_AVIVO(rdev))
 511                         return -EINVAL;
 512         }
 513         if (rdev->is_atom_bios) {
 514                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
 515                 return -EINVAL;
 516         } else {
 517                 r = radeon_combios_init(rdev);
 518                 if (r)
 519                         return r;
 520         }
 521         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 522         if (radeon_asic_reset(rdev)) {
 523                 dev_warn(rdev->dev,
 524                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 525                         RREG32(R_000E40_RBBM_STATUS),
 526                         RREG32(R_0007C0_CP_STAT));
 527         }
 528         /* check if cards are posted or not */
 529         if (radeon_boot_test_post_card(rdev) == false)
 530                 return -EINVAL;
 531
 532         /* Initialize clocks */
 533         radeon_get_clock_info(rdev->ddev);
 534         /* initialize memory controller */
 535         rs400_mc_init(rdev);
 536         /* Fence driver */
 537         r = radeon_fence_driver_init(rdev);
 538         if (r)
 539                 return r;
 540         r = radeon_irq_kms_init(rdev);
 541         if (r)
 542                 return r;
 543         /* Memory manager */
 544         r = radeon_bo_init(rdev);
 545         if (r)
 546                 return r;
 547         r = rs400_gart_init(rdev);
 548         if (r)
 549                 return r;
 550         r300_set_reg_safe(rdev);
 551
 552         rdev->accel_working = true;
 553         r = rs400_startup(rdev);
 554         if (r) {
 555                 /* Somethings want wront with the accel init stop accel */
 556                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 557                 r100_cp_fini(rdev);
 558                 radeon_wb_fini(rdev);
 559                 radeon_ib_pool_fini(rdev);
 560                 rs400_gart_fini(rdev);
 561                 radeon_irq_kms_fini(rdev);
 562                 rdev->accel_working = false;
 563         }
 564         return 0;
 565 }