sys/dev/drm2/radeon/rv515.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <sys/cdefs.h>
  30 __FBSDID("$FreeBSD$");
  31
  32 #include <dev/drm2/drmP.h>
  33 #include "rv515d.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "atom.h"
  37 #include "rv515_reg_safe.h"
  38
  39 /* This files gather functions specifics to: rv515 */
  40 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  41 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  42 static void rv515_gpu_init(struct radeon_device *rdev);
  43 #ifdef FREEBSD_WIP /* FreeBSD: to please GCC 4.2. */
  44 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  45 #endif
  46
  47 static const u32 crtc_offsets[2] =
  48 {
  49         0,
  50         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  51 };
  52
  53 void rv515_debugfs(struct radeon_device *rdev)
  54 {
  55         if (r100_debugfs_rbbm_init(rdev)) {
  56                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  57         }
  58         if (rv515_debugfs_pipes_info_init(rdev)) {
  59                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  60         }
  61         if (rv515_debugfs_ga_info_init(rdev)) {
  62                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  63         }
  64 }
  65
  66 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  67 {
  68         int r;
  69
  70         r = radeon_ring_lock(rdev, ring, 64);
  71         if (r) {
  72                 return;
  73         }
  74         radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
  75         radeon_ring_write(ring,
  76                           ISYNC_ANY2D_IDLE3D |
  77                           ISYNC_ANY3D_IDLE2D |
  78                           ISYNC_WAIT_IDLEGUI |
  79                           ISYNC_CPSCRATCH_IDLEGUI);
  80         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  81         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  82         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  83         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  84         radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
  85         radeon_ring_write(ring, 0);
  86         radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
  87         radeon_ring_write(ring, 0);
  88         radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
  89         radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
  90         radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
  91         radeon_ring_write(ring, 0);
  92         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
  93         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
  94         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
  95         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
  96         radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
  97         radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
  98         radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
  99         radeon_ring_write(ring, 0);
 100         radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
 101         radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
 102         radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
 103         radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
 104         radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
 105         radeon_ring_write(ring,
 106                           ((6 << MS_X0_SHIFT) |
 107                            (6 << MS_Y0_SHIFT) |
 108                            (6 << MS_X1_SHIFT) |
 109                            (6 << MS_Y1_SHIFT) |
 110                            (6 << MS_X2_SHIFT) |
 111                            (6 << MS_Y2_SHIFT) |
 112                            (6 << MSBD0_Y_SHIFT) |
 113                            (6 << MSBD0_X_SHIFT)));
 114         radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
 115         radeon_ring_write(ring,
 116                           ((6 << MS_X3_SHIFT) |
 117                            (6 << MS_Y3_SHIFT) |
 118                            (6 << MS_X4_SHIFT) |
 119                            (6 << MS_Y4_SHIFT) |
 120                            (6 << MS_X5_SHIFT) |
 121                            (6 << MS_Y5_SHIFT) |
 122                            (6 << MSBD1_SHIFT)));
 123         radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
 124         radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
 125         radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
 126         radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
 127         radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
 128         radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
 129         radeon_ring_write(ring, PACKET0(0x20C8, 0));
 130         radeon_ring_write(ring, 0);
 131         radeon_ring_unlock_commit(rdev, ring);
 132 }
 133
 134 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
 135 {
 136         unsigned i;
 137         uint32_t tmp;
 138
 139         for (i = 0; i < rdev->usec_timeout; i++) {
 140                 /* read MC_STATUS */
 141                 tmp = RREG32_MC(MC_STATUS);
 142                 if (tmp & MC_STATUS_IDLE) {
 143                         return 0;
 144                 }
 145                 DRM_UDELAY(1);
 146         }
 147         return -1;
 148 }
 149
 150 void rv515_vga_render_disable(struct radeon_device *rdev)
 151 {
 152         WREG32(R_000300_VGA_RENDER_CONTROL,
 153                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 154 }
 155
 156 static void rv515_gpu_init(struct radeon_device *rdev)
 157 {
 158         unsigned pipe_select_current, gb_pipe_select, tmp;
 159
 160         if (r100_gui_wait_for_idle(rdev)) {
 161                 DRM_ERROR("Failed to wait GUI idle while "
 162                        "resetting GPU. Bad things might happen.\n");
 163         }
 164         rv515_vga_render_disable(rdev);
 165         r420_pipes_init(rdev);
 166         gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
 167         tmp = RREG32(R300_DST_PIPE_CONFIG);
 168         pipe_select_current = (tmp >> 2) & 3;
 169         tmp = (1 << pipe_select_current) |
 170               (((gb_pipe_select >> 8) & 0xF) << 4);
 171         WREG32_PLL(0x000D, tmp);
 172         if (r100_gui_wait_for_idle(rdev)) {
 173                 DRM_ERROR("Failed to wait GUI idle while "
 174                        "resetting GPU. Bad things might happen.\n");
 175         }
 176         if (rv515_mc_wait_for_idle(rdev)) {
 177                 DRM_ERROR("Failed to wait MC idle while "
 178                        "programming pipes. Bad things might happen.\n");
 179         }
 180 }
 181
 182 static void rv515_vram_get_type(struct radeon_device *rdev)
 183 {
 184         uint32_t tmp;
 185
 186         rdev->mc.vram_width = 128;
 187         rdev->mc.vram_is_ddr = true;
 188         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
 189         switch (tmp) {
 190         case 0:
 191                 rdev->mc.vram_width = 64;
 192                 break;
 193         case 1:
 194                 rdev->mc.vram_width = 128;
 195                 break;
 196         default:
 197                 rdev->mc.vram_width = 128;
 198                 break;
 199         }
 200 }
 201
 202 static void rv515_mc_init(struct radeon_device *rdev)
 203 {
 204
 205         rv515_vram_get_type(rdev);
 206         r100_vram_init_sizes(rdev);
 207         radeon_vram_location(rdev, &rdev->mc, 0);
 208         rdev->mc.gtt_base_align = 0;
 209         if (!(rdev->flags & RADEON_IS_AGP))
 210                 radeon_gtt_location(rdev, &rdev->mc);
 211         radeon_update_bandwidth_info(rdev);
 212 }
 213
 214 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
 215 {
 216         uint32_t r;
 217
 218         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
 219         r = RREG32(MC_IND_DATA);
 220         WREG32(MC_IND_INDEX, 0);
 221         return r;
 222 }
 223
 224 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 225 {
 226         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
 227         WREG32(MC_IND_DATA, (v));
 228         WREG32(MC_IND_INDEX, 0);
 229 }
 230
 231 #if defined(CONFIG_DEBUG_FS)
 232 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
 233 {
 234         struct drm_info_node *node = (struct drm_info_node *) m->private;
 235         struct drm_device *dev = node->minor->dev;
 236         struct radeon_device *rdev = dev->dev_private;
 237         uint32_t tmp;
 238
 239         tmp = RREG32(GB_PIPE_SELECT);
 240         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
 241         tmp = RREG32(SU_REG_DEST);
 242         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
 243         tmp = RREG32(GB_TILE_CONFIG);
 244         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
 245         tmp = RREG32(DST_PIPE_CONFIG);
 246         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
 247         return 0;
 248 }
 249
 250 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
 251 {
 252         struct drm_info_node *node = (struct drm_info_node *) m->private;
 253         struct drm_device *dev = node->minor->dev;
 254         struct radeon_device *rdev = dev->dev_private;
 255         uint32_t tmp;
 256
 257         tmp = RREG32(0x2140);
 258         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
 259         radeon_asic_reset(rdev);
 260         tmp = RREG32(0x425C);
 261         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
 262         return 0;
 263 }
 264
 265 static struct drm_info_list rv515_pipes_info_list[] = {
 266         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
 267 };
 268
 269 static struct drm_info_list rv515_ga_info_list[] = {
 270         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
 271 };
 272 #endif
 273
 274 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
 275 {
 276 #if defined(CONFIG_DEBUG_FS)
 277         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
 278 #else
 279         return 0;
 280 #endif
 281 }
 282
 283 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
 284 {
 285 #if defined(CONFIG_DEBUG_FS)
 286         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
 287 #else
 288         return 0;
 289 #endif
 290 }
 291
 292 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
 293 {
 294         u32 crtc_enabled, tmp, frame_count, blackout;
 295         int i, j;
 296
 297         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
 298         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
 299
 300         /* disable VGA render */
 301         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
 302         /* blank the display controllers */
 303         for (i = 0; i < rdev->num_crtc; i++) {
 304                 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
 305                 if (crtc_enabled) {
 306                         save->crtc_enabled[i] = true;
 307                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 308                         if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
 309                                 radeon_wait_for_vblank(rdev, i);
 310                                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 311                                 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 312                                 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 313                                 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 314                         }
 315                         /* wait for the next frame */
 316                         frame_count = radeon_get_vblank_counter(rdev, i);
 317                         for (j = 0; j < rdev->usec_timeout; j++) {
 318                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
 319                                         break;
 320                                 udelay(1);
 321                         }
 322
 323                         /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
 324                         WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
 325                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 326                         tmp &= ~AVIVO_CRTC_EN;
 327                         WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 328                         WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
 329                         save->crtc_enabled[i] = false;
 330                         /* ***** */
 331                 } else {
 332                         save->crtc_enabled[i] = false;
 333                 }
 334         }
 335
 336         radeon_mc_wait_for_idle(rdev);
 337
 338         if (rdev->family >= CHIP_R600) {
 339                 if (rdev->family >= CHIP_RV770)
 340                         blackout = RREG32(R700_MC_CITF_CNTL);
 341                 else
 342                         blackout = RREG32(R600_CITF_CNTL);
 343                 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
 344                         /* Block CPU access */
 345                         WREG32(R600_BIF_FB_EN, 0);
 346                         /* blackout the MC */
 347                         blackout |= R600_BLACKOUT_MASK;
 348                         if (rdev->family >= CHIP_RV770)
 349                                 WREG32(R700_MC_CITF_CNTL, blackout);
 350                         else
 351                                 WREG32(R600_CITF_CNTL, blackout);
 352                 }
 353         }
 354         /* wait for the MC to settle */
 355         udelay(100);
 356
 357         /* lock double buffered regs */
 358         for (i = 0; i < rdev->num_crtc; i++) {
 359                 if (save->crtc_enabled[i]) {
 360                         tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 361                         if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
 362                                 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 363                                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
 364                         }
 365                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 366                         if (!(tmp & 1)) {
 367                                 tmp |= 1;
 368                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 369                         }
 370                 }
 371         }
 372 }
 373
 374 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
 375 {
 376         u32 tmp, frame_count;
 377         int i, j;
 378
 379         /* update crtc base addresses */
 380         for (i = 0; i < rdev->num_crtc; i++) {
 381                 if (rdev->family >= CHIP_RV770) {
 382                         if (i == 0) {
 383                                 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
 384                                        upper_32_bits(rdev->mc.vram_start));
 385                                 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
 386                                        upper_32_bits(rdev->mc.vram_start));
 387                         } else {
 388                                 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
 389                                        upper_32_bits(rdev->mc.vram_start));
 390                                 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
 391                                        upper_32_bits(rdev->mc.vram_start));
 392                         }
 393                 }
 394                 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
 395                        (u32)rdev->mc.vram_start);
 396                 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
 397                        (u32)rdev->mc.vram_start);
 398         }
 399         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 400
 401         /* unlock regs and wait for update */
 402         for (i = 0; i < rdev->num_crtc; i++) {
 403                 if (save->crtc_enabled[i]) {
 404                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
 405                         if ((tmp & 0x3) != 0) {
 406                                 tmp &= ~0x3;
 407                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
 408                         }
 409                         tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 410                         if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
 411                                 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 412                                 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
 413                         }
 414                         tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
 415                         if (tmp & 1) {
 416                                 tmp &= ~1;
 417                                 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
 418                         }
 419                         for (j = 0; j < rdev->usec_timeout; j++) {
 420                                 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
 421                                 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
 422                                         break;
 423                                 udelay(1);
 424                         }
 425                 }
 426         }
 427
 428         if (rdev->family >= CHIP_R600) {
 429                 /* unblackout the MC */
 430                 if (rdev->family >= CHIP_RV770)
 431                         tmp = RREG32(R700_MC_CITF_CNTL);
 432                 else
 433                         tmp = RREG32(R600_CITF_CNTL);
 434                 tmp &= ~R600_BLACKOUT_MASK;
 435                 if (rdev->family >= CHIP_RV770)
 436                         WREG32(R700_MC_CITF_CNTL, tmp);
 437                 else
 438                         WREG32(R600_CITF_CNTL, tmp);
 439                 /* allow CPU access */
 440                 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
 441         }
 442
 443         for (i = 0; i < rdev->num_crtc; i++) {
 444                 if (save->crtc_enabled[i]) {
 445                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
 446                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
 447                         WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
 448                         /* wait for the next frame */
 449                         frame_count = radeon_get_vblank_counter(rdev, i);
 450                         for (j = 0; j < rdev->usec_timeout; j++) {
 451                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
 452                                         break;
 453                                 udelay(1);
 454                         }
 455                 }
 456         }
 457         /* Unlock vga access */
 458         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
 459         mdelay(1);
 460         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
 461 }
 462
 463 static void rv515_mc_program(struct radeon_device *rdev)
 464 {
 465         struct rv515_mc_save save;
 466
 467         /* Stops all mc clients */
 468         rv515_mc_stop(rdev, &save);
 469
 470         /* Wait for mc idle */
 471         if (rv515_mc_wait_for_idle(rdev))
 472                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
 473         /* Write VRAM size in case we are limiting it */
 474         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
 475         /* Program MC, should be a 32bits limited address space */
 476         WREG32_MC(R_000001_MC_FB_LOCATION,
 477                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
 478                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
 479         WREG32(R_000134_HDP_FB_LOCATION,
 480                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
 481         if (rdev->flags & RADEON_IS_AGP) {
 482                 WREG32_MC(R_000002_MC_AGP_LOCATION,
 483                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
 484                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
 485                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
 486                 WREG32_MC(R_000004_MC_AGP_BASE_2,
 487                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
 488         } else {
 489                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
 490                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
 491                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
 492         }
 493
 494         rv515_mc_resume(rdev, &save);
 495 }
 496
 497 void rv515_clock_startup(struct radeon_device *rdev)
 498 {
 499         if (radeon_dynclks != -1 && radeon_dynclks)
 500                 radeon_atom_set_clock_gating(rdev, 1);
 501         /* We need to force on some of the block */
 502         WREG32_PLL(R_00000F_CP_DYN_CNTL,
 503                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
 504         WREG32_PLL(R_000011_E2_DYN_CNTL,
 505                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
 506         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
 507                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
 508 }
 509
 510 static int rv515_startup(struct radeon_device *rdev)
 511 {
 512         int r;
 513
 514         rv515_mc_program(rdev);
 515         /* Resume clock */
 516         rv515_clock_startup(rdev);
 517         /* Initialize GPU configuration (# pipes, ...) */
 518         rv515_gpu_init(rdev);
 519         /* Initialize GART (initialize after TTM so we can allocate
 520          * memory through TTM but finalize after TTM) */
 521         if (rdev->flags & RADEON_IS_PCIE) {
 522                 r = rv370_pcie_gart_enable(rdev);
 523                 if (r)
 524                         return r;
 525         }
 526
 527         /* allocate wb buffer */
 528         r = radeon_wb_init(rdev);
 529         if (r)
 530                 return r;
 531
 532         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
 533         if (r) {
 534                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
 535                 return r;
 536         }
 537
 538         /* Enable IRQ */
 539         rs600_irq_set(rdev);
 540         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
 541         /* 1M ring buffer */
 542         r = r100_cp_init(rdev, 1024 * 1024);
 543         if (r) {
 544                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
 545                 return r;
 546         }
 547
 548         r = radeon_ib_pool_init(rdev);
 549         if (r) {
 550                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
 551                 return r;
 552         }
 553
 554         return 0;
 555 }
 556
 557 int rv515_resume(struct radeon_device *rdev)
 558 {
 559         int r;
 560
 561         /* Make sur GART are not working */
 562         if (rdev->flags & RADEON_IS_PCIE)
 563                 rv370_pcie_gart_disable(rdev);
 564         /* Resume clock before doing reset */
 565         rv515_clock_startup(rdev);
 566         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 567         if (radeon_asic_reset(rdev)) {
 568                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 569                         RREG32(R_000E40_RBBM_STATUS),
 570                         RREG32(R_0007C0_CP_STAT));
 571         }
 572         /* post */
 573         atom_asic_init(rdev->mode_info.atom_context);
 574         /* Resume clock after posting */
 575         rv515_clock_startup(rdev);
 576         /* Initialize surface registers */
 577         radeon_surface_init(rdev);
 578
 579         rdev->accel_working = true;
 580         r =  rv515_startup(rdev);
 581         if (r) {
 582                 rdev->accel_working = false;
 583         }
 584         return r;
 585 }
 586
 587 int rv515_suspend(struct radeon_device *rdev)
 588 {
 589         r100_cp_disable(rdev);
 590         radeon_wb_disable(rdev);
 591         rs600_irq_disable(rdev);
 592         if (rdev->flags & RADEON_IS_PCIE)
 593                 rv370_pcie_gart_disable(rdev);
 594         return 0;
 595 }
 596
 597 void rv515_set_safe_registers(struct radeon_device *rdev)
 598 {
 599         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
 600         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
 601 }
 602
 603 void rv515_fini(struct radeon_device *rdev)
 604 {
 605         r100_cp_fini(rdev);
 606         radeon_wb_fini(rdev);
 607         radeon_ib_pool_fini(rdev);
 608         radeon_gem_fini(rdev);
 609         rv370_pcie_gart_fini(rdev);
 610         radeon_agp_fini(rdev);
 611         radeon_irq_kms_fini(rdev);
 612         radeon_fence_driver_fini(rdev);
 613         radeon_bo_fini(rdev);
 614         radeon_atombios_fini(rdev);
 615         free(rdev->bios, DRM_MEM_DRIVER);
 616         rdev->bios = NULL;
 617 }
 618
 619 int rv515_init(struct radeon_device *rdev)
 620 {
 621         int r;
 622
 623         /* Initialize scratch registers */
 624         radeon_scratch_init(rdev);
 625         /* Initialize surface registers */
 626         radeon_surface_init(rdev);
 627         /* TODO: disable VGA need to use VGA request */
 628         /* restore some register to sane defaults */
 629         r100_restore_sanity(rdev);
 630         /* BIOS*/
 631         if (!radeon_get_bios(rdev)) {
 632                 if (ASIC_IS_AVIVO(rdev))
 633                         return -EINVAL;
 634         }
 635         if (rdev->is_atom_bios) {
 636                 r = radeon_atombios_init(rdev);
 637                 if (r)
 638                         return r;
 639         } else {
 640                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
 641                 return -EINVAL;
 642         }
 643         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
 644         if (radeon_asic_reset(rdev)) {
 645                 dev_warn(rdev->dev,
 646                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
 647                         RREG32(R_000E40_RBBM_STATUS),
 648                         RREG32(R_0007C0_CP_STAT));
 649         }
 650         /* check if cards are posted or not */
 651         if (radeon_boot_test_post_card(rdev) == false)
 652                 return -EINVAL;
 653         /* Initialize clocks */
 654         radeon_get_clock_info(rdev->ddev);
 655         /* initialize AGP */
 656         if (rdev->flags & RADEON_IS_AGP) {
 657                 r = radeon_agp_init(rdev);
 658                 if (r) {
 659                         radeon_agp_disable(rdev);
 660                 }
 661         }
 662         /* initialize memory controller */
 663         rv515_mc_init(rdev);
 664         rv515_debugfs(rdev);
 665         /* Fence driver */
 666         r = radeon_fence_driver_init(rdev);
 667         if (r)
 668                 return r;
 669         r = radeon_irq_kms_init(rdev);
 670         if (r)
 671                 return r;
 672         /* Memory manager */
 673         r = radeon_bo_init(rdev);
 674         if (r)
 675                 return r;
 676         r = rv370_pcie_gart_init(rdev);
 677         if (r)
 678                 return r;
 679         rv515_set_safe_registers(rdev);
 680
 681         rdev->accel_working = true;
 682         r = rv515_startup(rdev);
 683         if (r) {
 684                 /* Somethings want wront with the accel init stop accel */
 685                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
 686                 r100_cp_fini(rdev);
 687                 radeon_wb_fini(rdev);
 688                 radeon_ib_pool_fini(rdev);
 689                 radeon_irq_kms_fini(rdev);
 690                 rv370_pcie_gart_fini(rdev);
 691                 radeon_agp_fini(rdev);
 692                 rdev->accel_working = false;
 693         }
 694         return 0;
 695 }
 696
 697 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
 698 {
 699         int index_reg = 0x6578 + crtc->crtc_offset;
 700         int data_reg = 0x657c + crtc->crtc_offset;
 701
 702         WREG32(0x659C + crtc->crtc_offset, 0x0);
 703         WREG32(0x6594 + crtc->crtc_offset, 0x705);
 704         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
 705         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
 706         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
 707         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
 708         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
 709         WREG32(index_reg, 0x0);
 710         WREG32(data_reg, 0x841880A8);
 711         WREG32(index_reg, 0x1);
 712         WREG32(data_reg, 0x84208680);
 713         WREG32(index_reg, 0x2);
 714         WREG32(data_reg, 0xBFF880B0);
 715         WREG32(index_reg, 0x100);
 716         WREG32(data_reg, 0x83D88088);
 717         WREG32(index_reg, 0x101);
 718         WREG32(data_reg, 0x84608680);
 719         WREG32(index_reg, 0x102);
 720         WREG32(data_reg, 0xBFF080D0);
 721         WREG32(index_reg, 0x200);
 722         WREG32(data_reg, 0x83988068);
 723         WREG32(index_reg, 0x201);
 724         WREG32(data_reg, 0x84A08680);
 725         WREG32(index_reg, 0x202);
 726         WREG32(data_reg, 0xBFF080F8);
 727         WREG32(index_reg, 0x300);
 728         WREG32(data_reg, 0x83588058);
 729         WREG32(index_reg, 0x301);
 730         WREG32(data_reg, 0x84E08660);
 731         WREG32(index_reg, 0x302);
 732         WREG32(data_reg, 0xBFF88120);
 733         WREG32(index_reg, 0x400);
 734         WREG32(data_reg, 0x83188040);
 735         WREG32(index_reg, 0x401);
 736         WREG32(data_reg, 0x85008660);
 737         WREG32(index_reg, 0x402);
 738         WREG32(data_reg, 0xBFF88150);
 739         WREG32(index_reg, 0x500);
 740         WREG32(data_reg, 0x82D88030);
 741         WREG32(index_reg, 0x501);
 742         WREG32(data_reg, 0x85408640);
 743         WREG32(index_reg, 0x502);
 744         WREG32(data_reg, 0xBFF88180);
 745         WREG32(index_reg, 0x600);
 746         WREG32(data_reg, 0x82A08018);
 747         WREG32(index_reg, 0x601);
 748         WREG32(data_reg, 0x85808620);
 749         WREG32(index_reg, 0x602);
 750         WREG32(data_reg, 0xBFF081B8);
 751         WREG32(index_reg, 0x700);
 752         WREG32(data_reg, 0x82608010);
 753         WREG32(index_reg, 0x701);
 754         WREG32(data_reg, 0x85A08600);
 755         WREG32(index_reg, 0x702);
 756         WREG32(data_reg, 0x800081F0);
 757         WREG32(index_reg, 0x800);
 758         WREG32(data_reg, 0x8228BFF8);
 759         WREG32(index_reg, 0x801);
 760         WREG32(data_reg, 0x85E085E0);
 761         WREG32(index_reg, 0x802);
 762         WREG32(data_reg, 0xBFF88228);
 763         WREG32(index_reg, 0x10000);
 764         WREG32(data_reg, 0x82A8BF00);
 765         WREG32(index_reg, 0x10001);
 766         WREG32(data_reg, 0x82A08CC0);
 767         WREG32(index_reg, 0x10002);
 768         WREG32(data_reg, 0x8008BEF8);
 769         WREG32(index_reg, 0x10100);
 770         WREG32(data_reg, 0x81F0BF28);
 771         WREG32(index_reg, 0x10101);
 772         WREG32(data_reg, 0x83608CA0);
 773         WREG32(index_reg, 0x10102);
 774         WREG32(data_reg, 0x8018BED0);
 775         WREG32(index_reg, 0x10200);
 776         WREG32(data_reg, 0x8148BF38);
 777         WREG32(index_reg, 0x10201);
 778         WREG32(data_reg, 0x84408C80);
 779         WREG32(index_reg, 0x10202);
 780         WREG32(data_reg, 0x8008BEB8);
 781         WREG32(index_reg, 0x10300);
 782         WREG32(data_reg, 0x80B0BF78);
 783         WREG32(index_reg, 0x10301);
 784         WREG32(data_reg, 0x85008C20);
 785         WREG32(index_reg, 0x10302);
 786         WREG32(data_reg, 0x8020BEA0);
 787         WREG32(index_reg, 0x10400);
 788         WREG32(data_reg, 0x8028BF90);
 789         WREG32(index_reg, 0x10401);
 790         WREG32(data_reg, 0x85E08BC0);
 791         WREG32(index_reg, 0x10402);
 792         WREG32(data_reg, 0x8018BE90);
 793         WREG32(index_reg, 0x10500);
 794         WREG32(data_reg, 0xBFB8BFB0);
 795         WREG32(index_reg, 0x10501);
 796         WREG32(data_reg, 0x86C08B40);
 797         WREG32(index_reg, 0x10502);
 798         WREG32(data_reg, 0x8010BE90);
 799         WREG32(index_reg, 0x10600);
 800         WREG32(data_reg, 0xBF58BFC8);
 801         WREG32(index_reg, 0x10601);
 802         WREG32(data_reg, 0x87A08AA0);
 803         WREG32(index_reg, 0x10602);
 804         WREG32(data_reg, 0x8010BE98);
 805         WREG32(index_reg, 0x10700);
 806         WREG32(data_reg, 0xBF10BFF0);
 807         WREG32(index_reg, 0x10701);
 808         WREG32(data_reg, 0x886089E0);
 809         WREG32(index_reg, 0x10702);
 810         WREG32(data_reg, 0x8018BEB0);
 811         WREG32(index_reg, 0x10800);
 812         WREG32(data_reg, 0xBED8BFE8);
 813         WREG32(index_reg, 0x10801);
 814         WREG32(data_reg, 0x89408940);
 815         WREG32(index_reg, 0x10802);
 816         WREG32(data_reg, 0xBFE8BED8);
 817         WREG32(index_reg, 0x20000);
 818         WREG32(data_reg, 0x80008000);
 819         WREG32(index_reg, 0x20001);
 820         WREG32(data_reg, 0x90008000);
 821         WREG32(index_reg, 0x20002);
 822         WREG32(data_reg, 0x80008000);
 823         WREG32(index_reg, 0x20003);
 824         WREG32(data_reg, 0x80008000);
 825         WREG32(index_reg, 0x20100);
 826         WREG32(data_reg, 0x80108000);
 827         WREG32(index_reg, 0x20101);
 828         WREG32(data_reg, 0x8FE0BF70);
 829         WREG32(index_reg, 0x20102);
 830         WREG32(data_reg, 0xBFE880C0);
 831         WREG32(index_reg, 0x20103);
 832         WREG32(data_reg, 0x80008000);
 833         WREG32(index_reg, 0x20200);
 834         WREG32(data_reg, 0x8018BFF8);
 835         WREG32(index_reg, 0x20201);
 836         WREG32(data_reg, 0x8F80BF08);
 837         WREG32(index_reg, 0x20202);
 838         WREG32(data_reg, 0xBFD081A0);
 839         WREG32(index_reg, 0x20203);
 840         WREG32(data_reg, 0xBFF88000);
 841         WREG32(index_reg, 0x20300);
 842         WREG32(data_reg, 0x80188000);
 843         WREG32(index_reg, 0x20301);
 844         WREG32(data_reg, 0x8EE0BEC0);
 845         WREG32(index_reg, 0x20302);
 846         WREG32(data_reg, 0xBFB082A0);
 847         WREG32(index_reg, 0x20303);
 848         WREG32(data_reg, 0x80008000);
 849         WREG32(index_reg, 0x20400);
 850         WREG32(data_reg, 0x80188000);
 851         WREG32(index_reg, 0x20401);
 852         WREG32(data_reg, 0x8E00BEA0);
 853         WREG32(index_reg, 0x20402);
 854         WREG32(data_reg, 0xBF8883C0);
 855         WREG32(index_reg, 0x20403);
 856         WREG32(data_reg, 0x80008000);
 857         WREG32(index_reg, 0x20500);
 858         WREG32(data_reg, 0x80188000);
 859         WREG32(index_reg, 0x20501);
 860         WREG32(data_reg, 0x8D00BE90);
 861         WREG32(index_reg, 0x20502);
 862         WREG32(data_reg, 0xBF588500);
 863         WREG32(index_reg, 0x20503);
 864         WREG32(data_reg, 0x80008008);
 865         WREG32(index_reg, 0x20600);
 866         WREG32(data_reg, 0x80188000);
 867         WREG32(index_reg, 0x20601);
 868         WREG32(data_reg, 0x8BC0BE98);
 869         WREG32(index_reg, 0x20602);
 870         WREG32(data_reg, 0xBF308660);
 871         WREG32(index_reg, 0x20603);
 872         WREG32(data_reg, 0x80008008);
 873         WREG32(index_reg, 0x20700);
 874         WREG32(data_reg, 0x80108000);
 875         WREG32(index_reg, 0x20701);
 876         WREG32(data_reg, 0x8A80BEB0);
 877         WREG32(index_reg, 0x20702);
 878         WREG32(data_reg, 0xBF0087C0);
 879         WREG32(index_reg, 0x20703);
 880         WREG32(data_reg, 0x80008008);
 881         WREG32(index_reg, 0x20800);
 882         WREG32(data_reg, 0x80108000);
 883         WREG32(index_reg, 0x20801);
 884         WREG32(data_reg, 0x8920BED0);
 885         WREG32(index_reg, 0x20802);
 886         WREG32(data_reg, 0xBED08920);
 887         WREG32(index_reg, 0x20803);
 888         WREG32(data_reg, 0x80008010);
 889         WREG32(index_reg, 0x30000);
 890         WREG32(data_reg, 0x90008000);
 891         WREG32(index_reg, 0x30001);
 892         WREG32(data_reg, 0x80008000);
 893         WREG32(index_reg, 0x30100);
 894         WREG32(data_reg, 0x8FE0BF90);
 895         WREG32(index_reg, 0x30101);
 896         WREG32(data_reg, 0xBFF880A0);
 897         WREG32(index_reg, 0x30200);
 898         WREG32(data_reg, 0x8F60BF40);
 899         WREG32(index_reg, 0x30201);
 900         WREG32(data_reg, 0xBFE88180);
 901         WREG32(index_reg, 0x30300);
 902         WREG32(data_reg, 0x8EC0BF00);
 903         WREG32(index_reg, 0x30301);
 904         WREG32(data_reg, 0xBFC88280);
 905         WREG32(index_reg, 0x30400);
 906         WREG32(data_reg, 0x8DE0BEE0);
 907         WREG32(index_reg, 0x30401);
 908         WREG32(data_reg, 0xBFA083A0);
 909         WREG32(index_reg, 0x30500);
 910         WREG32(data_reg, 0x8CE0BED0);
 911         WREG32(index_reg, 0x30501);
 912         WREG32(data_reg, 0xBF7884E0);
 913         WREG32(index_reg, 0x30600);
 914         WREG32(data_reg, 0x8BA0BED8);
 915         WREG32(index_reg, 0x30601);
 916         WREG32(data_reg, 0xBF508640);
 917         WREG32(index_reg, 0x30700);
 918         WREG32(data_reg, 0x8A60BEE8);
 919         WREG32(index_reg, 0x30701);
 920         WREG32(data_reg, 0xBF2087A0);
 921         WREG32(index_reg, 0x30800);
 922         WREG32(data_reg, 0x8900BF00);
 923         WREG32(index_reg, 0x30801);
 924         WREG32(data_reg, 0xBF008900);
 925 }
 926
 927 struct rv515_watermark {
 928         u32        lb_request_fifo_depth;
 929         fixed20_12 num_line_pair;
 930         fixed20_12 estimated_width;
 931         fixed20_12 worst_case_latency;
 932         fixed20_12 consumption_rate;
 933         fixed20_12 active_time;
 934         fixed20_12 dbpp;
 935         fixed20_12 priority_mark_max;
 936         fixed20_12 priority_mark;
 937         fixed20_12 sclk;
 938 };
 939
 940 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
 941                                   struct radeon_crtc *crtc,
 942                                   struct rv515_watermark *wm)
 943 {
 944         struct drm_display_mode *mode = &crtc->base.mode;
 945         fixed20_12 a, b, c;
 946         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
 947         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
 948
 949         if (!crtc->base.enabled) {
 950                 /* FIXME: wouldn't it better to set priority mark to maximum */
 951                 wm->lb_request_fifo_depth = 4;
 952                 return;
 953         }
 954
 955         if (crtc->vsc.full > dfixed_const(2))
 956                 wm->num_line_pair.full = dfixed_const(2);
 957         else
 958                 wm->num_line_pair.full = dfixed_const(1);
 959
 960         b.full = dfixed_const(mode->crtc_hdisplay);
 961         c.full = dfixed_const(256);
 962         a.full = dfixed_div(b, c);
 963         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
 964         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
 965         if (a.full < dfixed_const(4)) {
 966                 wm->lb_request_fifo_depth = 4;
 967         } else {
 968                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
 969         }
 970
 971         /* Determine consumption rate
 972          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
 973          *  vtaps = number of vertical taps,
 974          *  vsc = vertical scaling ratio, defined as source/destination
 975          *  hsc = horizontal scaling ration, defined as source/destination
 976          */
 977         a.full = dfixed_const(mode->clock);
 978         b.full = dfixed_const(1000);
 979         a.full = dfixed_div(a, b);
 980         pclk.full = dfixed_div(b, a);
 981         if (crtc->rmx_type != RMX_OFF) {
 982                 b.full = dfixed_const(2);
 983                 if (crtc->vsc.full > b.full)
 984                         b.full = crtc->vsc.full;
 985                 b.full = dfixed_mul(b, crtc->hsc);
 986                 c.full = dfixed_const(2);
 987                 b.full = dfixed_div(b, c);
 988                 consumption_time.full = dfixed_div(pclk, b);
 989         } else {
 990                 consumption_time.full = pclk.full;
 991         }
 992         a.full = dfixed_const(1);
 993         wm->consumption_rate.full = dfixed_div(a, consumption_time);
 994
 995
 996         /* Determine line time
 997          *  LineTime = total time for one line of displayhtotal
 998          *  LineTime = total number of horizontal pixels
 999          *  pclk = pixel clock period(ns)
1000          */
1001         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1002         line_time.full = dfixed_mul(a, pclk);
1003
1004         /* Determine active time
1005          *  ActiveTime = time of active region of display within one line,
1006          *  hactive = total number of horizontal active pixels
1007          *  htotal = total number of horizontal pixels
1008          */
1009         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1010         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1011         wm->active_time.full = dfixed_mul(line_time, b);
1012         wm->active_time.full = dfixed_div(wm->active_time, a);
1013
1014         /* Determine chunk time
1015          * ChunkTime = the time it takes the DCP to send one chunk of data
1016          * to the LB which consists of pipeline delay and inter chunk gap
1017          * sclk = system clock(Mhz)
1018          */
1019         a.full = dfixed_const(600 * 1000);
1020         chunk_time.full = dfixed_div(a, rdev->pm.sclk);
1021         read_delay_latency.full = dfixed_const(1000);
1022
1023         /* Determine the worst case latency
1024          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1025          * WorstCaseLatency = worst case time from urgent to when the MC starts
1026          *                    to return data
1027          * READ_DELAY_IDLE_MAX = constant of 1us
1028          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1029          *             which consists of pipeline delay and inter chunk gap
1030          */
1031         if (dfixed_trunc(wm->num_line_pair) > 1) {
1032                 a.full = dfixed_const(3);
1033                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1034                 wm->worst_case_latency.full += read_delay_latency.full;
1035         } else {
1036                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1037         }
1038
1039         /* Determine the tolerable latency
1040          * TolerableLatency = Any given request has only 1 line time
1041          *                    for the data to be returned
1042          * LBRequestFifoDepth = Number of chunk requests the LB can
1043          *                      put into the request FIFO for a display
1044          *  LineTime = total time for one line of display
1045          *  ChunkTime = the time it takes the DCP to send one chunk
1046          *              of data to the LB which consists of
1047          *  pipeline delay and inter chunk gap
1048          */
1049         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1050                 tolerable_latency.full = line_time.full;
1051         } else {
1052                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1053                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1054                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1055                 tolerable_latency.full = line_time.full - tolerable_latency.full;
1056         }
1057         /* We assume worst case 32bits (4 bytes) */
1058         wm->dbpp.full = dfixed_const(2 * 16);
1059
1060         /* Determine the maximum priority mark
1061          *  width = viewport width in pixels
1062          */
1063         a.full = dfixed_const(16);
1064         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1065         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1066         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1067
1068         /* Determine estimated width */
1069         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1070         estimated_width.full = dfixed_div(estimated_width, consumption_time);
1071         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1072                 wm->priority_mark.full = wm->priority_mark_max.full;
1073         } else {
1074                 a.full = dfixed_const(16);
1075                 wm->priority_mark.full = dfixed_div(estimated_width, a);
1076                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1077                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1078         }
1079 }
1080
1081 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1082 {
1083         struct drm_display_mode *mode0 = NULL;
1084         struct drm_display_mode *mode1 = NULL;
1085         struct rv515_watermark wm0;
1086         struct rv515_watermark wm1;
1087         u32 tmp;
1088         u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1089         u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1090         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1091         fixed20_12 a, b;
1092
1093         if (rdev->mode_info.crtcs[0]->base.enabled)
1094                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1095         if (rdev->mode_info.crtcs[1]->base.enabled)
1096                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1097         rs690_line_buffer_adjust(rdev, mode0, mode1);
1098
1099         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1100         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1101
1102         tmp = wm0.lb_request_fifo_depth;
1103         tmp |= wm1.lb_request_fifo_depth << 16;
1104         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1105
1106         if (mode0 && mode1) {
1107                 if (dfixed_trunc(wm0.dbpp) > 64)
1108                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1109                 else
1110                         a.full = wm0.num_line_pair.full;
1111                 if (dfixed_trunc(wm1.dbpp) > 64)
1112                         b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1113                 else
1114                         b.full = wm1.num_line_pair.full;
1115                 a.full += b.full;
1116                 fill_rate.full = dfixed_div(wm0.sclk, a);
1117                 if (wm0.consumption_rate.full > fill_rate.full) {
1118                         b.full = wm0.consumption_rate.full - fill_rate.full;
1119                         b.full = dfixed_mul(b, wm0.active_time);
1120                         a.full = dfixed_const(16);
1121                         b.full = dfixed_div(b, a);
1122                         a.full = dfixed_mul(wm0.worst_case_latency,
1123                                                 wm0.consumption_rate);
1124                         priority_mark02.full = a.full + b.full;
1125                 } else {
1126                         a.full = dfixed_mul(wm0.worst_case_latency,
1127                                                 wm0.consumption_rate);
1128                         b.full = dfixed_const(16 * 1000);
1129                         priority_mark02.full = dfixed_div(a, b);
1130                 }
1131                 if (wm1.consumption_rate.full > fill_rate.full) {
1132                         b.full = wm1.consumption_rate.full - fill_rate.full;
1133                         b.full = dfixed_mul(b, wm1.active_time);
1134                         a.full = dfixed_const(16);
1135                         b.full = dfixed_div(b, a);
1136                         a.full = dfixed_mul(wm1.worst_case_latency,
1137                                                 wm1.consumption_rate);
1138                         priority_mark12.full = a.full + b.full;
1139                 } else {
1140                         a.full = dfixed_mul(wm1.worst_case_latency,
1141                                                 wm1.consumption_rate);
1142                         b.full = dfixed_const(16 * 1000);
1143                         priority_mark12.full = dfixed_div(a, b);
1144                 }
1145                 if (wm0.priority_mark.full > priority_mark02.full)
1146                         priority_mark02.full = wm0.priority_mark.full;
1147                 if (wm0.priority_mark_max.full > priority_mark02.full)
1148                         priority_mark02.full = wm0.priority_mark_max.full;
1149                 if (wm1.priority_mark.full > priority_mark12.full)
1150                         priority_mark12.full = wm1.priority_mark.full;
1151                 if (wm1.priority_mark_max.full > priority_mark12.full)
1152                         priority_mark12.full = wm1.priority_mark_max.full;
1153                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1154                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1155                 if (rdev->disp_priority == 2) {
1156                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1157                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1158                 }
1159         } else if (mode0) {
1160                 if (dfixed_trunc(wm0.dbpp) > 64)
1161                         a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
1162                 else
1163                         a.full = wm0.num_line_pair.full;
1164                 fill_rate.full = dfixed_div(wm0.sclk, a);
1165                 if (wm0.consumption_rate.full > fill_rate.full) {
1166                         b.full = wm0.consumption_rate.full - fill_rate.full;
1167                         b.full = dfixed_mul(b, wm0.active_time);
1168                         a.full = dfixed_const(16);
1169                         b.full = dfixed_div(b, a);
1170                         a.full = dfixed_mul(wm0.worst_case_latency,
1171                                                 wm0.consumption_rate);
1172                         priority_mark02.full = a.full + b.full;
1173                 } else {
1174                         a.full = dfixed_mul(wm0.worst_case_latency,
1175                                                 wm0.consumption_rate);
1176                         b.full = dfixed_const(16);
1177                         priority_mark02.full = dfixed_div(a, b);
1178                 }
1179                 if (wm0.priority_mark.full > priority_mark02.full)
1180                         priority_mark02.full = wm0.priority_mark.full;
1181                 if (wm0.priority_mark_max.full > priority_mark02.full)
1182                         priority_mark02.full = wm0.priority_mark_max.full;
1183                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1184                 if (rdev->disp_priority == 2)
1185                         d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1186         } else if (mode1) {
1187                 if (dfixed_trunc(wm1.dbpp) > 64)
1188                         a.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
1189                 else
1190                         a.full = wm1.num_line_pair.full;
1191                 fill_rate.full = dfixed_div(wm1.sclk, a);
1192                 if (wm1.consumption_rate.full > fill_rate.full) {
1193                         b.full = wm1.consumption_rate.full - fill_rate.full;
1194                         b.full = dfixed_mul(b, wm1.active_time);
1195                         a.full = dfixed_const(16);
1196                         b.full = dfixed_div(b, a);
1197                         a.full = dfixed_mul(wm1.worst_case_latency,
1198                                                 wm1.consumption_rate);
1199                         priority_mark12.full = a.full + b.full;
1200                 } else {
1201                         a.full = dfixed_mul(wm1.worst_case_latency,
1202                                                 wm1.consumption_rate);
1203                         b.full = dfixed_const(16 * 1000);
1204                         priority_mark12.full = dfixed_div(a, b);
1205                 }
1206                 if (wm1.priority_mark.full > priority_mark12.full)
1207                         priority_mark12.full = wm1.priority_mark.full;
1208                 if (wm1.priority_mark_max.full > priority_mark12.full)
1209                         priority_mark12.full = wm1.priority_mark_max.full;
1210                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1211                 if (rdev->disp_priority == 2)
1212                         d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1213         }
1214
1215         WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1216         WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
1217         WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1218         WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
1219 }
1220
1221 void rv515_bandwidth_update(struct radeon_device *rdev)
1222 {
1223         uint32_t tmp;
1224         struct drm_display_mode *mode0 = NULL;
1225         struct drm_display_mode *mode1 = NULL;
1226
1227         radeon_update_display_priority(rdev);
1228
1229         if (rdev->mode_info.crtcs[0]->base.enabled)
1230                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1231         if (rdev->mode_info.crtcs[1]->base.enabled)
1232                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1233         /*
1234          * Set display0/1 priority up in the memory controller for
1235          * modes if the user specifies HIGH for displaypriority
1236          * option.
1237          */
1238         if ((rdev->disp_priority == 2) &&
1239             (rdev->family == CHIP_RV515)) {
1240                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1241                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1242                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1243                 if (mode1)
1244                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1245                 if (mode0)
1246                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1247                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1248         }
1249         rv515_bandwidth_avivo_update(rdev);
1250 }