sys/dev/e1000/e1000_82575.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2014, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82575EB Gigabit Network Connection
  37  * 82575EB Gigabit Backplane Connection
  38  * 82575GB Gigabit Network Connection
  39  * 82576 Gigabit Network Connection
  40  * 82576 Quad Port Gigabit Mezzanine Adapter
  41  * 82580 Gigabit Network Connection
  42  * I350 Gigabit Network Connection
  43  */
  44
  45 #include "e1000_api.h"
  46 #include "e1000_i210.h"
  47
  48 static s32  e1000_init_phy_params_82575(struct e1000_hw *hw);
  49 static s32  e1000_init_mac_params_82575(struct e1000_hw *hw);
  50 static s32  e1000_acquire_phy_82575(struct e1000_hw *hw);
  51 static void e1000_release_phy_82575(struct e1000_hw *hw);
  52 static s32  e1000_acquire_nvm_82575(struct e1000_hw *hw);
  53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
  54 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_media_swap(struct e1000_hw *hw);
  56 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
  57 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
  58                                          u16 *duplex);
  59 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
  60 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
  61                                            u16 *data);
  62 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
  63 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
  64 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
  65                                      u32 offset, u16 *data);
  66 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
  67                                       u32 offset, u16 data);
  68 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
  69                                           bool active);
  70 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
  71                                           bool active);
  72 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
  73                                           bool active);
  74 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
  75 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
  76 static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
  77 static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
  78 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
  79 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
  80                                             u32 offset, u16 data);
  81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
  82 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  83 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
  84                                                  u16 *speed, u16 *duplex);
  85 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
  86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
  87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
  88 static s32  e1000_reset_init_script_82575(struct e1000_hw *hw);
  89 static s32  e1000_read_mac_addr_82575(struct e1000_hw *hw);
  90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
  91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
  92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
  93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
  94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
  95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
  96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
  97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
  98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
  99                                                  u16 offset);
 100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
 101                                                    u16 offset);
 102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
 104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
 105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
 106
 107 static void e1000_i2c_start(struct e1000_hw *hw);
 108 static void e1000_i2c_stop(struct e1000_hw *hw);
 109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
 110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
 111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
 112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
 113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
 114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
 116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
 117 static bool e1000_get_i2c_data(u32 *i2cctl);
 118
 119 static const u16 e1000_82580_rxpbs_table[] = {
 120         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 121 #define E1000_82580_RXPBS_TABLE_SIZE \
 122         (sizeof(e1000_82580_rxpbs_table) / \
 123          sizeof(e1000_82580_rxpbs_table[0]))
 124
 125
 126 /**
 127  *  e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 128  *  @hw: pointer to the HW structure
 129  *
 130  *  Called to determine if the I2C pins are being used for I2C or as an
 131  *  external MDIO interface since the two options are mutually exclusive.
 132  **/
 133 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 134 {
 135         u32 reg = 0;
 136         bool ext_mdio = FALSE;
 137
 138         DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
 139
 140         switch (hw->mac.type) {
 141         case e1000_82575:
 142         case e1000_82576:
 143                 reg = E1000_READ_REG(hw, E1000_MDIC);
 144                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 145                 break;
 146         case e1000_82580:
 147         case e1000_i350:
 148         case e1000_i354:
 149         case e1000_i210:
 150         case e1000_i211:
 151                 reg = E1000_READ_REG(hw, E1000_MDICNFG);
 152                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 153                 break;
 154         default:
 155                 break;
 156         }
 157         return ext_mdio;
 158 }
 159
 160 /**
 161  *  e1000_init_phy_params_82575 - Init PHY func ptrs.
 162  *  @hw: pointer to the HW structure
 163  **/
 164 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
 165 {
 166         struct e1000_phy_info *phy = &hw->phy;
 167         s32 ret_val = E1000_SUCCESS;
 168         u32 ctrl_ext;
 169
 170         DEBUGFUNC("e1000_init_phy_params_82575");
 171
 172         phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
 173         phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 174
 175         if (hw->phy.media_type != e1000_media_type_copper) {
 176                 phy->type = e1000_phy_none;
 177                 goto out;
 178         }
 179
 180         phy->ops.power_up   = e1000_power_up_phy_copper;
 181         phy->ops.power_down = e1000_power_down_phy_copper_82575;
 182
 183         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 184         phy->reset_delay_us     = 100;
 185
 186         phy->ops.acquire        = e1000_acquire_phy_82575;
 187         phy->ops.check_reset_block = e1000_check_reset_block_generic;
 188         phy->ops.commit         = e1000_phy_sw_reset_generic;
 189         phy->ops.get_cfg_done   = e1000_get_cfg_done_82575;
 190         phy->ops.release        = e1000_release_phy_82575;
 191
 192         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 193
 194         if (e1000_sgmii_active_82575(hw)) {
 195                 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 196                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 197         } else {
 198                 phy->ops.reset = e1000_phy_hw_reset_generic;
 199                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 200         }
 201
 202         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 203         e1000_reset_mdicnfg_82580(hw);
 204
 205         if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
 206                 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
 207                 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 208         } else {
 209                 switch (hw->mac.type) {
 210                 case e1000_82580:
 211                 case e1000_i350:
 212                 case e1000_i354:
 213                         phy->ops.read_reg = e1000_read_phy_reg_82580;
 214                         phy->ops.write_reg = e1000_write_phy_reg_82580;
 215                         break;
 216                 case e1000_i210:
 217                 case e1000_i211:
 218                         phy->ops.read_reg = e1000_read_phy_reg_gs40g;
 219                         phy->ops.write_reg = e1000_write_phy_reg_gs40g;
 220                         break;
 221                 default:
 222                         phy->ops.read_reg = e1000_read_phy_reg_igp;
 223                         phy->ops.write_reg = e1000_write_phy_reg_igp;
 224                 }
 225         }
 226
 227         /* Set phy->phy_addr and phy->id. */
 228         ret_val = e1000_get_phy_id_82575(hw);
 229
 230         /* Verify phy id and set remaining function pointers */
 231         switch (phy->id) {
 232         case M88E1543_E_PHY_ID:
 233         case M88E1512_E_PHY_ID:
 234         case I347AT4_E_PHY_ID:
 235         case M88E1112_E_PHY_ID:
 236         case M88E1340M_E_PHY_ID:
 237         case M88E1111_I_PHY_ID:
 238                 phy->type               = e1000_phy_m88;
 239                 phy->ops.check_polarity = e1000_check_polarity_m88;
 240                 phy->ops.get_info       = e1000_get_phy_info_m88;
 241                 if (phy->id == I347AT4_E_PHY_ID ||
 242                     phy->id == M88E1112_E_PHY_ID ||
 243                     phy->id == M88E1340M_E_PHY_ID)
 244                         phy->ops.get_cable_length =
 245                                          e1000_get_cable_length_m88_gen2;
 246                 else if (phy->id == M88E1543_E_PHY_ID ||
 247                          phy->id == M88E1512_E_PHY_ID)
 248                         phy->ops.get_cable_length =
 249                                          e1000_get_cable_length_m88_gen2;
 250                 else
 251                         phy->ops.get_cable_length = e1000_get_cable_length_m88;
 252                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 253                 /* Check if this PHY is confgured for media swap. */
 254                 if (phy->id == M88E1112_E_PHY_ID) {
 255                         u16 data;
 256
 257                         ret_val = phy->ops.write_reg(hw,
 258                                                      E1000_M88E1112_PAGE_ADDR,
 259                                                      2);
 260                         if (ret_val)
 261                                 goto out;
 262
 263                         ret_val = phy->ops.read_reg(hw,
 264                                                     E1000_M88E1112_MAC_CTRL_1,
 265                                                     &data);
 266                         if (ret_val)
 267                                 goto out;
 268
 269                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 270                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 271                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 272                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 273                                 hw->mac.ops.check_for_link =
 274                                                 e1000_check_for_link_media_swap;
 275                 }
 276                 if (phy->id == M88E1512_E_PHY_ID) {
 277                         ret_val = e1000_initialize_M88E1512_phy(hw);
 278                         if (ret_val)
 279                                 goto out;
 280                 }
 281                 break;
 282         case IGP03E1000_E_PHY_ID:
 283         case IGP04E1000_E_PHY_ID:
 284                 phy->type = e1000_phy_igp_3;
 285                 phy->ops.check_polarity = e1000_check_polarity_igp;
 286                 phy->ops.get_info = e1000_get_phy_info_igp;
 287                 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 288                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 289                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
 290                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 291                 break;
 292         case I82580_I_PHY_ID:
 293         case I350_I_PHY_ID:
 294                 phy->type = e1000_phy_82580;
 295                 phy->ops.check_polarity = e1000_check_polarity_82577;
 296                 phy->ops.force_speed_duplex =
 297                                          e1000_phy_force_speed_duplex_82577;
 298                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 299                 phy->ops.get_info = e1000_get_phy_info_82577;
 300                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 301                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 302                 break;
 303         case I210_I_PHY_ID:
 304                 phy->type               = e1000_phy_i210;
 305                 phy->ops.check_polarity = e1000_check_polarity_m88;
 306                 phy->ops.get_info       = e1000_get_phy_info_m88;
 307                 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
 308                 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
 309                 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 310                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 311                 break;
 312         default:
 313                 ret_val = -E1000_ERR_PHY;
 314                 goto out;
 315         }
 316
 317 out:
 318         return ret_val;
 319 }
 320
 321 /**
 322  *  e1000_init_nvm_params_82575 - Init NVM func ptrs.
 323  *  @hw: pointer to the HW structure
 324  **/
 325 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
 326 {
 327         struct e1000_nvm_info *nvm = &hw->nvm;
 328         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 329         u16 size;
 330
 331         DEBUGFUNC("e1000_init_nvm_params_82575");
 332
 333         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 334                      E1000_EECD_SIZE_EX_SHIFT);
 335         /*
 336          * Added to a constant, "size" becomes the left-shift value
 337          * for setting word_size.
 338          */
 339         size += NVM_WORD_SIZE_BASE_SHIFT;
 340
 341         /* Just in case size is out of range, cap it to the largest
 342          * EEPROM size supported
 343          */
 344         if (size > 15)
 345                 size = 15;
 346
 347         nvm->word_size = 1 << size;
 348         if (hw->mac.type < e1000_i210) {
 349                 nvm->opcode_bits = 8;
 350                 nvm->delay_usec = 1;
 351
 352                 switch (nvm->override) {
 353                 case e1000_nvm_override_spi_large:
 354                         nvm->page_size = 32;
 355                         nvm->address_bits = 16;
 356                         break;
 357                 case e1000_nvm_override_spi_small:
 358                         nvm->page_size = 8;
 359                         nvm->address_bits = 8;
 360                         break;
 361                 default:
 362                         nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 363                         nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 364                                             16 : 8;
 365                         break;
 366                 }
 367                 if (nvm->word_size == (1 << 15))
 368                         nvm->page_size = 128;
 369
 370                 nvm->type = e1000_nvm_eeprom_spi;
 371         } else {
 372                 nvm->type = e1000_nvm_flash_hw;
 373         }
 374
 375         /* Function Pointers */
 376         nvm->ops.acquire = e1000_acquire_nvm_82575;
 377         nvm->ops.release = e1000_release_nvm_82575;
 378         if (nvm->word_size < (1 << 15))
 379                 nvm->ops.read = e1000_read_nvm_eerd;
 380         else
 381                 nvm->ops.read = e1000_read_nvm_spi;
 382
 383         nvm->ops.write = e1000_write_nvm_spi;
 384         nvm->ops.validate = e1000_validate_nvm_checksum_generic;
 385         nvm->ops.update = e1000_update_nvm_checksum_generic;
 386         nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 387
 388         /* override generic family function pointers for specific descendants */
 389         switch (hw->mac.type) {
 390         case e1000_82580:
 391                 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
 392                 nvm->ops.update = e1000_update_nvm_checksum_82580;
 393                 break;
 394         case e1000_i350:
 395         case e1000_i354:
 396                 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
 397                 nvm->ops.update = e1000_update_nvm_checksum_i350;
 398                 break;
 399         default:
 400                 break;
 401         }
 402
 403         return E1000_SUCCESS;
 404 }
 405
 406 /**
 407  *  e1000_init_mac_params_82575 - Init MAC func ptrs.
 408  *  @hw: pointer to the HW structure
 409  **/
 410 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
 411 {
 412         struct e1000_mac_info *mac = &hw->mac;
 413         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 414
 415         DEBUGFUNC("e1000_init_mac_params_82575");
 416
 417         /* Derives media type */
 418         e1000_get_media_type_82575(hw);
 419         /* Set mta register count */
 420         mac->mta_reg_count = 128;
 421         /* Set uta register count */
 422         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 423         /* Set rar entry count */
 424         mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 425         if (mac->type == e1000_82576)
 426                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 427         if (mac->type == e1000_82580)
 428                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 429         if (mac->type == e1000_i350 || mac->type == e1000_i354)
 430                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 431
 432         /* Enable EEE default settings for EEE supported devices */
 433         if (mac->type >= e1000_i350)
 434                 dev_spec->eee_disable = FALSE;
 435
 436         /* Allow a single clear of the SW semaphore on I210 and newer */
 437         if (mac->type >= e1000_i210)
 438                 dev_spec->clear_semaphore_once = TRUE;
 439
 440         /* Set if part includes ASF firmware */
 441         mac->asf_firmware_present = TRUE;
 442         /* FWSM register */
 443         mac->has_fwsm = TRUE;
 444         /* ARC supported; valid only if manageability features are enabled. */
 445         mac->arc_subsystem_valid =
 446                 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
 447
 448         /* Function pointers */
 449
 450         /* bus type/speed/width */
 451         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 452         /* reset */
 453         if (mac->type >= e1000_82580)
 454                 mac->ops.reset_hw = e1000_reset_hw_82580;
 455         else
 456         mac->ops.reset_hw = e1000_reset_hw_82575;
 457         /* hw initialization */
 458         if ((mac->type == e1000_i210) || (mac->type == e1000_i211))
 459                 mac->ops.init_hw = e1000_init_hw_i210;
 460         else
 461         mac->ops.init_hw = e1000_init_hw_82575;
 462         /* link setup */
 463         mac->ops.setup_link = e1000_setup_link_generic;
 464         /* physical interface link setup */
 465         mac->ops.setup_physical_interface =
 466                 (hw->phy.media_type == e1000_media_type_copper)
 467                 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 468         /* physical interface shutdown */
 469         mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 470         /* physical interface power up */
 471         mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
 472         /* check for link */
 473         mac->ops.check_for_link = e1000_check_for_link_82575;
 474         /* read mac address */
 475         mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
 476         /* configure collision distance */
 477         mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 478         /* multicast address update */
 479         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 480         if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
 481                 /* writing VFTA */
 482                 mac->ops.write_vfta = e1000_write_vfta_i350;
 483                 /* clearing VFTA */
 484                 mac->ops.clear_vfta = e1000_clear_vfta_i350;
 485         } else {
 486                 /* writing VFTA */
 487                 mac->ops.write_vfta = e1000_write_vfta_generic;
 488                 /* clearing VFTA */
 489                 mac->ops.clear_vfta = e1000_clear_vfta_generic;
 490         }
 491         if (hw->mac.type >= e1000_82580)
 492                 mac->ops.validate_mdi_setting =
 493                                 e1000_validate_mdi_setting_crossover_generic;
 494         /* ID LED init */
 495         mac->ops.id_led_init = e1000_id_led_init_generic;
 496         /* blink LED */
 497         mac->ops.blink_led = e1000_blink_led_generic;
 498         /* setup LED */
 499         mac->ops.setup_led = e1000_setup_led_generic;
 500         /* cleanup LED */
 501         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 502         /* turn on/off LED */
 503         mac->ops.led_on = e1000_led_on_generic;
 504         mac->ops.led_off = e1000_led_off_generic;
 505         /* clear hardware counters */
 506         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
 507         /* link info */
 508         mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
 509         /* acquire SW_FW sync */
 510         mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
 511         mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
 512         if (mac->type >= e1000_i210) {
 513                 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
 514                 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
 515         }
 516
 517         /* set lan id for port to determine which phy lock to use */
 518         hw->mac.ops.set_lan_id(hw);
 519
 520         return E1000_SUCCESS;
 521 }
 522
 523 /**
 524  *  e1000_init_function_pointers_82575 - Init func ptrs.
 525  *  @hw: pointer to the HW structure
 526  *
 527  *  Called to initialize all function pointers and parameters.
 528  **/
 529 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
 530 {
 531         DEBUGFUNC("e1000_init_function_pointers_82575");
 532
 533         hw->mac.ops.init_params = e1000_init_mac_params_82575;
 534         hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
 535         hw->phy.ops.init_params = e1000_init_phy_params_82575;
 536         hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
 537 }
 538
 539 /**
 540  *  e1000_acquire_phy_82575 - Acquire rights to access PHY
 541  *  @hw: pointer to the HW structure
 542  *
 543  *  Acquire access rights to the correct PHY.
 544  **/
 545 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
 546 {
 547         u16 mask = E1000_SWFW_PHY0_SM;
 548
 549         DEBUGFUNC("e1000_acquire_phy_82575");
 550
 551         if (hw->bus.func == E1000_FUNC_1)
 552                 mask = E1000_SWFW_PHY1_SM;
 553         else if (hw->bus.func == E1000_FUNC_2)
 554                 mask = E1000_SWFW_PHY2_SM;
 555         else if (hw->bus.func == E1000_FUNC_3)
 556                 mask = E1000_SWFW_PHY3_SM;
 557
 558         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 559 }
 560
 561 /**
 562  *  e1000_release_phy_82575 - Release rights to access PHY
 563  *  @hw: pointer to the HW structure
 564  *
 565  *  A wrapper to release access rights to the correct PHY.
 566  **/
 567 static void e1000_release_phy_82575(struct e1000_hw *hw)
 568 {
 569         u16 mask = E1000_SWFW_PHY0_SM;
 570
 571         DEBUGFUNC("e1000_release_phy_82575");
 572
 573         if (hw->bus.func == E1000_FUNC_1)
 574                 mask = E1000_SWFW_PHY1_SM;
 575         else if (hw->bus.func == E1000_FUNC_2)
 576                 mask = E1000_SWFW_PHY2_SM;
 577         else if (hw->bus.func == E1000_FUNC_3)
 578                 mask = E1000_SWFW_PHY3_SM;
 579
 580         hw->mac.ops.release_swfw_sync(hw, mask);
 581 }
 582
 583 /**
 584  *  e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 585  *  @hw: pointer to the HW structure
 586  *  @offset: register offset to be read
 587  *  @data: pointer to the read data
 588  *
 589  *  Reads the PHY register at offset using the serial gigabit media independent
 590  *  interface and stores the retrieved information in data.
 591  **/
 592 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 593                                           u16 *data)
 594 {
 595         s32 ret_val = -E1000_ERR_PARAM;
 596
 597         DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
 598
 599         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 600                 DEBUGOUT1("PHY Address %u is out of range\n", offset);
 601                 goto out;
 602         }
 603
 604         ret_val = hw->phy.ops.acquire(hw);
 605         if (ret_val)
 606                 goto out;
 607
 608         ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
 609
 610         hw->phy.ops.release(hw);
 611
 612 out:
 613         return ret_val;
 614 }
 615
 616 /**
 617  *  e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 618  *  @hw: pointer to the HW structure
 619  *  @offset: register offset to write to
 620  *  @data: data to write at register offset
 621  *
 622  *  Writes the data to PHY register at the offset using the serial gigabit
 623  *  media independent interface.
 624  **/
 625 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 626                                            u16 data)
 627 {
 628         s32 ret_val = -E1000_ERR_PARAM;
 629
 630         DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
 631
 632         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 633                 DEBUGOUT1("PHY Address %d is out of range\n", offset);
 634                 goto out;
 635         }
 636
 637         ret_val = hw->phy.ops.acquire(hw);
 638         if (ret_val)
 639                 goto out;
 640
 641         ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
 642
 643         hw->phy.ops.release(hw);
 644
 645 out:
 646         return ret_val;
 647 }
 648
 649 /**
 650  *  e1000_get_phy_id_82575 - Retrieve PHY addr and id
 651  *  @hw: pointer to the HW structure
 652  *
 653  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 654  *  sgmi interface.
 655  **/
 656 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
 657 {
 658         struct e1000_phy_info *phy = &hw->phy;
 659         s32  ret_val = E1000_SUCCESS;
 660         u16 phy_id;
 661         u32 ctrl_ext;
 662         u32 mdic;
 663
 664         DEBUGFUNC("e1000_get_phy_id_82575");
 665
 666         /* some i354 devices need an extra read for phy id */
 667         if (hw->mac.type == e1000_i354)
 668                 e1000_get_phy_id(hw);
 669
 670         /*
 671          * For SGMII PHYs, we try the list of possible addresses until
 672          * we find one that works.  For non-SGMII PHYs
 673          * (e.g. integrated copper PHYs), an address of 1 should
 674          * work.  The result of this function should mean phy->phy_addr
 675          * and phy->id are set correctly.
 676          */
 677         if (!e1000_sgmii_active_82575(hw)) {
 678                 phy->addr = 1;
 679                 ret_val = e1000_get_phy_id(hw);
 680                 goto out;
 681         }
 682
 683         if (e1000_sgmii_uses_mdio_82575(hw)) {
 684                 switch (hw->mac.type) {
 685                 case e1000_82575:
 686                 case e1000_82576:
 687                         mdic = E1000_READ_REG(hw, E1000_MDIC);
 688                         mdic &= E1000_MDIC_PHY_MASK;
 689                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 690                         break;
 691                 case e1000_82580:
 692                 case e1000_i350:
 693                 case e1000_i354:
 694                 case e1000_i210:
 695                 case e1000_i211:
 696                         mdic = E1000_READ_REG(hw, E1000_MDICNFG);
 697                         mdic &= E1000_MDICNFG_PHY_MASK;
 698                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 699                         break;
 700                 default:
 701                         ret_val = -E1000_ERR_PHY;
 702                         goto out;
 703                         break;
 704                 }
 705                 ret_val = e1000_get_phy_id(hw);
 706                 goto out;
 707         }
 708
 709         /* Power on sgmii phy if it is disabled */
 710         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 711         E1000_WRITE_REG(hw, E1000_CTRL_EXT,
 712                         ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 713         E1000_WRITE_FLUSH(hw);
 714         msec_delay(300);
 715
 716         /*
 717          * The address field in the I2CCMD register is 3 bits and 0 is invalid.
 718          * Therefore, we need to test 1-7
 719          */
 720         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 721                 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 722                 if (ret_val == E1000_SUCCESS) {
 723                         DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
 724                                   phy_id, phy->addr);
 725                         /*
 726                          * At the time of this writing, The M88 part is
 727                          * the only supported SGMII PHY product.
 728                          */
 729                         if (phy_id == M88_VENDOR)
 730                                 break;
 731                 } else {
 732                         DEBUGOUT1("PHY address %u was unreadable\n",
 733                                   phy->addr);
 734                 }
 735         }
 736
 737         /* A valid PHY type couldn't be found. */
 738         if (phy->addr == 8) {
 739                 phy->addr = 0;
 740                 ret_val = -E1000_ERR_PHY;
 741         } else {
 742                 ret_val = e1000_get_phy_id(hw);
 743         }
 744
 745         /* restore previous sfp cage power state */
 746         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 747
 748 out:
 749         return ret_val;
 750 }
 751
 752 /**
 753  *  e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 754  *  @hw: pointer to the HW structure
 755  *
 756  *  Resets the PHY using the serial gigabit media independent interface.
 757  **/
 758 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 759 {
 760         s32 ret_val = E1000_SUCCESS;
 761         struct e1000_phy_info *phy = &hw->phy;
 762
 763         DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
 764
 765         /*
 766          * This isn't a TRUE "hard" reset, but is the only reset
 767          * available to us at this time.
 768          */
 769
 770         DEBUGOUT("Soft resetting SGMII attached PHY...\n");
 771
 772         if (!(hw->phy.ops.write_reg))
 773                 goto out;
 774
 775         /*
 776          * SFP documentation requires the following to configure the SPF module
 777          * to work on SGMII.  No further documentation is given.
 778          */
 779         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 780         if (ret_val)
 781                 goto out;
 782
 783         ret_val = hw->phy.ops.commit(hw);
 784         if (ret_val)
 785                 goto out;
 786
 787         if (phy->id == M88E1512_E_PHY_ID)
 788                 ret_val = e1000_initialize_M88E1512_phy(hw);
 789 out:
 790         return ret_val;
 791 }
 792
 793 /**
 794  *  e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 795  *  @hw: pointer to the HW structure
 796  *  @active: TRUE to enable LPLU, FALSE to disable
 797  *
 798  *  Sets the LPLU D0 state according to the active flag.  When
 799  *  activating LPLU this function also disables smart speed
 800  *  and vice versa.  LPLU will not be activated unless the
 801  *  device autonegotiation advertisement meets standards of
 802  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 803  *  This is a function pointer entry point only called by
 804  *  PHY setup routines.
 805  **/
 806 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 807 {
 808         struct e1000_phy_info *phy = &hw->phy;
 809         s32 ret_val = E1000_SUCCESS;
 810         u16 data;
 811
 812         DEBUGFUNC("e1000_set_d0_lplu_state_82575");
 813
 814         if (!(hw->phy.ops.read_reg))
 815                 goto out;
 816
 817         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 818         if (ret_val)
 819                 goto out;
 820
 821         if (active) {
 822                 data |= IGP02E1000_PM_D0_LPLU;
 823                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 824                                              data);
 825                 if (ret_val)
 826                         goto out;
 827
 828                 /* When LPLU is enabled, we should disable SmartSpeed */
 829                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 830                                             &data);
 831                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 832                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 833                                              data);
 834                 if (ret_val)
 835                         goto out;
 836         } else {
 837                 data &= ~IGP02E1000_PM_D0_LPLU;
 838                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 839                                              data);
 840                 /*
 841                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 842                  * during Dx states where the power conservation is most
 843                  * important.  During driver activity we should enable
 844                  * SmartSpeed, so performance is maintained.
 845                  */
 846                 if (phy->smart_speed == e1000_smart_speed_on) {
 847                         ret_val = phy->ops.read_reg(hw,
 848                                                     IGP01E1000_PHY_PORT_CONFIG,
 849                                                     &data);
 850                         if (ret_val)
 851                                 goto out;
 852
 853                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 854                         ret_val = phy->ops.write_reg(hw,
 855                                                      IGP01E1000_PHY_PORT_CONFIG,
 856                                                      data);
 857                         if (ret_val)
 858                                 goto out;
 859                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 860                         ret_val = phy->ops.read_reg(hw,
 861                                                     IGP01E1000_PHY_PORT_CONFIG,
 862                                                     &data);
 863                         if (ret_val)
 864                                 goto out;
 865
 866                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 867                         ret_val = phy->ops.write_reg(hw,
 868                                                      IGP01E1000_PHY_PORT_CONFIG,
 869                                                      data);
 870                         if (ret_val)
 871                                 goto out;
 872                 }
 873         }
 874
 875 out:
 876         return ret_val;
 877 }
 878
 879 /**
 880  *  e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 881  *  @hw: pointer to the HW structure
 882  *  @active: TRUE to enable LPLU, FALSE to disable
 883  *
 884  *  Sets the LPLU D0 state according to the active flag.  When
 885  *  activating LPLU this function also disables smart speed
 886  *  and vice versa.  LPLU will not be activated unless the
 887  *  device autonegotiation advertisement meets standards of
 888  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 889  *  This is a function pointer entry point only called by
 890  *  PHY setup routines.
 891  **/
 892 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 893 {
 894         struct e1000_phy_info *phy = &hw->phy;
 895         u32 data;
 896
 897         DEBUGFUNC("e1000_set_d0_lplu_state_82580");
 898
 899         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 900
 901         if (active) {
 902                 data |= E1000_82580_PM_D0_LPLU;
 903
 904                 /* When LPLU is enabled, we should disable SmartSpeed */
 905                 data &= ~E1000_82580_PM_SPD;
 906         } else {
 907                 data &= ~E1000_82580_PM_D0_LPLU;
 908
 909                 /*
 910                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 911                  * during Dx states where the power conservation is most
 912                  * important.  During driver activity we should enable
 913                  * SmartSpeed, so performance is maintained.
 914                  */
 915                 if (phy->smart_speed == e1000_smart_speed_on)
 916                         data |= E1000_82580_PM_SPD;
 917                 else if (phy->smart_speed == e1000_smart_speed_off)
 918                         data &= ~E1000_82580_PM_SPD;
 919         }
 920
 921         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 922         return E1000_SUCCESS;
 923 }
 924
 925 /**
 926  *  e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
 927  *  @hw: pointer to the HW structure
 928  *  @active: boolean used to enable/disable lplu
 929  *
 930  *  Success returns 0, Failure returns 1
 931  *
 932  *  The low power link up (lplu) state is set to the power management level D3
 933  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 934  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 935  *  is used during Dx states where the power conservation is most important.
 936  *  During driver activity, SmartSpeed should be enabled so performance is
 937  *  maintained.
 938  **/
 939 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 940 {
 941         struct e1000_phy_info *phy = &hw->phy;
 942         u32 data;
 943
 944         DEBUGFUNC("e1000_set_d3_lplu_state_82580");
 945
 946         data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
 947
 948         if (!active) {
 949                 data &= ~E1000_82580_PM_D3_LPLU;
 950                 /*
 951                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 952                  * during Dx states where the power conservation is most
 953                  * important.  During driver activity we should enable
 954                  * SmartSpeed, so performance is maintained.
 955                  */
 956                 if (phy->smart_speed == e1000_smart_speed_on)
 957                         data |= E1000_82580_PM_SPD;
 958                 else if (phy->smart_speed == e1000_smart_speed_off)
 959                         data &= ~E1000_82580_PM_SPD;
 960         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 961                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 962                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 963                 data |= E1000_82580_PM_D3_LPLU;
 964                 /* When LPLU is enabled, we should disable SmartSpeed */
 965                 data &= ~E1000_82580_PM_SPD;
 966         }
 967
 968         E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
 969         return E1000_SUCCESS;
 970 }
 971
 972 /**
 973  *  e1000_acquire_nvm_82575 - Request for access to EEPROM
 974  *  @hw: pointer to the HW structure
 975  *
 976  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 977  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 978  *  Return successful if access grant bit set, else clear the request for
 979  *  EEPROM access and return -E1000_ERR_NVM (-1).
 980  **/
 981 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
 982 {
 983         s32 ret_val = E1000_SUCCESS;
 984
 985         DEBUGFUNC("e1000_acquire_nvm_82575");
 986
 987         ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 988         if (ret_val)
 989                 goto out;
 990
 991         /*
 992          * Check if there is some access
 993          * error this access may hook on
 994          */
 995         if (hw->mac.type == e1000_i350) {
 996                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 997                 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
 998                     E1000_EECD_TIMEOUT)) {
 999                         /* Clear all access error flags */
1000                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1001                                         E1000_EECD_ERROR_CLR);
1002                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1003                 }
1004         }
1005
1006         if (hw->mac.type == e1000_82580) {
1007                 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
1008                 if (eecd & E1000_EECD_BLOCKED) {
1009                         /* Clear access error flag */
1010                         E1000_WRITE_REG(hw, E1000_EECD, eecd |
1011                                         E1000_EECD_BLOCKED);
1012                         DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
1013                 }
1014         }
1015
1016         ret_val = e1000_acquire_nvm_generic(hw);
1017         if (ret_val)
1018                 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1019
1020 out:
1021         return ret_val;
1022 }
1023
1024 /**
1025  *  e1000_release_nvm_82575 - Release exclusive access to EEPROM
1026  *  @hw: pointer to the HW structure
1027  *
1028  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1029  *  then release the semaphores acquired.
1030  **/
1031 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1032 {
1033         DEBUGFUNC("e1000_release_nvm_82575");
1034
1035         e1000_release_nvm_generic(hw);
1036
1037         e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1038 }
1039
1040 /**
1041  *  e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1042  *  @hw: pointer to the HW structure
1043  *  @mask: specifies which semaphore to acquire
1044  *
1045  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1046  *  will also specify which port we're acquiring the lock for.
1047  **/
1048 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1049 {
1050         u32 swfw_sync;
1051         u32 swmask = mask;
1052         u32 fwmask = mask << 16;
1053         s32 ret_val = E1000_SUCCESS;
1054         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1055
1056         DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1057
1058         while (i < timeout) {
1059                 if (e1000_get_hw_semaphore_generic(hw)) {
1060                         ret_val = -E1000_ERR_SWFW_SYNC;
1061                         goto out;
1062                 }
1063
1064                 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1065                 if (!(swfw_sync & (fwmask | swmask)))
1066                         break;
1067
1068                 /*
1069                  * Firmware currently using resource (fwmask)
1070                  * or other software thread using resource (swmask)
1071                  */
1072                 e1000_put_hw_semaphore_generic(hw);
1073                 msec_delay_irq(5);
1074                 i++;
1075         }
1076
1077         if (i == timeout) {
1078                 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1079                 ret_val = -E1000_ERR_SWFW_SYNC;
1080                 goto out;
1081         }
1082
1083         swfw_sync |= swmask;
1084         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1085
1086         e1000_put_hw_semaphore_generic(hw);
1087
1088 out:
1089         return ret_val;
1090 }
1091
1092 /**
1093  *  e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1094  *  @hw: pointer to the HW structure
1095  *  @mask: specifies which semaphore to acquire
1096  *
1097  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1098  *  will also specify which port we're releasing the lock for.
1099  **/
1100 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1101 {
1102         u32 swfw_sync;
1103
1104         DEBUGFUNC("e1000_release_swfw_sync_82575");
1105
1106         while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1107                 ; /* Empty */
1108
1109         swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1110         swfw_sync &= ~mask;
1111         E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1112
1113         e1000_put_hw_semaphore_generic(hw);
1114 }
1115
1116 /**
1117  *  e1000_get_cfg_done_82575 - Read config done bit
1118  *  @hw: pointer to the HW structure
1119  *
1120  *  Read the management control register for the config done bit for
1121  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1122  *  to read the config done bit, so an error is *ONLY* logged and returns
1123  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
1124  *  would not be able to be reset or change link.
1125  **/
1126 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1127 {
1128         s32 timeout = PHY_CFG_TIMEOUT;
1129         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1130
1131         DEBUGFUNC("e1000_get_cfg_done_82575");
1132
1133         if (hw->bus.func == E1000_FUNC_1)
1134                 mask = E1000_NVM_CFG_DONE_PORT_1;
1135         else if (hw->bus.func == E1000_FUNC_2)
1136                 mask = E1000_NVM_CFG_DONE_PORT_2;
1137         else if (hw->bus.func == E1000_FUNC_3)
1138                 mask = E1000_NVM_CFG_DONE_PORT_3;
1139         while (timeout) {
1140                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1141                         break;
1142                 msec_delay(1);
1143                 timeout--;
1144         }
1145         if (!timeout)
1146                 DEBUGOUT("MNG configuration cycle has not completed.\n");
1147
1148         /* If EEPROM is not marked present, init the PHY manually */
1149         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1150             (hw->phy.type == e1000_phy_igp_3))
1151                 e1000_phy_init_script_igp3(hw);
1152
1153         return E1000_SUCCESS;
1154 }
1155
1156 /**
1157  *  e1000_get_link_up_info_82575 - Get link speed/duplex info
1158  *  @hw: pointer to the HW structure
1159  *  @speed: stores the current speed
1160  *  @duplex: stores the current duplex
1161  *
1162  *  This is a wrapper function, if using the serial gigabit media independent
1163  *  interface, use PCS to retrieve the link speed and duplex information.
1164  *  Otherwise, use the generic function to get the link speed and duplex info.
1165  **/
1166 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1167                                         u16 *duplex)
1168 {
1169         s32 ret_val;
1170
1171         DEBUGFUNC("e1000_get_link_up_info_82575");
1172
1173         if (hw->phy.media_type != e1000_media_type_copper)
1174                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1175                                                                duplex);
1176         else
1177                 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1178                                                                     duplex);
1179
1180         return ret_val;
1181 }
1182
1183 /**
1184  *  e1000_check_for_link_82575 - Check for link
1185  *  @hw: pointer to the HW structure
1186  *
1187  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1188  *  use the generic interface for determining link.
1189  **/
1190 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1191 {
1192         s32 ret_val;
1193         u16 speed, duplex;
1194
1195         DEBUGFUNC("e1000_check_for_link_82575");
1196
1197         if (hw->phy.media_type != e1000_media_type_copper) {
1198                 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1199                                                                &duplex);
1200                 /*
1201                  * Use this flag to determine if link needs to be checked or
1202                  * not.  If we have link clear the flag so that we do not
1203                  * continue to check for link.
1204                  */
1205                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1206
1207                 /*
1208                  * Configure Flow Control now that Auto-Neg has completed.
1209                  * First, we need to restore the desired flow control
1210                  * settings because we may have had to re-autoneg with a
1211                  * different link partner.
1212                  */
1213                 ret_val = e1000_config_fc_after_link_up_generic(hw);
1214                 if (ret_val)
1215                         DEBUGOUT("Error configuring flow control\n");
1216         } else {
1217                 ret_val = e1000_check_for_copper_link_generic(hw);
1218         }
1219
1220         return ret_val;
1221 }
1222
1223 /**
1224  *  e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1225  *  @hw: pointer to the HW structure
1226  *
1227  *  Poll the M88E1112 interfaces to see which interface achieved link.
1228  */
1229 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1230 {
1231         struct e1000_phy_info *phy = &hw->phy;
1232         s32 ret_val;
1233         u16 data;
1234         u8 port = 0;
1235
1236         DEBUGFUNC("e1000_check_for_link_media_swap");
1237
1238         /* Check the copper medium. */
1239         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1240         if (ret_val)
1241                 return ret_val;
1242
1243         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         if (data & E1000_M88E1112_STATUS_LINK)
1248                 port = E1000_MEDIA_PORT_COPPER;
1249
1250         /* Check the other medium. */
1251         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1252         if (ret_val)
1253                 return ret_val;
1254
1255         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1256         if (ret_val)
1257                 return ret_val;
1258
1259         /* reset page to 0 */
1260         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1261         if (ret_val)
1262                 return ret_val;
1263
1264         if (data & E1000_M88E1112_STATUS_LINK)
1265                 port = E1000_MEDIA_PORT_OTHER;
1266
1267         /* Determine if a swap needs to happen. */
1268         if (port && (hw->dev_spec._82575.media_port != port)) {
1269                 hw->dev_spec._82575.media_port = port;
1270                 hw->dev_spec._82575.media_changed = TRUE;
1271         } else {
1272                 ret_val = e1000_check_for_link_82575(hw);
1273         }
1274
1275         return E1000_SUCCESS;
1276 }
1277
1278 /**
1279  *  e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1280  *  @hw: pointer to the HW structure
1281  **/
1282 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1283 {
1284         u32 reg;
1285
1286         DEBUGFUNC("e1000_power_up_serdes_link_82575");
1287
1288         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1289             !e1000_sgmii_active_82575(hw))
1290                 return;
1291
1292         /* Enable PCS to turn on link */
1293         reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1294         reg |= E1000_PCS_CFG_PCS_EN;
1295         E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1296
1297         /* Power up the laser */
1298         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1299         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1300         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1301
1302         /* flush the write to verify completion */
1303         E1000_WRITE_FLUSH(hw);
1304         msec_delay(1);
1305 }
1306
1307 /**
1308  *  e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1309  *  @hw: pointer to the HW structure
1310  *  @speed: stores the current speed
1311  *  @duplex: stores the current duplex
1312  *
1313  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1314  *  duplex, then store the values in the pointers provided.
1315  **/
1316 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1317                                                 u16 *speed, u16 *duplex)
1318 {
1319         struct e1000_mac_info *mac = &hw->mac;
1320         u32 pcs;
1321         u32 status;
1322
1323         DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1324
1325         /*
1326          * Read the PCS Status register for link state. For non-copper mode,
1327          * the status register is not accurate. The PCS status register is
1328          * used instead.
1329          */
1330         pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1331
1332         /*
1333          * The link up bit determines when link is up on autoneg.
1334          */
1335         if (pcs & E1000_PCS_LSTS_LINK_OK) {
1336                 mac->serdes_has_link = TRUE;
1337
1338                 /* Detect and store PCS speed */
1339                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1340                         *speed = SPEED_1000;
1341                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1342                         *speed = SPEED_100;
1343                 else
1344                         *speed = SPEED_10;
1345
1346                 /* Detect and store PCS duplex */
1347                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1348                         *duplex = FULL_DUPLEX;
1349                 else
1350                         *duplex = HALF_DUPLEX;
1351
1352                 /* Check if it is an I354 2.5Gb backplane connection. */
1353                 if (mac->type == e1000_i354) {
1354                         status = E1000_READ_REG(hw, E1000_STATUS);
1355                         if ((status & E1000_STATUS_2P5_SKU) &&
1356                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1357                                 *speed = SPEED_2500;
1358                                 *duplex = FULL_DUPLEX;
1359                                 DEBUGOUT("2500 Mbs, ");
1360                                 DEBUGOUT("Full Duplex\n");
1361                         }
1362                 }
1363
1364         } else {
1365                 mac->serdes_has_link = FALSE;
1366                 *speed = 0;
1367                 *duplex = 0;
1368         }
1369
1370         return E1000_SUCCESS;
1371 }
1372
1373 /**
1374  *  e1000_shutdown_serdes_link_82575 - Remove link during power down
1375  *  @hw: pointer to the HW structure
1376  *
1377  *  In the case of serdes shut down sfp and PCS on driver unload
1378  *  when management pass thru is not enabled.
1379  **/
1380 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1381 {
1382         u32 reg;
1383
1384         DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1385
1386         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1387             !e1000_sgmii_active_82575(hw))
1388                 return;
1389
1390         if (!e1000_enable_mng_pass_thru(hw)) {
1391                 /* Disable PCS to turn off link */
1392                 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1393                 reg &= ~E1000_PCS_CFG_PCS_EN;
1394                 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1395
1396                 /* shutdown the laser */
1397                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1398                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1399                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1400
1401                 /* flush the write to verify completion */
1402                 E1000_WRITE_FLUSH(hw);
1403                 msec_delay(1);
1404         }
1405
1406         return;
1407 }
1408
1409 /**
1410  *  e1000_reset_hw_82575 - Reset hardware
1411  *  @hw: pointer to the HW structure
1412  *
1413  *  This resets the hardware into a known state.
1414  **/
1415 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1416 {
1417         u32 ctrl;
1418         s32 ret_val;
1419
1420         DEBUGFUNC("e1000_reset_hw_82575");
1421
1422         /*
1423          * Prevent the PCI-E bus from sticking if there is no TLP connection
1424          * on the last TLP read/write transaction when MAC is reset.
1425          */
1426         ret_val = e1000_disable_pcie_master_generic(hw);
1427         if (ret_val)
1428                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1429
1430         /* set the completion timeout for interface */
1431         ret_val = e1000_set_pcie_completion_timeout(hw);
1432         if (ret_val)
1433                 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1434
1435         DEBUGOUT("Masking off all interrupts\n");
1436         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1437
1438         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1439         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1440         E1000_WRITE_FLUSH(hw);
1441
1442         msec_delay(10);
1443
1444         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1445
1446         DEBUGOUT("Issuing a global reset to MAC\n");
1447         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1448
1449         ret_val = e1000_get_auto_rd_done_generic(hw);
1450         if (ret_val) {
1451                 /*
1452                  * When auto config read does not complete, do not
1453                  * return with an error. This can happen in situations
1454                  * where there is no eeprom and prevents getting link.
1455                  */
1456                 DEBUGOUT("Auto Read Done did not complete\n");
1457         }
1458
1459         /* If EEPROM is not present, run manual init scripts */
1460         if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1461                 e1000_reset_init_script_82575(hw);
1462
1463         /* Clear any pending interrupt events. */
1464         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1465         E1000_READ_REG(hw, E1000_ICR);
1466
1467         /* Install any alternate MAC address into RAR0 */
1468         ret_val = e1000_check_alt_mac_addr_generic(hw);
1469
1470         return ret_val;
1471 }
1472
1473 /**
1474  *  e1000_init_hw_82575 - Initialize hardware
1475  *  @hw: pointer to the HW structure
1476  *
1477  *  This inits the hardware readying it for operation.
1478  **/
1479 s32 e1000_init_hw_82575(struct e1000_hw *hw)
1480 {
1481         struct e1000_mac_info *mac = &hw->mac;
1482         s32 ret_val;
1483         u16 i, rar_count = mac->rar_entry_count;
1484
1485         DEBUGFUNC("e1000_init_hw_82575");
1486
1487         /* Initialize identification LED */
1488         ret_val = mac->ops.id_led_init(hw);
1489         if (ret_val) {
1490                 DEBUGOUT("Error initializing identification LED\n");
1491                 /* This is not fatal and we should not stop init due to this */
1492         }
1493
1494         /* Disabling VLAN filtering */
1495         DEBUGOUT("Initializing the IEEE VLAN\n");
1496         mac->ops.clear_vfta(hw);
1497
1498         /* Setup the receive address */
1499         e1000_init_rx_addrs_generic(hw, rar_count);
1500
1501         /* Zero out the Multicast HASH table */
1502         DEBUGOUT("Zeroing the MTA\n");
1503         for (i = 0; i < mac->mta_reg_count; i++)
1504                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1505
1506         /* Zero out the Unicast HASH table */
1507         DEBUGOUT("Zeroing the UTA\n");
1508         for (i = 0; i < mac->uta_reg_count; i++)
1509                 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1510
1511         /* Setup link and flow control */
1512         ret_val = mac->ops.setup_link(hw);
1513
1514         /* Set the default MTU size */
1515         hw->dev_spec._82575.mtu = 1500;
1516
1517         /*
1518          * Clear all of the statistics registers (clear on read).  It is
1519          * important that we do this after we have tried to establish link
1520          * because the symbol error count will increment wildly if there
1521          * is no link.
1522          */
1523         e1000_clear_hw_cntrs_82575(hw);
1524
1525         return ret_val;
1526 }
1527
1528 /**
1529  *  e1000_setup_copper_link_82575 - Configure copper link settings
1530  *  @hw: pointer to the HW structure
1531  *
1532  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1533  *  for link, once link is established calls to configure collision distance
1534  *  and flow control are called.
1535  **/
1536 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1537 {
1538         u32 ctrl;
1539         s32 ret_val;
1540         u32 phpm_reg;
1541
1542         DEBUGFUNC("e1000_setup_copper_link_82575");
1543
1544         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1545         ctrl |= E1000_CTRL_SLU;
1546         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1547         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1548
1549         /* Clear Go Link Disconnect bit on supported devices */
1550         switch (hw->mac.type) {
1551         case e1000_82580:
1552         case e1000_i350:
1553         case e1000_i210:
1554         case e1000_i211:
1555                 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1556                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1557                 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1558                 break;
1559         default:
1560                 break;
1561         }
1562
1563         ret_val = e1000_setup_serdes_link_82575(hw);
1564         if (ret_val)
1565                 goto out;
1566
1567         if (e1000_sgmii_active_82575(hw)) {
1568                 /* allow time for SFP cage time to power up phy */
1569                 msec_delay(300);
1570
1571                 ret_val = hw->phy.ops.reset(hw);
1572                 if (ret_val) {
1573                         DEBUGOUT("Error resetting the PHY.\n");
1574                         goto out;
1575                 }
1576         }
1577         switch (hw->phy.type) {
1578         case e1000_phy_i210:
1579         case e1000_phy_m88:
1580                 switch (hw->phy.id) {
1581                 case I347AT4_E_PHY_ID:
1582                 case M88E1112_E_PHY_ID:
1583                 case M88E1340M_E_PHY_ID:
1584                 case M88E1543_E_PHY_ID:
1585                 case M88E1512_E_PHY_ID:
1586                 case I210_I_PHY_ID:
1587                         ret_val = e1000_copper_link_setup_m88_gen2(hw);
1588                         break;
1589                 default:
1590                         ret_val = e1000_copper_link_setup_m88(hw);
1591                         break;
1592                 }
1593                 break;
1594         case e1000_phy_igp_3:
1595                 ret_val = e1000_copper_link_setup_igp(hw);
1596                 break;
1597         case e1000_phy_82580:
1598                 ret_val = e1000_copper_link_setup_82577(hw);
1599                 break;
1600         default:
1601                 ret_val = -E1000_ERR_PHY;
1602                 break;
1603         }
1604
1605         if (ret_val)
1606                 goto out;
1607
1608         ret_val = e1000_setup_copper_link_generic(hw);
1609 out:
1610         return ret_val;
1611 }
1612
1613 /**
1614  *  e1000_setup_serdes_link_82575 - Setup link for serdes
1615  *  @hw: pointer to the HW structure
1616  *
1617  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1618  *  used on copper connections where the serialized gigabit media independent
1619  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1620  *  for auto-negotiation or forces speed/duplex.
1621  **/
1622 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1623 {
1624         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1625         bool pcs_autoneg;
1626         s32 ret_val = E1000_SUCCESS;
1627         u16 data;
1628
1629         DEBUGFUNC("e1000_setup_serdes_link_82575");
1630
1631         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1632             !e1000_sgmii_active_82575(hw))
1633                 return ret_val;
1634
1635         /*
1636          * On the 82575, SerDes loopback mode persists until it is
1637          * explicitly turned off or a power cycle is performed.  A read to
1638          * the register does not indicate its status.  Therefore, we ensure
1639          * loopback mode is disabled during initialization.
1640          */
1641         E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1642
1643         /* power on the sfp cage if present */
1644         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1645         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1646         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1647
1648         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1649         ctrl_reg |= E1000_CTRL_SLU;
1650
1651         /* set both sw defined pins on 82575/82576*/
1652         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1653                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1654
1655         reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1656
1657         /* default pcs_autoneg to the same setting as mac autoneg */
1658         pcs_autoneg = hw->mac.autoneg;
1659
1660         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1661         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1662                 /* sgmii mode lets the phy handle forcing speed/duplex */
1663                 pcs_autoneg = TRUE;
1664                 /* autoneg time out should be disabled for SGMII mode */
1665                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1666                 break;
1667         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1668                 /* disable PCS autoneg and support parallel detect only */
1669                 pcs_autoneg = FALSE;
1670                 /* fall through to default case */
1671         default:
1672                 if (hw->mac.type == e1000_82575 ||
1673                     hw->mac.type == e1000_82576) {
1674                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1675                         if (ret_val) {
1676                                 DEBUGOUT("NVM Read Error\n");
1677                                 return ret_val;
1678                         }
1679
1680                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1681                                 pcs_autoneg = FALSE;
1682                 }
1683
1684                 /*
1685                  * non-SGMII modes only supports a speed of 1000/Full for the
1686                  * link so it is best to just force the MAC and let the pcs
1687                  * link either autoneg or be forced to 1000/Full
1688                  */
1689                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1690                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1691
1692                 /* set speed of 1000/Full if speed/duplex is forced */
1693                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1694                 break;
1695         }
1696
1697         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1698
1699         /*
1700          * New SerDes mode allows for forcing speed or autonegotiating speed
1701          * at 1gb. Autoneg should be default set by most drivers. This is the
1702          * mode that will be compatible with older link partners and switches.
1703          * However, both are supported by the hardware and some drivers/tools.
1704          */
1705         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1706                  E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1707
1708         if (pcs_autoneg) {
1709                 /* Set PCS register for autoneg */
1710                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1711                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1712
1713                 /* Disable force flow control for autoneg */
1714                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1715
1716                 /* Configure flow control advertisement for autoneg */
1717                 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1718                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1719
1720                 switch (hw->fc.requested_mode) {
1721                 case e1000_fc_full:
1722                 case e1000_fc_rx_pause:
1723                         anadv_reg |= E1000_TXCW_ASM_DIR;
1724                         anadv_reg |= E1000_TXCW_PAUSE;
1725                         break;
1726                 case e1000_fc_tx_pause:
1727                         anadv_reg |= E1000_TXCW_ASM_DIR;
1728                         break;
1729                 default:
1730                         break;
1731                 }
1732
1733                 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1734
1735                 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1736         } else {
1737                 /* Set PCS register for forced link */
1738                 reg |= E1000_PCS_LCTL_FSD;      /* Force Speed */
1739
1740                 /* Force flow control for forced link */
1741                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1742
1743                 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1744         }
1745
1746         E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1747
1748         if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1749                 e1000_force_mac_fc_generic(hw);
1750
1751         return ret_val;
1752 }
1753
1754 /**
1755  *  e1000_get_media_type_82575 - derives current media type.
1756  *  @hw: pointer to the HW structure
1757  *
1758  *  The media type is chosen reflecting few settings.
1759  *  The following are taken into account:
1760  *  - link mode set in the current port Init Control Word #3
1761  *  - current link mode settings in CSR register
1762  *  - MDIO vs. I2C PHY control interface chosen
1763  *  - SFP module media type
1764  **/
1765 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1766 {
1767         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1768         s32 ret_val = E1000_SUCCESS;
1769         u32 ctrl_ext = 0;
1770         u32 link_mode = 0;
1771
1772         /* Set internal phy as default */
1773         dev_spec->sgmii_active = FALSE;
1774         dev_spec->module_plugged = FALSE;
1775
1776         /* Get CSR setting */
1777         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1778
1779         /* extract link mode setting */
1780         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1781
1782         switch (link_mode) {
1783         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1784                 hw->phy.media_type = e1000_media_type_internal_serdes;
1785                 break;
1786         case E1000_CTRL_EXT_LINK_MODE_GMII:
1787                 hw->phy.media_type = e1000_media_type_copper;
1788                 break;
1789         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1790                 /* Get phy control interface type set (MDIO vs. I2C)*/
1791                 if (e1000_sgmii_uses_mdio_82575(hw)) {
1792                         hw->phy.media_type = e1000_media_type_copper;
1793                         dev_spec->sgmii_active = TRUE;
1794                         break;
1795                 }
1796                 /* fall through for I2C based SGMII */
1797         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1798                 /* read media type from SFP EEPROM */
1799                 ret_val = e1000_set_sfp_media_type_82575(hw);
1800                 if ((ret_val != E1000_SUCCESS) ||
1801                     (hw->phy.media_type == e1000_media_type_unknown)) {
1802                         /*
1803                          * If media type was not identified then return media
1804                          * type defined by the CTRL_EXT settings.
1805                          */
1806                         hw->phy.media_type = e1000_media_type_internal_serdes;
1807
1808                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1809                                 hw->phy.media_type = e1000_media_type_copper;
1810                                 dev_spec->sgmii_active = TRUE;
1811                         }
1812
1813                         break;
1814                 }
1815
1816                 /* do not change link mode for 100BaseFX */
1817                 if (dev_spec->eth_flags.e100_base_fx)
1818                         break;
1819
1820                 /* change current link mode setting */
1821                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1822
1823                 if (hw->phy.media_type == e1000_media_type_copper)
1824                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1825                 else
1826                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1827
1828                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1829
1830                 break;
1831         }
1832
1833         return ret_val;
1834 }
1835
1836 /**
1837  *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
1838  *  @hw: pointer to the HW structure
1839  *
1840  *  The media type is chosen based on SFP module.
1841  *  compatibility flags retrieved from SFP ID EEPROM.
1842  **/
1843 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1844 {
1845         s32 ret_val = E1000_ERR_CONFIG;
1846         u32 ctrl_ext = 0;
1847         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1848         struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1849         u8 tranceiver_type = 0;
1850         s32 timeout = 3;
1851
1852         /* Turn I2C interface ON and power on sfp cage */
1853         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1854         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1855         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1856
1857         E1000_WRITE_FLUSH(hw);
1858
1859         /* Read SFP module data */
1860         while (timeout) {
1861                 ret_val = e1000_read_sfp_data_byte(hw,
1862                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1863                         &tranceiver_type);
1864                 if (ret_val == E1000_SUCCESS)
1865                         break;
1866                 msec_delay(100);
1867                 timeout--;
1868         }
1869         if (ret_val != E1000_SUCCESS)
1870                 goto out;
1871
1872         ret_val = e1000_read_sfp_data_byte(hw,
1873                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1874                         (u8 *)eth_flags);
1875         if (ret_val != E1000_SUCCESS)
1876                 goto out;
1877
1878         /* Check if there is some SFP module plugged and powered */
1879         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1880             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1881                 dev_spec->module_plugged = TRUE;
1882                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1883                         hw->phy.media_type = e1000_media_type_internal_serdes;
1884                 } else if (eth_flags->e100_base_fx) {
1885                         dev_spec->sgmii_active = TRUE;
1886                         hw->phy.media_type = e1000_media_type_internal_serdes;
1887                 } else if (eth_flags->e1000_base_t) {
1888                         dev_spec->sgmii_active = TRUE;
1889                         hw->phy.media_type = e1000_media_type_copper;
1890                 } else {
1891                         hw->phy.media_type = e1000_media_type_unknown;
1892                         DEBUGOUT("PHY module has not been recognized\n");
1893                         goto out;
1894                 }
1895         } else {
1896                 hw->phy.media_type = e1000_media_type_unknown;
1897         }
1898         ret_val = E1000_SUCCESS;
1899 out:
1900         /* Restore I2C interface setting */
1901         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1902         return ret_val;
1903 }
1904
1905 /**
1906  *  e1000_valid_led_default_82575 - Verify a valid default LED config
1907  *  @hw: pointer to the HW structure
1908  *  @data: pointer to the NVM (EEPROM)
1909  *
1910  *  Read the EEPROM for the current default LED configuration.  If the
1911  *  LED configuration is not valid, set to a valid LED configuration.
1912  **/
1913 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1914 {
1915         s32 ret_val;
1916
1917         DEBUGFUNC("e1000_valid_led_default_82575");
1918
1919         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1920         if (ret_val) {
1921                 DEBUGOUT("NVM Read Error\n");
1922                 goto out;
1923         }
1924
1925         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1926                 switch (hw->phy.media_type) {
1927                 case e1000_media_type_internal_serdes:
1928                         *data = ID_LED_DEFAULT_82575_SERDES;
1929                         break;
1930                 case e1000_media_type_copper:
1931                 default:
1932                         *data = ID_LED_DEFAULT;
1933                         break;
1934                 }
1935         }
1936 out:
1937         return ret_val;
1938 }
1939
1940 /**
1941  *  e1000_sgmii_active_82575 - Return sgmii state
1942  *  @hw: pointer to the HW structure
1943  *
1944  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1945  *  which can be enabled for use in the embedded applications.  Simply
1946  *  return the current state of the sgmii interface.
1947  **/
1948 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1949 {
1950         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1951         return dev_spec->sgmii_active;
1952 }
1953
1954 /**
1955  *  e1000_reset_init_script_82575 - Inits HW defaults after reset
1956  *  @hw: pointer to the HW structure
1957  *
1958  *  Inits recommended HW defaults after a reset when there is no EEPROM
1959  *  detected. This is only for the 82575.
1960  **/
1961 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1962 {
1963         DEBUGFUNC("e1000_reset_init_script_82575");
1964
1965         if (hw->mac.type == e1000_82575) {
1966                 DEBUGOUT("Running reset init script for 82575\n");
1967                 /* SerDes configuration via SERDESCTRL */
1968                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1969                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1970                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1971                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1972
1973                 /* CCM configuration via CCMCTL register */
1974                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1975                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1976
1977                 /* PCIe lanes configuration */
1978                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1979                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1980                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1981                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1982
1983                 /* PCIe PLL Configuration */
1984                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1985                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1986                 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1987         }
1988
1989         return E1000_SUCCESS;
1990 }
1991
1992 /**
1993  *  e1000_read_mac_addr_82575 - Read device MAC address
1994  *  @hw: pointer to the HW structure
1995  **/
1996 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1997 {
1998         s32 ret_val;
1999
2000         DEBUGFUNC("e1000_read_mac_addr_82575");
2001
2002         /*
2003          * If there's an alternate MAC address place it in RAR0
2004          * so that it will override the Si installed default perm
2005          * address.
2006          */
2007         ret_val = e1000_check_alt_mac_addr_generic(hw);
2008         if (ret_val)
2009                 goto out;
2010
2011         ret_val = e1000_read_mac_addr_generic(hw);
2012
2013 out:
2014         return ret_val;
2015 }
2016
2017 /**
2018  *  e1000_config_collision_dist_82575 - Configure collision distance
2019  *  @hw: pointer to the HW structure
2020  *
2021  *  Configures the collision distance to the default value and is used
2022  *  during link setup.
2023  **/
2024 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
2025 {
2026         u32 tctl_ext;
2027
2028         DEBUGFUNC("e1000_config_collision_dist_82575");
2029
2030         tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
2031
2032         tctl_ext &= ~E1000_TCTL_EXT_COLD;
2033         tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2034
2035         E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2036         E1000_WRITE_FLUSH(hw);
2037 }
2038
2039 /**
2040  * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2041  * @hw: pointer to the HW structure
2042  *
2043  * In the case of a PHY power down to save power, or to turn off link during a
2044  * driver unload, or wake on lan is not enabled, remove the link.
2045  **/
2046 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2047 {
2048         struct e1000_phy_info *phy = &hw->phy;
2049
2050         if (!(phy->ops.check_reset_block))
2051                 return;
2052
2053         /* If the management interface is not enabled, then power down */
2054         if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2055                 e1000_power_down_phy_copper(hw);
2056
2057         return;
2058 }
2059
2060 /**
2061  *  e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2062  *  @hw: pointer to the HW structure
2063  *
2064  *  Clears the hardware counters by reading the counter registers.
2065  **/
2066 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2067 {
2068         DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2069
2070         e1000_clear_hw_cntrs_base_generic(hw);
2071
2072         E1000_READ_REG(hw, E1000_PRC64);
2073         E1000_READ_REG(hw, E1000_PRC127);
2074         E1000_READ_REG(hw, E1000_PRC255);
2075         E1000_READ_REG(hw, E1000_PRC511);
2076         E1000_READ_REG(hw, E1000_PRC1023);
2077         E1000_READ_REG(hw, E1000_PRC1522);
2078         E1000_READ_REG(hw, E1000_PTC64);
2079         E1000_READ_REG(hw, E1000_PTC127);
2080         E1000_READ_REG(hw, E1000_PTC255);
2081         E1000_READ_REG(hw, E1000_PTC511);
2082         E1000_READ_REG(hw, E1000_PTC1023);
2083         E1000_READ_REG(hw, E1000_PTC1522);
2084
2085         E1000_READ_REG(hw, E1000_ALGNERRC);
2086         E1000_READ_REG(hw, E1000_RXERRC);
2087         E1000_READ_REG(hw, E1000_TNCRS);
2088         E1000_READ_REG(hw, E1000_CEXTERR);
2089         E1000_READ_REG(hw, E1000_TSCTC);
2090         E1000_READ_REG(hw, E1000_TSCTFC);
2091
2092         E1000_READ_REG(hw, E1000_MGTPRC);
2093         E1000_READ_REG(hw, E1000_MGTPDC);
2094         E1000_READ_REG(hw, E1000_MGTPTC);
2095
2096         E1000_READ_REG(hw, E1000_IAC);
2097         E1000_READ_REG(hw, E1000_ICRXOC);
2098
2099         E1000_READ_REG(hw, E1000_ICRXPTC);
2100         E1000_READ_REG(hw, E1000_ICRXATC);
2101         E1000_READ_REG(hw, E1000_ICTXPTC);
2102         E1000_READ_REG(hw, E1000_ICTXATC);
2103         E1000_READ_REG(hw, E1000_ICTXQEC);
2104         E1000_READ_REG(hw, E1000_ICTXQMTC);
2105         E1000_READ_REG(hw, E1000_ICRXDMTC);
2106
2107         E1000_READ_REG(hw, E1000_CBTMPC);
2108         E1000_READ_REG(hw, E1000_HTDPMC);
2109         E1000_READ_REG(hw, E1000_CBRMPC);
2110         E1000_READ_REG(hw, E1000_RPTHC);
2111         E1000_READ_REG(hw, E1000_HGPTC);
2112         E1000_READ_REG(hw, E1000_HTCBDPC);
2113         E1000_READ_REG(hw, E1000_HGORCL);
2114         E1000_READ_REG(hw, E1000_HGORCH);
2115         E1000_READ_REG(hw, E1000_HGOTCL);
2116         E1000_READ_REG(hw, E1000_HGOTCH);
2117         E1000_READ_REG(hw, E1000_LENERRS);
2118
2119         /* This register should not be read in copper configurations */
2120         if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2121             e1000_sgmii_active_82575(hw))
2122                 E1000_READ_REG(hw, E1000_SCVPC);
2123 }
2124
2125 /**
2126  *  e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2127  *  @hw: pointer to the HW structure
2128  *
2129  *  After rx enable if managability is enabled then there is likely some
2130  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
2131  *  function clears the fifos and flushes any packets that came in as rx was
2132  *  being enabled.
2133  **/
2134 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2135 {
2136         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2137         int i, ms_wait;
2138
2139         DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2140         if (hw->mac.type != e1000_82575 ||
2141             !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2142                 return;
2143
2144         /* Disable all Rx queues */
2145         for (i = 0; i < 4; i++) {
2146                 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2147                 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2148                                 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2149         }
2150         /* Poll all queues to verify they have shut down */
2151         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2152                 msec_delay(1);
2153                 rx_enabled = 0;
2154                 for (i = 0; i < 4; i++)
2155                         rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2156                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2157                         break;
2158         }
2159
2160         if (ms_wait == 10)
2161                 DEBUGOUT("Queue disable timed out after 10ms\n");
2162
2163         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2164          * incoming packets are rejected.  Set enable and wait 2ms so that
2165          * any packet that was coming in as RCTL.EN was set is flushed
2166          */
2167         rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2168         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2169
2170         rlpml = E1000_READ_REG(hw, E1000_RLPML);
2171         E1000_WRITE_REG(hw, E1000_RLPML, 0);
2172
2173         rctl = E1000_READ_REG(hw, E1000_RCTL);
2174         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2175         temp_rctl |= E1000_RCTL_LPE;
2176
2177         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2178         E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2179         E1000_WRITE_FLUSH(hw);
2180         msec_delay(2);
2181
2182         /* Enable Rx queues that were previously enabled and restore our
2183          * previous state
2184          */
2185         for (i = 0; i < 4; i++)
2186                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2187         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2188         E1000_WRITE_FLUSH(hw);
2189
2190         E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2191         E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2192
2193         /* Flush receive errors generated by workaround */
2194         E1000_READ_REG(hw, E1000_ROC);
2195         E1000_READ_REG(hw, E1000_RNBC);
2196         E1000_READ_REG(hw, E1000_MPC);
2197 }
2198
2199 /**
2200  *  e1000_set_pcie_completion_timeout - set pci-e completion timeout
2201  *  @hw: pointer to the HW structure
2202  *
2203  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2204  *  however the hardware default for these parts is 500us to 1ms which is less
2205  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2206  *  increase the value to either 10ms to 200ms for capability version 1 config,
2207  *  or 16ms to 55ms for version 2.
2208  **/
2209 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2210 {
2211         u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2212         s32 ret_val = E1000_SUCCESS;
2213         u16 pcie_devctl2;
2214
2215         /* only take action if timeout value is defaulted to 0 */
2216         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2217                 goto out;
2218
2219         /*
2220          * if capababilities version is type 1 we can write the
2221          * timeout of 10ms to 200ms through the GCR register
2222          */
2223         if (!(gcr & E1000_GCR_CAP_VER2)) {
2224                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2225                 goto out;
2226         }
2227
2228         /*
2229          * for version 2 capabilities we need to write the config space
2230          * directly in order to set the completion timeout value for
2231          * 16ms to 55ms
2232          */
2233         ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2234                                           &pcie_devctl2);
2235         if (ret_val)
2236                 goto out;
2237
2238         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2239
2240         ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2241                                            &pcie_devctl2);
2242 out:
2243         /* disable completion timeout resend */
2244         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2245
2246         E1000_WRITE_REG(hw, E1000_GCR, gcr);
2247         return ret_val;
2248 }
2249
2250 /**
2251  *  e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2252  *  @hw: pointer to the hardware struct
2253  *  @enable: state to enter, either enabled or disabled
2254  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2255  *
2256  *  enables/disables L2 switch anti-spoofing functionality.
2257  **/
2258 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2259 {
2260         u32 reg_val, reg_offset;
2261
2262         switch (hw->mac.type) {
2263         case e1000_82576:
2264                 reg_offset = E1000_DTXSWC;
2265                 break;
2266         case e1000_i350:
2267         case e1000_i354:
2268                 reg_offset = E1000_TXSWC;
2269                 break;
2270         default:
2271                 return;
2272         }
2273
2274         reg_val = E1000_READ_REG(hw, reg_offset);
2275         if (enable) {
2276                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2277                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2278                 /* The PF can spoof - it has to in order to
2279                  * support emulation mode NICs
2280                  */
2281                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2282         } else {
2283                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2284                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2285         }
2286         E1000_WRITE_REG(hw, reg_offset, reg_val);
2287 }
2288
2289 /**
2290  *  e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2291  *  @hw: pointer to the hardware struct
2292  *  @enable: state to enter, either enabled or disabled
2293  *
2294  *  enables/disables L2 switch loopback functionality.
2295  **/
2296 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2297 {
2298         u32 dtxswc;
2299
2300         switch (hw->mac.type) {
2301         case e1000_82576:
2302                 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2303                 if (enable)
2304                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2305                 else
2306                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2307                 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2308                 break;
2309         case e1000_i350:
2310         case e1000_i354:
2311                 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2312                 if (enable)
2313                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2314                 else
2315                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2316                 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2317                 break;
2318         default:
2319                 /* Currently no other hardware supports loopback */
2320                 break;
2321         }
2322
2323
2324 }
2325
2326 /**
2327  *  e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2328  *  @hw: pointer to the hardware struct
2329  *  @enable: state to enter, either enabled or disabled
2330  *
2331  *  enables/disables replication of packets across multiple pools.
2332  **/
2333 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2334 {
2335         u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2336
2337         if (enable)
2338                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2339         else
2340                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2341
2342         E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2343 }
2344
2345 /**
2346  *  e1000_read_phy_reg_82580 - Read 82580 MDI control register
2347  *  @hw: pointer to the HW structure
2348  *  @offset: register offset to be read
2349  *  @data: pointer to the read data
2350  *
2351  *  Reads the MDI control register in the PHY at offset and stores the
2352  *  information read to data.
2353  **/
2354 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2355 {
2356         s32 ret_val;
2357
2358         DEBUGFUNC("e1000_read_phy_reg_82580");
2359
2360         ret_val = hw->phy.ops.acquire(hw);
2361         if (ret_val)
2362                 goto out;
2363
2364         ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2365
2366         hw->phy.ops.release(hw);
2367
2368 out:
2369         return ret_val;
2370 }
2371
2372 /**
2373  *  e1000_write_phy_reg_82580 - Write 82580 MDI control register
2374  *  @hw: pointer to the HW structure
2375  *  @offset: register offset to write to
2376  *  @data: data to write to register at offset
2377  *
2378  *  Writes data to MDI control register in the PHY at offset.
2379  **/
2380 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2381 {
2382         s32 ret_val;
2383
2384         DEBUGFUNC("e1000_write_phy_reg_82580");
2385
2386         ret_val = hw->phy.ops.acquire(hw);
2387         if (ret_val)
2388                 goto out;
2389
2390         ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2391
2392         hw->phy.ops.release(hw);
2393
2394 out:
2395         return ret_val;
2396 }
2397
2398 /**
2399  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2400  *  @hw: pointer to the HW structure
2401  *
2402  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2403  *  the values found in the EEPROM.  This addresses an issue in which these
2404  *  bits are not restored from EEPROM after reset.
2405  **/
2406 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2407 {
2408         s32 ret_val = E1000_SUCCESS;
2409         u32 mdicnfg;
2410         u16 nvm_data = 0;
2411
2412         DEBUGFUNC("e1000_reset_mdicnfg_82580");
2413
2414         if (hw->mac.type != e1000_82580)
2415                 goto out;
2416         if (!e1000_sgmii_active_82575(hw))
2417                 goto out;
2418
2419         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2420                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2421                                    &nvm_data);
2422         if (ret_val) {
2423                 DEBUGOUT("NVM Read Error\n");
2424                 goto out;
2425         }
2426
2427         mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2428         if (nvm_data & NVM_WORD24_EXT_MDIO)
2429                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2430         if (nvm_data & NVM_WORD24_COM_MDIO)
2431                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2432         E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2433 out:
2434         return ret_val;
2435 }
2436
2437 /**
2438  *  e1000_reset_hw_82580 - Reset hardware
2439  *  @hw: pointer to the HW structure
2440  *
2441  *  This resets function or entire device (all ports, etc.)
2442  *  to a known state.
2443  **/
2444 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2445 {
2446         s32 ret_val = E1000_SUCCESS;
2447         /* BH SW mailbox bit in SW_FW_SYNC */
2448         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2449         u32 ctrl;
2450         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2451
2452         DEBUGFUNC("e1000_reset_hw_82580");
2453
2454         hw->dev_spec._82575.global_device_reset = FALSE;
2455
2456         /* 82580 does not reliably do global_device_reset due to hw errata */
2457         if (hw->mac.type == e1000_82580)
2458                 global_device_reset = FALSE;
2459
2460         /* Get current control state. */
2461         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2462
2463         /*
2464          * Prevent the PCI-E bus from sticking if there is no TLP connection
2465          * on the last TLP read/write transaction when MAC is reset.
2466          */
2467         ret_val = e1000_disable_pcie_master_generic(hw);
2468         if (ret_val)
2469                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2470
2471         DEBUGOUT("Masking off all interrupts\n");
2472         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2473         E1000_WRITE_REG(hw, E1000_RCTL, 0);
2474         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2475         E1000_WRITE_FLUSH(hw);
2476
2477         msec_delay(10);
2478
2479         /* Determine whether or not a global dev reset is requested */
2480         if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2481             swmbsw_mask))
2482                         global_device_reset = FALSE;
2483
2484         if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2485             E1000_STAT_DEV_RST_SET))
2486                 ctrl |= E1000_CTRL_DEV_RST;
2487         else
2488                 ctrl |= E1000_CTRL_RST;
2489
2490         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2491
2492         switch (hw->device_id) {
2493         case E1000_DEV_ID_DH89XXCC_SGMII:
2494                 break;
2495         default:
2496                 E1000_WRITE_FLUSH(hw);
2497                 break;
2498         }
2499
2500         /* Add delay to insure DEV_RST or RST has time to complete */
2501         msec_delay(5);
2502
2503         ret_val = e1000_get_auto_rd_done_generic(hw);
2504         if (ret_val) {
2505                 /*
2506                  * When auto config read does not complete, do not
2507                  * return with an error. This can happen in situations
2508                  * where there is no eeprom and prevents getting link.
2509                  */
2510                 DEBUGOUT("Auto Read Done did not complete\n");
2511         }
2512
2513         /* clear global device reset status bit */
2514         E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2515
2516         /* Clear any pending interrupt events. */
2517         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2518         E1000_READ_REG(hw, E1000_ICR);
2519
2520         ret_val = e1000_reset_mdicnfg_82580(hw);
2521         if (ret_val)
2522                 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2523
2524         /* Install any alternate MAC address into RAR0 */
2525         ret_val = e1000_check_alt_mac_addr_generic(hw);
2526
2527         /* Release semaphore */
2528         if (global_device_reset)
2529                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2530
2531         return ret_val;
2532 }
2533
2534 /**
2535  *  e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2536  *  @data: data received by reading RXPBS register
2537  *
2538  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2539  *  This function converts the retrieved value into the correct table value
2540  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2541  *  0x0 36  72 144   1   2   4   8  16
2542  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2543  */
2544 u16 e1000_rxpbs_adjust_82580(u32 data)
2545 {
2546         u16 ret_val = 0;
2547
2548         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2549                 ret_val = e1000_82580_rxpbs_table[data];
2550
2551         return ret_val;
2552 }
2553
2554 /**
2555  *  e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2556  *  checksum
2557  *  @hw: pointer to the HW structure
2558  *  @offset: offset in words of the checksum protected region
2559  *
2560  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2561  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2562  **/
2563 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2564 {
2565         s32 ret_val = E1000_SUCCESS;
2566         u16 checksum = 0;
2567         u16 i, nvm_data;
2568
2569         DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2570
2571         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2572                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2573                 if (ret_val) {
2574                         DEBUGOUT("NVM Read Error\n");
2575                         goto out;
2576                 }
2577                 checksum += nvm_data;
2578         }
2579
2580         if (checksum != (u16) NVM_SUM) {
2581                 DEBUGOUT("NVM Checksum Invalid\n");
2582                 ret_val = -E1000_ERR_NVM;
2583                 goto out;
2584         }
2585
2586 out:
2587         return ret_val;
2588 }
2589
2590 /**
2591  *  e1000_update_nvm_checksum_with_offset - Update EEPROM
2592  *  checksum
2593  *  @hw: pointer to the HW structure
2594  *  @offset: offset in words of the checksum protected region
2595  *
2596  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2597  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2598  *  value to the EEPROM.
2599  **/
2600 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2601 {
2602         s32 ret_val;
2603         u16 checksum = 0;
2604         u16 i, nvm_data;
2605
2606         DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2607
2608         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2609                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2610                 if (ret_val) {
2611                         DEBUGOUT("NVM Read Error while updating checksum.\n");
2612                         goto out;
2613                 }
2614                 checksum += nvm_data;
2615         }
2616         checksum = (u16) NVM_SUM - checksum;
2617         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2618                                     &checksum);
2619         if (ret_val)
2620                 DEBUGOUT("NVM Write Error while updating checksum.\n");
2621
2622 out:
2623         return ret_val;
2624 }
2625
2626 /**
2627  *  e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2628  *  @hw: pointer to the HW structure
2629  *
2630  *  Calculates the EEPROM section checksum by reading/adding each word of
2631  *  the EEPROM and then verifies that the sum of the EEPROM is
2632  *  equal to 0xBABA.
2633  **/
2634 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2635 {
2636         s32 ret_val;
2637         u16 eeprom_regions_count = 1;
2638         u16 j, nvm_data;
2639         u16 nvm_offset;
2640
2641         DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2642
2643         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2644         if (ret_val) {
2645                 DEBUGOUT("NVM Read Error\n");
2646                 goto out;
2647         }
2648
2649         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2650                 /* if chekcsums compatibility bit is set validate checksums
2651                  * for all 4 ports. */
2652                 eeprom_regions_count = 4;
2653         }
2654
2655         for (j = 0; j < eeprom_regions_count; j++) {
2656                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2657                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2658                                                                   nvm_offset);
2659                 if (ret_val != E1000_SUCCESS)
2660                         goto out;
2661         }
2662
2663 out:
2664         return ret_val;
2665 }
2666
2667 /**
2668  *  e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2669  *  @hw: pointer to the HW structure
2670  *
2671  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2672  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2673  *  checksum and writes the value to the EEPROM.
2674  **/
2675 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2676 {
2677         s32 ret_val;
2678         u16 j, nvm_data;
2679         u16 nvm_offset;
2680
2681         DEBUGFUNC("e1000_update_nvm_checksum_82580");
2682
2683         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2684         if (ret_val) {
2685                 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2686                 goto out;
2687         }
2688
2689         if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2690                 /* set compatibility bit to validate checksums appropriately */
2691                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2692                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2693                                             &nvm_data);
2694                 if (ret_val) {
2695                         DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2696                         goto out;
2697                 }
2698         }
2699
2700         for (j = 0; j < 4; j++) {
2701                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2702                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2703                 if (ret_val)
2704                         goto out;
2705         }
2706
2707 out:
2708         return ret_val;
2709 }
2710
2711 /**
2712  *  e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2713  *  @hw: pointer to the HW structure
2714  *
2715  *  Calculates the EEPROM section checksum by reading/adding each word of
2716  *  the EEPROM and then verifies that the sum of the EEPROM is
2717  *  equal to 0xBABA.
2718  **/
2719 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2720 {
2721         s32 ret_val = E1000_SUCCESS;
2722         u16 j;
2723         u16 nvm_offset;
2724
2725         DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2726
2727         for (j = 0; j < 4; j++) {
2728                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2729                 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2730                                                                   nvm_offset);
2731                 if (ret_val != E1000_SUCCESS)
2732                         goto out;
2733         }
2734
2735 out:
2736         return ret_val;
2737 }
2738
2739 /**
2740  *  e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2741  *  @hw: pointer to the HW structure
2742  *
2743  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2744  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2745  *  checksum and writes the value to the EEPROM.
2746  **/
2747 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2748 {
2749         s32 ret_val = E1000_SUCCESS;
2750         u16 j;
2751         u16 nvm_offset;
2752
2753         DEBUGFUNC("e1000_update_nvm_checksum_i350");
2754
2755         for (j = 0; j < 4; j++) {
2756                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2757                 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2758                 if (ret_val != E1000_SUCCESS)
2759                         goto out;
2760         }
2761
2762 out:
2763         return ret_val;
2764 }
2765
2766 /**
2767  *  __e1000_access_emi_reg - Read/write EMI register
2768  *  @hw: pointer to the HW structure
2769  *  @addr: EMI address to program
2770  *  @data: pointer to value to read/write from/to the EMI address
2771  *  @read: boolean flag to indicate read or write
2772  **/
2773 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2774                                   u16 *data, bool read)
2775 {
2776         s32 ret_val;
2777
2778         DEBUGFUNC("__e1000_access_emi_reg");
2779
2780         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2781         if (ret_val)
2782                 return ret_val;
2783
2784         if (read)
2785                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2786         else
2787                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2788
2789         return ret_val;
2790 }
2791
2792 /**
2793  *  e1000_read_emi_reg - Read Extended Management Interface register
2794  *  @hw: pointer to the HW structure
2795  *  @addr: EMI address to program
2796  *  @data: value to be read from the EMI address
2797  **/
2798 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2799 {
2800         DEBUGFUNC("e1000_read_emi_reg");
2801
2802         return __e1000_access_emi_reg(hw, addr, data, TRUE);
2803 }
2804
2805 /**
2806  *  e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY
2807  *  @hw: pointer to the HW structure
2808  *
2809  *  Initialize Marverl 1512 to work correctly with Avoton.
2810  **/
2811 s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
2812 {
2813         struct e1000_phy_info *phy = &hw->phy;
2814         s32 ret_val = E1000_SUCCESS;
2815
2816         DEBUGFUNC("e1000_initialize_M88E1512_phy");
2817
2818         /* Check if this is correct PHY. */
2819         if (phy->id != M88E1512_E_PHY_ID)
2820                 goto out;
2821
2822         /* Switch to PHY page 0xFF. */
2823         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2824         if (ret_val)
2825                 goto out;
2826
2827         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2828         if (ret_val)
2829                 goto out;
2830
2831         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2832         if (ret_val)
2833                 goto out;
2834
2835         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2836         if (ret_val)
2837                 goto out;
2838
2839         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2840         if (ret_val)
2841                 goto out;
2842
2843         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2844         if (ret_val)
2845                 goto out;
2846
2847         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2848         if (ret_val)
2849                 goto out;
2850
2851         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2852         if (ret_val)
2853                 goto out;
2854
2855         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2856         if (ret_val)
2857                 goto out;
2858
2859         /* Switch to PHY page 0xFB. */
2860         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2861         if (ret_val)
2862                 goto out;
2863
2864         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2865         if (ret_val)
2866                 goto out;
2867
2868         /* Switch to PHY page 0x12. */
2869         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2870         if (ret_val)
2871                 goto out;
2872
2873         /* Change mode to SGMII-to-Copper */
2874         ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2875         if (ret_val)
2876                 goto out;
2877
2878         /* Return the PHY to page 0. */
2879         ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2880         if (ret_val)
2881                 goto out;
2882
2883         ret_val = phy->ops.commit(hw);
2884         if (ret_val) {
2885                 DEBUGOUT("Error committing the PHY changes\n");
2886                 return ret_val;
2887         }
2888
2889         msec_delay(1000);
2890 out:
2891         return ret_val;
2892 }
2893
2894 /**
2895  *  e1000_set_eee_i350 - Enable/disable EEE support
2896  *  @hw: pointer to the HW structure
2897  *
2898  *  Enable/disable EEE based on setting in dev_spec structure.
2899  *
2900  **/
2901 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2902 {
2903         u32 ipcnfg, eeer;
2904
2905         DEBUGFUNC("e1000_set_eee_i350");
2906
2907         if ((hw->mac.type < e1000_i350) ||
2908             (hw->phy.media_type != e1000_media_type_copper))
2909                 goto out;
2910         ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2911         eeer = E1000_READ_REG(hw, E1000_EEER);
2912
2913         /* enable or disable per user setting */
2914         if (!(hw->dev_spec._82575.eee_disable)) {
2915                 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2916
2917                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2918                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2919                          E1000_EEER_LPI_FC);
2920
2921                 /* This bit should not be set in normal operation. */
2922                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2923                         DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2924         } else {
2925                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2926                 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2927                           E1000_EEER_LPI_FC);
2928         }
2929         E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2930         E1000_WRITE_REG(hw, E1000_EEER, eeer);
2931         E1000_READ_REG(hw, E1000_IPCNFG);
2932         E1000_READ_REG(hw, E1000_EEER);
2933 out:
2934
2935         return E1000_SUCCESS;
2936 }
2937
2938 /**
2939  *  e1000_set_eee_i354 - Enable/disable EEE support
2940  *  @hw: pointer to the HW structure
2941  *
2942  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2943  *
2944  **/
2945 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2946 {
2947         struct e1000_phy_info *phy = &hw->phy;
2948         s32 ret_val = E1000_SUCCESS;
2949         u16 phy_data;
2950
2951         DEBUGFUNC("e1000_set_eee_i354");
2952
2953         if ((hw->phy.media_type != e1000_media_type_copper) ||
2954             ((phy->id != M88E1543_E_PHY_ID) &&
2955             (phy->id != M88E1512_E_PHY_ID)))
2956                 goto out;
2957
2958         if (!hw->dev_spec._82575.eee_disable) {
2959                 /* Switch to PHY page 18. */
2960                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2961                 if (ret_val)
2962                         goto out;
2963
2964                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2965                                             &phy_data);
2966                 if (ret_val)
2967                         goto out;
2968
2969                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2970                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2971                                              phy_data);
2972                 if (ret_val)
2973                         goto out;
2974
2975                 /* Return the PHY to page 0. */
2976                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2977                 if (ret_val)
2978                         goto out;
2979
2980                 /* Turn on EEE advertisement. */
2981                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2982                                                E1000_EEE_ADV_DEV_I354,
2983                                                &phy_data);
2984                 if (ret_val)
2985                         goto out;
2986
2987                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2988                             E1000_EEE_ADV_1000_SUPPORTED;
2989                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2990                                                 E1000_EEE_ADV_DEV_I354,
2991                                                 phy_data);
2992         } else {
2993                 /* Turn off EEE advertisement. */
2994                 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2995                                                E1000_EEE_ADV_DEV_I354,
2996                                                &phy_data);
2997                 if (ret_val)
2998                         goto out;
2999
3000                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
3001                               E1000_EEE_ADV_1000_SUPPORTED);
3002                 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
3003                                                 E1000_EEE_ADV_DEV_I354,
3004                                                 phy_data);
3005         }
3006
3007 out:
3008         return ret_val;
3009 }
3010
3011 /**
3012  *  e1000_get_eee_status_i354 - Get EEE status
3013  *  @hw: pointer to the HW structure
3014  *  @status: EEE status
3015  *
3016  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
3017  *  been received.
3018  **/
3019 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
3020 {
3021         struct e1000_phy_info *phy = &hw->phy;
3022         s32 ret_val = E1000_SUCCESS;
3023         u16 phy_data;
3024
3025         DEBUGFUNC("e1000_get_eee_status_i354");
3026
3027         /* Check if EEE is supported on this device. */
3028         if ((hw->phy.media_type != e1000_media_type_copper) ||
3029             ((phy->id != M88E1543_E_PHY_ID) &&
3030             (phy->id != M88E1512_E_PHY_ID)))
3031                 goto out;
3032
3033         ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
3034                                        E1000_PCS_STATUS_DEV_I354,
3035                                        &phy_data);
3036         if (ret_val)
3037                 goto out;
3038
3039         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
3040                               E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE;
3041
3042 out:
3043         return ret_val;
3044 }
3045
3046 /* Due to a hw errata, if the host tries to  configure the VFTA register
3047  * while performing queries from the BMC or DMA, then the VFTA in some
3048  * cases won't be written.
3049  */
3050
3051 /**
3052  *  e1000_clear_vfta_i350 - Clear VLAN filter table
3053  *  @hw: pointer to the HW structure
3054  *
3055  *  Clears the register array which contains the VLAN filter table by
3056  *  setting all the values to 0.
3057  **/
3058 void e1000_clear_vfta_i350(struct e1000_hw *hw)
3059 {
3060         u32 offset;
3061         int i;
3062
3063         DEBUGFUNC("e1000_clear_vfta_350");
3064
3065         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
3066                 for (i = 0; i < 10; i++)
3067                         E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
3068
3069                 E1000_WRITE_FLUSH(hw);
3070         }
3071 }
3072
3073 /**
3074  *  e1000_write_vfta_i350 - Write value to VLAN filter table
3075  *  @hw: pointer to the HW structure
3076  *  @offset: register offset in VLAN filter table
3077  *  @value: register value written to VLAN filter table
3078  *
3079  *  Writes value at the given offset in the register array which stores
3080  *  the VLAN filter table.
3081  **/
3082 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
3083 {
3084         int i;
3085
3086         DEBUGFUNC("e1000_write_vfta_350");
3087
3088         for (i = 0; i < 10; i++)
3089                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
3090
3091         E1000_WRITE_FLUSH(hw);
3092 }
3093
3094
3095 /**
3096  *  e1000_set_i2c_bb - Enable I2C bit-bang
3097  *  @hw: pointer to the HW structure
3098  *
3099  *  Enable I2C bit-bang interface
3100  *
3101  **/
3102 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
3103 {
3104         s32 ret_val = E1000_SUCCESS;
3105         u32 ctrl_ext, i2cparams;
3106
3107         DEBUGFUNC("e1000_set_i2c_bb");
3108
3109         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
3110         ctrl_ext |= E1000_CTRL_I2C_ENA;
3111         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
3112         E1000_WRITE_FLUSH(hw);
3113
3114         i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
3115         i2cparams |= E1000_I2CBB_EN;
3116         i2cparams |= E1000_I2C_DATA_OE_N;
3117         i2cparams |= E1000_I2C_CLK_OE_N;
3118         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
3119         E1000_WRITE_FLUSH(hw);
3120
3121         return ret_val;
3122 }
3123
3124 /**
3125  *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
3126  *  @hw: pointer to hardware structure
3127  *  @byte_offset: byte offset to read
3128  *  @dev_addr: device address
3129  *  @data: value read
3130  *
3131  *  Performs byte read operation over I2C interface at
3132  *  a specified device address.
3133  **/
3134 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3135                                 u8 dev_addr, u8 *data)
3136 {
3137         s32 status = E1000_SUCCESS;
3138         u32 max_retry = 10;
3139         u32 retry = 1;
3140         u16 swfw_mask = 0;
3141
3142         bool nack = TRUE;
3143
3144         DEBUGFUNC("e1000_read_i2c_byte_generic");
3145
3146         swfw_mask = E1000_SWFW_PHY0_SM;
3147
3148         do {
3149                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3150                     != E1000_SUCCESS) {
3151                         status = E1000_ERR_SWFW_SYNC;
3152                         goto read_byte_out;
3153                 }
3154
3155                 e1000_i2c_start(hw);
3156
3157                 /* Device Address and write indication */
3158                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3159                 if (status != E1000_SUCCESS)
3160                         goto fail;
3161
3162                 status = e1000_get_i2c_ack(hw);
3163                 if (status != E1000_SUCCESS)
3164                         goto fail;
3165
3166                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3167                 if (status != E1000_SUCCESS)
3168                         goto fail;
3169
3170                 status = e1000_get_i2c_ack(hw);
3171                 if (status != E1000_SUCCESS)
3172                         goto fail;
3173
3174                 e1000_i2c_start(hw);
3175
3176                 /* Device Address and read indication */
3177                 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3178                 if (status != E1000_SUCCESS)
3179                         goto fail;
3180
3181                 status = e1000_get_i2c_ack(hw);
3182                 if (status != E1000_SUCCESS)
3183                         goto fail;
3184
3185                 status = e1000_clock_in_i2c_byte(hw, data);
3186                 if (status != E1000_SUCCESS)
3187                         goto fail;
3188
3189                 status = e1000_clock_out_i2c_bit(hw, nack);
3190                 if (status != E1000_SUCCESS)
3191                         goto fail;
3192
3193                 e1000_i2c_stop(hw);
3194                 break;
3195
3196 fail:
3197                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3198                 msec_delay(100);
3199                 e1000_i2c_bus_clear(hw);
3200                 retry++;
3201                 if (retry < max_retry)
3202                         DEBUGOUT("I2C byte read error - Retrying.\n");
3203                 else
3204                         DEBUGOUT("I2C byte read error.\n");
3205
3206         } while (retry < max_retry);
3207
3208         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3209
3210 read_byte_out:
3211
3212         return status;
3213 }
3214
3215 /**
3216  *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3217  *  @hw: pointer to hardware structure
3218  *  @byte_offset: byte offset to write
3219  *  @dev_addr: device address
3220  *  @data: value to write
3221  *
3222  *  Performs byte write operation over I2C interface at
3223  *  a specified device address.
3224  **/
3225 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3226                                  u8 dev_addr, u8 data)
3227 {
3228         s32 status = E1000_SUCCESS;
3229         u32 max_retry = 1;
3230         u32 retry = 0;
3231         u16 swfw_mask = 0;
3232
3233         DEBUGFUNC("e1000_write_i2c_byte_generic");
3234
3235         swfw_mask = E1000_SWFW_PHY0_SM;
3236
3237         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3238                 status = E1000_ERR_SWFW_SYNC;
3239                 goto write_byte_out;
3240         }
3241
3242         do {
3243                 e1000_i2c_start(hw);
3244
3245                 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3246                 if (status != E1000_SUCCESS)
3247                         goto fail;
3248
3249                 status = e1000_get_i2c_ack(hw);
3250                 if (status != E1000_SUCCESS)
3251                         goto fail;
3252
3253                 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3254                 if (status != E1000_SUCCESS)
3255                         goto fail;
3256
3257                 status = e1000_get_i2c_ack(hw);
3258                 if (status != E1000_SUCCESS)
3259                         goto fail;
3260
3261                 status = e1000_clock_out_i2c_byte(hw, data);
3262                 if (status != E1000_SUCCESS)
3263                         goto fail;
3264
3265                 status = e1000_get_i2c_ack(hw);
3266                 if (status != E1000_SUCCESS)
3267                         goto fail;
3268
3269                 e1000_i2c_stop(hw);
3270                 break;
3271
3272 fail:
3273                 e1000_i2c_bus_clear(hw);
3274                 retry++;
3275                 if (retry < max_retry)
3276                         DEBUGOUT("I2C byte write error - Retrying.\n");
3277                 else
3278                         DEBUGOUT("I2C byte write error.\n");
3279         } while (retry < max_retry);
3280
3281         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3282
3283 write_byte_out:
3284
3285         return status;
3286 }
3287
3288 /**
3289  *  e1000_i2c_start - Sets I2C start condition
3290  *  @hw: pointer to hardware structure
3291  *
3292  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
3293  **/
3294 static void e1000_i2c_start(struct e1000_hw *hw)
3295 {
3296         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3297
3298         DEBUGFUNC("e1000_i2c_start");
3299
3300         /* Start condition must begin with data and clock high */
3301         e1000_set_i2c_data(hw, &i2cctl, 1);
3302         e1000_raise_i2c_clk(hw, &i2cctl);
3303
3304         /* Setup time for start condition (4.7us) */
3305         usec_delay(E1000_I2C_T_SU_STA);
3306
3307         e1000_set_i2c_data(hw, &i2cctl, 0);
3308
3309         /* Hold time for start condition (4us) */
3310         usec_delay(E1000_I2C_T_HD_STA);
3311
3312         e1000_lower_i2c_clk(hw, &i2cctl);
3313
3314         /* Minimum low period of clock is 4.7 us */
3315         usec_delay(E1000_I2C_T_LOW);
3316
3317 }
3318
3319 /**
3320  *  e1000_i2c_stop - Sets I2C stop condition
3321  *  @hw: pointer to hardware structure
3322  *
3323  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
3324  **/
3325 static void e1000_i2c_stop(struct e1000_hw *hw)
3326 {
3327         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3328
3329         DEBUGFUNC("e1000_i2c_stop");
3330
3331         /* Stop condition must begin with data low and clock high */
3332         e1000_set_i2c_data(hw, &i2cctl, 0);
3333         e1000_raise_i2c_clk(hw, &i2cctl);
3334
3335         /* Setup time for stop condition (4us) */
3336         usec_delay(E1000_I2C_T_SU_STO);
3337
3338         e1000_set_i2c_data(hw, &i2cctl, 1);
3339
3340         /* bus free time between stop and start (4.7us)*/
3341         usec_delay(E1000_I2C_T_BUF);
3342 }
3343
3344 /**
3345  *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3346  *  @hw: pointer to hardware structure
3347  *  @data: data byte to clock in
3348  *
3349  *  Clocks in one byte data via I2C data/clock
3350  **/
3351 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3352 {
3353         s32 i;
3354         bool bit = 0;
3355
3356         DEBUGFUNC("e1000_clock_in_i2c_byte");
3357
3358         *data = 0;
3359         for (i = 7; i >= 0; i--) {
3360                 e1000_clock_in_i2c_bit(hw, &bit);
3361                 *data |= bit << i;
3362         }
3363
3364         return E1000_SUCCESS;
3365 }
3366
3367 /**
3368  *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3369  *  @hw: pointer to hardware structure
3370  *  @data: data byte clocked out
3371  *
3372  *  Clocks out one byte data via I2C data/clock
3373  **/
3374 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3375 {
3376         s32 status = E1000_SUCCESS;
3377         s32 i;
3378         u32 i2cctl;
3379         bool bit = 0;
3380
3381         DEBUGFUNC("e1000_clock_out_i2c_byte");
3382
3383         for (i = 7; i >= 0; i--) {
3384                 bit = (data >> i) & 0x1;
3385                 status = e1000_clock_out_i2c_bit(hw, bit);
3386
3387                 if (status != E1000_SUCCESS)
3388                         break;
3389         }
3390
3391         /* Release SDA line (set high) */
3392         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3393
3394         i2cctl |= E1000_I2C_DATA_OE_N;
3395         E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3396         E1000_WRITE_FLUSH(hw);
3397
3398         return status;
3399 }
3400
3401 /**
3402  *  e1000_get_i2c_ack - Polls for I2C ACK
3403  *  @hw: pointer to hardware structure
3404  *
3405  *  Clocks in/out one bit via I2C data/clock
3406  **/
3407 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3408 {
3409         s32 status = E1000_SUCCESS;
3410         u32 i = 0;
3411         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3412         u32 timeout = 10;
3413         bool ack = TRUE;
3414
3415         DEBUGFUNC("e1000_get_i2c_ack");
3416
3417         e1000_raise_i2c_clk(hw, &i2cctl);
3418
3419         /* Minimum high period of clock is 4us */
3420         usec_delay(E1000_I2C_T_HIGH);
3421
3422         /* Wait until SCL returns high */
3423         for (i = 0; i < timeout; i++) {
3424                 usec_delay(1);
3425                 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3426                 if (i2cctl & E1000_I2C_CLK_IN)
3427                         break;
3428         }
3429         if (!(i2cctl & E1000_I2C_CLK_IN))
3430                 return E1000_ERR_I2C;
3431
3432         ack = e1000_get_i2c_data(&i2cctl);
3433         if (ack) {
3434                 DEBUGOUT("I2C ack was not received.\n");
3435                 status = E1000_ERR_I2C;
3436         }
3437
3438         e1000_lower_i2c_clk(hw, &i2cctl);
3439
3440         /* Minimum low period of clock is 4.7 us */
3441         usec_delay(E1000_I2C_T_LOW);
3442
3443         return status;
3444 }
3445
3446 /**
3447  *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3448  *  @hw: pointer to hardware structure
3449  *  @data: read data value
3450  *
3451  *  Clocks in one bit via I2C data/clock
3452  **/
3453 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3454 {
3455         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3456
3457         DEBUGFUNC("e1000_clock_in_i2c_bit");
3458
3459         e1000_raise_i2c_clk(hw, &i2cctl);
3460
3461         /* Minimum high period of clock is 4us */
3462         usec_delay(E1000_I2C_T_HIGH);
3463
3464         i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3465         *data = e1000_get_i2c_data(&i2cctl);
3466
3467         e1000_lower_i2c_clk(hw, &i2cctl);
3468
3469         /* Minimum low period of clock is 4.7 us */
3470         usec_delay(E1000_I2C_T_LOW);
3471
3472         return E1000_SUCCESS;
3473 }
3474
3475 /**
3476  *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3477  *  @hw: pointer to hardware structure
3478  *  @data: data value to write
3479  *
3480  *  Clocks out one bit via I2C data/clock
3481  **/
3482 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3483 {
3484         s32 status;
3485         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3486
3487         DEBUGFUNC("e1000_clock_out_i2c_bit");
3488
3489         status = e1000_set_i2c_data(hw, &i2cctl, data);
3490         if (status == E1000_SUCCESS) {
3491                 e1000_raise_i2c_clk(hw, &i2cctl);
3492
3493                 /* Minimum high period of clock is 4us */
3494                 usec_delay(E1000_I2C_T_HIGH);
3495
3496                 e1000_lower_i2c_clk(hw, &i2cctl);
3497
3498                 /* Minimum low period of clock is 4.7 us.
3499                  * This also takes care of the data hold time.
3500                  */
3501                 usec_delay(E1000_I2C_T_LOW);
3502         } else {
3503                 status = E1000_ERR_I2C;
3504                 DEBUGOUT1("I2C data was not set to %X\n", data);
3505         }
3506
3507         return status;
3508 }
3509 /**
3510  *  e1000_raise_i2c_clk - Raises the I2C SCL clock
3511  *  @hw: pointer to hardware structure
3512  *  @i2cctl: Current value of I2CCTL register
3513  *
3514  *  Raises the I2C clock line '0'->'1'
3515  **/
3516 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3517 {
3518         DEBUGFUNC("e1000_raise_i2c_clk");
3519
3520         *i2cctl |= E1000_I2C_CLK_OUT;
3521         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3522         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3523         E1000_WRITE_FLUSH(hw);
3524
3525         /* SCL rise time (1000ns) */
3526         usec_delay(E1000_I2C_T_RISE);
3527 }
3528
3529 /**
3530  *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
3531  *  @hw: pointer to hardware structure
3532  *  @i2cctl: Current value of I2CCTL register
3533  *
3534  *  Lowers the I2C clock line '1'->'0'
3535  **/
3536 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3537 {
3538
3539         DEBUGFUNC("e1000_lower_i2c_clk");
3540
3541         *i2cctl &= ~E1000_I2C_CLK_OUT;
3542         *i2cctl &= ~E1000_I2C_CLK_OE_N;
3543         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3544         E1000_WRITE_FLUSH(hw);
3545
3546         /* SCL fall time (300ns) */
3547         usec_delay(E1000_I2C_T_FALL);
3548 }
3549
3550 /**
3551  *  e1000_set_i2c_data - Sets the I2C data bit
3552  *  @hw: pointer to hardware structure
3553  *  @i2cctl: Current value of I2CCTL register
3554  *  @data: I2C data value (0 or 1) to set
3555  *
3556  *  Sets the I2C data bit
3557  **/
3558 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3559 {
3560         s32 status = E1000_SUCCESS;
3561
3562         DEBUGFUNC("e1000_set_i2c_data");
3563
3564         if (data)
3565                 *i2cctl |= E1000_I2C_DATA_OUT;
3566         else
3567                 *i2cctl &= ~E1000_I2C_DATA_OUT;
3568
3569         *i2cctl &= ~E1000_I2C_DATA_OE_N;
3570         *i2cctl |= E1000_I2C_CLK_OE_N;
3571         E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3572         E1000_WRITE_FLUSH(hw);
3573
3574         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3575         usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3576
3577         *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3578         if (data != e1000_get_i2c_data(i2cctl)) {
3579                 status = E1000_ERR_I2C;
3580                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3581         }
3582
3583         return status;
3584 }
3585
3586 /**
3587  *  e1000_get_i2c_data - Reads the I2C SDA data bit
3588  *  @hw: pointer to hardware structure
3589  *  @i2cctl: Current value of I2CCTL register
3590  *
3591  *  Returns the I2C data bit value
3592  **/
3593 static bool e1000_get_i2c_data(u32 *i2cctl)
3594 {
3595         bool data;
3596
3597         DEBUGFUNC("e1000_get_i2c_data");
3598
3599         if (*i2cctl & E1000_I2C_DATA_IN)
3600                 data = 1;
3601         else
3602                 data = 0;
3603
3604         return data;
3605 }
3606
3607 /**
3608  *  e1000_i2c_bus_clear - Clears the I2C bus
3609  *  @hw: pointer to hardware structure
3610  *
3611  *  Clears the I2C bus by sending nine clock pulses.
3612  *  Used when data line is stuck low.
3613  **/
3614 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3615 {
3616         u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3617         u32 i;
3618
3619         DEBUGFUNC("e1000_i2c_bus_clear");
3620
3621         e1000_i2c_start(hw);
3622
3623         e1000_set_i2c_data(hw, &i2cctl, 1);
3624
3625         for (i = 0; i < 9; i++) {
3626                 e1000_raise_i2c_clk(hw, &i2cctl);
3627
3628                 /* Min high period of clock is 4us */
3629                 usec_delay(E1000_I2C_T_HIGH);
3630
3631                 e1000_lower_i2c_clk(hw, &i2cctl);
3632
3633                 /* Min low period of clock is 4.7us*/
3634                 usec_delay(E1000_I2C_T_LOW);
3635         }
3636
3637         e1000_i2c_start(hw);
3638
3639         /* Put the i2c bus back to default state */
3640         e1000_i2c_stop(hw);
3641 }
3642