sys/dev/e1000/e1000_ich8lan.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2014, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /* 82562G 10/100 Network Connection
  36  * 82562G-2 10/100 Network Connection
  37  * 82562GT 10/100 Network Connection
  38  * 82562GT-2 10/100 Network Connection
  39  * 82562V 10/100 Network Connection
  40  * 82562V-2 10/100 Network Connection
  41  * 82566DC-2 Gigabit Network Connection
  42  * 82566DC Gigabit Network Connection
  43  * 82566DM-2 Gigabit Network Connection
  44  * 82566DM Gigabit Network Connection
  45  * 82566MC Gigabit Network Connection
  46  * 82566MM Gigabit Network Connection
  47  * 82567LM Gigabit Network Connection
  48  * 82567LF Gigabit Network Connection
  49  * 82567V Gigabit Network Connection
  50  * 82567LM-2 Gigabit Network Connection
  51  * 82567LF-2 Gigabit Network Connection
  52  * 82567V-2 Gigabit Network Connection
  53  * 82567LF-3 Gigabit Network Connection
  54  * 82567LM-3 Gigabit Network Connection
  55  * 82567LM-4 Gigabit Network Connection
  56  * 82577LM Gigabit Network Connection
  57  * 82577LC Gigabit Network Connection
  58  * 82578DM Gigabit Network Connection
  59  * 82578DC Gigabit Network Connection
  60  * 82579LM Gigabit Network Connection
  61  * 82579V Gigabit Network Connection
  62  * Ethernet Connection I217-LM
  63  * Ethernet Connection I217-V
  64  * Ethernet Connection I218-V
  65  * Ethernet Connection I218-LM
  66  * Ethernet Connection (2) I218-LM
  67  * Ethernet Connection (2) I218-V
  68  * Ethernet Connection (3) I218-LM
  69  * Ethernet Connection (3) I218-V
  70  */
  71
  72 #include "e1000_api.h"
  73
  74 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  75 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  76 static s32  e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
  77 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw);
  78 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  79 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
  80 static int  e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
  81 static int  e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
  82 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
  83 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
  84                                               u8 *mc_addr_list,
  85                                               u32 mc_addr_count);
  86 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  87 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  88 static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
  89 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  90                                             bool active);
  91 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  92                                             bool active);
  93 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  94                                    u16 words, u16 *data);
  95 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  96                                     u16 words, u16 *data);
  97 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  98 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  99 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
 100                                             u16 *data);
 101 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 102 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 103 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
 104 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
 105 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 106 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 107 static s32  e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 108 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
 109                                            u16 *speed, u16 *duplex);
 110 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 111 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 112 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
 113 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 114 static s32  e1000_setup_led_pchlan(struct e1000_hw *hw);
 115 static s32  e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 116 static s32  e1000_led_on_pchlan(struct e1000_hw *hw);
 117 static s32  e1000_led_off_pchlan(struct e1000_hw *hw);
 118 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 119 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 120 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 121 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 122 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 123                                           u32 offset, u8 *data);
 124 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                           u8 size, u16 *data);
 126 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 127                                           u32 offset, u16 *data);
 128 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 129                                                  u32 offset, u8 byte);
 130 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 131 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 132 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
 133 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 134 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 135 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 136 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr);
 137
 138 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 139 /* Offset 04h HSFSTS */
 140 union ich8_hws_flash_status {
 141         struct ich8_hsfsts {
 142                 u16 flcdone:1; /* bit 0 Flash Cycle Done */
 143                 u16 flcerr:1; /* bit 1 Flash Cycle Error */
 144                 u16 dael:1; /* bit 2 Direct Access error Log */
 145                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
 146                 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
 147                 u16 reserved1:2; /* bit 13:6 Reserved */
 148                 u16 reserved2:6; /* bit 13:6 Reserved */
 149                 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
 150                 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 151         } hsf_status;
 152         u16 regval;
 153 };
 154
 155 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 156 /* Offset 06h FLCTL */
 157 union ich8_hws_flash_ctrl {
 158         struct ich8_hsflctl {
 159                 u16 flcgo:1;   /* 0 Flash Cycle Go */
 160                 u16 flcycle:2;   /* 2:1 Flash Cycle */
 161                 u16 reserved:5;   /* 7:3 Reserved  */
 162                 u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
 163                 u16 flockdn:6;   /* 15:10 Reserved */
 164         } hsf_ctrl;
 165         u16 regval;
 166 };
 167
 168 /* ICH Flash Region Access Permissions */
 169 union ich8_hws_flash_regacc {
 170         struct ich8_flracc {
 171                 u32 grra:8; /* 0:7 GbE region Read Access */
 172                 u32 grwa:8; /* 8:15 GbE region Write Access */
 173                 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
 174                 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 175         } hsf_flregacc;
 176         u16 regval;
 177 };
 178
 179 /**
 180  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 181  *  @hw: pointer to the HW structure
 182  *
 183  *  Test access to the PHY registers by reading the PHY ID registers.  If
 184  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 185  *  otherwise assume the read PHY ID is correct if it is valid.
 186  *
 187  *  Assumes the sw/fw/hw semaphore is already acquired.
 188  **/
 189 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 190 {
 191         u16 phy_reg = 0;
 192         u32 phy_id = 0;
 193         s32 ret_val = 0;
 194         u16 retry_count;
 195         u32 mac_reg = 0;
 196
 197         for (retry_count = 0; retry_count < 2; retry_count++) {
 198                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);
 199                 if (ret_val || (phy_reg == 0xFFFF))
 200                         continue;
 201                 phy_id = (u32)(phy_reg << 16);
 202
 203                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);
 204                 if (ret_val || (phy_reg == 0xFFFF)) {
 205                         phy_id = 0;
 206                         continue;
 207                 }
 208                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 209                 break;
 210         }
 211
 212         if (hw->phy.id) {
 213                 if  (hw->phy.id == phy_id)
 214                         goto out;
 215         } else if (phy_id) {
 216                 hw->phy.id = phy_id;
 217                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 218                 goto out;
 219         }
 220
 221         /* In case the PHY needs to be in mdio slow mode,
 222          * set slow mode and try to get the PHY id again.
 223          */
 224         if (hw->mac.type < e1000_pch_lpt) {
 225                 hw->phy.ops.release(hw);
 226                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 227                 if (!ret_val)
 228                         ret_val = e1000_get_phy_id(hw);
 229                 hw->phy.ops.acquire(hw);
 230         }
 231
 232         if (ret_val)
 233                 return FALSE;
 234 out:
 235         if (hw->mac.type == e1000_pch_lpt) {
 236                 /* Unforce SMBus mode in PHY */
 237                 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);
 238                 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 239                 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);
 240
 241                 /* Unforce SMBus mode in MAC */
 242                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 243                 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 244                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 245         }
 246
 247         return TRUE;
 248 }
 249
 250 /**
 251  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 252  *  @hw: pointer to the HW structure
 253  *
 254  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 255  *  used to reset the PHY to a quiescent state when necessary.
 256  **/
 257 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 258 {
 259         u32 mac_reg;
 260
 261         DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");
 262
 263         /* Set Phy Config Counter to 50msec */
 264         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
 265         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 266         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 267         E1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);
 268
 269         /* Toggle LANPHYPC Value bit */
 270         mac_reg = E1000_READ_REG(hw, E1000_CTRL);
 271         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 272         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 273         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 274         E1000_WRITE_FLUSH(hw);
 275         usec_delay(10);
 276         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 277         E1000_WRITE_REG(hw, E1000_CTRL, mac_reg);
 278         E1000_WRITE_FLUSH(hw);
 279
 280         if (hw->mac.type < e1000_pch_lpt) {
 281                 msec_delay(50);
 282         } else {
 283                 u16 count = 20;
 284
 285                 do {
 286                         msec_delay(5);
 287                 } while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &
 288                            E1000_CTRL_EXT_LPCD) && count--);
 289
 290                 msec_delay(30);
 291         }
 292 }
 293
 294 /**
 295  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 296  *  @hw: pointer to the HW structure
 297  *
 298  *  Workarounds/flow necessary for PHY initialization during driver load
 299  *  and resume paths.
 300  **/
 301 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 302 {
 303         u32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);
 304         s32 ret_val;
 305
 306         DEBUGFUNC("e1000_init_phy_workarounds_pchlan");
 307
 308         /* Gate automatic PHY configuration by hardware on managed and
 309          * non-managed 82579 and newer adapters.
 310          */
 311         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
 312
 313         /* It is not possible to be certain of the current state of ULP
 314          * so forcibly disable it.
 315          */
 316         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 317         e1000_disable_ulp_lpt_lp(hw, TRUE);
 318
 319         ret_val = hw->phy.ops.acquire(hw);
 320         if (ret_val) {
 321                 DEBUGOUT("Failed to initialize PHY flow\n");
 322                 goto out;
 323         }
 324
 325         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 326          * inaccessible and resetting the PHY is not blocked, toggle the
 327          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 328          */
 329         switch (hw->mac.type) {
 330         case e1000_pch_lpt:
 331                 if (e1000_phy_is_accessible_pchlan(hw))
 332                         break;
 333
 334                 /* Before toggling LANPHYPC, see if PHY is accessible by
 335                  * forcing MAC to SMBus mode first.
 336                  */
 337                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 338                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 339                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 340
 341                 /* Wait 50 milliseconds for MAC to finish any retries
 342                  * that it might be trying to perform from previous
 343                  * attempts to acknowledge any phy read requests.
 344                  */
 345                  msec_delay(50);
 346
 347                 /* fall-through */
 348         case e1000_pch2lan:
 349                 if (e1000_phy_is_accessible_pchlan(hw))
 350                         break;
 351
 352                 /* fall-through */
 353         case e1000_pchlan:
 354                 if ((hw->mac.type == e1000_pchlan) &&
 355                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 356                         break;
 357
 358                 if (hw->phy.ops.check_reset_block(hw)) {
 359                         DEBUGOUT("Required LANPHYPC toggle blocked by ME\n");
 360                         ret_val = -E1000_ERR_PHY;
 361                         break;
 362                 }
 363
 364                 /* Toggle LANPHYPC Value bit */
 365                 e1000_toggle_lanphypc_pch_lpt(hw);
 366                 if (hw->mac.type >= e1000_pch_lpt) {
 367                         if (e1000_phy_is_accessible_pchlan(hw))
 368                                 break;
 369
 370                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 371                          * so ensure that the MAC is also out of SMBus mode
 372                          */
 373                         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
 374                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 375                         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
 376
 377                         if (e1000_phy_is_accessible_pchlan(hw))
 378                                 break;
 379
 380                         ret_val = -E1000_ERR_PHY;
 381                 }
 382                 break;
 383         default:
 384                 break;
 385         }
 386
 387         hw->phy.ops.release(hw);
 388         if (!ret_val) {
 389
 390                 /* Check to see if able to reset PHY.  Print error if not */
 391                 if (hw->phy.ops.check_reset_block(hw)) {
 392                         ERROR_REPORT("Reset blocked by ME\n");
 393                         goto out;
 394                 }
 395
 396                 /* Reset the PHY before any access to it.  Doing so, ensures
 397                  * that the PHY is in a known good state before we read/write
 398                  * PHY registers.  The generic reset is sufficient here,
 399                  * because we haven't determined the PHY type yet.
 400                  */
 401                 ret_val = e1000_phy_hw_reset_generic(hw);
 402                 if (ret_val)
 403                         goto out;
 404
 405                 /* On a successful reset, possibly need to wait for the PHY
 406                  * to quiesce to an accessible state before returning control
 407                  * to the calling function.  If the PHY does not quiesce, then
 408                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 409                  *  the PHY is in.
 410                  */
 411                 ret_val = hw->phy.ops.check_reset_block(hw);
 412                 if (ret_val)
 413                         ERROR_REPORT("ME blocked access to PHY after reset\n");
 414         }
 415
 416 out:
 417         /* Ungate automatic PHY configuration on non-managed 82579 */
 418         if ((hw->mac.type == e1000_pch2lan) &&
 419             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 420                 msec_delay(10);
 421                 e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
 422         }
 423
 424         return ret_val;
 425 }
 426
 427 /**
 428  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 429  *  @hw: pointer to the HW structure
 430  *
 431  *  Initialize family-specific PHY parameters and function pointers.
 432  **/
 433 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 434 {
 435         struct e1000_phy_info *phy = &hw->phy;
 436         s32 ret_val;
 437
 438         DEBUGFUNC("e1000_init_phy_params_pchlan");
 439
 440         phy->addr               = 1;
 441         phy->reset_delay_us     = 100;
 442
 443         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 444         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 445         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 446         phy->ops.set_page       = e1000_set_page_igp;
 447         phy->ops.read_reg       = e1000_read_phy_reg_hv;
 448         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 449         phy->ops.read_reg_page  = e1000_read_phy_reg_page_hv;
 450         phy->ops.release        = e1000_release_swflag_ich8lan;
 451         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 452         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 453         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 454         phy->ops.write_reg      = e1000_write_phy_reg_hv;
 455         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 456         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 457         phy->ops.power_up       = e1000_power_up_phy_copper;
 458         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 459         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 460
 461         phy->id = e1000_phy_unknown;
 462
 463         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 464         if (ret_val)
 465                 return ret_val;
 466
 467         if (phy->id == e1000_phy_unknown)
 468                 switch (hw->mac.type) {
 469                 default:
 470                         ret_val = e1000_get_phy_id(hw);
 471                         if (ret_val)
 472                                 return ret_val;
 473                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 474                                 break;
 475                         /* fall-through */
 476                 case e1000_pch2lan:
 477                 case e1000_pch_lpt:
 478                         /* In case the PHY needs to be in mdio slow mode,
 479                          * set slow mode and try to get the PHY id again.
 480                          */
 481                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 482                         if (ret_val)
 483                                 return ret_val;
 484                         ret_val = e1000_get_phy_id(hw);
 485                         if (ret_val)
 486                                 return ret_val;
 487                         break;
 488                 }
 489         phy->type = e1000_get_phy_type_from_id(phy->id);
 490
 491         switch (phy->type) {
 492         case e1000_phy_82577:
 493         case e1000_phy_82579:
 494         case e1000_phy_i217:
 495                 phy->ops.check_polarity = e1000_check_polarity_82577;
 496                 phy->ops.force_speed_duplex =
 497                         e1000_phy_force_speed_duplex_82577;
 498                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 499                 phy->ops.get_info = e1000_get_phy_info_82577;
 500                 phy->ops.commit = e1000_phy_sw_reset_generic;
 501                 break;
 502         case e1000_phy_82578:
 503                 phy->ops.check_polarity = e1000_check_polarity_m88;
 504                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 505                 phy->ops.get_cable_length = e1000_get_cable_length_m88;
 506                 phy->ops.get_info = e1000_get_phy_info_m88;
 507                 break;
 508         default:
 509                 ret_val = -E1000_ERR_PHY;
 510                 break;
 511         }
 512
 513         return ret_val;
 514 }
 515
 516 /**
 517  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 518  *  @hw: pointer to the HW structure
 519  *
 520  *  Initialize family-specific PHY parameters and function pointers.
 521  **/
 522 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 523 {
 524         struct e1000_phy_info *phy = &hw->phy;
 525         s32 ret_val;
 526         u16 i = 0;
 527
 528         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 529
 530         phy->addr               = 1;
 531         phy->reset_delay_us     = 100;
 532
 533         phy->ops.acquire        = e1000_acquire_swflag_ich8lan;
 534         phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
 535         phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 536         phy->ops.get_cfg_done   = e1000_get_cfg_done_ich8lan;
 537         phy->ops.read_reg       = e1000_read_phy_reg_igp;
 538         phy->ops.release        = e1000_release_swflag_ich8lan;
 539         phy->ops.reset          = e1000_phy_hw_reset_ich8lan;
 540         phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
 541         phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
 542         phy->ops.write_reg      = e1000_write_phy_reg_igp;
 543         phy->ops.power_up       = e1000_power_up_phy_copper;
 544         phy->ops.power_down     = e1000_power_down_phy_copper_ich8lan;
 545
 546         /* We may need to do this twice - once for IGP and if that fails,
 547          * we'll set BM func pointers and try again
 548          */
 549         ret_val = e1000_determine_phy_address(hw);
 550         if (ret_val) {
 551                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 552                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 553                 ret_val = e1000_determine_phy_address(hw);
 554                 if (ret_val) {
 555                         DEBUGOUT("Cannot determine PHY addr. Erroring out\n");
 556                         return ret_val;
 557                 }
 558         }
 559
 560         phy->id = 0;
 561         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 562                (i++ < 100)) {
 563                 msec_delay(1);
 564                 ret_val = e1000_get_phy_id(hw);
 565                 if (ret_val)
 566                         return ret_val;
 567         }
 568
 569         /* Verify phy id */
 570         switch (phy->id) {
 571         case IGP03E1000_E_PHY_ID:
 572                 phy->type = e1000_phy_igp_3;
 573                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 574                 phy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;
 575                 phy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;
 576                 phy->ops.get_info = e1000_get_phy_info_igp;
 577                 phy->ops.check_polarity = e1000_check_polarity_igp;
 578                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 579                 break;
 580         case IFE_E_PHY_ID:
 581         case IFE_PLUS_E_PHY_ID:
 582         case IFE_C_E_PHY_ID:
 583                 phy->type = e1000_phy_ife;
 584                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 585                 phy->ops.get_info = e1000_get_phy_info_ife;
 586                 phy->ops.check_polarity = e1000_check_polarity_ife;
 587                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 588                 break;
 589         case BME1000_E_PHY_ID:
 590                 phy->type = e1000_phy_bm;
 591                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 592                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 593                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 594                 phy->ops.commit = e1000_phy_sw_reset_generic;
 595                 phy->ops.get_info = e1000_get_phy_info_m88;
 596                 phy->ops.check_polarity = e1000_check_polarity_m88;
 597                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 598                 break;
 599         default:
 600                 return -E1000_ERR_PHY;
 601                 break;
 602         }
 603
 604         return E1000_SUCCESS;
 605 }
 606
 607 /**
 608  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 609  *  @hw: pointer to the HW structure
 610  *
 611  *  Initialize family-specific NVM parameters and function
 612  *  pointers.
 613  **/
 614 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 615 {
 616         struct e1000_nvm_info *nvm = &hw->nvm;
 617         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 618         u32 gfpreg, sector_base_addr, sector_end_addr;
 619         u16 i;
 620
 621         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 622
 623         /* Can't read flash registers if the register set isn't mapped. */
 624         nvm->type = e1000_nvm_flash_sw;
 625         if (!hw->flash_address) {
 626                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 627                 return -E1000_ERR_CONFIG;
 628         }
 629
 630         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 631
 632         /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 633          * Add 1 to sector_end_addr since this sector is included in
 634          * the overall size.
 635          */
 636         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 637         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 638
 639         /* flash_base_addr is byte-aligned */
 640         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 641
 642         /* find total size of the NVM, then cut in half since the total
 643          * size represents two separate NVM banks.
 644          */
 645         nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 646                                 << FLASH_SECTOR_ADDR_SHIFT);
 647         nvm->flash_bank_size /= 2;
 648         /* Adjust to word count */
 649         nvm->flash_bank_size /= sizeof(u16);
 650
 651         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 652
 653         /* Clear shadow ram */
 654         for (i = 0; i < nvm->word_size; i++) {
 655                 dev_spec->shadow_ram[i].modified = FALSE;
 656                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 657         }
 658
 659         E1000_MUTEX_INIT(&dev_spec->nvm_mutex);
 660         E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 661
 662         /* Function Pointers */
 663         nvm->ops.acquire        = e1000_acquire_nvm_ich8lan;
 664         nvm->ops.release        = e1000_release_nvm_ich8lan;
 665         nvm->ops.read           = e1000_read_nvm_ich8lan;
 666         nvm->ops.update         = e1000_update_nvm_checksum_ich8lan;
 667         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 668         nvm->ops.validate       = e1000_validate_nvm_checksum_ich8lan;
 669         nvm->ops.write          = e1000_write_nvm_ich8lan;
 670
 671         return E1000_SUCCESS;
 672 }
 673
 674 /**
 675  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 676  *  @hw: pointer to the HW structure
 677  *
 678  *  Initialize family-specific MAC parameters and function
 679  *  pointers.
 680  **/
 681 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 682 {
 683         struct e1000_mac_info *mac = &hw->mac;
 684
 685         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 686
 687         /* Set media type function pointer */
 688         hw->phy.media_type = e1000_media_type_copper;
 689
 690         /* Set mta register count */
 691         mac->mta_reg_count = 32;
 692         /* Set rar entry count */
 693         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 694         if (mac->type == e1000_ich8lan)
 695                 mac->rar_entry_count--;
 696         /* Set if part includes ASF firmware */
 697         mac->asf_firmware_present = TRUE;
 698         /* FWSM register */
 699         mac->has_fwsm = TRUE;
 700         /* ARC subsystem not supported */
 701         mac->arc_subsystem_valid = FALSE;
 702         /* Adaptive IFS supported */
 703         mac->adaptive_ifs = TRUE;
 704
 705         /* Function pointers */
 706
 707         /* bus type/speed/width */
 708         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 709         /* function id */
 710         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 711         /* reset */
 712         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 713         /* hw initialization */
 714         mac->ops.init_hw = e1000_init_hw_ich8lan;
 715         /* link setup */
 716         mac->ops.setup_link = e1000_setup_link_ich8lan;
 717         /* physical interface setup */
 718         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 719         /* check for link */
 720         mac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;
 721         /* link info */
 722         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 723         /* multicast address update */
 724         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 725         /* clear hardware counters */
 726         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 727
 728         /* LED and other operations */
 729         switch (mac->type) {
 730         case e1000_ich8lan:
 731         case e1000_ich9lan:
 732         case e1000_ich10lan:
 733                 /* check management mode */
 734                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 735                 /* ID LED init */
 736                 mac->ops.id_led_init = e1000_id_led_init_generic;
 737                 /* blink LED */
 738                 mac->ops.blink_led = e1000_blink_led_generic;
 739                 /* setup LED */
 740                 mac->ops.setup_led = e1000_setup_led_generic;
 741                 /* cleanup LED */
 742                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 743                 /* turn on/off LED */
 744                 mac->ops.led_on = e1000_led_on_ich8lan;
 745                 mac->ops.led_off = e1000_led_off_ich8lan;
 746                 break;
 747         case e1000_pch2lan:
 748                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 749                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 750                 /* fall-through */
 751         case e1000_pch_lpt:
 752                 /* multicast address update for pch2 */
 753                 mac->ops.update_mc_addr_list =
 754                         e1000_update_mc_addr_list_pch2lan;
 755         case e1000_pchlan:
 756                 /* check management mode */
 757                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 758                 /* ID LED init */
 759                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 760                 /* setup LED */
 761                 mac->ops.setup_led = e1000_setup_led_pchlan;
 762                 /* cleanup LED */
 763                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 764                 /* turn on/off LED */
 765                 mac->ops.led_on = e1000_led_on_pchlan;
 766                 mac->ops.led_off = e1000_led_off_pchlan;
 767                 break;
 768         default:
 769                 break;
 770         }
 771
 772         if (mac->type == e1000_pch_lpt) {
 773                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 774                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 775                 mac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;
 776                 mac->ops.set_obff_timer = e1000_set_obff_timer_pch_lpt;
 777         }
 778
 779         /* Enable PCS Lock-loss workaround for ICH8 */
 780         if (mac->type == e1000_ich8lan)
 781                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 782
 783         return E1000_SUCCESS;
 784 }
 785
 786 /**
 787  *  __e1000_access_emi_reg_locked - Read/write EMI register
 788  *  @hw: pointer to the HW structure
 789  *  @addr: EMI address to program
 790  *  @data: pointer to value to read/write from/to the EMI address
 791  *  @read: boolean flag to indicate read or write
 792  *
 793  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 794  **/
 795 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 796                                          u16 *data, bool read)
 797 {
 798         s32 ret_val;
 799
 800         DEBUGFUNC("__e1000_access_emi_reg_locked");
 801
 802         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);
 803         if (ret_val)
 804                 return ret_val;
 805
 806         if (read)
 807                 ret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,
 808                                                       data);
 809         else
 810                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
 811                                                        *data);
 812
 813         return ret_val;
 814 }
 815
 816 /**
 817  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 818  *  @hw: pointer to the HW structure
 819  *  @addr: EMI address to program
 820  *  @data: value to be read from the EMI address
 821  *
 822  *  Assumes the SW/FW/HW Semaphore is already acquired.
 823  **/
 824 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 825 {
 826         DEBUGFUNC("e1000_read_emi_reg_locked");
 827
 828         return __e1000_access_emi_reg_locked(hw, addr, data, TRUE);
 829 }
 830
 831 /**
 832  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 833  *  @hw: pointer to the HW structure
 834  *  @addr: EMI address to program
 835  *  @data: value to be written to the EMI address
 836  *
 837  *  Assumes the SW/FW/HW Semaphore is already acquired.
 838  **/
 839 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 840 {
 841         DEBUGFUNC("e1000_read_emi_reg_locked");
 842
 843         return __e1000_access_emi_reg_locked(hw, addr, &data, FALSE);
 844 }
 845
 846 /**
 847  *  e1000_set_eee_pchlan - Enable/disable EEE support
 848  *  @hw: pointer to the HW structure
 849  *
 850  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 851  *  the link and the EEE capabilities of the link partner.  The LPI Control
 852  *  register bits will remain set only if/when link is up.
 853  *
 854  *  EEE LPI must not be asserted earlier than one second after link is up.
 855  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 856  *  can be link issues with some switches.  Other devices can have EEE LPI
 857  *  enabled immediately upon link up since they have a timer in hardware which
 858  *  prevents LPI from being asserted too early.
 859  **/
 860 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 861 {
 862         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 863         s32 ret_val;
 864         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 865
 866         DEBUGFUNC("e1000_set_eee_pchlan");
 867
 868         switch (hw->phy.type) {
 869         case e1000_phy_82579:
 870                 lpa = I82579_EEE_LP_ABILITY;
 871                 pcs_status = I82579_EEE_PCS_STATUS;
 872                 adv_addr = I82579_EEE_ADVERTISEMENT;
 873                 break;
 874         case e1000_phy_i217:
 875                 lpa = I217_EEE_LP_ABILITY;
 876                 pcs_status = I217_EEE_PCS_STATUS;
 877                 adv_addr = I217_EEE_ADVERTISEMENT;
 878                 break;
 879         default:
 880                 return E1000_SUCCESS;
 881         }
 882
 883         ret_val = hw->phy.ops.acquire(hw);
 884         if (ret_val)
 885                 return ret_val;
 886
 887         ret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 888         if (ret_val)
 889                 goto release;
 890
 891         /* Clear bits that enable EEE in various speeds */
 892         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 893
 894         /* Enable EEE if not disabled by user */
 895         if (!dev_spec->eee_disable) {
 896                 /* Save off link partner's EEE ability */
 897                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 898                                                     &dev_spec->eee_lp_ability);
 899                 if (ret_val)
 900                         goto release;
 901
 902                 /* Read EEE advertisement */
 903                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 904                 if (ret_val)
 905                         goto release;
 906
 907                 /* Enable EEE only for speeds in which the link partner is
 908                  * EEE capable and for which we advertise EEE.
 909                  */
 910                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 911                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 912
 913                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 914                         hw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);
 915                         if (data & NWAY_LPAR_100TX_FD_CAPS)
 916                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 917                         else
 918                                 /* EEE is not supported in 100Half, so ignore
 919                                  * partner's EEE in 100 ability if full-duplex
 920                                  * is not advertised.
 921                                  */
 922                                 dev_spec->eee_lp_ability &=
 923                                     ~I82579_EEE_100_SUPPORTED;
 924                 }
 925         }
 926
 927         if (hw->phy.type == e1000_phy_82579) {
 928                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 929                                                     &data);
 930                 if (ret_val)
 931                         goto release;
 932
 933                 data &= ~I82579_LPI_100_PLL_SHUT;
 934                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 935                                                      data);
 936         }
 937
 938         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 939         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 940         if (ret_val)
 941                 goto release;
 942
 943         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 944 release:
 945         hw->phy.ops.release(hw);
 946
 947         return ret_val;
 948 }
 949
 950 /**
 951  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 952  *  @hw:   pointer to the HW structure
 953  *  @link: link up bool flag
 954  *
 955  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 956  *  preventing further DMA write requests.  Workaround the issue by disabling
 957  *  the de-assertion of the clock request when in 1Gpbs mode.
 958  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 959  *  speeds in order to avoid Tx hangs.
 960  **/
 961 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 962 {
 963         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
 964         u32 status = E1000_READ_REG(hw, E1000_STATUS);
 965         s32 ret_val = E1000_SUCCESS;
 966         u16 reg;
 967
 968         if (link && (status & E1000_STATUS_SPEED_1000)) {
 969                 ret_val = hw->phy.ops.acquire(hw);
 970                 if (ret_val)
 971                         return ret_val;
 972
 973                 ret_val =
 974                     e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 975                                                &reg);
 976                 if (ret_val)
 977                         goto release;
 978
 979                 ret_val =
 980                     e1000_write_kmrn_reg_locked(hw,
 981                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 982                                                 reg &
 983                                                 ~E1000_KMRNCTRLSTA_K1_ENABLE);
 984                 if (ret_val)
 985                         goto release;
 986
 987                 usec_delay(10);
 988
 989                 E1000_WRITE_REG(hw, E1000_FEXTNVM6,
 990                                 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 991
 992                 ret_val =
 993                     e1000_write_kmrn_reg_locked(hw,
 994                                                 E1000_KMRNCTRLSTA_K1_CONFIG,
 995                                                 reg);
 996 release:
 997                 hw->phy.ops.release(hw);
 998         } else {
 999                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
1000                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
1001
1002                 if (!link || ((status & E1000_STATUS_SPEED_100) &&
1003                               (status & E1000_STATUS_FD)))
1004                         goto update_fextnvm6;
1005
1006                 ret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, &reg);
1007                 if (ret_val)
1008                         return ret_val;
1009
1010                 /* Clear link status transmit timeout */
1011                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
1012
1013                 if (status & E1000_STATUS_SPEED_100) {
1014                         /* Set inband Tx timeout to 5x10us for 100Half */
1015                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1016
1017                         /* Do not extend the K1 entry latency for 100Half */
1018                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1019                 } else {
1020                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
1021                         reg |= 50 <<
1022                                I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
1023
1024                         /* Extend the K1 entry latency for 10 Mbps */
1025                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
1026                 }
1027
1028                 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);
1029                 if (ret_val)
1030                         return ret_val;
1031
1032 update_fextnvm6:
1033                 E1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);
1034         }
1035
1036         return ret_val;
1037 }
1038
1039 static u64 e1000_ltr2ns(u16 ltr)
1040 {
1041         u32 value, scale;
1042
1043         /* Determine the latency in nsec based on the LTR value & scale */
1044         value = ltr & E1000_LTRV_VALUE_MASK;
1045         scale = (ltr & E1000_LTRV_SCALE_MASK) >> E1000_LTRV_SCALE_SHIFT;
1046
1047         return value * (1 << (scale * E1000_LTRV_SCALE_FACTOR));
1048 }
1049
1050 /**
1051  *  e1000_platform_pm_pch_lpt - Set platform power management values
1052  *  @hw: pointer to the HW structure
1053  *  @link: bool indicating link status
1054  *
1055  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1056  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1057  *  when link is up (which must not exceed the maximum latency supported
1058  *  by the platform), otherwise specify there is no LTR requirement.
1059  *  Unlike TRUE-PCIe devices which set the LTR maximum snoop/no-snoop
1060  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1061  *  Capability register set, on this device LTR is set by writing the
1062  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1063  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1064  *  message to the PMC.
1065  *
1066  *  Use the LTR value to calculate the Optimized Buffer Flush/Fill (OBFF)
1067  *  high-water mark.
1068  **/
1069 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1070 {
1071         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1072                   link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1073         u16 lat_enc = 0;        /* latency encoded */
1074         s32 obff_hwm = 0;
1075
1076         DEBUGFUNC("e1000_platform_pm_pch_lpt");
1077
1078         if (link) {
1079                 u16 speed, duplex, scale = 0;
1080                 u16 max_snoop, max_nosnoop;
1081                 u16 max_ltr_enc;        /* max LTR latency encoded */
1082                 s64 lat_ns;             /* latency (ns) */
1083                 s64 value;
1084                 u32 rxa;
1085
1086                 if (!hw->mac.max_frame_size) {
1087                         DEBUGOUT("max_frame_size not set.\n");
1088                         return -E1000_ERR_CONFIG;
1089                 }
1090
1091                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1092                 if (!speed) {
1093                         DEBUGOUT("Speed not set.\n");
1094                         return -E1000_ERR_CONFIG;
1095                 }
1096
1097                 /* Rx Packet Buffer Allocation size (KB) */
1098                 rxa = E1000_READ_REG(hw, E1000_PBA) & E1000_PBA_RXA_MASK;
1099
1100                 /* Determine the maximum latency tolerated by the device.
1101                  *
1102                  * Per the PCIe spec, the tolerated latencies are encoded as
1103                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1104                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1105                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1106                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1107                  */
1108                 lat_ns = ((s64)rxa * 1024 -
1109                           (2 * (s64)hw->mac.max_frame_size)) * 8 * 1000;
1110                 if (lat_ns < 0)
1111                         lat_ns = 0;
1112                 else
1113                         lat_ns /= speed;
1114
1115                 value = lat_ns;
1116                 while (value > E1000_LTRV_VALUE_MASK) {
1117                         scale++;
1118                         value = E1000_DIVIDE_ROUND_UP(value, (1 << 5));
1119                 }
1120                 if (scale > E1000_LTRV_SCALE_MAX) {
1121                         DEBUGOUT1("Invalid LTR latency scale %d\n", scale);
1122                         return -E1000_ERR_CONFIG;
1123                 }
1124                 lat_enc = (u16)((scale << E1000_LTRV_SCALE_SHIFT) | value);
1125
1126                 /* Determine the maximum latency tolerated by the platform */
1127                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT, &max_snoop);
1128                 e1000_read_pci_cfg(hw, E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1129                 max_ltr_enc = E1000_MAX(max_snoop, max_nosnoop);
1130
1131                 if (lat_enc > max_ltr_enc) {
1132                         lat_enc = max_ltr_enc;
1133                         lat_ns = e1000_ltr2ns(max_ltr_enc);
1134                 }
1135
1136                 if (lat_ns) {
1137                         lat_ns *= speed * 1000;
1138                         lat_ns /= 8;
1139                         lat_ns /= 1000000000;
1140                         obff_hwm = (s32)(rxa - lat_ns);
1141                 }
1142                 if ((obff_hwm < 0) || (obff_hwm > E1000_SVT_OFF_HWM_MASK)) {
1143                         DEBUGOUT1("Invalid high water mark %d\n", obff_hwm);
1144                         return -E1000_ERR_CONFIG;
1145                 }
1146         }
1147
1148         /* Set Snoop and No-Snoop latencies the same */
1149         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1150         E1000_WRITE_REG(hw, E1000_LTRV, reg);
1151
1152         /* Set OBFF high water mark */
1153         reg = E1000_READ_REG(hw, E1000_SVT) & ~E1000_SVT_OFF_HWM_MASK;
1154         reg |= obff_hwm;
1155         E1000_WRITE_REG(hw, E1000_SVT, reg);
1156
1157         /* Enable OBFF */
1158         reg = E1000_READ_REG(hw, E1000_SVCR);
1159         reg |= E1000_SVCR_OFF_EN;
1160         /* Always unblock interrupts to the CPU even when the system is
1161          * in OBFF mode. This ensures that small round-robin traffic
1162          * (like ping) does not get dropped or experience long latency.
1163          */
1164         reg |= E1000_SVCR_OFF_MASKINT;
1165         E1000_WRITE_REG(hw, E1000_SVCR, reg);
1166
1167         return E1000_SUCCESS;
1168 }
1169
1170 /**
1171  *  e1000_set_obff_timer_pch_lpt - Update Optimized Buffer Flush/Fill timer
1172  *  @hw: pointer to the HW structure
1173  *  @itr: interrupt throttling rate
1174  *
1175  *  Configure OBFF with the updated interrupt rate.
1176  **/
1177 static s32 e1000_set_obff_timer_pch_lpt(struct e1000_hw *hw, u32 itr)
1178 {
1179         u32 svcr;
1180         s32 timer;
1181
1182         DEBUGFUNC("e1000_set_obff_timer_pch_lpt");
1183
1184         /* Convert ITR value into microseconds for OBFF timer */
1185         timer = itr & E1000_ITR_MASK;
1186         timer = (timer * E1000_ITR_MULT) / 1000;
1187
1188         if ((timer < 0) || (timer > E1000_ITR_MASK)) {
1189                 DEBUGOUT1("Invalid OBFF timer %d\n", timer);
1190                 return -E1000_ERR_CONFIG;
1191         }
1192
1193         svcr = E1000_READ_REG(hw, E1000_SVCR);
1194         svcr &= ~E1000_SVCR_OFF_TIMER_MASK;
1195         svcr |= timer << E1000_SVCR_OFF_TIMER_SHIFT;
1196         E1000_WRITE_REG(hw, E1000_SVCR, svcr);
1197
1198         return E1000_SUCCESS;
1199 }
1200
1201 /**
1202  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1203  *  @hw: pointer to the HW structure
1204  *  @to_sx: boolean indicating a system power state transition to Sx
1205  *
1206  *  When link is down, configure ULP mode to significantly reduce the power
1207  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1208  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1209  *  system, configure the ULP mode by software.
1210  */
1211 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1212 {
1213         u32 mac_reg;
1214         s32 ret_val = E1000_SUCCESS;
1215         u16 phy_reg;
1216
1217         if ((hw->mac.type < e1000_pch_lpt) ||
1218             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1219             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1220             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1221             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1222             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1223                 return 0;
1224
1225         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1226                 /* Request ME configure ULP mode in the PHY */
1227                 mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1228                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1229                 E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1230
1231                 goto out;
1232         }
1233
1234         if (!to_sx) {
1235                 int i = 0;
1236
1237                 /* Poll up to 5 seconds for Cable Disconnected indication */
1238                 while (!(E1000_READ_REG(hw, E1000_FEXT) &
1239                          E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1240                         /* Bail if link is re-acquired */
1241                         if (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)
1242                                 return -E1000_ERR_PHY;
1243
1244                         if (i++ == 100)
1245                                 break;
1246
1247                         msec_delay(50);
1248                 }
1249                 DEBUGOUT2("CABLE_DISCONNECTED %s set after %dmsec\n",
1250                          (E1000_READ_REG(hw, E1000_FEXT) &
1251                           E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not",
1252                          i * 50);
1253         }
1254
1255         ret_val = hw->phy.ops.acquire(hw);
1256         if (ret_val)
1257                 goto out;
1258
1259         /* Force SMBus mode in PHY */
1260         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1261         if (ret_val)
1262                 goto release;
1263         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1264         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1265
1266         /* Force SMBus mode in MAC */
1267         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1268         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1269         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1270
1271         /* Set Inband ULP Exit, Reset to SMBus mode and
1272          * Disable SMBus Release on PERST# in PHY
1273          */
1274         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1275         if (ret_val)
1276                 goto release;
1277         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1278                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1279         if (to_sx) {
1280                 if (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)
1281                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1282
1283                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1284         } else {
1285                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1286         }
1287         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1288
1289         /* Set Disable SMBus Release on PERST# in MAC */
1290         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1291         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1292         E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1293
1294         /* Commit ULP changes in PHY by starting auto ULP configuration */
1295         phy_reg |= I218_ULP_CONFIG1_START;
1296         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1297 release:
1298         hw->phy.ops.release(hw);
1299 out:
1300         if (ret_val) {
1301                 DEBUGOUT1("Error in ULP enable flow: %d\n", ret_val);
1302         } else
1303                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1304
1305         return ret_val;
1306 }
1307
1308 /**
1309  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1310  *  @hw: pointer to the HW structure
1311  *  @force: boolean indicating whether or not to force disabling ULP
1312  *
1313  *  Un-configure ULP mode when link is up, the system is transitioned from
1314  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1315  *  system, poll for an indication from ME that ULP has been un-configured.
1316  *  If not on an ME enabled system, un-configure the ULP mode by software.
1317  *
1318  *  During nominal operation, this function is called when link is acquired
1319  *  to disable ULP mode (force=FALSE); otherwise, for example when unloading
1320  *  the driver or during Sx->S0 transitions, this is called with force=TRUE
1321  *  to forcibly disable ULP.
1322  */
1323 s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1324 {
1325         s32 ret_val = E1000_SUCCESS;
1326         u32 mac_reg;
1327         u16 phy_reg;
1328         int i = 0;
1329
1330         if ((hw->mac.type < e1000_pch_lpt) ||
1331             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1332             (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||
1333             (hw->device_id == E1000_DEV_ID_PCH_I218_LM2) ||
1334             (hw->device_id == E1000_DEV_ID_PCH_I218_V2) ||
1335             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1336                 return 0;
1337
1338         if (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {
1339                 if (force) {
1340                         /* Request ME un-configure ULP mode in the PHY */
1341                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1342                         mac_reg &= ~E1000_H2ME_ULP;
1343                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1344                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1345                 }
1346
1347                 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1348                 while (E1000_READ_REG(hw, E1000_FWSM) &
1349                        E1000_FWSM_ULP_CFG_DONE) {
1350                         if (i++ == 10) {
1351                                 ret_val = -E1000_ERR_PHY;
1352                                 goto out;
1353                         }
1354
1355                         msec_delay(10);
1356                 }
1357                 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1358
1359                 if (force) {
1360                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1361                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1362                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1363                 } else {
1364                         /* Clear H2ME.ULP after ME ULP configuration */
1365                         mac_reg = E1000_READ_REG(hw, E1000_H2ME);
1366                         mac_reg &= ~E1000_H2ME_ULP;
1367                         E1000_WRITE_REG(hw, E1000_H2ME, mac_reg);
1368                 }
1369
1370                 goto out;
1371         }
1372
1373         ret_val = hw->phy.ops.acquire(hw);
1374         if (ret_val)
1375                 goto out;
1376
1377         if (force)
1378                 /* Toggle LANPHYPC Value bit */
1379                 e1000_toggle_lanphypc_pch_lpt(hw);
1380
1381         /* Unforce SMBus mode in PHY */
1382         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1383         if (ret_val) {
1384                 /* The MAC might be in PCIe mode, so temporarily force to
1385                  * SMBus mode in order to access the PHY.
1386                  */
1387                 mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1388                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1389                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1390
1391                 msec_delay(50);
1392
1393                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1394                                                        &phy_reg);
1395                 if (ret_val)
1396                         goto release;
1397         }
1398         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1399         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1400
1401         /* Unforce SMBus mode in MAC */
1402         mac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1403         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1404         E1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);
1405
1406         /* When ULP mode was previously entered, K1 was disabled by the
1407          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1408          */
1409         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1410         if (ret_val)
1411                 goto release;
1412         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1413         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1414
1415         /* Clear ULP enabled configuration */
1416         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1417         if (ret_val)
1418                 goto release;
1419                 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1420                              I218_ULP_CONFIG1_STICKY_ULP |
1421                              I218_ULP_CONFIG1_RESET_TO_SMBUS |
1422                              I218_ULP_CONFIG1_WOL_HOST |
1423                              I218_ULP_CONFIG1_INBAND_EXIT |
1424                              I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1425                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1426
1427                 /* Commit ULP changes by starting auto ULP configuration */
1428                 phy_reg |= I218_ULP_CONFIG1_START;
1429                 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1430
1431                 /* Clear Disable SMBus Release on PERST# in MAC */
1432                 mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);
1433                 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1434                 E1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);
1435
1436 release:
1437         hw->phy.ops.release(hw);
1438         if (force) {
1439                 hw->phy.ops.reset(hw);
1440                 msec_delay(50);
1441         }
1442 out:
1443         if (ret_val) {
1444                 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1445         } else
1446                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1447
1448         return ret_val;
1449 }
1450
1451 /**
1452  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1453  *  @hw: pointer to the HW structure
1454  *
1455  *  Checks to see of the link status of the hardware has changed.  If a
1456  *  change in link status has been detected, then we read the PHY registers
1457  *  to get the current speed/duplex if link exists.
1458  **/
1459 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1460 {
1461         struct e1000_mac_info *mac = &hw->mac;
1462         s32 ret_val;
1463         bool link;
1464         u16 phy_reg;
1465
1466         DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
1467
1468         /* We only want to go out to the PHY registers to see if Auto-Neg
1469          * has completed and/or if our link status has changed.  The
1470          * get_link_status flag is set upon receiving a Link Status
1471          * Change or Rx Sequence Error interrupt.
1472          */
1473         if (!mac->get_link_status)
1474                 return E1000_SUCCESS;
1475
1476                 /* First we want to see if the MII Status Register reports
1477                  * link.  If so, then we want to get the current speed/duplex
1478                  * of the PHY.
1479                  */
1480                 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1481                 if (ret_val)
1482                         return ret_val;
1483
1484         if (hw->mac.type == e1000_pchlan) {
1485                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1486                 if (ret_val)
1487                         return ret_val;
1488         }
1489
1490         /* When connected at 10Mbps half-duplex, some parts are excessively
1491          * aggressive resulting in many collisions. To avoid this, increase
1492          * the IPG and reduce Rx latency in the PHY.
1493          */
1494         if (((hw->mac.type == e1000_pch2lan) ||
1495              (hw->mac.type == e1000_pch_lpt)) && link) {
1496                 u32 reg;
1497                 reg = E1000_READ_REG(hw, E1000_STATUS);
1498                 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1499                         u16 emi_addr;
1500
1501                         reg = E1000_READ_REG(hw, E1000_TIPG);
1502                         reg &= ~E1000_TIPG_IPGT_MASK;
1503                         reg |= 0xFF;
1504                         E1000_WRITE_REG(hw, E1000_TIPG, reg);
1505
1506                         /* Reduce Rx latency in analog PHY */
1507                         ret_val = hw->phy.ops.acquire(hw);
1508                         if (ret_val)
1509                                 return ret_val;
1510
1511                         if (hw->mac.type == e1000_pch2lan)
1512                                 emi_addr = I82579_RX_CONFIG;
1513                         else
1514                                 emi_addr = I217_RX_CONFIG;
1515                         ret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);
1516
1517                         hw->phy.ops.release(hw);
1518
1519                         if (ret_val)
1520                                 return ret_val;
1521                 }
1522         }
1523
1524         /* Work-around I218 hang issue */
1525         if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1526             (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1527             (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) ||
1528             (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) {
1529                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1530                 if (ret_val)
1531                         return ret_val;
1532         }
1533         if (hw->mac.type == e1000_pch_lpt) {
1534                 /* Set platform power management values for
1535                  * Latency Tolerance Reporting (LTR)
1536                  * Optimized Buffer Flush/Fill (OBFF)
1537                  */
1538                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1539                 if (ret_val)
1540                         return ret_val;
1541         }
1542
1543         /* Clear link partner's EEE ability */
1544         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1545
1546         if (!link)
1547                 return E1000_SUCCESS; /* No link detected */
1548
1549         mac->get_link_status = FALSE;
1550
1551         switch (hw->mac.type) {
1552         case e1000_pch2lan:
1553                 ret_val = e1000_k1_workaround_lv(hw);
1554                 if (ret_val)
1555                         return ret_val;
1556                 /* fall-thru */
1557         case e1000_pchlan:
1558                 if (hw->phy.type == e1000_phy_82578) {
1559                         ret_val = e1000_link_stall_workaround_hv(hw);
1560                         if (ret_val)
1561                                 return ret_val;
1562                 }
1563
1564                 /* Workaround for PCHx parts in half-duplex:
1565                  * Set the number of preambles removed from the packet
1566                  * when it is passed from the PHY to the MAC to prevent
1567                  * the MAC from misinterpreting the packet type.
1568                  */
1569                 hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1570                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1571
1572                 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
1573                     E1000_STATUS_FD)
1574                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1575
1576                 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1577                 break;
1578         default:
1579                 break;
1580         }
1581
1582         /* Check if there was DownShift, must be checked
1583          * immediately after link-up
1584          */
1585         e1000_check_downshift_generic(hw);
1586
1587         /* Enable/Disable EEE after link up */
1588         if (hw->phy.type > e1000_phy_82579) {
1589                 ret_val = e1000_set_eee_pchlan(hw);
1590                 if (ret_val)
1591                         return ret_val;
1592         }
1593
1594         /* If we are forcing speed/duplex, then we simply return since
1595          * we have already determined whether we have link or not.
1596          */
1597         if (!mac->autoneg)
1598                 return -E1000_ERR_CONFIG;
1599
1600         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1601          * of MAC speed/duplex configuration.  So we only need to
1602          * configure Collision Distance in the MAC.
1603          */
1604         mac->ops.config_collision_dist(hw);
1605
1606         /* Configure Flow Control now that Auto-Neg has completed.
1607          * First, we need to restore the desired flow control
1608          * settings because we may have had to re-autoneg with a
1609          * different link partner.
1610          */
1611         ret_val = e1000_config_fc_after_link_up_generic(hw);
1612         if (ret_val)
1613                 DEBUGOUT("Error configuring flow control\n");
1614
1615         return ret_val;
1616 }
1617
1618 /**
1619  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
1620  *  @hw: pointer to the HW structure
1621  *
1622  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
1623  **/
1624 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
1625 {
1626         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
1627
1628         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
1629         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
1630         switch (hw->mac.type) {
1631         case e1000_ich8lan:
1632         case e1000_ich9lan:
1633         case e1000_ich10lan:
1634                 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
1635                 break;
1636         case e1000_pchlan:
1637         case e1000_pch2lan:
1638         case e1000_pch_lpt:
1639                 hw->phy.ops.init_params = e1000_init_phy_params_pchlan;
1640                 break;
1641         default:
1642                 break;
1643         }
1644 }
1645
1646 /**
1647  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1648  *  @hw: pointer to the HW structure
1649  *
1650  *  Acquires the mutex for performing NVM operations.
1651  **/
1652 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1653 {
1654         DEBUGFUNC("e1000_acquire_nvm_ich8lan");
1655
1656         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1657
1658         return E1000_SUCCESS;
1659 }
1660
1661 /**
1662  *  e1000_release_nvm_ich8lan - Release NVM mutex
1663  *  @hw: pointer to the HW structure
1664  *
1665  *  Releases the mutex used while performing NVM operations.
1666  **/
1667 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1668 {
1669         DEBUGFUNC("e1000_release_nvm_ich8lan");
1670
1671         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);
1672
1673         return;
1674 }
1675
1676 /**
1677  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1678  *  @hw: pointer to the HW structure
1679  *
1680  *  Acquires the software control flag for performing PHY and select
1681  *  MAC CSR accesses.
1682  **/
1683 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1684 {
1685         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1686         s32 ret_val = E1000_SUCCESS;
1687
1688         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
1689
1690         E1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1691
1692         while (timeout) {
1693                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1694                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1695                         break;
1696
1697                 msec_delay_irq(1);
1698                 timeout--;
1699         }
1700
1701         if (!timeout) {
1702                 DEBUGOUT("SW has already locked the resource.\n");
1703                 ret_val = -E1000_ERR_CONFIG;
1704                 goto out;
1705         }
1706
1707         timeout = SW_FLAG_TIMEOUT;
1708
1709         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1710         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1711
1712         while (timeout) {
1713                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1714                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1715                         break;
1716
1717                 msec_delay_irq(1);
1718                 timeout--;
1719         }
1720
1721         if (!timeout) {
1722                 DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1723                           E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
1724                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1725                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1726                 ret_val = -E1000_ERR_CONFIG;
1727                 goto out;
1728         }
1729
1730 out:
1731         if (ret_val)
1732                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1733
1734         return ret_val;
1735 }
1736
1737 /**
1738  *  e1000_release_swflag_ich8lan - Release software control flag
1739  *  @hw: pointer to the HW structure
1740  *
1741  *  Releases the software control flag for performing PHY and select
1742  *  MAC CSR accesses.
1743  **/
1744 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1745 {
1746         u32 extcnf_ctrl;
1747
1748         DEBUGFUNC("e1000_release_swflag_ich8lan");
1749
1750         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
1751
1752         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1753                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1754                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
1755         } else {
1756                 DEBUGOUT("Semaphore unexpectedly released by sw/fw/hw\n");
1757         }
1758
1759         E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
1760
1761         return;
1762 }
1763
1764 /**
1765  *  e1000_check_mng_mode_ich8lan - Checks management mode
1766  *  @hw: pointer to the HW structure
1767  *
1768  *  This checks if the adapter has any manageability enabled.
1769  *  This is a function pointer entry point only called by read/write
1770  *  routines for the PHY and NVM parts.
1771  **/
1772 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1773 {
1774         u32 fwsm;
1775
1776         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
1777
1778         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1779
1780         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1781                ((fwsm & E1000_FWSM_MODE_MASK) ==
1782                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1783 }
1784
1785 /**
1786  *  e1000_check_mng_mode_pchlan - Checks management mode
1787  *  @hw: pointer to the HW structure
1788  *
1789  *  This checks if the adapter has iAMT enabled.
1790  *  This is a function pointer entry point only called by read/write
1791  *  routines for the PHY and NVM parts.
1792  **/
1793 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1794 {
1795         u32 fwsm;
1796
1797         DEBUGFUNC("e1000_check_mng_mode_pchlan");
1798
1799         fwsm = E1000_READ_REG(hw, E1000_FWSM);
1800
1801         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1802                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1803 }
1804
1805 /**
1806  *  e1000_rar_set_pch2lan - Set receive address register
1807  *  @hw: pointer to the HW structure
1808  *  @addr: pointer to the receive address
1809  *  @index: receive address array register
1810  *
1811  *  Sets the receive address array register at index to the address passed
1812  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1813  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1814  *  Use SHRA[0-3] in place of those reserved for ME.
1815  **/
1816 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1817 {
1818         u32 rar_low, rar_high;
1819
1820         DEBUGFUNC("e1000_rar_set_pch2lan");
1821
1822         /* HW expects these in little endian so we reverse the byte order
1823          * from network order (big endian) to little endian
1824          */
1825         rar_low = ((u32) addr[0] |
1826                    ((u32) addr[1] << 8) |
1827                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1828
1829         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1830
1831         /* If MAC address zero, no need to set the AV bit */
1832         if (rar_low || rar_high)
1833                 rar_high |= E1000_RAH_AV;
1834
1835         if (index == 0) {
1836                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1837                 E1000_WRITE_FLUSH(hw);
1838                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1839                 E1000_WRITE_FLUSH(hw);
1840                 return E1000_SUCCESS;
1841         }
1842
1843         /* RAR[1-6] are owned by manageability.  Skip those and program the
1844          * next address into the SHRA register array.
1845          */
1846         if (index < (u32) (hw->mac.rar_entry_count)) {
1847                 s32 ret_val;
1848
1849                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1850                 if (ret_val)
1851                         goto out;
1852
1853                 E1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);
1854                 E1000_WRITE_FLUSH(hw);
1855                 E1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);
1856                 E1000_WRITE_FLUSH(hw);
1857
1858                 e1000_release_swflag_ich8lan(hw);
1859
1860                 /* verify the register updates */
1861                 if ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&
1862                     (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))
1863                         return E1000_SUCCESS;
1864
1865                 DEBUGOUT2("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1866                          (index - 1), E1000_READ_REG(hw, E1000_FWSM));
1867         }
1868
1869 out:
1870         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1871         return -E1000_ERR_CONFIG;
1872 }
1873
1874 /**
1875  *  e1000_rar_set_pch_lpt - Set receive address registers
1876  *  @hw: pointer to the HW structure
1877  *  @addr: pointer to the receive address
1878  *  @index: receive address array register
1879  *
1880  *  Sets the receive address register array at index to the address passed
1881  *  in by addr. For LPT, RAR[0] is the base address register that is to
1882  *  contain the MAC address. SHRA[0-10] are the shared receive address
1883  *  registers that are shared between the Host and manageability engine (ME).
1884  **/
1885 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1886 {
1887         u32 rar_low, rar_high;
1888         u32 wlock_mac;
1889
1890         DEBUGFUNC("e1000_rar_set_pch_lpt");
1891
1892         /* HW expects these in little endian so we reverse the byte order
1893          * from network order (big endian) to little endian
1894          */
1895         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
1896                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
1897
1898         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
1899
1900         /* If MAC address zero, no need to set the AV bit */
1901         if (rar_low || rar_high)
1902                 rar_high |= E1000_RAH_AV;
1903
1904         if (index == 0) {
1905                 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
1906                 E1000_WRITE_FLUSH(hw);
1907                 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
1908                 E1000_WRITE_FLUSH(hw);
1909                 return E1000_SUCCESS;
1910         }
1911
1912         /* The manageability engine (ME) can lock certain SHRAR registers that
1913          * it is using - those registers are unavailable for use.
1914          */
1915         if (index < hw->mac.rar_entry_count) {
1916                 wlock_mac = E1000_READ_REG(hw, E1000_FWSM) &
1917                             E1000_FWSM_WLOCK_MAC_MASK;
1918                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1919
1920                 /* Check if all SHRAR registers are locked */
1921                 if (wlock_mac == 1)
1922                         goto out;
1923
1924                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1925                         s32 ret_val;
1926
1927                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1928
1929                         if (ret_val)
1930                                 goto out;
1931
1932                         E1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),
1933                                         rar_low);
1934                         E1000_WRITE_FLUSH(hw);
1935                         E1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),
1936                                         rar_high);
1937                         E1000_WRITE_FLUSH(hw);
1938
1939                         e1000_release_swflag_ich8lan(hw);
1940
1941                         /* verify the register updates */
1942                         if ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1943                             (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))
1944                                 return E1000_SUCCESS;
1945                 }
1946         }
1947
1948 out:
1949         DEBUGOUT1("Failed to write receive address at index %d\n", index);
1950         return -E1000_ERR_CONFIG;
1951 }
1952
1953 /**
1954  *  e1000_update_mc_addr_list_pch2lan - Update Multicast addresses
1955  *  @hw: pointer to the HW structure
1956  *  @mc_addr_list: array of multicast addresses to program
1957  *  @mc_addr_count: number of multicast addresses to program
1958  *
1959  *  Updates entire Multicast Table Array of the PCH2 MAC and PHY.
1960  *  The caller must have a packed mc_addr_list of multicast addresses.
1961  **/
1962 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
1963                                               u8 *mc_addr_list,
1964                                               u32 mc_addr_count)
1965 {
1966         u16 phy_reg = 0;
1967         int i;
1968         s32 ret_val;
1969
1970         DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
1971
1972         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
1973
1974         ret_val = hw->phy.ops.acquire(hw);
1975         if (ret_val)
1976                 return;
1977
1978         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1979         if (ret_val)
1980                 goto release;
1981
1982         for (i = 0; i < hw->mac.mta_reg_count; i++) {
1983                 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
1984                                            (u16)(hw->mac.mta_shadow[i] &
1985                                                  0xFFFF));
1986                 hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
1987                                            (u16)((hw->mac.mta_shadow[i] >> 16) &
1988                                                  0xFFFF));
1989         }
1990
1991         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1992
1993 release:
1994         hw->phy.ops.release(hw);
1995 }
1996
1997 /**
1998  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1999  *  @hw: pointer to the HW structure
2000  *
2001  *  Checks if firmware is blocking the reset of the PHY.
2002  *  This is a function pointer entry point only called by
2003  *  reset routines.
2004  **/
2005 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2006 {
2007         u32 fwsm;
2008         bool blocked = FALSE;
2009         int i = 0;
2010
2011         DEBUGFUNC("e1000_check_reset_block_ich8lan");
2012
2013         do {
2014                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
2015                 if (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {
2016                         blocked = TRUE;
2017                         msec_delay(10);
2018                         continue;
2019                 }
2020                 blocked = FALSE;
2021         } while (blocked && (i++ < 10));
2022         return blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;
2023 }
2024
2025 /**
2026  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2027  *  @hw: pointer to the HW structure
2028  *
2029  *  Assumes semaphore already acquired.
2030  *
2031  **/
2032 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2033 {
2034         u16 phy_data;
2035         u32 strap = E1000_READ_REG(hw, E1000_STRAP);
2036         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2037                 E1000_STRAP_SMT_FREQ_SHIFT;
2038         s32 ret_val;
2039
2040         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2041
2042         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2043         if (ret_val)
2044                 return ret_val;
2045
2046         phy_data &= ~HV_SMB_ADDR_MASK;
2047         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2048         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2049
2050         if (hw->phy.type == e1000_phy_i217) {
2051                 /* Restore SMBus frequency */
2052                 if (freq--) {
2053                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2054                         phy_data |= (freq & (1 << 0)) <<
2055                                 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2056                         phy_data |= (freq & (1 << 1)) <<
2057                                 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2058                 } else {
2059                         DEBUGOUT("Unsupported SMB frequency in PHY\n");
2060                 }
2061         }
2062
2063         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2064 }
2065
2066 /**
2067  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2068  *  @hw:   pointer to the HW structure
2069  *
2070  *  SW should configure the LCD from the NVM extended configuration region
2071  *  as a workaround for certain parts.
2072  **/
2073 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2074 {
2075         struct e1000_phy_info *phy = &hw->phy;
2076         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2077         s32 ret_val = E1000_SUCCESS;
2078         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2079
2080         DEBUGFUNC("e1000_sw_lcd_config_ich8lan");
2081
2082         /* Initialize the PHY from the NVM on ICH platforms.  This
2083          * is needed due to an issue where the NVM configuration is
2084          * not properly autoloaded after power transitions.
2085          * Therefore, after each PHY reset, we will load the
2086          * configuration data out of the NVM manually.
2087          */
2088         switch (hw->mac.type) {
2089         case e1000_ich8lan:
2090                 if (phy->type != e1000_phy_igp_3)
2091                         return ret_val;
2092
2093                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||
2094                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {
2095                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2096                         break;
2097                 }
2098                 /* Fall-thru */
2099         case e1000_pchlan:
2100         case e1000_pch2lan:
2101         case e1000_pch_lpt:
2102                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2103                 break;
2104         default:
2105                 return ret_val;
2106         }
2107
2108         ret_val = hw->phy.ops.acquire(hw);
2109         if (ret_val)
2110                 return ret_val;
2111
2112         data = E1000_READ_REG(hw, E1000_FEXTNVM);
2113         if (!(data & sw_cfg_mask))
2114                 goto release;
2115
2116         /* Make sure HW does not configure LCD from PHY
2117          * extended configuration before SW configuration
2118          */
2119         data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2120         if ((hw->mac.type < e1000_pch2lan) &&
2121             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2122                         goto release;
2123
2124         cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
2125         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2126         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2127         if (!cnf_size)
2128                 goto release;
2129
2130         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2131         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2132
2133         if (((hw->mac.type == e1000_pchlan) &&
2134              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2135             (hw->mac.type > e1000_pchlan)) {
2136                 /* HW configures the SMBus address and LEDs when the
2137                  * OEM and LCD Write Enable bits are set in the NVM.
2138                  * When both NVM bits are cleared, SW will configure
2139                  * them instead.
2140                  */
2141                 ret_val = e1000_write_smbus_addr(hw);
2142                 if (ret_val)
2143                         goto release;
2144
2145                 data = E1000_READ_REG(hw, E1000_LEDCTL);
2146                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2147                                                         (u16)data);
2148                 if (ret_val)
2149                         goto release;
2150         }
2151
2152         /* Configure LCD from extended configuration region. */
2153
2154         /* cnf_base_addr is in DWORD */
2155         word_addr = (u16)(cnf_base_addr << 1);
2156
2157         for (i = 0; i < cnf_size; i++) {
2158                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
2159                                            &reg_data);
2160                 if (ret_val)
2161                         goto release;
2162
2163                 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
2164                                            1, &reg_addr);
2165                 if (ret_val)
2166                         goto release;
2167
2168                 /* Save off the PHY page for future writes. */
2169                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2170                         phy_page = reg_data;
2171                         continue;
2172                 }
2173
2174                 reg_addr &= PHY_REG_MASK;
2175                 reg_addr |= phy_page;
2176
2177                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
2178                                                     reg_data);
2179                 if (ret_val)
2180                         goto release;
2181         }
2182
2183 release:
2184         hw->phy.ops.release(hw);
2185         return ret_val;
2186 }
2187
2188 /**
2189  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2190  *  @hw:   pointer to the HW structure
2191  *  @link: link up bool flag
2192  *
2193  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2194  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2195  *  If link is down, the function will restore the default K1 setting located
2196  *  in the NVM.
2197  **/
2198 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2199 {
2200         s32 ret_val = E1000_SUCCESS;
2201         u16 status_reg = 0;
2202         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2203
2204         DEBUGFUNC("e1000_k1_gig_workaround_hv");
2205
2206         if (hw->mac.type != e1000_pchlan)
2207                 return E1000_SUCCESS;
2208
2209         /* Wrap the whole flow with the sw flag */
2210         ret_val = hw->phy.ops.acquire(hw);
2211         if (ret_val)
2212                 return ret_val;
2213
2214         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2215         if (link) {
2216                 if (hw->phy.type == e1000_phy_82578) {
2217                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
2218                                                               &status_reg);
2219                         if (ret_val)
2220                                 goto release;
2221
2222                         status_reg &= (BM_CS_STATUS_LINK_UP |
2223                                        BM_CS_STATUS_RESOLVED |
2224                                        BM_CS_STATUS_SPEED_MASK);
2225
2226                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2227                                            BM_CS_STATUS_RESOLVED |
2228                                            BM_CS_STATUS_SPEED_1000))
2229                                 k1_enable = FALSE;
2230                 }
2231
2232                 if (hw->phy.type == e1000_phy_82577) {
2233                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
2234                                                               &status_reg);
2235                         if (ret_val)
2236                                 goto release;
2237
2238                         status_reg &= (HV_M_STATUS_LINK_UP |
2239                                        HV_M_STATUS_AUTONEG_COMPLETE |
2240                                        HV_M_STATUS_SPEED_MASK);
2241
2242                         if (status_reg == (HV_M_STATUS_LINK_UP |
2243                                            HV_M_STATUS_AUTONEG_COMPLETE |
2244                                            HV_M_STATUS_SPEED_1000))
2245                                 k1_enable = FALSE;
2246                 }
2247
2248                 /* Link stall fix for link up */
2249                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2250                                                        0x0100);
2251                 if (ret_val)
2252                         goto release;
2253
2254         } else {
2255                 /* Link stall fix for link down */
2256                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
2257                                                        0x4100);
2258                 if (ret_val)
2259                         goto release;
2260         }
2261
2262         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2263
2264 release:
2265         hw->phy.ops.release(hw);
2266
2267         return ret_val;
2268 }
2269
2270 /**
2271  *  e1000_configure_k1_ich8lan - Configure K1 power state
2272  *  @hw: pointer to the HW structure
2273  *  @enable: K1 state to configure
2274  *
2275  *  Configure the K1 power state based on the provided parameter.
2276  *  Assumes semaphore already acquired.
2277  *
2278  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2279  **/
2280 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2281 {
2282         s32 ret_val;
2283         u32 ctrl_reg = 0;
2284         u32 ctrl_ext = 0;
2285         u32 reg = 0;
2286         u16 kmrn_reg = 0;
2287
2288         DEBUGFUNC("e1000_configure_k1_ich8lan");
2289
2290         ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2291                                              &kmrn_reg);
2292         if (ret_val)
2293                 return ret_val;
2294
2295         if (k1_enable)
2296                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2297         else
2298                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2299
2300         ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2301                                               kmrn_reg);
2302         if (ret_val)
2303                 return ret_val;
2304
2305         usec_delay(20);
2306         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2307         ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
2308
2309         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2310         reg |= E1000_CTRL_FRCSPD;
2311         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2312
2313         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2314         E1000_WRITE_FLUSH(hw);
2315         usec_delay(20);
2316         E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
2317         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2318         E1000_WRITE_FLUSH(hw);
2319         usec_delay(20);
2320
2321         return E1000_SUCCESS;
2322 }
2323
2324 /**
2325  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2326  *  @hw:       pointer to the HW structure
2327  *  @d0_state: boolean if entering d0 or d3 device state
2328  *
2329  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2330  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2331  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2332  **/
2333 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2334 {
2335         s32 ret_val = 0;
2336         u32 mac_reg;
2337         u16 oem_reg;
2338
2339         DEBUGFUNC("e1000_oem_bits_config_ich8lan");
2340
2341         if (hw->mac.type < e1000_pchlan)
2342                 return ret_val;
2343
2344         ret_val = hw->phy.ops.acquire(hw);
2345         if (ret_val)
2346                 return ret_val;
2347
2348         if (hw->mac.type == e1000_pchlan) {
2349                 mac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2350                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2351                         goto release;
2352         }
2353
2354         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);
2355         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2356                 goto release;
2357
2358         mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2359
2360         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
2361         if (ret_val)
2362                 goto release;
2363
2364         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2365
2366         if (d0_state) {
2367                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2368                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2369
2370                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2371                         oem_reg |= HV_OEM_BITS_LPLU;
2372         } else {
2373                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2374                     E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2375                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2376
2377                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2378                     E1000_PHY_CTRL_NOND0A_LPLU))
2379                         oem_reg |= HV_OEM_BITS_LPLU;
2380         }
2381
2382         /* Set Restart auto-neg to activate the bits */
2383         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2384             !hw->phy.ops.check_reset_block(hw))
2385                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2386
2387         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
2388
2389 release:
2390         hw->phy.ops.release(hw);
2391
2392         return ret_val;
2393 }
2394
2395
2396 /**
2397  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2398  *  @hw:   pointer to the HW structure
2399  **/
2400 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2401 {
2402         s32 ret_val;
2403         u16 data;
2404
2405         DEBUGFUNC("e1000_set_mdio_slow_mode_hv");
2406
2407         ret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);
2408         if (ret_val)
2409                 return ret_val;
2410
2411         data |= HV_KMRN_MDIO_SLOW;
2412
2413         ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);
2414
2415         return ret_val;
2416 }
2417
2418 /**
2419  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2420  *  done after every PHY reset.
2421  **/
2422 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2423 {
2424         s32 ret_val = E1000_SUCCESS;
2425         u16 phy_data;
2426
2427         DEBUGFUNC("e1000_hv_phy_workarounds_ich8lan");
2428
2429         if (hw->mac.type != e1000_pchlan)
2430                 return E1000_SUCCESS;
2431
2432         /* Set MDIO slow mode before any other MDIO access */
2433         if (hw->phy.type == e1000_phy_82577) {
2434                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2435                 if (ret_val)
2436                         return ret_val;
2437         }
2438
2439         if (((hw->phy.type == e1000_phy_82577) &&
2440              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2441             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2442                 /* Disable generation of early preamble */
2443                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
2444                 if (ret_val)
2445                         return ret_val;
2446
2447                 /* Preamble tuning for SSC */
2448                 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
2449                                                 0xA204);
2450                 if (ret_val)
2451                         return ret_val;
2452         }
2453
2454         if (hw->phy.type == e1000_phy_82578) {
2455                 /* Return registers to default by doing a soft reset then
2456                  * writing 0x3140 to the control register.
2457                  */
2458                 if (hw->phy.revision < 2) {
2459                         e1000_phy_sw_reset_generic(hw);
2460                         ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
2461                                                         0x3140);
2462                 }
2463         }
2464
2465         /* Select page 0 */
2466         ret_val = hw->phy.ops.acquire(hw);
2467         if (ret_val)
2468                 return ret_val;
2469
2470         hw->phy.addr = 1;
2471         ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2472         hw->phy.ops.release(hw);
2473         if (ret_val)
2474                 return ret_val;
2475
2476         /* Configure the K1 Si workaround during phy reset assuming there is
2477          * link so that it disables K1 if link is in 1Gbps.
2478          */
2479         ret_val = e1000_k1_gig_workaround_hv(hw, TRUE);
2480         if (ret_val)
2481                 return ret_val;
2482
2483         /* Workaround for link disconnects on a busy hub in half duplex */
2484         ret_val = hw->phy.ops.acquire(hw);
2485         if (ret_val)
2486                 return ret_val;
2487         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2488         if (ret_val)
2489                 goto release;
2490         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
2491                                                phy_data & 0x00FF);
2492         if (ret_val)
2493                 goto release;
2494
2495         /* set MSE higher to enable link to stay up when noise is high */
2496         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2497 release:
2498         hw->phy.ops.release(hw);
2499
2500         return ret_val;
2501 }
2502
2503 /**
2504  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2505  *  @hw:   pointer to the HW structure
2506  **/
2507 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2508 {
2509         u32 mac_reg;
2510         u16 i, phy_reg = 0;
2511         s32 ret_val;
2512
2513         DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
2514
2515         ret_val = hw->phy.ops.acquire(hw);
2516         if (ret_val)
2517                 return;
2518         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2519         if (ret_val)
2520                 goto release;
2521
2522         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2523         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2524                 mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
2525                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2526                                            (u16)(mac_reg & 0xFFFF));
2527                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2528                                            (u16)((mac_reg >> 16) & 0xFFFF));
2529
2530                 mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
2531                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2532                                            (u16)(mac_reg & 0xFFFF));
2533                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2534                                            (u16)((mac_reg & E1000_RAH_AV)
2535                                                  >> 16));
2536         }
2537
2538         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2539
2540 release:
2541         hw->phy.ops.release(hw);
2542 }
2543
2544 static u32 e1000_calc_rx_da_crc(u8 mac[])
2545 {
2546         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
2547         u32 i, j, mask, crc;
2548
2549         DEBUGFUNC("e1000_calc_rx_da_crc");
2550
2551         crc = 0xffffffff;
2552         for (i = 0; i < 6; i++) {
2553                 crc = crc ^ mac[i];
2554                 for (j = 8; j > 0; j--) {
2555                         mask = (crc & 1) * (-1);
2556                         crc = (crc >> 1) ^ (poly & mask);
2557                 }
2558         }
2559         return ~crc;
2560 }
2561
2562 /**
2563  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2564  *  with 82579 PHY
2565  *  @hw: pointer to the HW structure
2566  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2567  **/
2568 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2569 {
2570         s32 ret_val = E1000_SUCCESS;
2571         u16 phy_reg, data;
2572         u32 mac_reg;
2573         u16 i;
2574
2575         DEBUGFUNC("e1000_lv_jumbo_workaround_ich8lan");
2576
2577         if (hw->mac.type < e1000_pch2lan)
2578                 return E1000_SUCCESS;
2579
2580         /* disable Rx path while enabling/disabling workaround */
2581         hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
2582         ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
2583                                         phy_reg | (1 << 14));
2584         if (ret_val)
2585                 return ret_val;
2586
2587         if (enable) {
2588                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2589                  * SHRAL/H) and initial CRC values to the MAC
2590                  */
2591                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2592                         u8 mac_addr[ETH_ADDR_LEN] = {0};
2593                         u32 addr_high, addr_low;
2594
2595                         addr_high = E1000_READ_REG(hw, E1000_RAH(i));
2596                         if (!(addr_high & E1000_RAH_AV))
2597                                 continue;
2598                         addr_low = E1000_READ_REG(hw, E1000_RAL(i));
2599                         mac_addr[0] = (addr_low & 0xFF);
2600                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2601                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2602                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2603                         mac_addr[4] = (addr_high & 0xFF);
2604                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2605
2606                         E1000_WRITE_REG(hw, E1000_PCH_RAICC(i),
2607                                         e1000_calc_rx_da_crc(mac_addr));
2608                 }
2609
2610                 /* Write Rx addresses to the PHY */
2611                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2612
2613                 /* Enable jumbo frame workaround in the MAC */
2614                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2615                 mac_reg &= ~(1 << 14);
2616                 mac_reg |= (7 << 15);
2617                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2618
2619                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2620                 mac_reg |= E1000_RCTL_SECRC;
2621                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2622
2623                 ret_val = e1000_read_kmrn_reg_generic(hw,
2624                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2625                                                 &data);
2626                 if (ret_val)
2627                         return ret_val;
2628                 ret_val = e1000_write_kmrn_reg_generic(hw,
2629                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2630                                                 data | (1 << 0));
2631                 if (ret_val)
2632                         return ret_val;
2633                 ret_val = e1000_read_kmrn_reg_generic(hw,
2634                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2635                                                 &data);
2636                 if (ret_val)
2637                         return ret_val;
2638                 data &= ~(0xF << 8);
2639                 data |= (0xB << 8);
2640                 ret_val = e1000_write_kmrn_reg_generic(hw,
2641                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2642                                                 data);
2643                 if (ret_val)
2644                         return ret_val;
2645
2646                 /* Enable jumbo frame workaround in the PHY */
2647                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2648                 data &= ~(0x7F << 5);
2649                 data |= (0x37 << 5);
2650                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2651                 if (ret_val)
2652                         return ret_val;
2653                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2654                 data &= ~(1 << 13);
2655                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2656                 if (ret_val)
2657                         return ret_val;
2658                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2659                 data &= ~(0x3FF << 2);
2660                 data |= (E1000_TX_PTR_GAP << 2);
2661                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2662                 if (ret_val)
2663                         return ret_val;
2664                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
2665                 if (ret_val)
2666                         return ret_val;
2667                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2668                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
2669                                                 (1 << 10));
2670                 if (ret_val)
2671                         return ret_val;
2672         } else {
2673                 /* Write MAC register values back to h/w defaults */
2674                 mac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);
2675                 mac_reg &= ~(0xF << 14);
2676                 E1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);
2677
2678                 mac_reg = E1000_READ_REG(hw, E1000_RCTL);
2679                 mac_reg &= ~E1000_RCTL_SECRC;
2680                 E1000_WRITE_REG(hw, E1000_RCTL, mac_reg);
2681
2682                 ret_val = e1000_read_kmrn_reg_generic(hw,
2683                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2684                                                 &data);
2685                 if (ret_val)
2686                         return ret_val;
2687                 ret_val = e1000_write_kmrn_reg_generic(hw,
2688                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2689                                                 data & ~(1 << 0));
2690                 if (ret_val)
2691                         return ret_val;
2692                 ret_val = e1000_read_kmrn_reg_generic(hw,
2693                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2694                                                 &data);
2695                 if (ret_val)
2696                         return ret_val;
2697                 data &= ~(0xF << 8);
2698                 data |= (0xB << 8);
2699                 ret_val = e1000_write_kmrn_reg_generic(hw,
2700                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2701                                                 data);
2702                 if (ret_val)
2703                         return ret_val;
2704
2705                 /* Write PHY register values back to h/w defaults */
2706                 hw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);
2707                 data &= ~(0x7F << 5);
2708                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);
2709                 if (ret_val)
2710                         return ret_val;
2711                 hw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);
2712                 data |= (1 << 13);
2713                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);
2714                 if (ret_val)
2715                         return ret_val;
2716                 hw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);
2717                 data &= ~(0x3FF << 2);
2718                 data |= (0x8 << 2);
2719                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
2720                 if (ret_val)
2721                         return ret_val;
2722                 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);
2723                 if (ret_val)
2724                         return ret_val;
2725                 hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
2726                 ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
2727                                                 ~(1 << 10));
2728                 if (ret_val)
2729                         return ret_val;
2730         }
2731
2732         /* re-enable Rx path after enabling/disabling workaround */
2733         return hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
2734                                      ~(1 << 14));
2735 }
2736
2737 /**
2738  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2739  *  done after every PHY reset.
2740  **/
2741 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2742 {
2743         s32 ret_val = E1000_SUCCESS;
2744
2745         DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");
2746
2747         if (hw->mac.type != e1000_pch2lan)
2748                 return E1000_SUCCESS;
2749
2750         /* Set MDIO slow mode before any other MDIO access */
2751         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2752         if (ret_val)
2753                 return ret_val;
2754
2755         ret_val = hw->phy.ops.acquire(hw);
2756         if (ret_val)
2757                 return ret_val;
2758         /* set MSE higher to enable link to stay up when noise is high */
2759         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2760         if (ret_val)
2761                 goto release;
2762         /* drop link after 5 times MSE threshold was reached */
2763         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2764 release:
2765         hw->phy.ops.release(hw);
2766
2767         return ret_val;
2768 }
2769
2770 /**
2771  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2772  *  @hw:   pointer to the HW structure
2773  *
2774  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2775  *  Disable K1 for 1000 and 100 speeds
2776  **/
2777 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2778 {
2779         s32 ret_val = E1000_SUCCESS;
2780         u16 status_reg = 0;
2781
2782         DEBUGFUNC("e1000_k1_workaround_lv");
2783
2784         if (hw->mac.type != e1000_pch2lan)
2785                 return E1000_SUCCESS;
2786
2787         /* Set K1 beacon duration based on 10Mbs speed */
2788         ret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);
2789         if (ret_val)
2790                 return ret_val;
2791
2792         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2793             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2794                 if (status_reg &
2795                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2796                         u16 pm_phy_reg;
2797
2798                         /* LV 1G/100 Packet drop issue wa  */
2799                         ret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,
2800                                                        &pm_phy_reg);
2801                         if (ret_val)
2802                                 return ret_val;
2803                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2804                         ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,
2805                                                         pm_phy_reg);
2806                         if (ret_val)
2807                                 return ret_val;
2808                 } else {
2809                         u32 mac_reg;
2810                         mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
2811                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2812                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2813                         E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
2814                 }
2815         }
2816
2817         return ret_val;
2818 }
2819
2820 /**
2821  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2822  *  @hw:   pointer to the HW structure
2823  *  @gate: boolean set to TRUE to gate, FALSE to ungate
2824  *
2825  *  Gate/ungate the automatic PHY configuration via hardware; perform
2826  *  the configuration via software instead.
2827  **/
2828 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2829 {
2830         u32 extcnf_ctrl;
2831
2832         DEBUGFUNC("e1000_gate_hw_phy_config_ich8lan");
2833
2834         if (hw->mac.type < e1000_pch2lan)
2835                 return;
2836
2837         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
2838
2839         if (gate)
2840                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2841         else
2842                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2843
2844         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
2845 }
2846
2847 /**
2848  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2849  *  @hw: pointer to the HW structure
2850  *
2851  *  Check the appropriate indication the MAC has finished configuring the
2852  *  PHY after a software reset.
2853  **/
2854 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2855 {
2856         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2857
2858         DEBUGFUNC("e1000_lan_init_done_ich8lan");
2859
2860         /* Wait for basic configuration completes before proceeding */
2861         do {
2862                 data = E1000_READ_REG(hw, E1000_STATUS);
2863                 data &= E1000_STATUS_LAN_INIT_DONE;
2864                 usec_delay(100);
2865         } while ((!data) && --loop);
2866
2867         /* If basic configuration is incomplete before the above loop
2868          * count reaches 0, loading the configuration from NVM will
2869          * leave the PHY in a bad state possibly resulting in no link.
2870          */
2871         if (loop == 0)
2872                 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
2873
2874         /* Clear the Init Done bit for the next init event */
2875         data = E1000_READ_REG(hw, E1000_STATUS);
2876         data &= ~E1000_STATUS_LAN_INIT_DONE;
2877         E1000_WRITE_REG(hw, E1000_STATUS, data);
2878 }
2879
2880 /**
2881  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2882  *  @hw: pointer to the HW structure
2883  **/
2884 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2885 {
2886         s32 ret_val = E1000_SUCCESS;
2887         u16 reg;
2888
2889         DEBUGFUNC("e1000_post_phy_reset_ich8lan");
2890
2891         if (hw->phy.ops.check_reset_block(hw))
2892                 return E1000_SUCCESS;
2893
2894         /* Allow time for h/w to get to quiescent state after reset */
2895         msec_delay(10);
2896
2897         /* Perform any necessary post-reset workarounds */
2898         switch (hw->mac.type) {
2899         case e1000_pchlan:
2900                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2901                 if (ret_val)
2902                         return ret_val;
2903                 break;
2904         case e1000_pch2lan:
2905                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2906                 if (ret_val)
2907                         return ret_val;
2908                 break;
2909         default:
2910                 break;
2911         }
2912
2913         /* Clear the host wakeup bit after lcd reset */
2914         if (hw->mac.type >= e1000_pchlan) {
2915                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
2916                 reg &= ~BM_WUC_HOST_WU_BIT;
2917                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
2918         }
2919
2920         /* Configure the LCD with the extended configuration region in NVM */
2921         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2922         if (ret_val)
2923                 return ret_val;
2924
2925         /* Configure the LCD with the OEM bits in NVM */
2926         ret_val = e1000_oem_bits_config_ich8lan(hw, TRUE);
2927
2928         if (hw->mac.type == e1000_pch2lan) {
2929                 /* Ungate automatic PHY configuration on non-managed 82579 */
2930                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
2931                     E1000_ICH_FWSM_FW_VALID)) {
2932                         msec_delay(10);
2933                         e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
2934                 }
2935
2936                 /* Set EEE LPI Update Timer to 200usec */
2937                 ret_val = hw->phy.ops.acquire(hw);
2938                 if (ret_val)
2939                         return ret_val;
2940                 ret_val = e1000_write_emi_reg_locked(hw,
2941                                                      I82579_LPI_UPDATE_TIMER,
2942                                                      0x1387);
2943                 hw->phy.ops.release(hw);
2944         }
2945
2946         return ret_val;
2947 }
2948
2949 /**
2950  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2951  *  @hw: pointer to the HW structure
2952  *
2953  *  Resets the PHY
2954  *  This is a function pointer entry point called by drivers
2955  *  or other shared routines.
2956  **/
2957 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2958 {
2959         s32 ret_val = E1000_SUCCESS;
2960
2961         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
2962
2963         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2964         if ((hw->mac.type == e1000_pch2lan) &&
2965             !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
2966                 e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
2967
2968         ret_val = e1000_phy_hw_reset_generic(hw);
2969         if (ret_val)
2970                 return ret_val;
2971
2972         return e1000_post_phy_reset_ich8lan(hw);
2973 }
2974
2975 /**
2976  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2977  *  @hw: pointer to the HW structure
2978  *  @active: TRUE to enable LPLU, FALSE to disable
2979  *
2980  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2981  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2982  *  the phy speed. This function will manually set the LPLU bit and restart
2983  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2984  *  since it configures the same bit.
2985  **/
2986 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2987 {
2988         s32 ret_val;
2989         u16 oem_reg;
2990
2991         DEBUGFUNC("e1000_set_lplu_state_pchlan");
2992
2993         ret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);
2994         if (ret_val)
2995                 return ret_val;
2996
2997         if (active)
2998                 oem_reg |= HV_OEM_BITS_LPLU;
2999         else
3000                 oem_reg &= ~HV_OEM_BITS_LPLU;
3001
3002         if (!hw->phy.ops.check_reset_block(hw))
3003                 oem_reg |= HV_OEM_BITS_RESTART_AN;
3004
3005         return hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
3006 }
3007
3008 /**
3009  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3010  *  @hw: pointer to the HW structure
3011  *  @active: TRUE to enable LPLU, FALSE to disable
3012  *
3013  *  Sets the LPLU D0 state according to the active flag.  When
3014  *  activating LPLU this function also disables smart speed
3015  *  and vice versa.  LPLU will not be activated unless the
3016  *  device autonegotiation advertisement meets standards of
3017  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3018  *  This is a function pointer entry point only called by
3019  *  PHY setup routines.
3020  **/
3021 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3022 {
3023         struct e1000_phy_info *phy = &hw->phy;
3024         u32 phy_ctrl;
3025         s32 ret_val = E1000_SUCCESS;
3026         u16 data;
3027
3028         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
3029
3030         if (phy->type == e1000_phy_ife)
3031                 return E1000_SUCCESS;
3032
3033         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3034
3035         if (active) {
3036                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3037                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3038
3039                 if (phy->type != e1000_phy_igp_3)
3040                         return E1000_SUCCESS;
3041
3042                 /* Call gig speed drop workaround on LPLU before accessing
3043                  * any PHY registers
3044                  */
3045                 if (hw->mac.type == e1000_ich8lan)
3046                         e1000_gig_downshift_workaround_ich8lan(hw);
3047
3048                 /* When LPLU is enabled, we should disable SmartSpeed */
3049                 ret_val = phy->ops.read_reg(hw,
3050                                             IGP01E1000_PHY_PORT_CONFIG,
3051                                             &data);
3052                 if (ret_val)
3053                         return ret_val;
3054                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3055                 ret_val = phy->ops.write_reg(hw,
3056                                              IGP01E1000_PHY_PORT_CONFIG,
3057                                              data);
3058                 if (ret_val)
3059                         return ret_val;
3060         } else {
3061                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3062                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3063
3064                 if (phy->type != e1000_phy_igp_3)
3065                         return E1000_SUCCESS;
3066
3067                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3068                  * during Dx states where the power conservation is most
3069                  * important.  During driver activity we should enable
3070                  * SmartSpeed, so performance is maintained.
3071                  */
3072                 if (phy->smart_speed == e1000_smart_speed_on) {
3073                         ret_val = phy->ops.read_reg(hw,
3074                                                     IGP01E1000_PHY_PORT_CONFIG,
3075                                                     &data);
3076                         if (ret_val)
3077                                 return ret_val;
3078
3079                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3080                         ret_val = phy->ops.write_reg(hw,
3081                                                      IGP01E1000_PHY_PORT_CONFIG,
3082                                                      data);
3083                         if (ret_val)
3084                                 return ret_val;
3085                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3086                         ret_val = phy->ops.read_reg(hw,
3087                                                     IGP01E1000_PHY_PORT_CONFIG,
3088                                                     &data);
3089                         if (ret_val)
3090                                 return ret_val;
3091
3092                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3093                         ret_val = phy->ops.write_reg(hw,
3094                                                      IGP01E1000_PHY_PORT_CONFIG,
3095                                                      data);
3096                         if (ret_val)
3097                                 return ret_val;
3098                 }
3099         }
3100
3101         return E1000_SUCCESS;
3102 }
3103
3104 /**
3105  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3106  *  @hw: pointer to the HW structure
3107  *  @active: TRUE to enable LPLU, FALSE to disable
3108  *
3109  *  Sets the LPLU D3 state according to the active flag.  When
3110  *  activating LPLU this function also disables smart speed
3111  *  and vice versa.  LPLU will not be activated unless the
3112  *  device autonegotiation advertisement meets standards of
3113  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3114  *  This is a function pointer entry point only called by
3115  *  PHY setup routines.
3116  **/
3117 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3118 {
3119         struct e1000_phy_info *phy = &hw->phy;
3120         u32 phy_ctrl;
3121         s32 ret_val = E1000_SUCCESS;
3122         u16 data;
3123
3124         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
3125
3126         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
3127
3128         if (!active) {
3129                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3130                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3131
3132                 if (phy->type != e1000_phy_igp_3)
3133                         return E1000_SUCCESS;
3134
3135                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3136                  * during Dx states where the power conservation is most
3137                  * important.  During driver activity we should enable
3138                  * SmartSpeed, so performance is maintained.
3139                  */
3140                 if (phy->smart_speed == e1000_smart_speed_on) {
3141                         ret_val = phy->ops.read_reg(hw,
3142                                                     IGP01E1000_PHY_PORT_CONFIG,
3143                                                     &data);
3144                         if (ret_val)
3145                                 return ret_val;
3146
3147                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3148                         ret_val = phy->ops.write_reg(hw,
3149                                                      IGP01E1000_PHY_PORT_CONFIG,
3150                                                      data);
3151                         if (ret_val)
3152                                 return ret_val;
3153                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3154                         ret_val = phy->ops.read_reg(hw,
3155                                                     IGP01E1000_PHY_PORT_CONFIG,
3156                                                     &data);
3157                         if (ret_val)
3158                                 return ret_val;
3159
3160                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3161                         ret_val = phy->ops.write_reg(hw,
3162                                                      IGP01E1000_PHY_PORT_CONFIG,
3163                                                      data);
3164                         if (ret_val)
3165                                 return ret_val;
3166                 }
3167         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3168                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3169                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3170                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3171                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
3172
3173                 if (phy->type != e1000_phy_igp_3)
3174                         return E1000_SUCCESS;
3175
3176                 /* Call gig speed drop workaround on LPLU before accessing
3177                  * any PHY registers
3178                  */
3179                 if (hw->mac.type == e1000_ich8lan)
3180                         e1000_gig_downshift_workaround_ich8lan(hw);
3181
3182                 /* When LPLU is enabled, we should disable SmartSpeed */
3183                 ret_val = phy->ops.read_reg(hw,
3184                                             IGP01E1000_PHY_PORT_CONFIG,
3185                                             &data);
3186                 if (ret_val)
3187                         return ret_val;
3188
3189                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3190                 ret_val = phy->ops.write_reg(hw,
3191                                              IGP01E1000_PHY_PORT_CONFIG,
3192                                              data);
3193         }
3194
3195         return ret_val;
3196 }
3197
3198 /**
3199  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3200  *  @hw: pointer to the HW structure
3201  *  @bank:  pointer to the variable that returns the active bank
3202  *
3203  *  Reads signature byte from the NVM using the flash access registers.
3204  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3205  **/
3206 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3207 {
3208         u32 eecd;
3209         struct e1000_nvm_info *nvm = &hw->nvm;
3210         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3211         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3212         u8 sig_byte = 0;
3213         s32 ret_val;
3214
3215         DEBUGFUNC("e1000_valid_nvm_bank_detect_ich8lan");
3216
3217         switch (hw->mac.type) {
3218         case e1000_ich8lan:
3219         case e1000_ich9lan:
3220                 eecd = E1000_READ_REG(hw, E1000_EECD);
3221                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3222                     E1000_EECD_SEC1VAL_VALID_MASK) {
3223                         if (eecd & E1000_EECD_SEC1VAL)
3224                                 *bank = 1;
3225                         else
3226                                 *bank = 0;
3227
3228                         return E1000_SUCCESS;
3229                 }
3230                 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3231                 /* fall-thru */
3232         default:
3233                 /* set bank to 0 in case flash read fails */
3234                 *bank = 0;
3235
3236                 /* Check bank 0 */
3237                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3238                                                         &sig_byte);
3239                 if (ret_val)
3240                         return ret_val;
3241                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3242                     E1000_ICH_NVM_SIG_VALUE) {
3243                         *bank = 0;
3244                         return E1000_SUCCESS;
3245                 }
3246
3247                 /* Check bank 1 */
3248                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3249                                                         bank1_offset,
3250                                                         &sig_byte);
3251                 if (ret_val)
3252                         return ret_val;
3253                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3254                     E1000_ICH_NVM_SIG_VALUE) {
3255                         *bank = 1;
3256                         return E1000_SUCCESS;
3257                 }
3258
3259                 DEBUGOUT("ERROR: No valid NVM bank present\n");
3260                 return -E1000_ERR_NVM;
3261         }
3262 }
3263
3264 /**
3265  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3266  *  @hw: pointer to the HW structure
3267  *  @offset: The offset (in bytes) of the word(s) to read.
3268  *  @words: Size of data to read in words
3269  *  @data: Pointer to the word(s) to read at offset.
3270  *
3271  *  Reads a word(s) from the NVM using the flash access registers.
3272  **/
3273 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3274                                   u16 *data)
3275 {
3276         struct e1000_nvm_info *nvm = &hw->nvm;
3277         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3278         u32 act_offset;
3279         s32 ret_val = E1000_SUCCESS;
3280         u32 bank = 0;
3281         u16 i, word;
3282
3283         DEBUGFUNC("e1000_read_nvm_ich8lan");
3284
3285         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3286             (words == 0)) {
3287                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3288                 ret_val = -E1000_ERR_NVM;
3289                 goto out;
3290         }
3291
3292         nvm->ops.acquire(hw);
3293
3294         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3295         if (ret_val != E1000_SUCCESS) {
3296                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3297                 bank = 0;
3298         }
3299
3300         act_offset = (bank) ? nvm->flash_bank_size : 0;
3301         act_offset += offset;
3302
3303         ret_val = E1000_SUCCESS;
3304         for (i = 0; i < words; i++) {
3305                 if (dev_spec->shadow_ram[offset+i].modified) {
3306                         data[i] = dev_spec->shadow_ram[offset+i].value;
3307                 } else {
3308                         ret_val = e1000_read_flash_word_ich8lan(hw,
3309                                                                 act_offset + i,
3310                                                                 &word);
3311                         if (ret_val)
3312                                 break;
3313                         data[i] = word;
3314                 }
3315         }
3316
3317         nvm->ops.release(hw);
3318
3319 out:
3320         if (ret_val)
3321                 DEBUGOUT1("NVM read error: %d\n", ret_val);
3322
3323         return ret_val;
3324 }
3325
3326 /**
3327  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3328  *  @hw: pointer to the HW structure
3329  *
3330  *  This function does initial flash setup so that a new read/write/erase cycle
3331  *  can be started.
3332  **/
3333 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3334 {
3335         union ich8_hws_flash_status hsfsts;
3336         s32 ret_val = -E1000_ERR_NVM;
3337
3338         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
3339
3340         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3341
3342         /* Check if the flash descriptor is valid */
3343         if (!hsfsts.hsf_status.fldesvalid) {
3344                 DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
3345                 return -E1000_ERR_NVM;
3346         }
3347
3348         /* Clear FCERR and DAEL in hw status by writing 1 */
3349         hsfsts.hsf_status.flcerr = 1;
3350         hsfsts.hsf_status.dael = 1;
3351         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3352
3353         /* Either we should have a hardware SPI cycle in progress
3354          * bit to check against, in order to start a new cycle or
3355          * FDONE bit should be changed in the hardware so that it
3356          * is 1 after hardware reset, which can then be used as an
3357          * indication whether a cycle is in progress or has been
3358          * completed.
3359          */
3360
3361         if (!hsfsts.hsf_status.flcinprog) {
3362                 /* There is no cycle running at present,
3363                  * so we can start a cycle.
3364                  * Begin by setting Flash Cycle Done.
3365                  */
3366                 hsfsts.hsf_status.flcdone = 1;
3367                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
3368                 ret_val = E1000_SUCCESS;
3369         } else {
3370                 s32 i;
3371
3372                 /* Otherwise poll for sometime so the current
3373                  * cycle has a chance to end before giving up.
3374                  */
3375                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3376                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3377                                                               ICH_FLASH_HSFSTS);
3378                         if (!hsfsts.hsf_status.flcinprog) {
3379                                 ret_val = E1000_SUCCESS;
3380                                 break;
3381                         }
3382                         usec_delay(1);
3383                 }
3384                 if (ret_val == E1000_SUCCESS) {
3385                         /* Successful in waiting for previous cycle to timeout,
3386                          * now set the Flash Cycle Done.
3387                          */
3388                         hsfsts.hsf_status.flcdone = 1;
3389                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
3390                                                 hsfsts.regval);
3391                 } else {
3392                         DEBUGOUT("Flash controller busy, cannot get access\n");
3393                 }
3394         }
3395
3396         return ret_val;
3397 }
3398
3399 /**
3400  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3401  *  @hw: pointer to the HW structure
3402  *  @timeout: maximum time to wait for completion
3403  *
3404  *  This function starts a flash cycle and waits for its completion.
3405  **/
3406 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3407 {
3408         union ich8_hws_flash_ctrl hsflctl;
3409         union ich8_hws_flash_status hsfsts;
3410         u32 i = 0;
3411
3412         DEBUGFUNC("e1000_flash_cycle_ich8lan");
3413
3414         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3415         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3416         hsflctl.hsf_ctrl.flcgo = 1;
3417
3418         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3419
3420         /* wait till FDONE bit is set to 1 */
3421         do {
3422                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3423                 if (hsfsts.hsf_status.flcdone)
3424                         break;
3425                 usec_delay(1);
3426         } while (i++ < timeout);
3427
3428         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3429                 return E1000_SUCCESS;
3430
3431         return -E1000_ERR_NVM;
3432 }
3433
3434 /**
3435  *  e1000_read_flash_word_ich8lan - Read word from flash
3436  *  @hw: pointer to the HW structure
3437  *  @offset: offset to data location
3438  *  @data: pointer to the location for storing the data
3439  *
3440  *  Reads the flash word at offset into data.  Offset is converted
3441  *  to bytes before read.
3442  **/
3443 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3444                                          u16 *data)
3445 {
3446         DEBUGFUNC("e1000_read_flash_word_ich8lan");
3447
3448         if (!data)
3449                 return -E1000_ERR_NVM;
3450
3451         /* Must convert offset into bytes. */
3452         offset <<= 1;
3453
3454         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3455 }
3456
3457 /**
3458  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3459  *  @hw: pointer to the HW structure
3460  *  @offset: The offset of the byte to read.
3461  *  @data: Pointer to a byte to store the value read.
3462  *
3463  *  Reads a single byte from the NVM using the flash access registers.
3464  **/
3465 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3466                                          u8 *data)
3467 {
3468         s32 ret_val;
3469         u16 word = 0;
3470
3471         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3472
3473         if (ret_val)
3474                 return ret_val;
3475
3476         *data = (u8)word;
3477
3478         return E1000_SUCCESS;
3479 }
3480
3481 /**
3482  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3483  *  @hw: pointer to the HW structure
3484  *  @offset: The offset (in bytes) of the byte or word to read.
3485  *  @size: Size of data to read, 1=byte 2=word
3486  *  @data: Pointer to the word to store the value read.
3487  *
3488  *  Reads a byte or word from the NVM using the flash access registers.
3489  **/
3490 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3491                                          u8 size, u16 *data)
3492 {
3493         union ich8_hws_flash_status hsfsts;
3494         union ich8_hws_flash_ctrl hsflctl;
3495         u32 flash_linear_addr;
3496         u32 flash_data = 0;
3497         s32 ret_val = -E1000_ERR_NVM;
3498         u8 count = 0;
3499
3500         DEBUGFUNC("e1000_read_flash_data_ich8lan");
3501
3502         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3503                 return -E1000_ERR_NVM;
3504         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3505                              hw->nvm.flash_base_addr);
3506
3507         do {
3508                 usec_delay(1);
3509                 /* Steps */
3510                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3511                 if (ret_val != E1000_SUCCESS)
3512                         break;
3513                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3514
3515                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3516                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3517                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3518                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3519                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3520
3521                 ret_val = e1000_flash_cycle_ich8lan(hw,
3522                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
3523
3524                 /* Check if FCERR is set to 1, if set to 1, clear it
3525                  * and try the whole sequence a few more times, else
3526                  * read in (shift in) the Flash Data0, the order is
3527                  * least significant byte first msb to lsb
3528                  */
3529                 if (ret_val == E1000_SUCCESS) {
3530                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
3531                         if (size == 1)
3532                                 *data = (u8)(flash_data & 0x000000FF);
3533                         else if (size == 2)
3534                                 *data = (u16)(flash_data & 0x0000FFFF);
3535                         break;
3536                 } else {
3537                         /* If we've gotten here, then things are probably
3538                          * completely hosed, but if the error condition is
3539                          * detected, it won't hurt to give it another try...
3540                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3541                          */
3542                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
3543                                                               ICH_FLASH_HSFSTS);
3544                         if (hsfsts.hsf_status.flcerr) {
3545                                 /* Repeat for some time before giving up. */
3546                                 continue;
3547                         } else if (!hsfsts.hsf_status.flcdone) {
3548                                 DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3549                                 break;
3550                         }
3551                 }
3552         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3553
3554         return ret_val;
3555 }
3556
3557
3558 /**
3559  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3560  *  @hw: pointer to the HW structure
3561  *  @offset: The offset (in bytes) of the word(s) to write.
3562  *  @words: Size of data to write in words
3563  *  @data: Pointer to the word(s) to write at offset.
3564  *
3565  *  Writes a byte or word to the NVM using the flash access registers.
3566  **/
3567 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3568                                    u16 *data)
3569 {
3570         struct e1000_nvm_info *nvm = &hw->nvm;
3571         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3572         u16 i;
3573
3574         DEBUGFUNC("e1000_write_nvm_ich8lan");
3575
3576         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3577             (words == 0)) {
3578                 DEBUGOUT("nvm parameter(s) out of bounds\n");
3579                 return -E1000_ERR_NVM;
3580         }
3581
3582         nvm->ops.acquire(hw);
3583
3584         for (i = 0; i < words; i++) {
3585                 dev_spec->shadow_ram[offset+i].modified = TRUE;
3586                 dev_spec->shadow_ram[offset+i].value = data[i];
3587         }
3588
3589         nvm->ops.release(hw);
3590
3591         return E1000_SUCCESS;
3592 }
3593
3594 /**
3595  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3596  *  @hw: pointer to the HW structure
3597  *
3598  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3599  *  which writes the checksum to the shadow ram.  The changes in the shadow
3600  *  ram are then committed to the EEPROM by processing each bank at a time
3601  *  checking for the modified bit and writing only the pending changes.
3602  *  After a successful commit, the shadow ram is cleared and is ready for
3603  *  future writes.
3604  **/
3605 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3606 {
3607         struct e1000_nvm_info *nvm = &hw->nvm;
3608         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3609         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3610         s32 ret_val;
3611         u16 data = 0;
3612
3613         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
3614
3615         ret_val = e1000_update_nvm_checksum_generic(hw);
3616         if (ret_val)
3617                 goto out;
3618
3619         if (nvm->type != e1000_nvm_flash_sw)
3620                 goto out;
3621
3622         nvm->ops.acquire(hw);
3623
3624         /* We're writing to the opposite bank so if we're on bank 1,
3625          * write to bank 0 etc.  We also need to erase the segment that
3626          * is going to be written
3627          */
3628         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3629         if (ret_val != E1000_SUCCESS) {
3630                 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
3631                 bank = 0;
3632         }
3633
3634         if (bank == 0) {
3635                 new_bank_offset = nvm->flash_bank_size;
3636                 old_bank_offset = 0;
3637                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3638                 if (ret_val)
3639                         goto release;
3640         } else {
3641                 old_bank_offset = nvm->flash_bank_size;
3642                 new_bank_offset = 0;
3643                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3644                 if (ret_val)
3645                         goto release;
3646         }
3647         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3648                 if (dev_spec->shadow_ram[i].modified) {
3649                         data = dev_spec->shadow_ram[i].value;
3650                 } else {
3651                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3652                                                                 old_bank_offset,
3653                                                                 &data);
3654                         if (ret_val)
3655                                 break;
3656                 }
3657                 /* If the word is 0x13, then make sure the signature bits
3658                  * (15:14) are 11b until the commit has completed.
3659                  * This will allow us to write 10b which indicates the
3660                  * signature is valid.  We want to do this after the write
3661                  * has completed so that we don't mark the segment valid
3662                  * while the write is still in progress
3663                  */
3664                 if (i == E1000_ICH_NVM_SIG_WORD)
3665                         data |= E1000_ICH_NVM_SIG_MASK;
3666
3667                 /* Convert offset to bytes. */
3668                 act_offset = (i + new_bank_offset) << 1;
3669
3670                 usec_delay(100);
3671
3672                 /* Write the bytes to the new bank. */
3673                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3674                                                                act_offset,
3675                                                                (u8)data);
3676                 if (ret_val)
3677                         break;
3678
3679                 usec_delay(100);
3680                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3681                                                           act_offset + 1,
3682                                                           (u8)(data >> 8));
3683                 if (ret_val)
3684                         break;
3685          }
3686
3687         /* Don't bother writing the segment valid bits if sector
3688          * programming failed.
3689          */
3690         if (ret_val) {
3691                 DEBUGOUT("Flash commit failed.\n");
3692                 goto release;
3693         }
3694
3695         /* Finally validate the new segment by setting bit 15:14
3696          * to 10b in word 0x13 , this can be done without an
3697          * erase as well since these bits are 11 to start with
3698          * and we need to change bit 14 to 0b
3699          */
3700         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3701         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
3702         if (ret_val)
3703                 goto release;
3704
3705         data &= 0xBFFF;
3706         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset * 2 + 1,
3707                                                        (u8)(data >> 8));
3708         if (ret_val)
3709                 goto release;
3710
3711         /* And invalidate the previously valid segment by setting
3712          * its signature word (0x13) high_byte to 0b. This can be
3713          * done without an erase because flash erase sets all bits
3714          * to 1's. We can write 1's to 0's without an erase
3715          */
3716         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3717
3718         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3719
3720         if (ret_val)
3721                 goto release;
3722
3723         /* Great!  Everything worked, we can now clear the cached entries. */
3724         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
3725                 dev_spec->shadow_ram[i].modified = FALSE;
3726                 dev_spec->shadow_ram[i].value = 0xFFFF;
3727         }
3728
3729 release:
3730         nvm->ops.release(hw);
3731
3732         /* Reload the EEPROM, or else modifications will not appear
3733          * until after the next adapter reset.
3734          */
3735         if (!ret_val) {
3736                 nvm->ops.reload(hw);
3737                 msec_delay(10);
3738         }
3739
3740 out:
3741         if (ret_val)
3742                 DEBUGOUT1("NVM update error: %d\n", ret_val);
3743
3744         return ret_val;
3745 }
3746
3747 /**
3748  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3749  *  @hw: pointer to the HW structure
3750  *
3751  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3752  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
3753  *  calculated, in which case we need to calculate the checksum and set bit 6.
3754  **/
3755 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3756 {
3757         s32 ret_val;
3758         u16 data;
3759         u16 word;
3760         u16 valid_csum_mask;
3761
3762         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
3763
3764         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
3765          * the checksum needs to be fixed.  This bit is an indication that
3766          * the NVM was prepared by OEM software and did not calculate
3767          * the checksum...a likely scenario.
3768          */
3769         switch (hw->mac.type) {
3770         case e1000_pch_lpt:
3771                 word = NVM_COMPAT;
3772                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3773                 break;
3774         default:
3775                 word = NVM_FUTURE_INIT_WORD1;
3776                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3777                 break;
3778         }
3779
3780         ret_val = hw->nvm.ops.read(hw, word, 1, &data);
3781         if (ret_val)
3782                 return ret_val;
3783
3784         if (!(data & valid_csum_mask)) {
3785                 data |= valid_csum_mask;
3786                 ret_val = hw->nvm.ops.write(hw, word, 1, &data);
3787                 if (ret_val)
3788                         return ret_val;
3789                 ret_val = hw->nvm.ops.update(hw);
3790                 if (ret_val)
3791                         return ret_val;
3792         }
3793
3794         return e1000_validate_nvm_checksum_generic(hw);
3795 }
3796
3797 /**
3798  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3799  *  @hw: pointer to the HW structure
3800  *  @offset: The offset (in bytes) of the byte/word to read.
3801  *  @size: Size of data to read, 1=byte 2=word
3802  *  @data: The byte(s) to write to the NVM.
3803  *
3804  *  Writes one/two bytes to the NVM using the flash access registers.
3805  **/
3806 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3807                                           u8 size, u16 data)
3808 {
3809         union ich8_hws_flash_status hsfsts;
3810         union ich8_hws_flash_ctrl hsflctl;
3811         u32 flash_linear_addr;
3812         u32 flash_data = 0;
3813         s32 ret_val;
3814         u8 count = 0;
3815
3816         DEBUGFUNC("e1000_write_ich8_data");
3817
3818         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3819                 return -E1000_ERR_NVM;
3820
3821         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3822                              hw->nvm.flash_base_addr);
3823
3824         do {
3825                 usec_delay(1);
3826                 /* Steps */
3827                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3828                 if (ret_val != E1000_SUCCESS)
3829                         break;
3830                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
3831
3832                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3833                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3834                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3835                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
3836
3837                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
3838
3839                 if (size == 1)
3840                         flash_data = (u32)data & 0x00FF;
3841                 else
3842                         flash_data = (u32)data;
3843
3844                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
3845
3846                 /* check if FCERR is set to 1 , if set to 1, clear it
3847                  * and try the whole sequence a few more times else done
3848                  */
3849                 ret_val =
3850                     e1000_flash_cycle_ich8lan(hw,
3851                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3852                 if (ret_val == E1000_SUCCESS)
3853                         break;
3854
3855                 /* If we're here, then things are most likely
3856                  * completely hosed, but if the error condition
3857                  * is detected, it won't hurt to give it another
3858                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3859                  */
3860                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3861                 if (hsfsts.hsf_status.flcerr)
3862                         /* Repeat for some time before giving up. */
3863                         continue;
3864                 if (!hsfsts.hsf_status.flcdone) {
3865                         DEBUGOUT("Timeout error - flash cycle did not complete.\n");
3866                         break;
3867                 }
3868         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3869
3870         return ret_val;
3871 }
3872
3873
3874 /**
3875  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3876  *  @hw: pointer to the HW structure
3877  *  @offset: The index of the byte to read.
3878  *  @data: The byte to write to the NVM.
3879  *
3880  *  Writes a single byte to the NVM using the flash access registers.
3881  **/
3882 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3883                                           u8 data)
3884 {
3885         u16 word = (u16)data;
3886
3887         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
3888
3889         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3890 }
3891
3892
3893
3894 /**
3895  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3896  *  @hw: pointer to the HW structure
3897  *  @offset: The offset of the byte to write.
3898  *  @byte: The byte to write to the NVM.
3899  *
3900  *  Writes a single byte to the NVM using the flash access registers.
3901  *  Goes through a retry algorithm before giving up.
3902  **/
3903 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3904                                                 u32 offset, u8 byte)
3905 {
3906         s32 ret_val;
3907         u16 program_retries;
3908
3909         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
3910
3911         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3912         if (!ret_val)
3913                 return ret_val;
3914
3915         for (program_retries = 0; program_retries < 100; program_retries++) {
3916                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
3917                 usec_delay(100);
3918                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3919                 if (ret_val == E1000_SUCCESS)
3920                         break;
3921         }
3922         if (program_retries == 100)
3923                 return -E1000_ERR_NVM;
3924
3925         return E1000_SUCCESS;
3926 }
3927
3928 /**
3929  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3930  *  @hw: pointer to the HW structure
3931  *  @bank: 0 for first bank, 1 for second bank, etc.
3932  *
3933  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3934  *  bank N is 4096 * N + flash_reg_addr.
3935  **/
3936 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3937 {
3938         struct e1000_nvm_info *nvm = &hw->nvm;
3939         union ich8_hws_flash_status hsfsts;
3940         union ich8_hws_flash_ctrl hsflctl;
3941         u32 flash_linear_addr;
3942         /* bank size is in 16bit words - adjust to bytes */
3943         u32 flash_bank_size = nvm->flash_bank_size * 2;
3944         s32 ret_val;
3945         s32 count = 0;
3946         s32 j, iteration, sector_size;
3947
3948         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
3949
3950         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
3951
3952         /* Determine HW Sector size: Read BERASE bits of hw flash status
3953          * register
3954          * 00: The Hw sector is 256 bytes, hence we need to erase 16
3955          *     consecutive sectors.  The start index for the nth Hw sector
3956          *     can be calculated as = bank * 4096 + n * 256
3957          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3958          *     The start index for the nth Hw sector can be calculated
3959          *     as = bank * 4096
3960          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3961          *     (ich9 only, otherwise error condition)
3962          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3963          */
3964         switch (hsfsts.hsf_status.berasesz) {
3965         case 0:
3966                 /* Hw sector size 256 */
3967                 sector_size = ICH_FLASH_SEG_SIZE_256;
3968                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3969                 break;
3970         case 1:
3971                 sector_size = ICH_FLASH_SEG_SIZE_4K;
3972                 iteration = 1;
3973                 break;
3974         case 2:
3975                 sector_size = ICH_FLASH_SEG_SIZE_8K;
3976                 iteration = 1;
3977                 break;
3978         case 3:
3979                 sector_size = ICH_FLASH_SEG_SIZE_64K;
3980                 iteration = 1;
3981                 break;
3982         default:
3983                 return -E1000_ERR_NVM;
3984         }
3985
3986         /* Start with the base address, then add the sector offset. */
3987         flash_linear_addr = hw->nvm.flash_base_addr;
3988         flash_linear_addr += (bank) ? flash_bank_size : 0;
3989
3990         for (j = 0; j < iteration; j++) {
3991                 do {
3992                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3993
3994                         /* Steps */
3995                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
3996                         if (ret_val)
3997                                 return ret_val;
3998
3999                         /* Write a value 11 (block Erase) in Flash
4000                          * Cycle field in hw flash control
4001                          */
4002                         hsflctl.regval =
4003                             E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
4004
4005                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4006                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
4007                                                 hsflctl.regval);
4008
4009                         /* Write the last 24 bits of an index within the
4010                          * block into Flash Linear address field in Flash
4011                          * Address.
4012                          */
4013                         flash_linear_addr += (j * sector_size);
4014                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
4015                                               flash_linear_addr);
4016
4017                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4018                         if (ret_val == E1000_SUCCESS)
4019                                 break;
4020
4021                         /* Check if FCERR is set to 1.  If 1,
4022                          * clear it and try the whole sequence
4023                          * a few more times else Done
4024                          */
4025                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
4026                                                       ICH_FLASH_HSFSTS);
4027                         if (hsfsts.hsf_status.flcerr)
4028                                 /* repeat for some time before giving up */
4029                                 continue;
4030                         else if (!hsfsts.hsf_status.flcdone)
4031                                 return ret_val;
4032                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4033         }
4034
4035         return E1000_SUCCESS;
4036 }
4037
4038 /**
4039  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4040  *  @hw: pointer to the HW structure
4041  *  @data: Pointer to the LED settings
4042  *
4043  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4044  *  settings is all 0's or F's, set the LED default to a valid LED default
4045  *  setting.
4046  **/
4047 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4048 {
4049         s32 ret_val;
4050
4051         DEBUGFUNC("e1000_valid_led_default_ich8lan");
4052
4053         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
4054         if (ret_val) {
4055                 DEBUGOUT("NVM Read Error\n");
4056                 return ret_val;
4057         }
4058
4059         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4060                 *data = ID_LED_DEFAULT_ICH8LAN;
4061
4062         return E1000_SUCCESS;
4063 }
4064
4065 /**
4066  *  e1000_id_led_init_pchlan - store LED configurations
4067  *  @hw: pointer to the HW structure
4068  *
4069  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4070  *  the PHY LED configuration register.
4071  *
4072  *  PCH also does not have an "always on" or "always off" mode which
4073  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4074  *  in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),
4075  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4076  *  link based on logic in e1000_led_[on|off]_pchlan().
4077  **/
4078 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4079 {
4080         struct e1000_mac_info *mac = &hw->mac;
4081         s32 ret_val;
4082         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4083         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4084         u16 data, i, temp, shift;
4085
4086         DEBUGFUNC("e1000_id_led_init_pchlan");
4087
4088         /* Get default ID LED modes */
4089         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4090         if (ret_val)
4091                 return ret_val;
4092
4093         mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
4094         mac->ledctl_mode1 = mac->ledctl_default;
4095         mac->ledctl_mode2 = mac->ledctl_default;
4096
4097         for (i = 0; i < 4; i++) {
4098                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4099                 shift = (i * 5);
4100                 switch (temp) {
4101                 case ID_LED_ON1_DEF2:
4102                 case ID_LED_ON1_ON2:
4103                 case ID_LED_ON1_OFF2:
4104                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4105                         mac->ledctl_mode1 |= (ledctl_on << shift);
4106                         break;
4107                 case ID_LED_OFF1_DEF2:
4108                 case ID_LED_OFF1_ON2:
4109                 case ID_LED_OFF1_OFF2:
4110                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4111                         mac->ledctl_mode1 |= (ledctl_off << shift);
4112                         break;
4113                 default:
4114                         /* Do nothing */
4115                         break;
4116                 }
4117                 switch (temp) {
4118                 case ID_LED_DEF1_ON2:
4119                 case ID_LED_ON1_ON2:
4120                 case ID_LED_OFF1_ON2:
4121                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4122                         mac->ledctl_mode2 |= (ledctl_on << shift);
4123                         break;
4124                 case ID_LED_DEF1_OFF2:
4125                 case ID_LED_ON1_OFF2:
4126                 case ID_LED_OFF1_OFF2:
4127                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4128                         mac->ledctl_mode2 |= (ledctl_off << shift);
4129                         break;
4130                 default:
4131                         /* Do nothing */
4132                         break;
4133                 }
4134         }
4135
4136         return E1000_SUCCESS;
4137 }
4138
4139 /**
4140  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4141  *  @hw: pointer to the HW structure
4142  *
4143  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4144  *  register, so the the bus width is hard coded.
4145  **/
4146 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4147 {
4148         struct e1000_bus_info *bus = &hw->bus;
4149         s32 ret_val;
4150
4151         DEBUGFUNC("e1000_get_bus_info_ich8lan");
4152
4153         ret_val = e1000_get_bus_info_pcie_generic(hw);
4154
4155         /* ICH devices are "PCI Express"-ish.  They have
4156          * a configuration space, but do not contain
4157          * PCI Express Capability registers, so bus width
4158          * must be hardcoded.
4159          */
4160         if (bus->width == e1000_bus_width_unknown)
4161                 bus->width = e1000_bus_width_pcie_x1;
4162
4163         return ret_val;
4164 }
4165
4166 /**
4167  *  e1000_reset_hw_ich8lan - Reset the hardware
4168  *  @hw: pointer to the HW structure
4169  *
4170  *  Does a full reset of the hardware which includes a reset of the PHY and
4171  *  MAC.
4172  **/
4173 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4174 {
4175         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4176         u16 kum_cfg;
4177         u32 ctrl, reg;
4178         s32 ret_val;
4179
4180         DEBUGFUNC("e1000_reset_hw_ich8lan");
4181
4182         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4183          * on the last TLP read/write transaction when MAC is reset.
4184          */
4185         ret_val = e1000_disable_pcie_master_generic(hw);
4186         if (ret_val)
4187                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
4188
4189         DEBUGOUT("Masking off all interrupts\n");
4190         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4191
4192         /* Disable the Transmit and Receive units.  Then delay to allow
4193          * any pending transactions to complete before we hit the MAC
4194          * with the global reset.
4195          */
4196         E1000_WRITE_REG(hw, E1000_RCTL, 0);
4197         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
4198         E1000_WRITE_FLUSH(hw);
4199
4200         msec_delay(10);
4201
4202         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4203         if (hw->mac.type == e1000_ich8lan) {
4204                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4205                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
4206                 /* Set Packet Buffer Size to 16k. */
4207                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
4208         }
4209
4210         if (hw->mac.type == e1000_pchlan) {
4211                 /* Save the NVM K1 bit setting*/
4212                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4213                 if (ret_val)
4214                         return ret_val;
4215
4216                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4217                         dev_spec->nvm_k1_enabled = TRUE;
4218                 else
4219                         dev_spec->nvm_k1_enabled = FALSE;
4220         }
4221
4222         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4223
4224         if (!hw->phy.ops.check_reset_block(hw)) {
4225                 /* Full-chip reset requires MAC and PHY reset at the same
4226                  * time to make sure the interface between MAC and the
4227                  * external PHY is reset.
4228                  */
4229                 ctrl |= E1000_CTRL_PHY_RST;
4230
4231                 /* Gate automatic PHY configuration by hardware on
4232                  * non-managed 82579
4233                  */
4234                 if ((hw->mac.type == e1000_pch2lan) &&
4235                     !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))
4236                         e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
4237         }
4238         ret_val = e1000_acquire_swflag_ich8lan(hw);
4239         DEBUGOUT("Issuing a global reset to ich8lan\n");
4240         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
4241         /* cannot issue a flush here because it hangs the hardware */
4242         msec_delay(20);
4243
4244         /* Set Phy Config Counter to 50msec */
4245         if (hw->mac.type == e1000_pch2lan) {
4246                 reg = E1000_READ_REG(hw, E1000_FEXTNVM3);
4247                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4248                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4249                 E1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);
4250         }
4251
4252         if (!ret_val)
4253                 E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
4254
4255         if (ctrl & E1000_CTRL_PHY_RST) {
4256                 ret_val = hw->phy.ops.get_cfg_done(hw);
4257                 if (ret_val)
4258                         return ret_val;
4259
4260                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4261                 if (ret_val)
4262                         return ret_val;
4263         }
4264
4265         /* For PCH, this write will make sure that any noise
4266          * will be detected as a CRC error and be dropped rather than show up
4267          * as a bad packet to the DMA engine.
4268          */
4269         if (hw->mac.type == e1000_pchlan)
4270                 E1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);
4271
4272         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
4273         E1000_READ_REG(hw, E1000_ICR);
4274
4275         reg = E1000_READ_REG(hw, E1000_KABGTXD);
4276         reg |= E1000_KABGTXD_BGSQLBIAS;
4277         E1000_WRITE_REG(hw, E1000_KABGTXD, reg);
4278
4279         return E1000_SUCCESS;
4280 }
4281
4282 /**
4283  *  e1000_init_hw_ich8lan - Initialize the hardware
4284  *  @hw: pointer to the HW structure
4285  *
4286  *  Prepares the hardware for transmit and receive by doing the following:
4287  *   - initialize hardware bits
4288  *   - initialize LED identification
4289  *   - setup receive address registers
4290  *   - setup flow control
4291  *   - setup transmit descriptors
4292  *   - clear statistics
4293  **/
4294 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4295 {
4296         struct e1000_mac_info *mac = &hw->mac;
4297         u32 ctrl_ext, txdctl, snoop;
4298         s32 ret_val;
4299         u16 i;
4300
4301         DEBUGFUNC("e1000_init_hw_ich8lan");
4302
4303         e1000_initialize_hw_bits_ich8lan(hw);
4304
4305         /* Initialize identification LED */
4306         ret_val = mac->ops.id_led_init(hw);
4307         /* An error is not fatal and we should not stop init due to this */
4308         if (ret_val)
4309                 DEBUGOUT("Error initializing identification LED\n");
4310
4311         /* Setup the receive address. */
4312         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
4313
4314         /* Zero out the Multicast HASH table */
4315         DEBUGOUT("Zeroing the MTA\n");
4316         for (i = 0; i < mac->mta_reg_count; i++)
4317                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4318
4319         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4320          * the ME.  Disable wakeup by clearing the host wakeup bit.
4321          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4322          */
4323         if (hw->phy.type == e1000_phy_82578) {
4324                 hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
4325                 i &= ~BM_WUC_HOST_WU_BIT;
4326                 hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
4327                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4328                 if (ret_val)
4329                         return ret_val;
4330         }
4331
4332         /* Setup link and flow control */
4333         ret_val = mac->ops.setup_link(hw);
4334
4335         /* Set the transmit descriptor write-back policy for both queues */
4336         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
4337         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4338                   E1000_TXDCTL_FULL_TX_DESC_WB);
4339         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4340                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4341         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
4342         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
4343         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4344                   E1000_TXDCTL_FULL_TX_DESC_WB);
4345         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4346                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4347         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
4348
4349         /* ICH8 has opposite polarity of no_snoop bits.
4350          * By default, we should use snoop behavior.
4351          */
4352         if (mac->type == e1000_ich8lan)
4353                 snoop = PCIE_ICH8_SNOOP_ALL;
4354         else
4355                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
4356         e1000_set_pcie_no_snoop_generic(hw, snoop);
4357
4358         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
4359         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4360         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
4361
4362         /* Clear all of the statistics registers (clear on read).  It is
4363          * important that we do this after we have tried to establish link
4364          * because the symbol error count will increment wildly if there
4365          * is no link.
4366          */
4367         e1000_clear_hw_cntrs_ich8lan(hw);
4368
4369         return ret_val;
4370 }
4371
4372 /**
4373  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4374  *  @hw: pointer to the HW structure
4375  *
4376  *  Sets/Clears required hardware bits necessary for correctly setting up the
4377  *  hardware for transmit and receive.
4378  **/
4379 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4380 {
4381         u32 reg;
4382
4383         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
4384
4385         /* Extended Device Control */
4386         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
4387         reg |= (1 << 22);
4388         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4389         if (hw->mac.type >= e1000_pchlan)
4390                 reg |= E1000_CTRL_EXT_PHYPDEN;
4391         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
4392
4393         /* Transmit Descriptor Control 0 */
4394         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
4395         reg |= (1 << 22);
4396         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
4397
4398         /* Transmit Descriptor Control 1 */
4399         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
4400         reg |= (1 << 22);
4401         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
4402
4403         /* Transmit Arbitration Control 0 */
4404         reg = E1000_READ_REG(hw, E1000_TARC(0));
4405         if (hw->mac.type == e1000_ich8lan)
4406                 reg |= (1 << 28) | (1 << 29);
4407         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4408         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
4409
4410         /* Transmit Arbitration Control 1 */
4411         reg = E1000_READ_REG(hw, E1000_TARC(1));
4412         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
4413                 reg &= ~(1 << 28);
4414         else
4415                 reg |= (1 << 28);
4416         reg |= (1 << 24) | (1 << 26) | (1 << 30);
4417         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
4418
4419         /* Device Status */
4420         if (hw->mac.type == e1000_ich8lan) {
4421                 reg = E1000_READ_REG(hw, E1000_STATUS);
4422                 reg &= ~(1 << 31);
4423                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
4424         }
4425
4426         /* work-around descriptor data corruption issue during nfs v2 udp
4427          * traffic, just disable the nfs filtering capability
4428          */
4429         reg = E1000_READ_REG(hw, E1000_RFCTL);
4430         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4431
4432         /* Disable IPv6 extension header parsing because some malformed
4433          * IPv6 headers can hang the Rx.
4434          */
4435         if (hw->mac.type == e1000_ich8lan)
4436                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4437         E1000_WRITE_REG(hw, E1000_RFCTL, reg);
4438
4439         /* Enable ECC on Lynxpoint */
4440         if (hw->mac.type == e1000_pch_lpt) {
4441                 reg = E1000_READ_REG(hw, E1000_PBECCSTS);
4442                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4443                 E1000_WRITE_REG(hw, E1000_PBECCSTS, reg);
4444
4445                 reg = E1000_READ_REG(hw, E1000_CTRL);
4446                 reg |= E1000_CTRL_MEHE;
4447                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
4448         }
4449
4450         return;
4451 }
4452
4453 /**
4454  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4455  *  @hw: pointer to the HW structure
4456  *
4457  *  Determines which flow control settings to use, then configures flow
4458  *  control.  Calls the appropriate media-specific link configuration
4459  *  function.  Assuming the adapter has a valid link partner, a valid link
4460  *  should be established.  Assumes the hardware has previously been reset
4461  *  and the transmitter and receiver are not enabled.
4462  **/
4463 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4464 {
4465         s32 ret_val;
4466
4467         DEBUGFUNC("e1000_setup_link_ich8lan");
4468
4469         if (hw->phy.ops.check_reset_block(hw))
4470                 return E1000_SUCCESS;
4471
4472         /* ICH parts do not have a word in the NVM to determine
4473          * the default flow control setting, so we explicitly
4474          * set it to full.
4475          */
4476         if (hw->fc.requested_mode == e1000_fc_default)
4477                 hw->fc.requested_mode = e1000_fc_full;
4478
4479         /* Save off the requested flow control mode for use later.  Depending
4480          * on the link partner's capabilities, we may or may not use this mode.
4481          */
4482         hw->fc.current_mode = hw->fc.requested_mode;
4483
4484         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
4485                 hw->fc.current_mode);
4486
4487         /* Continue to configure the copper link. */
4488         ret_val = hw->mac.ops.setup_physical_interface(hw);
4489         if (ret_val)
4490                 return ret_val;
4491
4492         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
4493         if ((hw->phy.type == e1000_phy_82578) ||
4494             (hw->phy.type == e1000_phy_82579) ||
4495             (hw->phy.type == e1000_phy_i217) ||
4496             (hw->phy.type == e1000_phy_82577)) {
4497                 E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
4498
4499                 ret_val = hw->phy.ops.write_reg(hw,
4500                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
4501                                              hw->fc.pause_time);
4502                 if (ret_val)
4503                         return ret_val;
4504         }
4505
4506         return e1000_set_fc_watermarks_generic(hw);
4507 }
4508
4509 /**
4510  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4511  *  @hw: pointer to the HW structure
4512  *
4513  *  Configures the kumeran interface to the PHY to wait the appropriate time
4514  *  when polling the PHY, then call the generic setup_copper_link to finish
4515  *  configuring the copper link.
4516  **/
4517 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4518 {
4519         u32 ctrl;
4520         s32 ret_val;
4521         u16 reg_data;
4522
4523         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
4524
4525         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4526         ctrl |= E1000_CTRL_SLU;
4527         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4528         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4529
4530         /* Set the mac to wait the maximum time between each iteration
4531          * and increase the max iterations when polling the phy;
4532          * this fixes erroneous timeouts at 10Mbps.
4533          */
4534         ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
4535                                                0xFFFF);
4536         if (ret_val)
4537                 return ret_val;
4538         ret_val = e1000_read_kmrn_reg_generic(hw,
4539                                               E1000_KMRNCTRLSTA_INBAND_PARAM,
4540                                               &reg_data);
4541         if (ret_val)
4542                 return ret_val;
4543         reg_data |= 0x3F;
4544         ret_val = e1000_write_kmrn_reg_generic(hw,
4545                                                E1000_KMRNCTRLSTA_INBAND_PARAM,
4546                                                reg_data);
4547         if (ret_val)
4548                 return ret_val;
4549
4550         switch (hw->phy.type) {
4551         case e1000_phy_igp_3:
4552                 ret_val = e1000_copper_link_setup_igp(hw);
4553                 if (ret_val)
4554                         return ret_val;
4555                 break;
4556         case e1000_phy_bm:
4557         case e1000_phy_82578:
4558                 ret_val = e1000_copper_link_setup_m88(hw);
4559                 if (ret_val)
4560                         return ret_val;
4561                 break;
4562         case e1000_phy_82577:
4563         case e1000_phy_82579:
4564                 ret_val = e1000_copper_link_setup_82577(hw);
4565                 if (ret_val)
4566                         return ret_val;
4567                 break;
4568         case e1000_phy_ife:
4569                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
4570                                                &reg_data);
4571                 if (ret_val)
4572                         return ret_val;
4573
4574                 reg_data &= ~IFE_PMC_AUTO_MDIX;
4575
4576                 switch (hw->phy.mdix) {
4577                 case 1:
4578                         reg_data &= ~IFE_PMC_FORCE_MDIX;
4579                         break;
4580                 case 2:
4581                         reg_data |= IFE_PMC_FORCE_MDIX;
4582                         break;
4583                 case 0:
4584                 default:
4585                         reg_data |= IFE_PMC_AUTO_MDIX;
4586                         break;
4587                 }
4588                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
4589                                                 reg_data);
4590                 if (ret_val)
4591                         return ret_val;
4592                 break;
4593         default:
4594                 break;
4595         }
4596
4597         return e1000_setup_copper_link_generic(hw);
4598 }
4599
4600 /**
4601  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4602  *  @hw: pointer to the HW structure
4603  *
4604  *  Calls the PHY specific link setup function and then calls the
4605  *  generic setup_copper_link to finish configuring the link for
4606  *  Lynxpoint PCH devices
4607  **/
4608 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4609 {
4610         u32 ctrl;
4611         s32 ret_val;
4612
4613         DEBUGFUNC("e1000_setup_copper_link_pch_lpt");
4614
4615         ctrl = E1000_READ_REG(hw, E1000_CTRL);
4616         ctrl |= E1000_CTRL_SLU;
4617         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4618         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
4619
4620         ret_val = e1000_copper_link_setup_82577(hw);
4621         if (ret_val)
4622                 return ret_val;
4623
4624         return e1000_setup_copper_link_generic(hw);
4625 }
4626
4627 /**
4628  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4629  *  @hw: pointer to the HW structure
4630  *  @speed: pointer to store current link speed
4631  *  @duplex: pointer to store the current link duplex
4632  *
4633  *  Calls the generic get_speed_and_duplex to retrieve the current link
4634  *  information and then calls the Kumeran lock loss workaround for links at
4635  *  gigabit speeds.
4636  **/
4637 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4638                                           u16 *duplex)
4639 {
4640         s32 ret_val;
4641
4642         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
4643
4644         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
4645         if (ret_val)
4646                 return ret_val;
4647
4648         if ((hw->mac.type == e1000_ich8lan) &&
4649             (hw->phy.type == e1000_phy_igp_3) &&
4650             (*speed == SPEED_1000)) {
4651                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4652         }
4653
4654         return ret_val;
4655 }
4656
4657 /**
4658  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4659  *  @hw: pointer to the HW structure
4660  *
4661  *  Work-around for 82566 Kumeran PCS lock loss:
4662  *  On link status change (i.e. PCI reset, speed change) and link is up and
4663  *  speed is gigabit-
4664  *    0) if workaround is optionally disabled do nothing
4665  *    1) wait 1ms for Kumeran link to come up
4666  *    2) check Kumeran Diagnostic register PCS lock loss bit
4667  *    3) if not set the link is locked (all is good), otherwise...
4668  *    4) reset the PHY
4669  *    5) repeat up to 10 times
4670  *  Note: this is only called for IGP3 copper when speed is 1gb.
4671  **/
4672 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4673 {
4674         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4675         u32 phy_ctrl;
4676         s32 ret_val;
4677         u16 i, data;
4678         bool link;
4679
4680         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
4681
4682         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4683                 return E1000_SUCCESS;
4684
4685         /* Make sure link is up before proceeding.  If not just return.
4686          * Attempting this while link is negotiating fouled up link
4687          * stability
4688          */
4689         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4690         if (!link)
4691                 return E1000_SUCCESS;
4692
4693         for (i = 0; i < 10; i++) {
4694                 /* read once to clear */
4695                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4696                 if (ret_val)
4697                         return ret_val;
4698                 /* and again to get new status */
4699                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
4700                 if (ret_val)
4701                         return ret_val;
4702
4703                 /* check for PCS lock */
4704                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4705                         return E1000_SUCCESS;
4706
4707                 /* Issue PHY reset */
4708                 hw->phy.ops.reset(hw);
4709                 msec_delay_irq(5);
4710         }
4711         /* Disable GigE link negotiation */
4712         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4713         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4714                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4715         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4716
4717         /* Call gig speed drop workaround on Gig disable before accessing
4718          * any PHY registers
4719          */
4720         e1000_gig_downshift_workaround_ich8lan(hw);
4721
4722         /* unable to acquire PCS lock */
4723         return -E1000_ERR_PHY;
4724 }
4725
4726 /**
4727  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
4728  *  @hw: pointer to the HW structure
4729  *  @state: boolean value used to set the current Kumeran workaround state
4730  *
4731  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
4732  *  /disabled - FALSE).
4733  **/
4734 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
4735                                                  bool state)
4736 {
4737         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4738
4739         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
4740
4741         if (hw->mac.type != e1000_ich8lan) {
4742                 DEBUGOUT("Workaround applies to ICH8 only.\n");
4743                 return;
4744         }
4745
4746         dev_spec->kmrn_lock_loss_workaround_enabled = state;
4747
4748         return;
4749 }
4750
4751 /**
4752  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4753  *  @hw: pointer to the HW structure
4754  *
4755  *  Workaround for 82566 power-down on D3 entry:
4756  *    1) disable gigabit link
4757  *    2) write VR power-down enable
4758  *    3) read it back
4759  *  Continue if successful, else issue LCD reset and repeat
4760  **/
4761 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4762 {
4763         u32 reg;
4764         u16 data;
4765         u8  retry = 0;
4766
4767         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
4768
4769         if (hw->phy.type != e1000_phy_igp_3)
4770                 return;
4771
4772         /* Try the workaround twice (if needed) */
4773         do {
4774                 /* Disable link */
4775                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
4776                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4777                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4778                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
4779
4780                 /* Call gig speed drop workaround on Gig disable before
4781                  * accessing any PHY registers
4782                  */
4783                 if (hw->mac.type == e1000_ich8lan)
4784                         e1000_gig_downshift_workaround_ich8lan(hw);
4785
4786                 /* Write VR power-down enable */
4787                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4788                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4789                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
4790                                       data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4791
4792                 /* Read it back and test */
4793                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
4794                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4795                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4796                         break;
4797
4798                 /* Issue PHY reset and repeat at most one more time */
4799                 reg = E1000_READ_REG(hw, E1000_CTRL);
4800                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
4801                 retry++;
4802         } while (retry);
4803 }
4804
4805 /**
4806  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4807  *  @hw: pointer to the HW structure
4808  *
4809  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4810  *  LPLU, Gig disable, MDIC PHY reset):
4811  *    1) Set Kumeran Near-end loopback
4812  *    2) Clear Kumeran Near-end loopback
4813  *  Should only be called for ICH8[m] devices with any 1G Phy.
4814  **/
4815 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4816 {
4817         s32 ret_val;
4818         u16 reg_data;
4819
4820         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
4821
4822         if ((hw->mac.type != e1000_ich8lan) ||
4823             (hw->phy.type == e1000_phy_ife))
4824                 return;
4825
4826         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4827                                               &reg_data);
4828         if (ret_val)
4829                 return;
4830         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4831         ret_val = e1000_write_kmrn_reg_generic(hw,
4832                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
4833                                                reg_data);
4834         if (ret_val)
4835                 return;
4836         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4837         e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4838                                      reg_data);
4839 }
4840
4841 /**
4842  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4843  *  @hw: pointer to the HW structure
4844  *
4845  *  During S0 to Sx transition, it is possible the link remains at gig
4846  *  instead of negotiating to a lower speed.  Before going to Sx, set
4847  *  'Gig Disable' to force link speed negotiation to a lower speed based on
4848  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
4849  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4850  *  needs to be written.
4851  *  Parts that support (and are linked to a partner which support) EEE in
4852  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4853  *  than 10Mbps w/o EEE.
4854  **/
4855 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4856 {
4857         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4858         u32 phy_ctrl;
4859         s32 ret_val;
4860
4861         DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
4862
4863         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
4864         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4865
4866         if (hw->phy.type == e1000_phy_i217) {
4867                 u16 phy_reg, device_id = hw->device_id;
4868
4869                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
4870                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4871                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4872                     (device_id == E1000_DEV_ID_PCH_I218_V3)) {
4873                         u32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);
4874
4875                         E1000_WRITE_REG(hw, E1000_FEXTNVM6,
4876                                         fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4877                 }
4878
4879                 ret_val = hw->phy.ops.acquire(hw);
4880                 if (ret_val)
4881                         goto out;
4882
4883                 if (!dev_spec->eee_disable) {
4884                         u16 eee_advert;
4885
4886                         ret_val =
4887                             e1000_read_emi_reg_locked(hw,
4888                                                       I217_EEE_ADVERTISEMENT,
4889                                                       &eee_advert);
4890                         if (ret_val)
4891                                 goto release;
4892
4893                         /* Disable LPLU if both link partners support 100BaseT
4894                          * EEE and 100Full is advertised on both ends of the
4895                          * link, and enable Auto Enable LPI since there will
4896                          * be no driver to enable LPI while in Sx.
4897                          */
4898                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4899                             (dev_spec->eee_lp_ability &
4900                              I82579_EEE_100_SUPPORTED) &&
4901                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
4902                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4903                                               E1000_PHY_CTRL_NOND0A_LPLU);
4904
4905                                 /* Set Auto Enable LPI after link up */
4906                                 hw->phy.ops.read_reg_locked(hw,
4907                                                             I217_LPI_GPIO_CTRL,
4908                                                             &phy_reg);
4909                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
4910                                 hw->phy.ops.write_reg_locked(hw,
4911                                                              I217_LPI_GPIO_CTRL,
4912                                                              phy_reg);
4913                         }
4914                 }
4915
4916                 /* For i217 Intel Rapid Start Technology support,
4917                  * when the system is going into Sx and no manageability engine
4918                  * is present, the driver must configure proxy to reset only on
4919                  * power good.  LPI (Low Power Idle) state must also reset only
4920                  * on power good, as well as the MTA (Multicast table array).
4921                  * The SMBus release must also be disabled on LCD reset.
4922                  */
4923                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
4924                       E1000_ICH_FWSM_FW_VALID)) {
4925                         /* Enable proxy to reset only on power good. */
4926                         hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
4927                                                     &phy_reg);
4928                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4929                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,
4930                                                      phy_reg);
4931
4932                         /* Set bit enable LPI (EEE) to reset only on
4933                          * power good.
4934                         */
4935                         hw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);
4936                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4937                         hw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);
4938
4939                         /* Disable the SMB release on LCD reset. */
4940                         hw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);
4941                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4942                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
4943                 }
4944
4945                 /* Enable MTA to reset for Intel Rapid Start Technology
4946                  * Support
4947                  */
4948                 hw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);
4949                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4950                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
4951
4952 release:
4953                 hw->phy.ops.release(hw);
4954         }
4955 out:
4956         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
4957
4958         if (hw->mac.type == e1000_ich8lan)
4959                 e1000_gig_downshift_workaround_ich8lan(hw);
4960
4961         if (hw->mac.type >= e1000_pchlan) {
4962                 e1000_oem_bits_config_ich8lan(hw, FALSE);
4963
4964                 /* Reset PHY to activate OEM bits on 82577/8 */
4965                 if (hw->mac.type == e1000_pchlan)
4966                         e1000_phy_hw_reset_generic(hw);
4967
4968                 ret_val = hw->phy.ops.acquire(hw);
4969                 if (ret_val)
4970                         return;
4971                 e1000_write_smbus_addr(hw);
4972                 hw->phy.ops.release(hw);
4973         }
4974
4975         return;
4976 }
4977
4978 /**
4979  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4980  *  @hw: pointer to the HW structure
4981  *
4982  *  During Sx to S0 transitions on non-managed devices or managed devices
4983  *  on which PHY resets are not blocked, if the PHY registers cannot be
4984  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
4985  *  the PHY.
4986  *  On i217, setup Intel Rapid Start Technology.
4987  **/
4988 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4989 {
4990         s32 ret_val;
4991
4992         DEBUGFUNC("e1000_resume_workarounds_pchlan");
4993
4994         if (hw->mac.type < e1000_pch2lan)
4995                 return;
4996
4997         ret_val = e1000_init_phy_workarounds_pchlan(hw);
4998         if (ret_val) {
4999                 DEBUGOUT1("Failed to init PHY flow ret_val=%d\n", ret_val);
5000                 return;
5001         }
5002
5003         /* For i217 Intel Rapid Start Technology support when the system
5004          * is transitioning from Sx and no manageability engine is present
5005          * configure SMBus to restore on reset, disable proxy, and enable
5006          * the reset on MTA (Multicast table array).
5007          */
5008         if (hw->phy.type == e1000_phy_i217) {
5009                 u16 phy_reg;
5010
5011                 ret_val = hw->phy.ops.acquire(hw);
5012                 if (ret_val) {
5013                         DEBUGOUT("Failed to setup iRST\n");
5014                         return;
5015                 }
5016
5017                 /* Clear Auto Enable LPI after link up */
5018                 hw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5019                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5020                 hw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5021
5022                 if (!(E1000_READ_REG(hw, E1000_FWSM) &
5023                     E1000_ICH_FWSM_FW_VALID)) {
5024                         /* Restore clear on SMB if no manageability engine
5025                          * is present
5026                          */
5027                         ret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,
5028                                                               &phy_reg);
5029                         if (ret_val)
5030                                 goto release;
5031                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5032                         hw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);
5033
5034                         /* Disable Proxy */
5035                         hw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);
5036                 }
5037                 /* Enable reset on MTA */
5038                 ret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,
5039                                                       &phy_reg);
5040                 if (ret_val)
5041                         goto release;
5042                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5043                 hw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);
5044 release:
5045                 if (ret_val)
5046                         DEBUGOUT1("Error %d in resume workarounds\n", ret_val);
5047                 hw->phy.ops.release(hw);
5048         }
5049 }
5050
5051 /**
5052  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5053  *  @hw: pointer to the HW structure
5054  *
5055  *  Return the LED back to the default configuration.
5056  **/
5057 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5058 {
5059         DEBUGFUNC("e1000_cleanup_led_ich8lan");
5060
5061         if (hw->phy.type == e1000_phy_ife)
5062                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5063                                              0);
5064
5065         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
5066         return E1000_SUCCESS;
5067 }
5068
5069 /**
5070  *  e1000_led_on_ich8lan - Turn LEDs on
5071  *  @hw: pointer to the HW structure
5072  *
5073  *  Turn on the LEDs.
5074  **/
5075 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5076 {
5077         DEBUGFUNC("e1000_led_on_ich8lan");
5078
5079         if (hw->phy.type == e1000_phy_ife)
5080                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5081                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5082
5083         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
5084         return E1000_SUCCESS;
5085 }
5086
5087 /**
5088  *  e1000_led_off_ich8lan - Turn LEDs off
5089  *  @hw: pointer to the HW structure
5090  *
5091  *  Turn off the LEDs.
5092  **/
5093 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5094 {
5095         DEBUGFUNC("e1000_led_off_ich8lan");
5096
5097         if (hw->phy.type == e1000_phy_ife)
5098                 return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5099                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
5100
5101         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
5102         return E1000_SUCCESS;
5103 }
5104
5105 /**
5106  *  e1000_setup_led_pchlan - Configures SW controllable LED
5107  *  @hw: pointer to the HW structure
5108  *
5109  *  This prepares the SW controllable LED for use.
5110  **/
5111 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5112 {
5113         DEBUGFUNC("e1000_setup_led_pchlan");
5114
5115         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5116                                      (u16)hw->mac.ledctl_mode1);
5117 }
5118
5119 /**
5120  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5121  *  @hw: pointer to the HW structure
5122  *
5123  *  Return the LED back to the default configuration.
5124  **/
5125 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5126 {
5127         DEBUGFUNC("e1000_cleanup_led_pchlan");
5128
5129         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
5130                                      (u16)hw->mac.ledctl_default);
5131 }
5132
5133 /**
5134  *  e1000_led_on_pchlan - Turn LEDs on
5135  *  @hw: pointer to the HW structure
5136  *
5137  *  Turn on the LEDs.
5138  **/
5139 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5140 {
5141         u16 data = (u16)hw->mac.ledctl_mode2;
5142         u32 i, led;
5143
5144         DEBUGFUNC("e1000_led_on_pchlan");
5145
5146         /* If no link, then turn LED on by setting the invert bit
5147          * for each LED that's mode is "link_up" in ledctl_mode2.
5148          */
5149         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5150                 for (i = 0; i < 3; i++) {
5151                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5152                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5153                             E1000_LEDCTL_MODE_LINK_UP)
5154                                 continue;
5155                         if (led & E1000_PHY_LED0_IVRT)
5156                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5157                         else
5158                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5159                 }
5160         }
5161
5162         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5163 }
5164
5165 /**
5166  *  e1000_led_off_pchlan - Turn LEDs off
5167  *  @hw: pointer to the HW structure
5168  *
5169  *  Turn off the LEDs.
5170  **/
5171 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5172 {
5173         u16 data = (u16)hw->mac.ledctl_mode1;
5174         u32 i, led;
5175
5176         DEBUGFUNC("e1000_led_off_pchlan");
5177
5178         /* If no link, then turn LED off by clearing the invert bit
5179          * for each LED that's mode is "link_up" in ledctl_mode1.
5180          */
5181         if (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
5182                 for (i = 0; i < 3; i++) {
5183                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5184                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5185                             E1000_LEDCTL_MODE_LINK_UP)
5186                                 continue;
5187                         if (led & E1000_PHY_LED0_IVRT)
5188                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5189                         else
5190                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5191                 }
5192         }
5193
5194         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
5195 }
5196
5197 /**
5198  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5199  *  @hw: pointer to the HW structure
5200  *
5201  *  Read appropriate register for the config done bit for completion status
5202  *  and configure the PHY through s/w for EEPROM-less parts.
5203  *
5204  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5205  *  config done bit, so only an error is logged and continues.  If we were
5206  *  to return with error, EEPROM-less silicon would not be able to be reset
5207  *  or change link.
5208  **/
5209 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5210 {
5211         s32 ret_val = E1000_SUCCESS;
5212         u32 bank = 0;
5213         u32 status;
5214
5215         DEBUGFUNC("e1000_get_cfg_done_ich8lan");
5216
5217         e1000_get_cfg_done_generic(hw);
5218
5219         /* Wait for indication from h/w that it has completed basic config */
5220         if (hw->mac.type >= e1000_ich10lan) {
5221                 e1000_lan_init_done_ich8lan(hw);
5222         } else {
5223                 ret_val = e1000_get_auto_rd_done_generic(hw);
5224                 if (ret_val) {
5225                         /* When auto config read does not complete, do not
5226                          * return with an error. This can happen in situations
5227                          * where there is no eeprom and prevents getting link.
5228                          */
5229                         DEBUGOUT("Auto Read Done did not complete\n");
5230                         ret_val = E1000_SUCCESS;
5231                 }
5232         }
5233
5234         /* Clear PHY Reset Asserted bit */
5235         status = E1000_READ_REG(hw, E1000_STATUS);
5236         if (status & E1000_STATUS_PHYRA)
5237                 E1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);
5238         else
5239                 DEBUGOUT("PHY Reset Asserted not set - needs delay\n");
5240
5241         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5242         if (hw->mac.type <= e1000_ich9lan) {
5243                 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
5244                     (hw->phy.type == e1000_phy_igp_3)) {
5245                         e1000_phy_init_script_igp3(hw);
5246                 }
5247         } else {
5248                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5249                         /* Maybe we should do a basic PHY config */
5250                         DEBUGOUT("EEPROM not present\n");
5251                         ret_val = -E1000_ERR_CONFIG;
5252                 }
5253         }
5254
5255         return ret_val;
5256 }
5257
5258 /**
5259  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5260  * @hw: pointer to the HW structure
5261  *
5262  * In the case of a PHY power down to save power, or to turn off link during a
5263  * driver unload, or wake on lan is not enabled, remove the link.
5264  **/
5265 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5266 {
5267         /* If the management interface is not enabled, then power down */
5268         if (!(hw->mac.ops.check_mng_mode(hw) ||
5269               hw->phy.ops.check_reset_block(hw)))
5270                 e1000_power_down_phy_copper(hw);
5271
5272         return;
5273 }
5274
5275 /**
5276  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5277  *  @hw: pointer to the HW structure
5278  *
5279  *  Clears hardware counters specific to the silicon family and calls
5280  *  clear_hw_cntrs_generic to clear all general purpose counters.
5281  **/
5282 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5283 {
5284         u16 phy_data;
5285         s32 ret_val;
5286
5287         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
5288
5289         e1000_clear_hw_cntrs_base_generic(hw);
5290
5291         E1000_READ_REG(hw, E1000_ALGNERRC);
5292         E1000_READ_REG(hw, E1000_RXERRC);
5293         E1000_READ_REG(hw, E1000_TNCRS);
5294         E1000_READ_REG(hw, E1000_CEXTERR);
5295         E1000_READ_REG(hw, E1000_TSCTC);
5296         E1000_READ_REG(hw, E1000_TSCTFC);
5297
5298         E1000_READ_REG(hw, E1000_MGTPRC);
5299         E1000_READ_REG(hw, E1000_MGTPDC);
5300         E1000_READ_REG(hw, E1000_MGTPTC);
5301
5302         E1000_READ_REG(hw, E1000_IAC);
5303         E1000_READ_REG(hw, E1000_ICRXOC);
5304
5305         /* Clear PHY statistics registers */
5306         if ((hw->phy.type == e1000_phy_82578) ||
5307             (hw->phy.type == e1000_phy_82579) ||
5308             (hw->phy.type == e1000_phy_i217) ||
5309             (hw->phy.type == e1000_phy_82577)) {
5310                 ret_val = hw->phy.ops.acquire(hw);
5311                 if (ret_val)
5312                         return;
5313                 ret_val = hw->phy.ops.set_page(hw,
5314                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5315                 if (ret_val)
5316                         goto release;
5317                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5318                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5319                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5320                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5321                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5322                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5323                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5324                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5325                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5326                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5327                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5328                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5329                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5330                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5331 release:
5332                 hw->phy.ops.release(hw);
5333         }
5334 }
5335