2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * Hardware defines for Freescale Fast Ethernet Controller.
41 #define FEC_IER_REG 0x0004
42 #define FEC_IEM_REG 0x0008
43 #define FEC_IER_HBERR (1U << 31)
44 #define FEC_IER_BABR (1 << 30)
45 #define FEC_IER_BABT (1 << 29)
46 #define FEC_IER_GRA (1 << 28)
47 #define FEC_IER_TXF (1 << 27)
48 #define FEC_IER_TXB (1 << 26)
49 #define FEC_IER_RXF (1 << 25)
50 #define FEC_IER_RXB (1 << 24)
51 #define FEC_IER_MII (1 << 23)
52 #define FEC_IER_EBERR (1 << 22)
53 #define FEC_IER_LC (1 << 21)
54 #define FEC_IER_RL (1 << 20)
55 #define FEC_IER_UN (1 << 19)
56 #define FEC_IER_PLR (1 << 18)
57 #define FEC_IER_WAKEUP (1 << 17)
58 #define FEC_IER_AVAIL (1 << 16)
59 #define FEC_IER_TIMER (1 << 15)
61 #define FEC_RDAR_REG 0x0010
62 #define FEC_RDAR_RDAR (1 << 24)
64 #define FEC_TDAR_REG 0x0014
65 #define FEC_TDAR_TDAR (1 << 24)
67 #define FEC_ECR_REG 0x0024
68 #define FEC_ECR_DBSWP (1 << 8)
69 #define FEC_ECR_STOPEN (1 << 7)
70 #define FEC_ECR_DBGEN (1 << 6)
71 #define FEC_ECR_SPEED (1 << 5)
72 #define FEC_ECR_EN1588 (1 << 4)
73 #define FEC_ECR_SLEEP (1 << 3)
74 #define FEC_ECR_MAGICEN (1 << 2)
75 #define FEC_ECR_ETHEREN (1 << 1)
76 #define FEC_ECR_RESET (1 << 0)
78 #define FEC_MMFR_REG 0x0040
79 #define FEC_MMFR_ST_SHIFT 30
80 #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT)
81 #define FEC_MMFR_OP_SHIFT 28
82 #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT)
83 #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT)
84 #define FEC_MMFR_PA_SHIFT 23
85 #define FEC_MMFR_PA_MASK (0x1f << FEC_MMFR_PA_SHIFT)
86 #define FEC_MMFR_RA_SHIFT 18
87 #define FEC_MMFR_RA_MASK (0x1f << FEC_MMFR_RA_SHIFT)
88 #define FEC_MMFR_TA_SHIFT 16
89 #define FEC_MMFR_TA_VALUE (0x02 << FEC_MMFR_TA_SHIFT)
90 #define FEC_MMFR_DATA_SHIFT 0
91 #define FEC_MMFR_DATA_MASK (0xffff << FEC_MMFR_DATA_SHIFT)
93 #define FEC_MSCR_REG 0x0044
94 #define FEC_MSCR_HOLDTIME_SHIFT 8
95 #define FEC_MSCR_HOLDTIME_MASK (0x07 << FEC_MSCR_HOLDTIME_SHIFT)
96 #define FEC_MSCR_DIS_PRE (1 << 7)
97 #define FEC_MSCR_MII_SPEED_SHIFT 1
98 #define FEC_MSCR_MII_SPEED_MASk (0x3f << FEC_MSCR_MII_SPEED_SHIFT)
100 #define FEC_MIBC_REG 0x0064
101 #define FEC_MIBC_DIS (1U << 31)
102 #define FEC_MIBC_IDLE (1 << 30)
103 #define FEC_MIBC_CLEAR (1 << 29) /* imx6 only */
105 #define FEC_RCR_REG 0x0084
106 #define FEC_RCR_GRS (1U << 31)
107 #define FEC_RCR_NLC (1 << 30)
108 #define FEC_RCR_MAX_FL_SHIFT 16
109 #define FEC_RCR_MAX_FL_MASK (0x3fff << FEC_RCR_MAX_FL_SHIFT)
110 #define FEC_RCR_CFEN (1 << 15)
111 #define FEC_RCR_CRCFWD (1 << 14)
112 #define FEC_RCR_PAUFWD (1 << 13)
113 #define FEC_RCR_PADEN (1 << 12)
114 #define FEC_RCR_RMII_10T (1 << 9)
115 #define FEC_RCR_RMII_MODE (1 << 8)
116 #define FEC_RCR_RGMII_EN (1 << 6)
117 #define FEC_RCR_FCE (1 << 5)
118 #define FEC_RCR_BC_REJ (1 << 4)
119 #define FEC_RCR_PROM (1 << 3)
120 #define FEC_RCR_MII_MODE (1 << 2)
121 #define FEC_RCR_DRT (1 << 1)
122 #define FEC_RCR_LOOP (1 << 0)
124 #define FEC_TCR_REG 0x00c4
125 #define FEC_TCR_ADDINS (1 << 9)
126 #define FEC_TCR_ADDSEL_SHIFT 5
127 #define FEC_TCR_ADDSEL_MASK (0x07 << FEC_TCR_ADDSEL_SHIFT)
128 #define FEC_TCR_RFC_PAUSE (1 << 4)
129 #define FEC_TCR_TFC_PAUSE (1 << 3)
130 #define FEC_TCR_FDEN (1 << 2)
131 #define FEC_TCR_GTS (1 << 0)
133 #define FEC_PALR_REG 0x00e4
134 #define FEC_PALR_PADDR1_SHIFT 0
135 #define FEC_PALR_PADDR1_MASK (0xffffffff << FEC_PALR_PADDR1_SHIFT)
137 #define FEC_PAUR_REG 0x00e8
138 #define FEC_PAUR_PADDR2_SHIFT 16
139 #define FEC_PAUR_PADDR2_MASK (0xffff << FEC_PAUR_PADDR2_SHIFT)
140 #define FEC_PAUR_TYPE_VALUE (0x8808)
142 #define FEC_OPD_REG 0x00ec
143 #define FEC_OPD_PAUSE_DUR_SHIFT 0
144 #define FEC_OPD_PAUSE_DUR_MASK (0xffff << FEC_OPD_PAUSE_DUR_SHIFT)
146 #define FEC_IAUR_REG 0x0118
147 #define FEC_IALR_REG 0x011c
149 #define FEC_GAUR_REG 0x0120
150 #define FEC_GALR_REG 0x0124
152 #define FEC_TFWR_REG 0x0144
153 #define FEC_TFWR_STRFWD (1 << 8)
154 #define FEC_TFWR_TWFR_SHIFT 0
155 #define FEC_TFWR_TWFR_MASK (0x3f << FEC_TFWR_TWFR_SHIFT)
156 #define FEC_TFWR_TWFR_128BYTE (0x02 << FEC_TFWR_TWFR_SHIFT)
158 #define FEC_RDSR_REG 0x0180
160 #define FEC_TDSR_REG 0x0184
162 #define FEC_MRBR_REG 0x0188
163 #define FEC_MRBR_R_BUF_SIZE_SHIFT 0
164 #define FEC_MRBR_R_BUF_SIZE_MASK (0x3fff << FEC_MRBR_R_BUF_SIZE_SHIFT)
166 #define FEC_RSFL_REG 0x0190
167 #define FEC_RSEM_REG 0x0194
168 #define FEC_RAEM_REG 0x0198
169 #define FEC_RAFL_REG 0x019c
170 #define FEC_TSEM_REG 0x01a0
171 #define FEC_TAEM_REG 0x01a4
172 #define FEC_TAFL_REG 0x01a8
173 #define FEC_TIPG_REG 0x01ac
174 #define FEC_FTRL_REG 0x01b0
176 #define FEC_TACC_REG 0x01c0
177 #define FEC_TACC_PROCHK (1 << 4)
178 #define FEC_TACC_IPCHK (1 << 3)
179 #define FEC_TACC_SHIFT16 (1 << 0)
181 #define FEC_RACC_REG 0x01c4
182 #define FEC_RACC_SHIFT16 (1 << 7)
183 #define FEC_RACC_LINEDIS (1 << 6)
184 #define FEC_RACC_PRODIS (1 << 2)
185 #define FEC_RACC_IPDIS (1 << 1)
186 #define FEC_RACC_PADREM (1 << 0)
189 * Statistics registers
191 #define FEC_RMON_T_DROP 0x200
192 #define FEC_RMON_T_PACKETS 0x204
193 #define FEC_RMON_T_BC_PKT 0x208
194 #define FEC_RMON_T_MC_PKT 0x20C
195 #define FEC_RMON_T_CRC_ALIGN 0x210
196 #define FEC_RMON_T_UNDERSIZE 0x214
197 #define FEC_RMON_T_OVERSIZE 0x218
198 #define FEC_RMON_T_FRAG 0x21C
199 #define FEC_RMON_T_JAB 0x220
200 #define FEC_RMON_T_COL 0x224
201 #define FEC_RMON_T_P64 0x228
202 #define FEC_RMON_T_P65TO127 0x22C
203 #define FEC_RMON_T_P128TO255 0x230
204 #define FEC_RMON_T_P256TO511 0x234
205 #define FEC_RMON_T_P512TO1023 0x238
206 #define FEC_RMON_T_P1024TO2047 0x23C
207 #define FEC_RMON_T_P_GTE2048 0x240
208 #define FEC_RMON_T_OCTECTS 0x240
209 #define FEC_IEEE_T_DROP 0x248
210 #define FEC_IEEE_T_FRAME_OK 0x24C
211 #define FEC_IEEE_T_1COL 0x250
212 #define FEC_IEEE_T_MCOL 0x254
213 #define FEC_IEEE_T_DEF 0x258
214 #define FEC_IEEE_T_LCOL 0x25C
215 #define FEC_IEEE_T_EXCOL 0x260
216 #define FEC_IEEE_T_MACERR 0x264
217 #define FEC_IEEE_T_CSERR 0x268
218 #define FEC_IEEE_T_SQE 0x26C
219 #define FEC_IEEE_T_FDXFC 0x270
220 #define FEC_IEEE_T_OCTETS_OK 0x274
221 #define FEC_RMON_R_PACKETS 0x284
222 #define FEC_RMON_R_BC_PKT 0x288
223 #define FEC_RMON_R_MC_PKT 0x28C
224 #define FEC_RMON_R_CRC_ALIGN 0x290
225 #define FEC_RMON_R_UNDERSIZE 0x294
226 #define FEC_RMON_R_OVERSIZE 0x298
227 #define FEC_RMON_R_FRAG 0x29C
228 #define FEC_RMON_R_JAB 0x2A0
229 #define FEC_RMON_R_RESVD_0 0x2A4
230 #define FEC_RMON_R_P64 0x2A8
231 #define FEC_RMON_R_P65TO127 0x2AC
232 #define FEC_RMON_R_P128TO255 0x2B0
233 #define FEC_RMON_R_P256TO511 0x2B4
234 #define FEC_RMON_R_P512TO1023 0x2B8
235 #define FEC_RMON_R_P1024TO2047 0x2BC
236 #define FEC_RMON_R_P_GTE2048 0x2C0
237 #define FEC_RMON_R_OCTETS 0x2C4
238 #define FEC_IEEE_R_DROP 0x2C8
239 #define FEC_IEEE_R_FRAME_OK 0x2CC
240 #define FEC_IEEE_R_CRC 0x2D0
241 #define FEC_IEEE_R_ALIGN 0x2D4
242 #define FEC_IEEE_R_MACERR 0x2D8
243 #define FEC_IEEE_R_FDXFC 0x2DC
244 #define FEC_IEEE_R_OCTETS_OK 0x2E0
246 #define FEC_MIIGSK_CFGR 0x300
247 #define FEC_MIIGSK_CFGR_FRCONT (1 << 6) /* Freq: 0=50MHz, 1=5MHz */
248 #define FEC_MIIGSK_CFGR_LBMODE (1 << 4) /* loopback mode */
249 #define FEC_MIIGSK_CFGR_EMODE (1 << 3) /* echo mode */
250 #define FEC_MIIGSK_CFGR_IF_MODE_MASK (0x3 << 0)
251 #define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0)
252 #define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
254 #define FEC_MIIGSK_ENR 0x308
255 #define FEC_MIIGSK_ENR_READY (1 << 2)
256 #define FEC_MIIGSK_ENR_EN (1 << 1)
259 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
260 * layout, but the bits in the flags field have different meanings.
268 #define FEC_TXDESC_READY (1U << 31)
269 #define FEC_TXDESC_T01 (1 << 30)
270 #define FEC_TXDESC_WRAP (1 << 29)
271 #define FEC_TXDESC_T02 (1 << 28)
272 #define FEC_TXDESC_L (1 << 27)
273 #define FEC_TXDESC_TC (1 << 26)
274 #define FEC_TXDESC_ABC (1 << 25)
275 #define FEC_TXDESC_LEN_MASK (0xffff)
277 #define FEC_RXDESC_EMPTY (1U << 31)
278 #define FEC_RXDESC_R01 (1 << 30)
279 #define FEC_RXDESC_WRAP (1 << 29)
280 #define FEC_RXDESC_R02 (1 << 28)
281 #define FEC_RXDESC_L (1 << 27)
282 #define FEC_RXDESC_M (1 << 24)
283 #define FEC_RXDESC_BC (1 << 23)
284 #define FEC_RXDESC_MC (1 << 22)
285 #define FEC_RXDESC_LG (1 << 21)
286 #define FEC_RXDESC_NO (1 << 20)
287 #define FEC_RXDESC_CR (1 << 18)
288 #define FEC_RXDESC_OV (1 << 17)
289 #define FEC_RXDESC_TR (1 << 16)
290 #define FEC_RXDESC_LEN_MASK (0xffff)
292 #define FEC_RXDESC_ERROR_BITS (FEC_RXDESC_LG | FEC_RXDESC_NO | \
293 FEC_RXDESC_OV | FEC_RXDESC_TR)
296 * The hardware imposes alignment restrictions on various objects involved in
297 * DMA transfers. These values are expressed in bytes (not bits).
299 #define FEC_DESC_RING_ALIGN 16
300 #define FEC_RXBUF_ALIGN 16
301 #define FEC_TXBUF_ALIGN 16
303 #endif /* IF_FFECREG_H */