2 * Copyright (c) 2011 Henrik Brix Andersen <brix@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 * AMD Geode LX CS5536 System Management Bus controller.
31 * Although AMD refers to this device as an SMBus controller, it
32 * really is an I2C controller (It lacks SMBus ALERT# and Alert
35 * The driver is implemented as an interrupt-driven state machine,
36 * supporting both master and slave mode.
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
44 #include <sys/mutex.h>
45 #include <sys/sysctl.h>
47 #include <sys/syslog.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <machine/bus.h>
55 #include <machine/resource.h>
57 #include <dev/iicbus/iiconf.h>
58 #include <dev/iicbus/iicbus.h>
60 #include "iicbus_if.h"
62 /* CS5536 PCI-ISA ID. */
63 #define GLXIIC_CS5536_DEV_ID 0x20901022
66 #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021
69 #define GLXIIC_SLOW 0x0258 /* 10 kHz. */
70 #define GLXIIC_FAST 0x0078 /* 50 kHz. */
71 #define GLXIIC_FASTEST 0x003c /* 100 kHz. */
73 /* Default bus activity timeout in milliseconds. */
74 #define GLXIIC_DEFAULT_TIMEOUT 35
76 /* GPIO register offsets. */
77 #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10
78 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34
80 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */
81 #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000
82 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000
84 /* SMB register offsets. */
85 #define GLXIIC_SMB_SDA 0x00
86 #define GLXIIC_SMB_STS 0x01
87 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7)
88 #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6)
89 #define GLXIIC_SMB_STS_BER_BIT (1 << 5)
90 #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4)
91 #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3)
92 #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2)
93 #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1)
94 #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0)
95 #define GLXIIC_SMB_CTRL_STS 0x02
96 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5)
97 #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4)
98 #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3)
99 #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2)
100 #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1)
101 #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0)
102 #define GLXIIC_SMB_CTRL1 0x03
103 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7)
104 #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6)
105 #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5)
106 #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4)
107 #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2)
108 #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1)
109 #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0)
110 #define GLXIIC_SMB_ADDR 0x04
111 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7)
112 #define GLXIIC_SMB_CTRL2 0x05
113 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0)
114 #define GLXIIC_SMB_CTRL3 0x06
118 GLXIIC_STATE_SLAVE_TX,
119 GLXIIC_STATE_SLAVE_RX,
120 GLXIIC_STATE_MASTER_ADDR,
121 GLXIIC_STATE_MASTER_TX,
122 GLXIIC_STATE_MASTER_RX,
123 GLXIIC_STATE_MASTER_STOP,
127 struct glxiic_softc {
128 device_t dev; /* Myself. */
129 device_t iicbus; /* IIC bus. */
130 struct mtx mtx; /* Lock. */
131 glxiic_state_t state; /* Driver state. */
132 struct callout callout; /* Driver state timeout callout. */
133 int timeout; /* Driver state timeout (ms). */
135 int smb_rid; /* SMB controller resource ID. */
136 struct resource *smb_res; /* SMB controller resource. */
137 int gpio_rid; /* GPIO resource ID. */
138 struct resource *gpio_res; /* GPIO resource. */
140 int irq_rid; /* IRQ resource ID. */
141 struct resource *irq_res; /* IRQ resource. */
142 void *irq_handler; /* IRQ handler cookie. */
143 int old_irq; /* IRQ mapped by board firmware. */
145 struct iic_msg *msg; /* Current master mode message. */
146 uint32_t nmsgs; /* Number of messages remaining. */
147 uint8_t *data; /* Current master mode data byte. */
148 uint16_t ndata; /* Number of data bytes remaining. */
149 int error; /* Last master mode error. */
151 uint8_t addr; /* Own address. */
152 uint16_t sclfrq; /* Bus frequency. */
156 #define GLXIIC_DEBUG_LOG(fmt, args...) \
157 log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args)
159 #define GLXIIC_DEBUG_LOG(fmt, args...)
162 #define GLXIIC_SCLFRQ(n) ((n << 1))
163 #define GLXIIC_SMBADDR(n) ((n >> 1))
164 #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16))
165 #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf)
167 #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx)
168 #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx)
169 #define GLXIIC_LOCK_INIT(_sc) \
170 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF)
171 #define GLXIIC_SLEEP(_sc) \
172 mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0)
173 #define GLXIIC_WAKEUP(_sc) wakeup(_sc);
174 #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
175 #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
177 typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc,
180 static glxiic_state_callback_t glxiic_state_idle_callback;
181 static glxiic_state_callback_t glxiic_state_slave_tx_callback;
182 static glxiic_state_callback_t glxiic_state_slave_rx_callback;
183 static glxiic_state_callback_t glxiic_state_master_addr_callback;
184 static glxiic_state_callback_t glxiic_state_master_tx_callback;
185 static glxiic_state_callback_t glxiic_state_master_rx_callback;
186 static glxiic_state_callback_t glxiic_state_master_stop_callback;
188 struct glxiic_state_table_entry {
189 glxiic_state_callback_t *callback;
192 typedef struct glxiic_state_table_entry glxiic_state_table_entry_t;
194 static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = {
195 [GLXIIC_STATE_IDLE] = {
196 .callback = &glxiic_state_idle_callback,
200 [GLXIIC_STATE_SLAVE_TX] = {
201 .callback = &glxiic_state_slave_tx_callback,
205 [GLXIIC_STATE_SLAVE_RX] = {
206 .callback = &glxiic_state_slave_rx_callback,
210 [GLXIIC_STATE_MASTER_ADDR] = {
211 .callback = &glxiic_state_master_addr_callback,
215 [GLXIIC_STATE_MASTER_TX] = {
216 .callback = &glxiic_state_master_tx_callback,
220 [GLXIIC_STATE_MASTER_RX] = {
221 .callback = &glxiic_state_master_rx_callback,
225 [GLXIIC_STATE_MASTER_STOP] = {
226 .callback = &glxiic_state_master_stop_callback,
231 static void glxiic_identify(driver_t *driver, device_t parent);
232 static int glxiic_probe(device_t dev);
233 static int glxiic_attach(device_t dev);
234 static int glxiic_detach(device_t dev);
236 static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc);
237 static void glxiic_stop_locked(struct glxiic_softc *sc);
238 static void glxiic_timeout(void *arg);
239 static void glxiic_start_timeout_locked(struct glxiic_softc *sc);
240 static void glxiic_set_state_locked(struct glxiic_softc *sc,
241 glxiic_state_t state);
242 static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc,
244 static void glxiic_intr(void *arg);
246 static int glxiic_reset(device_t dev, u_char speed, u_char addr,
248 static int glxiic_transfer(device_t dev, struct iic_msg *msgs,
251 static void glxiic_smb_map_interrupt(int irq);
252 static void glxiic_gpio_enable(struct glxiic_softc *sc);
253 static void glxiic_gpio_disable(struct glxiic_softc *sc);
254 static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed,
256 static void glxiic_smb_disable(struct glxiic_softc *sc);
258 static device_method_t glxiic_methods[] = {
259 DEVMETHOD(device_identify, glxiic_identify),
260 DEVMETHOD(device_probe, glxiic_probe),
261 DEVMETHOD(device_attach, glxiic_attach),
262 DEVMETHOD(device_detach, glxiic_detach),
264 DEVMETHOD(iicbus_reset, glxiic_reset),
265 DEVMETHOD(iicbus_transfer, glxiic_transfer),
266 DEVMETHOD(iicbus_callback, iicbus_null_callback),
271 static driver_t glxiic_driver = {
274 sizeof(struct glxiic_softc),
277 static devclass_t glxiic_devclass;
279 DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0);
280 DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0);
281 MODULE_DEPEND(glxiic, iicbus, 1, 1, 1);
284 glxiic_identify(driver_t *driver, device_t parent)
287 /* Prevent child from being added more than once. */
288 if (device_find_child(parent, driver->name, -1) != NULL)
291 if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) {
292 if (device_add_child(parent, driver->name, -1) == NULL)
293 device_printf(parent, "Could not add glxiic child\n");
298 glxiic_probe(device_t dev)
301 if (resource_disabled("glxiic", device_get_unit(dev)))
304 device_set_desc(dev, "AMD Geode CS5536 SMBus controller");
306 return (BUS_PROBE_DEFAULT);
310 glxiic_attach(device_t dev)
312 struct glxiic_softc *sc;
313 struct sysctl_ctx_list *ctx;
314 struct sysctl_oid *tree;
315 int error, irq, unit;
319 sc = device_get_softc(dev);
321 sc->state = GLXIIC_STATE_IDLE;
324 GLXIIC_LOCK_INIT(sc);
325 callout_init_mtx(&sc->callout, &sc->mtx, 0);
327 sc->smb_rid = PCIR_BAR(0);
328 sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid,
330 if (sc->smb_res == NULL) {
331 device_printf(dev, "Could not allocate SMBus I/O port\n");
336 sc->gpio_rid = PCIR_BAR(1);
337 sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
338 &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE);
339 if (sc->gpio_res == NULL) {
340 device_printf(dev, "Could not allocate GPIO I/O port\n");
345 /* Ensure the controller is not enabled by firmware. */
346 glxiic_smb_disable(sc);
348 /* Read the existing IRQ map. */
349 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
350 sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
352 unit = device_get_unit(dev);
353 if (resource_int_value("glxiic", unit, "irq", &irq) == 0) {
354 if (irq < 1 || irq > 15) {
355 device_printf(dev, "Bad value %d for glxiic.%d.irq\n",
362 device_printf(dev, "Using irq %d set by hint\n", irq);
363 } else if (sc->old_irq != 0) {
365 device_printf(dev, "Using irq %d set by firmware\n",
369 device_printf(dev, "No irq mapped by firmware");
370 printf(" and no glxiic.%d.irq hint provided\n", unit);
375 /* Map the SMBus interrupt to the requested legacy IRQ. */
376 glxiic_smb_map_interrupt(irq);
379 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
380 irq, irq, 1, RF_SHAREABLE | RF_ACTIVE);
381 if (sc->irq_res == NULL) {
382 device_printf(dev, "Could not allocate IRQ %d\n", irq);
387 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
388 NULL, glxiic_intr, sc, &(sc->irq_handler));
390 device_printf(dev, "Could not setup IRQ handler\n");
395 if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
396 device_printf(dev, "Could not allocate iicbus instance\n");
401 ctx = device_get_sysctl_ctx(dev);
402 tree = device_get_sysctl_tree(dev);
404 sc->timeout = GLXIIC_DEFAULT_TIMEOUT;
405 snprintf(tn, sizeof(tn), "dev.glxiic.%d.timeout", unit);
406 TUNABLE_INT_FETCH(tn, &sc->timeout);
407 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
408 "timeout", CTLFLAG_RW | CTLFLAG_TUN, &sc->timeout, 0,
409 "activity timeout in ms");
411 glxiic_gpio_enable(sc);
412 glxiic_smb_enable(sc, IIC_FASTEST, 0);
414 error = bus_generic_attach(dev);
416 device_printf(dev, "Could not probe and attach children\n");
421 callout_drain(&sc->callout);
423 if (sc->iicbus != NULL)
424 device_delete_child(dev, sc->iicbus);
425 if (sc->smb_res != NULL) {
426 glxiic_smb_disable(sc);
427 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
430 if (sc->gpio_res != NULL) {
431 glxiic_gpio_disable(sc);
432 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
435 if (sc->irq_handler != NULL)
436 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
437 if (sc->irq_res != NULL)
438 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
441 /* Restore the old SMBus interrupt mapping. */
442 glxiic_smb_map_interrupt(sc->old_irq);
444 GLXIIC_LOCK_DESTROY(sc);
451 glxiic_detach(device_t dev)
453 struct glxiic_softc *sc;
456 sc = device_get_softc(dev);
458 error = bus_generic_detach(dev);
461 if (sc->iicbus != NULL)
462 error = device_delete_child(dev, sc->iicbus);
465 callout_drain(&sc->callout);
467 if (sc->smb_res != NULL) {
468 glxiic_smb_disable(sc);
469 bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid,
472 if (sc->gpio_res != NULL) {
473 glxiic_gpio_disable(sc);
474 bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid,
477 if (sc->irq_handler != NULL)
478 bus_teardown_intr(dev, sc->irq_res, sc->irq_handler);
479 if (sc->irq_res != NULL)
480 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
483 /* Restore the old SMBus interrupt mapping. */
484 glxiic_smb_map_interrupt(sc->old_irq);
486 GLXIIC_LOCK_DESTROY(sc);
492 glxiic_read_status_locked(struct glxiic_softc *sc)
496 GLXIIC_ASSERT_LOCKED(sc);
498 status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS);
500 /* Clear all status flags except SDAST and STASTR after reading. */
501 bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT |
502 GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT |
503 GLXIIC_SMB_STS_NMATCH_BIT));
509 glxiic_stop_locked(struct glxiic_softc *sc)
511 uint8_t status, ctrl1;
513 GLXIIC_ASSERT_LOCKED(sc);
515 status = glxiic_read_status_locked(sc);
517 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
518 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
519 ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT);
522 * Perform a dummy read of SDA in master receive mode to clear
525 if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 &&
526 (status & GLXIIC_SMB_STS_SDAST_BIT) != 0)
527 bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
529 /* Check stall after start bit and clear if needed */
530 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
531 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
532 GLXIIC_SMB_STS_STASTR_BIT);
537 glxiic_timeout(void *arg)
539 struct glxiic_softc *sc;
542 sc = (struct glxiic_softc *)arg;
544 GLXIIC_DEBUG_LOG("timeout in state %d", sc->state);
546 if (glxiic_state_table[sc->state].master) {
547 sc->error = IIC_ETIMEOUT;
550 error = IIC_ETIMEOUT;
551 iicbus_intr(sc->iicbus, INTR_ERROR, &error);
554 glxiic_smb_disable(sc);
555 glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr);
556 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
560 glxiic_start_timeout_locked(struct glxiic_softc *sc)
563 GLXIIC_ASSERT_LOCKED(sc);
565 callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0,
566 glxiic_timeout, sc, 0);
570 glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state)
573 GLXIIC_ASSERT_LOCKED(sc);
575 if (state == GLXIIC_STATE_IDLE)
576 callout_stop(&sc->callout);
577 else if (sc->timeout > 0)
578 glxiic_start_timeout_locked(sc);
584 glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status)
586 uint8_t ctrl_sts, addr;
588 GLXIIC_ASSERT_LOCKED(sc);
590 ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS);
592 if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) {
593 if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) {
594 addr = sc->addr | LSB;
595 glxiic_set_state_locked(sc,
596 GLXIIC_STATE_SLAVE_TX);
598 addr = sc->addr & ~LSB;
599 glxiic_set_state_locked(sc,
600 GLXIIC_STATE_SLAVE_RX);
602 iicbus_intr(sc->iicbus, INTR_START, &addr);
603 } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) {
605 glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX);
606 iicbus_intr(sc->iicbus, INTR_GENERAL, &addr);
608 GLXIIC_DEBUG_LOG("unknown slave match");
609 return (IIC_ESTATUS);
616 glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status)
619 GLXIIC_ASSERT_LOCKED(sc);
621 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
622 GLXIIC_DEBUG_LOG("bus error in idle");
623 return (IIC_EBUSERR);
626 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
627 return (glxiic_handle_slave_match_locked(sc, status));
634 glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status)
638 GLXIIC_ASSERT_LOCKED(sc);
640 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
641 GLXIIC_DEBUG_LOG("bus error in slave tx");
642 return (IIC_EBUSERR);
645 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
646 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
647 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
651 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
652 iicbus_intr(sc->iicbus, INTR_NOACK, NULL);
656 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
657 /* Handle repeated start in slave mode. */
658 return (glxiic_handle_slave_match_locked(sc, status));
661 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
662 GLXIIC_DEBUG_LOG("not awaiting data in slave tx");
663 return (IIC_ESTATUS);
666 iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data);
667 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data);
669 glxiic_start_timeout_locked(sc);
675 glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status)
679 GLXIIC_ASSERT_LOCKED(sc);
681 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
682 GLXIIC_DEBUG_LOG("bus error in slave rx");
683 return (IIC_EBUSERR);
686 if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) {
687 iicbus_intr(sc->iicbus, INTR_STOP, NULL);
688 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
692 if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) {
693 /* Handle repeated start in slave mode. */
694 return (glxiic_handle_slave_match_locked(sc, status));
697 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
698 GLXIIC_DEBUG_LOG("no pending data in slave rx");
699 return (IIC_ESTATUS);
702 data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
703 iicbus_intr(sc->iicbus, INTR_RECEIVE, &data);
705 glxiic_start_timeout_locked(sc);
711 glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status)
716 GLXIIC_ASSERT_LOCKED(sc);
718 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
719 GLXIIC_DEBUG_LOG("bus error after master start");
720 return (IIC_EBUSERR);
723 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
724 GLXIIC_DEBUG_LOG("not bus master after master start");
725 return (IIC_ESTATUS);
728 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
729 GLXIIC_DEBUG_LOG("not awaiting address in master addr");
730 return (IIC_ESTATUS);
733 if ((sc->msg->flags & IIC_M_RD) != 0) {
734 slave = sc->msg->slave | LSB;
735 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX);
737 slave = sc->msg->slave & ~LSB;
738 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX);
741 sc->data = sc->msg->buf;
742 sc->ndata = sc->msg->len;
744 /* Handle address-only transfer. */
746 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
748 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave);
750 if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) {
751 /* Last byte from slave, set NACK. */
752 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
753 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
754 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
761 glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status)
764 GLXIIC_ASSERT_LOCKED(sc);
766 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
767 GLXIIC_DEBUG_LOG("bus error in master tx");
768 return (IIC_EBUSERR);
771 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
772 GLXIIC_DEBUG_LOG("not bus master in master tx");
773 return (IIC_ESTATUS);
776 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
777 GLXIIC_DEBUG_LOG("slave nack in master tx");
781 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
782 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
783 GLXIIC_SMB_STS_STASTR_BIT);
786 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
787 GLXIIC_DEBUG_LOG("not awaiting data in master tx");
788 return (IIC_ESTATUS);
791 bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++);
792 if (--sc->ndata == 0)
793 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
795 glxiic_start_timeout_locked(sc);
801 glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status)
805 GLXIIC_ASSERT_LOCKED(sc);
807 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
808 GLXIIC_DEBUG_LOG("bus error in master rx");
809 return (IIC_EBUSERR);
812 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
813 GLXIIC_DEBUG_LOG("not bus master in master rx");
814 return (IIC_ESTATUS);
817 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
818 GLXIIC_DEBUG_LOG("slave nack in rx");
822 if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) {
823 /* Bus is stalled, clear and wait for data. */
824 bus_write_1(sc->smb_res, GLXIIC_SMB_STS,
825 GLXIIC_SMB_STS_STASTR_BIT);
829 if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) {
830 GLXIIC_DEBUG_LOG("no pending data in master rx");
831 return (IIC_ESTATUS);
834 *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA);
835 if (--sc->ndata == 0) {
836 /* Proceed with stop on reading last byte. */
837 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP);
838 return (glxiic_state_table[sc->state].callback(sc, status));
841 if (sc->ndata == 1) {
842 /* Last byte from slave, set NACK. */
843 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
844 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
845 ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT);
848 glxiic_start_timeout_locked(sc);
854 glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status)
858 GLXIIC_ASSERT_LOCKED(sc);
860 if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) {
861 GLXIIC_DEBUG_LOG("bus error in master stop");
862 return (IIC_EBUSERR);
865 if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) {
866 GLXIIC_DEBUG_LOG("not bus master in master stop");
867 return (IIC_ESTATUS);
870 if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) {
871 GLXIIC_DEBUG_LOG("slave nack in master stop");
875 if (--sc->nmsgs > 0) {
876 /* Start transfer of next message. */
877 if ((sc->msg->flags & IIC_M_NOSTOP) == 0) {
878 glxiic_stop_locked(sc);
881 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
882 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
883 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
885 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
889 glxiic_stop_locked(sc);
890 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
891 sc->error = IIC_NOERR;
899 glxiic_intr(void *arg)
901 struct glxiic_softc *sc;
903 uint8_t status, data;
905 sc = (struct glxiic_softc *)arg;
909 status = glxiic_read_status_locked(sc);
911 /* Check if this interrupt originated from the SMBus. */
913 ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) {
915 error = glxiic_state_table[sc->state].callback(sc, status);
917 if (error != IIC_NOERR) {
918 if (glxiic_state_table[sc->state].master) {
919 glxiic_stop_locked(sc);
920 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
925 iicbus_intr(sc->iicbus, INTR_ERROR, &data);
926 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
935 glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
937 struct glxiic_softc *sc;
939 sc = device_get_softc(dev);
947 /* A disable/enable cycle resets the controller. */
948 glxiic_smb_disable(sc);
949 glxiic_smb_enable(sc, speed, addr);
951 if (glxiic_state_table[sc->state].master) {
952 sc->error = IIC_ESTATUS;
955 glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE);
963 glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
965 struct glxiic_softc *sc;
969 sc = device_get_softc(dev);
973 if (sc->state != GLXIIC_STATE_IDLE) {
980 glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR);
982 /* Set start bit and let glxiic_intr() handle the transfer. */
983 ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1);
984 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
985 ctrl1 | GLXIIC_SMB_CTRL1_START_BIT);
996 glxiic_smb_map_interrupt(int irq)
1001 /* Protect the read-modify-write operation. */
1004 irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH);
1005 old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map);
1007 if (irq != old_irq) {
1008 irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq);
1009 irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq);
1010 wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map);
1017 glxiic_gpio_enable(struct glxiic_softc *sc)
1020 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1021 GLXIIC_GPIO_14_15_ENABLE);
1022 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1023 GLXIIC_GPIO_14_15_ENABLE);
1027 glxiic_gpio_disable(struct glxiic_softc *sc)
1030 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL,
1031 GLXIIC_GPIO_14_15_DISABLE);
1032 bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL,
1033 GLXIIC_GPIO_14_15_DISABLE);
1037 glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr)
1045 sc->sclfrq = GLXIIC_SLOW;
1048 sc->sclfrq = GLXIIC_FAST;
1051 sc->sclfrq = GLXIIC_FASTEST;
1055 /* Reuse last frequency. */
1059 /* Set bus speed and enable controller. */
1060 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1061 GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT);
1064 /* Enable new match and global call match interrupts. */
1065 ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT |
1066 GLXIIC_SMB_CTRL1_GCMEN_BIT;
1067 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR,
1068 GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr));
1070 bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0);
1073 /* Enable stall after start and interrupt. */
1074 bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1,
1075 ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT);
1079 glxiic_smb_disable(struct glxiic_softc *sc)
1083 sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2);
1084 bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2,
1085 sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT);