sys/dev/mpr/mpi/mpi2_cnfg.h

   1 /*-
   2  * Copyright (c) 2012-2015 LSI Corp.
   3  * Copyright (c) 2013-2015 Avago Technologies
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 /*
  36  *  Copyright (c) 2000-2015 LSI Corporation.
  37  *  Copyright (c) 2013-2015 Avago Technologies
  38  *
  39  *
  40  *           Name:  mpi2_cnfg.h
  41  *          Title:  MPI Configuration messages and pages
  42  *  Creation Date:  November 10, 2006
  43  *
  44  *    mpi2_cnfg.h Version:  02.00.27
  45  *
  46  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  47  *        prefix are for use only on MPI v2.5 products, and must not be used
  48  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
  49  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  50  *
  51  *  Version History
  52  *  ---------------
  53  *
  54  *  Date      Version   Description
  55  *  --------  --------  ------------------------------------------------------
  56  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  57  *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
  58  *                      Added Manufacturing Page 11.
  59  *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
  60  *                      define.
  61  *  06-26-07  02.00.02  Adding generic structure for product-specific
  62  *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
  63  *                      Rework of BIOS Page 2 configuration page.
  64  *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
  65  *                      forms.
  66  *                      Added configuration pages IOC Page 8 and Driver
  67  *                      Persistent Mapping Page 0.
  68  *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
  69  *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
  70  *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
  71  *                      Page 0).
  72  *                      Added new value for AccessStatus field of SAS Device
  73  *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
  74  *  10-31-07  02.00.04  Added missing SEPDevHandle field to
  75  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  76  *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
  77  *                      NVDATA.
  78  *                      Modified IOC Page 7 to use masks and added field for
  79  *                      SASBroadcastPrimitiveMasks.
  80  *                      Added MPI2_CONFIG_PAGE_BIOS_4.
  81  *                      Added MPI2_CONFIG_PAGE_LOG_0.
  82  *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
  83  *                      Added SAS Device IDs.
  84  *                      Updated Integrated RAID configuration pages including
  85  *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
  86  *                      Page 0.
  87  *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
  88  *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
  89  *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
  90  *                      Added missing MaxNumRoutedSasAddresses field to
  91  *                      MPI2_CONFIG_PAGE_EXPANDER_0.
  92  *                      Added SAS Port Page 0.
  93  *                      Modified structure layout for
  94  *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
  95  *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
  96  *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
  97  *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
  98  *                      to 0x000000FF.
  99  *                      Added two new values for the Physical Disk Coercion Size
 100  *                      bits in the Flags field of Manufacturing Page 4.
 101  *                      Added product-specific Manufacturing pages 16 to 31.
 102  *                      Modified Flags bits for controlling write cache on SATA
 103  *                      drives in IO Unit Page 1.
 104  *                      Added new bit to AdditionalControlFlags of SAS IO Unit
 105  *                      Page 1 to control Invalid Topology Correction.
 106  *                      Added additional defines for RAID Volume Page 0
 107  *                      VolumeStatusFlags field.
 108  *                      Modified meaning of RAID Volume Page 0 VolumeSettings
 109  *                      define for auto-configure of hot-swap drives.
 110  *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
 111  *                      added related defines.
 112  *                      Added PhysDiskAttributes field (and related defines) to
 113  *                      RAID Physical Disk Page 0.
 114  *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
 115  *                      Added three new DiscoveryStatus bits for SAS IO Unit
 116  *                      Page 0 and SAS Expander Page 0.
 117  *                      Removed multiplexing information from SAS IO Unit pages.
 118  *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
 119  *                      Removed Zone Address Resolved bit from PhyInfo and from
 120  *                      Expander Page 0 Flags field.
 121  *                      Added two new AccessStatus values to SAS Device Page 0
 122  *                      for indicating routing problems. Added 3 reserved words
 123  *                      to this page.
 124  *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
 125  *                      Inserted missing reserved field into structure for IOC
 126  *                      Page 6.
 127  *                      Added more pending task bits to RAID Volume Page 0
 128  *                      VolumeStatusFlags defines.
 129  *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
 130  *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
 131  *                      and SAS Expander Page 0 to flag a downstream initiator
 132  *                      when in simplified routing mode.
 133  *                      Removed SATA Init Failure defines for DiscoveryStatus
 134  *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
 135  *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
 136  *                      Added PortGroups, DmaGroup, and ControlGroup fields to
 137  *                      SAS Device Page 0.
 138  *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
 139  *                      Unit Page 6.
 140  *                      Added expander reduced functionality data to SAS
 141  *                      Expander Page 0.
 142  *                      Added SAS PHY Page 2 and SAS PHY Page 3.
 143  *  07-30-09  02.00.12  Added IO Unit Page 7.
 144  *                      Added new device ids.
 145  *                      Added SAS IO Unit Page 5.
 146  *                      Added partial and slumber power management capable flags
 147  *                      to SAS Device Page 0 Flags field.
 148  *                      Added PhyInfo defines for power condition.
 149  *                      Added Ethernet configuration pages.
 150  *  10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
 151  *                      Added SAS PHY Page 4 structure and defines.
 152  *  02-10-10  02.00.14  Modified the comments for the configuration page
 153  *                      structures that contain an array of data. The host
 154  *                      should use the "count" field in the page data (e.g. the
 155  *                      NumPhys field) to determine the number of valid elements
 156  *                      in the array.
 157  *                      Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
 158  *                      Added PowerManagementCapabilities to IO Unit Page 7.
 159  *                      Added PortWidthModGroup field to
 160  *                      MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
 161  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
 162  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
 163  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
 164  *  05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
 165  *                      define.
 166  *                      Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
 167  *                      Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
 168  *  08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
 169  *                      defines.
 170  *  11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
 171  *                      MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
 172  *                      the Pinout field.
 173  *                      Added BoardTemperature and BoardTemperatureUnits fields
 174  *                      to MPI2_CONFIG_PAGE_IO_UNIT_7.
 175  *                      Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
 176  *                      and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
 177  *  02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
 178  *                      Added IO Unit Page 8, IO Unit Page 9,
 179  *                      and IO Unit Page 10.
 180  *                      Added SASNotifyPrimitiveMasks field to
 181  *                      MPI2_CONFIG_PAGE_IOC_7.
 182  *  03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
 183  *  05-25-11  02.00.20  Cleaned up a few comments.
 184  *  08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
 185  *                      for PCIe link as obsolete.
 186  *                      Added SpinupFlags field containing a Disable Spin-up bit
 187  *                      to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
 188  *                      Unit Page 4.
 189  *  11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
 190  *                      Added UEFIVersion field to BIOS Page 1 and defined new
 191  *                      BiosOptions bits.
 192  *                      Incorporating additions for MPI v2.5.
 193  *  11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
 194  *                      Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
 195  *  12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
 196  *                      obsolete for MPI v2.5 and later.
 197  *                      Added some defines for 12G SAS speeds.
 198  *  04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
 199  *                      Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
 200  *                      match the specification.
 201  *  08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
 202  *                      future use.
 203  *  12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
 204  *                      MPI2_CONFIG_PAGE_MAN_7.
 205  *                      Added EnclosureLevel and ConnectorName fields to
 206  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
 207  *                      Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
 208  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
 209  *                      Added EnclosureLevel field to
 210  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
 211  *                      Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
 212  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
 213  *  --------------------------------------------------------------------------
 214  */
 215
 216 #ifndef MPI2_CNFG_H
 217 #define MPI2_CNFG_H
 218
 219 /*****************************************************************************
 220 *   Configuration Page Header and defines
 221 *****************************************************************************/
 222
 223 /* Config Page Header */
 224 typedef struct _MPI2_CONFIG_PAGE_HEADER
 225 {
 226     U8                 PageVersion;                /* 0x00 */
 227     U8                 PageLength;                 /* 0x01 */
 228     U8                 PageNumber;                 /* 0x02 */
 229     U8                 PageType;                   /* 0x03 */
 230 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
 231   Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
 232
 233 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
 234 {
 235    MPI2_CONFIG_PAGE_HEADER  Struct;
 236    U8                       Bytes[4];
 237    U16                      Word16[2];
 238    U32                      Word32;
 239 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
 240   Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
 241
 242 /* Extended Config Page Header */
 243 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
 244 {
 245     U8                  PageVersion;                /* 0x00 */
 246     U8                  Reserved1;                  /* 0x01 */
 247     U8                  PageNumber;                 /* 0x02 */
 248     U8                  PageType;                   /* 0x03 */
 249     U16                 ExtPageLength;              /* 0x04 */
 250     U8                  ExtPageType;                /* 0x06 */
 251     U8                  Reserved2;                  /* 0x07 */
 252 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 253   MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 254   Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
 255
 256 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
 257 {
 258    MPI2_CONFIG_PAGE_HEADER          Struct;
 259    MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
 260    U8                               Bytes[8];
 261    U16                              Word16[4];
 262    U32                              Word32[2];
 263 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
 264   Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
 265
 266
 267 /* PageType field values */
 268 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
 269 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
 270 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
 271 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
 272
 273 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
 274 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
 275 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
 276 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
 277 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
 278 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
 279 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
 280 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
 281
 282 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
 283
 284
 285 /* ExtPageType field values */
 286 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
 287 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
 288 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
 289 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
 290 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
 291 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
 292 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
 293 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
 294 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
 295 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
 296 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
 297
 298
 299 /*****************************************************************************
 300 *   PageAddress defines
 301 *****************************************************************************/
 302
 303 /* RAID Volume PageAddress format */
 304 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
 305 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
 306 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
 307
 308 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
 309
 310
 311 /* RAID Physical Disk PageAddress format */
 312 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
 313 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
 314 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
 315 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
 316
 317 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
 318 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
 319
 320
 321 /* SAS Expander PageAddress format */
 322 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
 323 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
 324 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
 325 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
 326
 327 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
 328 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
 329 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
 330
 331
 332 /* SAS Device PageAddress format */
 333 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
 334 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 335 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
 336
 337 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
 338
 339
 340 /* SAS PHY PageAddress format */
 341 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
 342 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
 343 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
 344
 345 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
 346 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
 347
 348
 349 /* SAS Port PageAddress format */
 350 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
 351 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
 352 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
 353
 354 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
 355
 356
 357 /* SAS Enclosure PageAddress format */
 358 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
 359 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 360 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
 361
 362 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
 363
 364
 365 /* RAID Configuration PageAddress format */
 366 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
 367 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
 368 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
 369 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
 370
 371 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
 372
 373
 374 /* Driver Persistent Mapping PageAddress format */
 375 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
 376 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
 377
 378 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
 379 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
 380 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
 381
 382
 383 /* Ethernet PageAddress format */
 384 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
 385 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
 386
 387 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
 388
 389
 390
 391 /****************************************************************************
 392 *   Configuration messages
 393 ****************************************************************************/
 394
 395 /* Configuration Request Message */
 396 typedef struct _MPI2_CONFIG_REQUEST
 397 {
 398     U8                      Action;                     /* 0x00 */
 399     U8                      SGLFlags;                   /* 0x01 */
 400     U8                      ChainOffset;                /* 0x02 */
 401     U8                      Function;                   /* 0x03 */
 402     U16                     ExtPageLength;              /* 0x04 */
 403     U8                      ExtPageType;                /* 0x06 */
 404     U8                      MsgFlags;                   /* 0x07 */
 405     U8                      VP_ID;                      /* 0x08 */
 406     U8                      VF_ID;                      /* 0x09 */
 407     U16                     Reserved1;                  /* 0x0A */
 408     U8                      Reserved2;                  /* 0x0C */
 409     U8                      ProxyVF_ID;                 /* 0x0D */
 410     U16                     Reserved4;                  /* 0x0E */
 411     U32                     Reserved3;                  /* 0x10 */
 412     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 413     U32                     PageAddress;                /* 0x18 */
 414     MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
 415 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
 416   Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
 417
 418 /* values for the Action field */
 419 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
 420 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
 421 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
 422 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
 423 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
 424 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
 425 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
 426 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
 427
 428 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
 429
 430
 431 /* Config Reply Message */
 432 typedef struct _MPI2_CONFIG_REPLY
 433 {
 434     U8                      Action;                     /* 0x00 */
 435     U8                      SGLFlags;                   /* 0x01 */
 436     U8                      MsgLength;                  /* 0x02 */
 437     U8                      Function;                   /* 0x03 */
 438     U16                     ExtPageLength;              /* 0x04 */
 439     U8                      ExtPageType;                /* 0x06 */
 440     U8                      MsgFlags;                   /* 0x07 */
 441     U8                      VP_ID;                      /* 0x08 */
 442     U8                      VF_ID;                      /* 0x09 */
 443     U16                     Reserved1;                  /* 0x0A */
 444     U16                     Reserved2;                  /* 0x0C */
 445     U16                     IOCStatus;                  /* 0x0E */
 446     U32                     IOCLogInfo;                 /* 0x10 */
 447     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 448 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
 449   Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
 450
 451
 452
 453 /*****************************************************************************
 454 *
 455 *               C o n f i g u r a t i o n    P a g e s
 456 *
 457 *****************************************************************************/
 458
 459 /****************************************************************************
 460 *   Manufacturing Config pages
 461 ****************************************************************************/
 462
 463 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
 464
 465 /* MPI v2.0 SAS products */
 466 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
 467 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
 468 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
 469 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
 470 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
 471 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
 472 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
 473
 474 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
 475
 476 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
 477 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
 478 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
 479 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
 480 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
 481 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
 482 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
 483 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
 484 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
 485
 486 /* MPI v2.5 SAS products */
 487 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
 488 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
 489 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
 490 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
 491 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
 492 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
 493
 494
 495
 496
 497 /* Manufacturing Page 0 */
 498
 499 typedef struct _MPI2_CONFIG_PAGE_MAN_0
 500 {
 501     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 502     U8                      ChipName[16];               /* 0x04 */
 503     U8                      ChipRevision[8];            /* 0x14 */
 504     U8                      BoardName[16];              /* 0x1C */
 505     U8                      BoardAssembly[16];          /* 0x2C */
 506     U8                      BoardTracerNumber[16];      /* 0x3C */
 507 } MPI2_CONFIG_PAGE_MAN_0,
 508   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
 509   Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
 510
 511 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
 512
 513
 514 /* Manufacturing Page 1 */
 515
 516 typedef struct _MPI2_CONFIG_PAGE_MAN_1
 517 {
 518     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 519     U8                      VPD[256];                   /* 0x04 */
 520 } MPI2_CONFIG_PAGE_MAN_1,
 521   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
 522   Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
 523
 524 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
 525
 526
 527 typedef struct _MPI2_CHIP_REVISION_ID
 528 {
 529     U16 DeviceID;                                       /* 0x00 */
 530     U8  PCIRevisionID;                                  /* 0x02 */
 531     U8  Reserved;                                       /* 0x03 */
 532 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
 533   Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
 534
 535
 536 /* Manufacturing Page 2 */
 537
 538 /*
 539  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 540  * one and check Header.PageLength at runtime.
 541  */
 542 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
 543 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
 544 #endif
 545
 546 typedef struct _MPI2_CONFIG_PAGE_MAN_2
 547 {
 548     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 549     MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
 550     U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
 551 } MPI2_CONFIG_PAGE_MAN_2,
 552   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
 553   Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
 554
 555 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
 556
 557
 558 /* Manufacturing Page 3 */
 559
 560 /*
 561  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 562  * one and check Header.PageLength at runtime.
 563  */
 564 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
 565 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
 566 #endif
 567
 568 typedef struct _MPI2_CONFIG_PAGE_MAN_3
 569 {
 570     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 571     MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
 572     U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
 573 } MPI2_CONFIG_PAGE_MAN_3,
 574   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
 575   Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
 576
 577 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
 578
 579
 580 /* Manufacturing Page 4 */
 581
 582 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
 583 {
 584     U8                          PowerSaveFlags;                 /* 0x00 */
 585     U8                          InternalOperationsSleepTime;    /* 0x01 */
 586     U8                          InternalOperationsRunTime;      /* 0x02 */
 587     U8                          HostIdleTime;                   /* 0x03 */
 588 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 589   MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 590   Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
 591
 592 /* defines for the PowerSaveFlags field */
 593 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
 594 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
 595 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
 596 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
 597
 598 typedef struct _MPI2_CONFIG_PAGE_MAN_4
 599 {
 600     MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
 601     U32                                 Reserved1;              /* 0x04 */
 602     U32                                 Flags;                  /* 0x08 */
 603     U8                                  InquirySize;            /* 0x0C */
 604     U8                                  Reserved2;              /* 0x0D */
 605     U16                                 Reserved3;              /* 0x0E */
 606     U8                                  InquiryData[56];        /* 0x10 */
 607     U32                                 RAID0VolumeSettings;    /* 0x48 */
 608     U32                                 RAID1EVolumeSettings;   /* 0x4C */
 609     U32                                 RAID1VolumeSettings;    /* 0x50 */
 610     U32                                 RAID10VolumeSettings;   /* 0x54 */
 611     U32                                 Reserved4;              /* 0x58 */
 612     U32                                 Reserved5;              /* 0x5C */
 613     MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
 614     U8                                  MaxOCEDisks;            /* 0x64 */
 615     U8                                  ResyncRate;             /* 0x65 */
 616     U16                                 DataScrubDuration;      /* 0x66 */
 617     U8                                  MaxHotSpares;           /* 0x68 */
 618     U8                                  MaxPhysDisksPerVol;     /* 0x69 */
 619     U8                                  MaxPhysDisks;           /* 0x6A */
 620     U8                                  MaxVolumes;             /* 0x6B */
 621 } MPI2_CONFIG_PAGE_MAN_4,
 622   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
 623   Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
 624
 625 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
 626
 627 /* Manufacturing Page 4 Flags field */
 628 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
 629 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
 630
 631 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
 632 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
 633 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
 634
 635 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
 636 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
 637 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
 638 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
 639 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
 640
 641 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
 642 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
 643 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
 644 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
 645
 646 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
 647 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
 648 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
 649 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
 650 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
 651 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
 652 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
 653 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
 654
 655
 656 /* Manufacturing Page 5 */
 657
 658 /*
 659  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 660  * one and check the value returned for NumPhys at runtime.
 661  */
 662 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
 663 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
 664 #endif
 665
 666 typedef struct _MPI2_MANUFACTURING5_ENTRY
 667 {
 668     U64                                 WWID;           /* 0x00 */
 669     U64                                 DeviceName;     /* 0x08 */
 670 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
 671   Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
 672
 673 typedef struct _MPI2_CONFIG_PAGE_MAN_5
 674 {
 675     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 676     U8                                  NumPhys;        /* 0x04 */
 677     U8                                  Reserved1;      /* 0x05 */
 678     U16                                 Reserved2;      /* 0x06 */
 679     U32                                 Reserved3;      /* 0x08 */
 680     U32                                 Reserved4;      /* 0x0C */
 681     MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
 682 } MPI2_CONFIG_PAGE_MAN_5,
 683   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
 684   Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
 685
 686 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
 687
 688
 689 /* Manufacturing Page 6 */
 690
 691 typedef struct _MPI2_CONFIG_PAGE_MAN_6
 692 {
 693     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 694     U32                             ProductSpecificInfo;/* 0x04 */
 695 } MPI2_CONFIG_PAGE_MAN_6,
 696   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
 697   Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
 698
 699 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
 700
 701
 702 /* Manufacturing Page 7 */
 703
 704 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
 705 {
 706     U32                         Pinout;                 /* 0x00 */
 707     U8                          Connector[16];          /* 0x04 */
 708     U8                          Location;               /* 0x14 */
 709     U8                          ReceptacleID;           /* 0x15 */
 710     U16                         Slot;                   /* 0x16 */
 711     U32                         Reserved2;              /* 0x18 */
 712 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
 713   Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
 714
 715 /* defines for the Pinout field */
 716 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
 717 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
 718
 719 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
 720 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
 721 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
 722 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
 723 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
 724 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
 725 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
 726 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
 727 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
 728 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
 729 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
 730 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
 731 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
 732 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
 733 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
 734
 735 /* defines for the Location field */
 736 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
 737 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
 738 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
 739 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
 740 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
 741 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
 742 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
 743
 744 /*
 745  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 746  * one and check the value returned for NumPhys at runtime.
 747  */
 748 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
 749 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
 750 #endif
 751
 752 typedef struct _MPI2_CONFIG_PAGE_MAN_7
 753 {
 754     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 755     U32                             Reserved1;          /* 0x04 */
 756     U32                             Reserved2;          /* 0x08 */
 757     U32                             Flags;              /* 0x0C */
 758     U8                              EnclosureName[16];  /* 0x10 */
 759     U8                              NumPhys;            /* 0x20 */
 760     U8                              Reserved3;          /* 0x21 */
 761     U16                             Reserved4;          /* 0x22 */
 762     MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
 763 } MPI2_CONFIG_PAGE_MAN_7,
 764   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
 765   Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
 766
 767 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
 768
 769 /* defines for the Flags field */
 770 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
 771 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
 772 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
 773
 774
 775 /*
 776  * Generic structure to use for product-specific manufacturing pages
 777  * (currently Manufacturing Page 8 through Manufacturing Page 31).
 778  */
 779
 780 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
 781 {
 782     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 783     U32                             ProductSpecificInfo;/* 0x04 */
 784 } MPI2_CONFIG_PAGE_MAN_PS,
 785   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
 786   Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
 787
 788 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
 789 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
 790 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
 791 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
 792 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
 793 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
 794 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
 795 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
 796 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
 797 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
 798 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
 799 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
 800 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
 801 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
 802 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
 803 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
 804 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
 805 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
 806 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
 807 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
 808 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
 809 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
 810 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
 811 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
 812
 813
 814 /****************************************************************************
 815 *   IO Unit Config Pages
 816 ****************************************************************************/
 817
 818 /* IO Unit Page 0 */
 819
 820 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
 821 {
 822     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 823     U64                     UniqueValue;                /* 0x04 */
 824     MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
 825     MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
 826 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
 827   Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
 828
 829 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
 830
 831
 832 /* IO Unit Page 1 */
 833
 834 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
 835 {
 836     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 837     U32                     Flags;                      /* 0x04 */
 838 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
 839   Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
 840
 841 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
 842
 843 /* IO Unit Page 1 Flags defines */
 844 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
 845 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
 846 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
 847 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
 848 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
 849 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
 850 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
 851 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
 852 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
 853 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
 854 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
 855 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
 856 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
 857
 858
 859 /* IO Unit Page 3 */
 860
 861 /*
 862  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 863  * one and check the value returned for GPIOCount at runtime.
 864  */
 865 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
 866 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
 867 #endif
 868
 869 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
 870 {
 871     MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
 872     U8                      GPIOCount;                                /* 0x04 */
 873     U8                      Reserved1;                                /* 0x05 */
 874     U16                     Reserved2;                                /* 0x06 */
 875     U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
 876 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
 877   Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
 878
 879 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
 880
 881 /* defines for IO Unit Page 3 GPIOVal field */
 882 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
 883 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
 884 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
 885 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
 886
 887
 888 /* IO Unit Page 5 */
 889
 890 /*
 891  * Upper layer code (drivers, utilities, etc.) should leave this define set to
 892  * one and check the value returned for NumDmaEngines at runtime.
 893  */
 894 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
 895 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
 896 #endif
 897
 898 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
 899 {
 900     MPI2_CONFIG_PAGE_HEADER Header;                                     /* 0x00 */
 901     U64                     RaidAcceleratorBufferBaseAddress;           /* 0x04 */
 902     U64                     RaidAcceleratorBufferSize;                  /* 0x0C */
 903     U64                     RaidAcceleratorControlBaseAddress;          /* 0x14 */
 904     U8                      RAControlSize;                              /* 0x1C */
 905     U8                      NumDmaEngines;                              /* 0x1D */
 906     U8                      RAMinControlSize;                           /* 0x1E */
 907     U8                      RAMaxControlSize;                           /* 0x1F */
 908     U32                     Reserved1;                                  /* 0x20 */
 909     U32                     Reserved2;                                  /* 0x24 */
 910     U32                     Reserved3;                                  /* 0x28 */
 911     U32                     DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
 912 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
 913   Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
 914
 915 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
 916
 917 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
 918 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
 919 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
 920
 921 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
 922 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
 923 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
 924 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
 925
 926
 927 /* IO Unit Page 6 */
 928
 929 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
 930 {
 931     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 932     U16                     Flags;                                  /* 0x04 */
 933     U8                      RAHostControlSize;                      /* 0x06 */
 934     U8                      Reserved0;                              /* 0x07 */
 935     U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
 936     U32                     Reserved1;                              /* 0x10 */
 937     U32                     Reserved2;                              /* 0x14 */
 938     U32                     Reserved3;                              /* 0x18 */
 939 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
 940   Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
 941
 942 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
 943
 944 /* defines for IO Unit Page 6 Flags field */
 945 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
 946
 947
 948 /* IO Unit Page 7 */
 949
 950 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
 951 {
 952     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 953     U8                      CurrentPowerMode;                       /* 0x04 */ /* reserved in MPI 2.0 */
 954     U8                      PreviousPowerMode;                      /* 0x05 */ /* reserved in MPI 2.0 */
 955     U8                      PCIeWidth;                              /* 0x06 */
 956     U8                      PCIeSpeed;                              /* 0x07 */
 957     U32                     ProcessorState;                         /* 0x08 */
 958     U32                     PowerManagementCapabilities;            /* 0x0C */
 959     U16                     IOCTemperature;                         /* 0x10 */
 960     U8                      IOCTemperatureUnits;                    /* 0x12 */
 961     U8                      IOCSpeed;                               /* 0x13 */
 962     U16                     BoardTemperature;                       /* 0x14 */
 963     U8                      BoardTemperatureUnits;                  /* 0x16 */
 964     U8                      Reserved3;                              /* 0x17 */
 965     U32                     Reserved4;                              /* 0x18 */
 966     U32                     Reserved5;                              /* 0x1C */
 967     U32                     Reserved6;                              /* 0x20 */
 968     U32                     Reserved7;                              /* 0x24 */
 969 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
 970   Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
 971
 972 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x04)
 973
 974 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
 975 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
 976 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
 977 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
 978 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
 979 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
 980
 981 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
 982 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
 983 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
 984 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
 985 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
 986 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
 987
 988
 989 /* defines for IO Unit Page 7 PCIeWidth field */
 990 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
 991 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
 992 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
 993 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
 994
 995 /* defines for IO Unit Page 7 PCIeSpeed field */
 996 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
 997 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
 998 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
 999
1000 /* defines for IO Unit Page 7 ProcessorState field */
1001 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
1002 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
1003
1004 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
1005 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1006 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1007
1008 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
1009 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1010 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1011 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1012 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1013 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1014 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1015 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1016 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1017 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1018 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1019 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1020 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1021 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1022 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1023 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1024 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008) /* obsolete */
1025 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004) /* obsolete */
1026 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002) /* obsolete */
1027 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001) /* obsolete */
1028
1029 /* obsolete names for the PowerManagementCapabilities bits (above) */
1030 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1031 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1032 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1033 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /* obsolete */
1034 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /* obsolete */
1035
1036
1037 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
1038 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1039 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1040 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1041
1042 /* defines for IO Unit Page 7 IOCSpeed field */
1043 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1044 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1045 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1046 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1047
1048 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
1049 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1050 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1051 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1052
1053
1054 /* IO Unit Page 8 */
1055
1056 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1057
1058 typedef struct _MPI2_IOUNIT8_SENSOR
1059 {
1060     U16                     Flags;                                  /* 0x00 */
1061     U16                     Reserved1;                              /* 0x02 */
1062     U16                     Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
1063     U32                     Reserved2;                              /* 0x0C */
1064     U32                     Reserved3;                              /* 0x10 */
1065     U32                     Reserved4;                              /* 0x14 */
1066 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
1067   Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
1068
1069 /* defines for IO Unit Page 8 Sensor Flags field */
1070 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1071 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1072 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1073 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1074
1075 /*
1076  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1077  * one and check the value returned for NumSensors at runtime.
1078  */
1079 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1080 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1081 #endif
1082
1083 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8
1084 {
1085     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1086     U32                     Reserved1;                              /* 0x04 */
1087     U32                     Reserved2;                              /* 0x08 */
1088     U8                      NumSensors;                             /* 0x0C */
1089     U8                      PollingInterval;                        /* 0x0D */
1090     U16                     Reserved3;                              /* 0x0E */
1091     MPI2_IOUNIT8_SENSOR     Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1092 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1093   Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1094
1095 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1096
1097
1098 /* IO Unit Page 9 */
1099
1100 typedef struct _MPI2_IOUNIT9_SENSOR
1101 {
1102     U16                     CurrentTemperature;                     /* 0x00 */
1103     U16                     Reserved1;                              /* 0x02 */
1104     U8                      Flags;                                  /* 0x04 */
1105     U8                      Reserved2;                              /* 0x05 */
1106     U16                     Reserved3;                              /* 0x06 */
1107     U32                     Reserved4;                              /* 0x08 */
1108     U32                     Reserved5;                              /* 0x0C */
1109 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1110   Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1111
1112 /* defines for IO Unit Page 9 Sensor Flags field */
1113 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1114
1115 /*
1116  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1117  * one and check the value returned for NumSensors at runtime.
1118  */
1119 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1120 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1121 #endif
1122
1123 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9
1124 {
1125     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1126     U32                     Reserved1;                              /* 0x04 */
1127     U32                     Reserved2;                              /* 0x08 */
1128     U8                      NumSensors;                             /* 0x0C */
1129     U8                      Reserved4;                              /* 0x0D */
1130     U16                     Reserved3;                              /* 0x0E */
1131     MPI2_IOUNIT9_SENSOR     Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1132 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1133   Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1134
1135 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1136
1137
1138 /* IO Unit Page 10 */
1139
1140 typedef struct _MPI2_IOUNIT10_FUNCTION
1141 {
1142     U8                      CreditPercent;      /* 0x00 */
1143     U8                      Reserved1;          /* 0x01 */
1144     U16                     Reserved2;          /* 0x02 */
1145 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1146   Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1147
1148 /*
1149  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1150  * one and check the value returned for NumFunctions at runtime.
1151  */
1152 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1153 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1154 #endif
1155
1156 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10
1157 {
1158     MPI2_CONFIG_PAGE_HEADER Header;                                         /* 0x00 */
1159     U8                      NumFunctions;                                   /* 0x04 */
1160     U8                      Reserved1;                                      /* 0x05 */
1161     U16                     Reserved2;                                      /* 0x06 */
1162     U32                     Reserved3;                                      /* 0x08 */
1163     U32                     Reserved4;                                      /* 0x0C */
1164     MPI2_IOUNIT10_FUNCTION  Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];   /* 0x10 */
1165 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1166   Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1167
1168 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1169
1170
1171
1172 /****************************************************************************
1173 *   IOC Config Pages
1174 ****************************************************************************/
1175
1176 /* IOC Page 0 */
1177
1178 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1179 {
1180     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1181     U32                     Reserved1;                  /* 0x04 */
1182     U32                     Reserved2;                  /* 0x08 */
1183     U16                     VendorID;                   /* 0x0C */
1184     U16                     DeviceID;                   /* 0x0E */
1185     U8                      RevisionID;                 /* 0x10 */
1186     U8                      Reserved3;                  /* 0x11 */
1187     U16                     Reserved4;                  /* 0x12 */
1188     U32                     ClassCode;                  /* 0x14 */
1189     U16                     SubsystemVendorID;          /* 0x18 */
1190     U16                     SubsystemID;                /* 0x1A */
1191 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1192   Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1193
1194 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1195
1196
1197 /* IOC Page 1 */
1198
1199 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1200 {
1201     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1202     U32                     Flags;                      /* 0x04 */
1203     U32                     CoalescingTimeout;          /* 0x08 */
1204     U8                      CoalescingDepth;            /* 0x0C */
1205     U8                      PCISlotNum;                 /* 0x0D */
1206     U8                      PCIBusNum;                  /* 0x0E */
1207     U8                      PCIDomainSegment;           /* 0x0F */
1208     U32                     Reserved1;                  /* 0x10 */
1209     U32                     Reserved2;                  /* 0x14 */
1210 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1211   Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1212
1213 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1214
1215 /* defines for IOC Page 1 Flags field */
1216 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1217
1218 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1219 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1220 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1221
1222 /* IOC Page 6 */
1223
1224 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1225 {
1226     MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
1227     U32                     CapabilitiesFlags;              /* 0x04 */
1228     U8                      MaxDrivesRAID0;                 /* 0x08 */
1229     U8                      MaxDrivesRAID1;                 /* 0x09 */
1230     U8                      MaxDrivesRAID1E;                /* 0x0A */
1231     U8                      MaxDrivesRAID10;                /* 0x0B */
1232     U8                      MinDrivesRAID0;                 /* 0x0C */
1233     U8                      MinDrivesRAID1;                 /* 0x0D */
1234     U8                      MinDrivesRAID1E;                /* 0x0E */
1235     U8                      MinDrivesRAID10;                /* 0x0F */
1236     U32                     Reserved1;                      /* 0x10 */
1237     U8                      MaxGlobalHotSpares;             /* 0x14 */
1238     U8                      MaxPhysDisks;                   /* 0x15 */
1239     U8                      MaxVolumes;                     /* 0x16 */
1240     U8                      MaxConfigs;                     /* 0x17 */
1241     U8                      MaxOCEDisks;                    /* 0x18 */
1242     U8                      Reserved2;                      /* 0x19 */
1243     U16                     Reserved3;                      /* 0x1A */
1244     U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
1245     U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
1246     U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
1247     U32                     Reserved4;                      /* 0x28 */
1248     U32                     Reserved5;                      /* 0x2C */
1249     U16                     DefaultMetadataSize;            /* 0x30 */
1250     U16                     Reserved6;                      /* 0x32 */
1251     U16                     MaxBadBlockTableEntries;        /* 0x34 */
1252     U16                     Reserved7;                      /* 0x36 */
1253     U32                     IRNvsramVersion;                /* 0x38 */
1254 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1255   Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1256
1257 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1258
1259 /* defines for IOC Page 6 CapabilitiesFlags */
1260 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1261 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1262 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1263 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1264 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1265 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1266
1267
1268 /* IOC Page 7 */
1269
1270 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1271
1272 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1273 {
1274     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1275     U32                     Reserved1;                  /* 0x04 */
1276     U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1277     U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
1278     U16                     SASNotifyPrimitiveMasks;    /* 0x1A */
1279     U32                     Reserved3;                  /* 0x1C */
1280 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1281   Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1282
1283 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1284
1285
1286 /* IOC Page 8 */
1287
1288 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1289 {
1290     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1291     U8                      NumDevsPerEnclosure;        /* 0x04 */
1292     U8                      Reserved1;                  /* 0x05 */
1293     U16                     Reserved2;                  /* 0x06 */
1294     U16                     MaxPersistentEntries;       /* 0x08 */
1295     U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
1296     U16                     Flags;                      /* 0x0C */
1297     U16                     Reserved3;                  /* 0x0E */
1298     U16                     IRVolumeMappingFlags;       /* 0x10 */
1299     U16                     Reserved4;                  /* 0x12 */
1300     U32                     Reserved5;                  /* 0x14 */
1301 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1302   Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1303
1304 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1305
1306 /* defines for IOC Page 8 Flags field */
1307 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1308 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1309
1310 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1311 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1312 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1313
1314 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1315 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1316
1317 /* defines for IOC Page 8 IRVolumeMappingFlags */
1318 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1319 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1320 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1321
1322
1323 /****************************************************************************
1324 *   BIOS Config Pages
1325 ****************************************************************************/
1326
1327 /* BIOS Page 1 */
1328
1329 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1330 {
1331     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1332     U32                     BiosOptions;                /* 0x04 */
1333     U32                     IOCSettings;                /* 0x08 */
1334     U32                     Reserved1;                  /* 0x0C */
1335     U32                     DeviceSettings;             /* 0x10 */
1336     U16                     NumberOfDevices;            /* 0x14 */
1337     U16                     UEFIVersion;                /* 0x16 */
1338     U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
1339     U16                     IOTimeoutSequential;        /* 0x1A */
1340     U16                     IOTimeoutOther;             /* 0x1C */
1341     U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
1342 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1343   Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1344
1345 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x05)
1346
1347 /* values for BIOS Page 1 BiosOptions field */
1348 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1349 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1350
1351 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1352 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1353 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1354 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1355
1356 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1357
1358 /* values for BIOS Page 1 IOCSettings field */
1359 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1360 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1361 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1362
1363 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1364 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1365 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1366 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1367
1368 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1369 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1370 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1371 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1372 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1373
1374 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1375
1376 /* values for BIOS Page 1 DeviceSettings field */
1377 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1378 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1379 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1380 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1381 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1382
1383 /* defines for BIOS Page 1 UEFIVersion field */
1384 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1385 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1386 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1387 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1388
1389
1390
1391 /* BIOS Page 2 */
1392
1393 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1394 {
1395     U32         Reserved1;                              /* 0x00 */
1396     U32         Reserved2;                              /* 0x04 */
1397     U32         Reserved3;                              /* 0x08 */
1398     U32         Reserved4;                              /* 0x0C */
1399     U32         Reserved5;                              /* 0x10 */
1400     U32         Reserved6;                              /* 0x14 */
1401 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1402   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1403   Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1404
1405 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1406 {
1407     U64         SASAddress;                             /* 0x00 */
1408     U8          LUN[8];                                 /* 0x08 */
1409     U32         Reserved1;                              /* 0x10 */
1410     U32         Reserved2;                              /* 0x14 */
1411 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1412   Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1413
1414 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1415 {
1416     U64         EnclosureLogicalID;                     /* 0x00 */
1417     U32         Reserved1;                              /* 0x08 */
1418     U32         Reserved2;                              /* 0x0C */
1419     U16         SlotNumber;                             /* 0x10 */
1420     U16         Reserved3;                              /* 0x12 */
1421     U32         Reserved4;                              /* 0x14 */
1422 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1423   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1424   Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1425
1426 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1427 {
1428     U64         DeviceName;                             /* 0x00 */
1429     U8          LUN[8];                                 /* 0x08 */
1430     U32         Reserved1;                              /* 0x10 */
1431     U32         Reserved2;                              /* 0x14 */
1432 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1433   Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1434
1435 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1436 {
1437     MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1438     MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1439     MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1440     MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1441 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1442   Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1443
1444 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1445 {
1446     MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
1447     U32                         Reserved1;              /* 0x04 */
1448     U32                         Reserved2;              /* 0x08 */
1449     U32                         Reserved3;              /* 0x0C */
1450     U32                         Reserved4;              /* 0x10 */
1451     U32                         Reserved5;              /* 0x14 */
1452     U32                         Reserved6;              /* 0x18 */
1453     U8                          ReqBootDeviceForm;      /* 0x1C */
1454     U8                          Reserved7;              /* 0x1D */
1455     U16                         Reserved8;              /* 0x1E */
1456     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
1457     U8                          ReqAltBootDeviceForm;   /* 0x38 */
1458     U8                          Reserved9;              /* 0x39 */
1459     U16                         Reserved10;             /* 0x3A */
1460     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
1461     U8                          CurrentBootDeviceForm;  /* 0x58 */
1462     U8                          Reserved11;             /* 0x59 */
1463     U16                         Reserved12;             /* 0x5A */
1464     MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
1465 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1466   Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1467
1468 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1469
1470 /* values for BIOS Page 2 BootDeviceForm fields */
1471 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1472 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1473 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1474 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1475 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1476
1477
1478 /* BIOS Page 3 */
1479
1480 typedef struct _MPI2_ADAPTER_INFO
1481 {
1482     U8      PciBusNumber;                               /* 0x00 */
1483     U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
1484     U16     AdapterFlags;                               /* 0x02 */
1485 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1486   Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1487
1488 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1489 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1490
1491 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1492 {
1493     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1494     U32                     GlobalFlags;                /* 0x04 */
1495     U32                     BiosVersion;                /* 0x08 */
1496     MPI2_ADAPTER_INFO       AdapterOrder[4];            /* 0x0C */
1497     U32                     Reserved1;                  /* 0x1C */
1498 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1499   Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1500
1501 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x00)
1502
1503 /* values for BIOS Page 3 GlobalFlags */
1504 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1505 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1506 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1507
1508 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1509 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1510 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1511 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1512
1513
1514 /* BIOS Page 4 */
1515
1516 /*
1517  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1518  * one and check the value returned for NumPhys at runtime.
1519  */
1520 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1521 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1522 #endif
1523
1524 typedef struct _MPI2_BIOS4_ENTRY
1525 {
1526     U64                     ReassignmentWWID;       /* 0x00 */
1527     U64                     ReassignmentDeviceName; /* 0x08 */
1528 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1529   Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1530
1531 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1532 {
1533     MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
1534     U8                      NumPhys;                            /* 0x04 */
1535     U8                      Reserved1;                          /* 0x05 */
1536     U16                     Reserved2;                          /* 0x06 */
1537     MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
1538 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1539   Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1540
1541 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1542
1543
1544 /****************************************************************************
1545 *   RAID Volume Config Pages
1546 ****************************************************************************/
1547
1548 /* RAID Volume Page 0 */
1549
1550 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1551 {
1552     U8                      RAIDSetNum;                 /* 0x00 */
1553     U8                      PhysDiskMap;                /* 0x01 */
1554     U8                      PhysDiskNum;                /* 0x02 */
1555     U8                      Reserved;                   /* 0x03 */
1556 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1557   Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1558
1559 /* defines for the PhysDiskMap field */
1560 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1561 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1562
1563 typedef struct _MPI2_RAIDVOL0_SETTINGS
1564 {
1565     U16                     Settings;                   /* 0x00 */
1566     U8                      HotSparePool;               /* 0x01 */
1567     U8                      Reserved;                   /* 0x02 */
1568 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1569   Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1570
1571 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1572 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1573 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1574 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1575 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1576 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1577 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1578 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1579 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1580
1581 /* RAID Volume Page 0 VolumeSettings defines */
1582 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1583 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1584
1585 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1586 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1587 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1588 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1589
1590 /*
1591  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1592  * one and check the value returned for NumPhysDisks at runtime.
1593  */
1594 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1595 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1596 #endif
1597
1598 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1599 {
1600     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1601     U16                     DevHandle;                  /* 0x04 */
1602     U8                      VolumeState;                /* 0x06 */
1603     U8                      VolumeType;                 /* 0x07 */
1604     U32                     VolumeStatusFlags;          /* 0x08 */
1605     MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
1606     U64                     MaxLBA;                     /* 0x10 */
1607     U32                     StripeSize;                 /* 0x18 */
1608     U16                     BlockSize;                  /* 0x1C */
1609     U16                     Reserved1;                  /* 0x1E */
1610     U8                      SupportedPhysDisks;         /* 0x20 */
1611     U8                      ResyncRate;                 /* 0x21 */
1612     U16                     DataScrubDuration;          /* 0x22 */
1613     U8                      NumPhysDisks;               /* 0x24 */
1614     U8                      Reserved2;                  /* 0x25 */
1615     U8                      Reserved3;                  /* 0x26 */
1616     U8                      InactiveStatus;             /* 0x27 */
1617     MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1618 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1619   Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1620
1621 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1622
1623 /* values for RAID VolumeState */
1624 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1625 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1626 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1627 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1628 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1629 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1630
1631 /* values for RAID VolumeType */
1632 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1633 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1634 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1635 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1636 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1637
1638 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1639 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1640 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1641 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1642 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1643 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1644 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1645 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1646 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1647 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1648 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1649 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1650 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1651 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1652 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1653 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1654 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1655 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1656 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1657 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1658
1659 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1660 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1661 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1662 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1663 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1664
1665 /* values for RAID Volume Page 0 InactiveStatus field */
1666 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1667 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1668 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1669 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1670 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1671 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1672 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1673
1674
1675 /* RAID Volume Page 1 */
1676
1677 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1678 {
1679     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1680     U16                     DevHandle;                  /* 0x04 */
1681     U16                     Reserved0;                  /* 0x06 */
1682     U8                      GUID[24];                   /* 0x08 */
1683     U8                      Name[16];                   /* 0x20 */
1684     U64                     WWID;                       /* 0x30 */
1685     U32                     Reserved1;                  /* 0x38 */
1686     U32                     Reserved2;                  /* 0x3C */
1687 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1688   Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1689
1690 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1691
1692
1693 /****************************************************************************
1694 *   RAID Physical Disk Config Pages
1695 ****************************************************************************/
1696
1697 /* RAID Physical Disk Page 0 */
1698
1699 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1700 {
1701     U16                     Reserved1;                  /* 0x00 */
1702     U8                      HotSparePool;               /* 0x02 */
1703     U8                      Reserved2;                  /* 0x03 */
1704 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1705   Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1706
1707 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1708
1709 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1710 {
1711     U8                      VendorID[8];                /* 0x00 */
1712     U8                      ProductID[16];              /* 0x08 */
1713     U8                      ProductRevLevel[4];         /* 0x18 */
1714     U8                      SerialNum[32];              /* 0x1C */
1715 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1716   MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1717   Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1718
1719 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1720 {
1721     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1722     U16                             DevHandle;                  /* 0x04 */
1723     U8                              Reserved1;                  /* 0x06 */
1724     U8                              PhysDiskNum;                /* 0x07 */
1725     MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
1726     U32                             Reserved2;                  /* 0x0C */
1727     MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
1728     U32                             Reserved3;                  /* 0x4C */
1729     U8                              PhysDiskState;              /* 0x50 */
1730     U8                              OfflineReason;              /* 0x51 */
1731     U8                              IncompatibleReason;         /* 0x52 */
1732     U8                              PhysDiskAttributes;         /* 0x53 */
1733     U32                             PhysDiskStatusFlags;        /* 0x54 */
1734     U64                             DeviceMaxLBA;               /* 0x58 */
1735     U64                             HostMaxLBA;                 /* 0x60 */
1736     U64                             CoercedMaxLBA;              /* 0x68 */
1737     U16                             BlockSize;                  /* 0x70 */
1738     U16                             Reserved5;                  /* 0x72 */
1739     U32                             Reserved6;                  /* 0x74 */
1740 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1741   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1742   Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1743
1744 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1745
1746 /* PhysDiskState defines */
1747 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1748 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1749 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1750 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1751 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1752 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1753 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1754 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1755
1756 /* OfflineReason defines */
1757 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1758 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1759 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1760 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1761 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1762 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1763 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1764
1765 /* IncompatibleReason defines */
1766 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1767 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1768 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1769 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1770 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1771 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1772 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1773 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1774
1775 /* PhysDiskAttributes defines */
1776 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1777 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1778 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1779
1780 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1781 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1782 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1783
1784 /* PhysDiskStatusFlags defines */
1785 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1786 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1787 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1788 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1789 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1790 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1791 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1792 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1793
1794
1795 /* RAID Physical Disk Page 1 */
1796
1797 /*
1798  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1799  * one and check the value returned for NumPhysDiskPaths at runtime.
1800  */
1801 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1802 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1803 #endif
1804
1805 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1806 {
1807     U16             DevHandle;          /* 0x00 */
1808     U16             Reserved1;          /* 0x02 */
1809     U64             WWID;               /* 0x04 */
1810     U64             OwnerWWID;          /* 0x0C */
1811     U8              OwnerIdentifier;    /* 0x14 */
1812     U8              Reserved2;          /* 0x15 */
1813     U16             Flags;              /* 0x16 */
1814 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1815   Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1816
1817 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1818 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1819 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1820 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1821
1822 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1823 {
1824     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1825     U8                              NumPhysDiskPaths;           /* 0x04 */
1826     U8                              PhysDiskNum;                /* 0x05 */
1827     U16                             Reserved1;                  /* 0x06 */
1828     U32                             Reserved2;                  /* 0x08 */
1829     MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1830 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1831   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1832   Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1833
1834 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1835
1836
1837 /****************************************************************************
1838 *   values for fields used by several types of SAS Config Pages
1839 ****************************************************************************/
1840
1841 /* values for NegotiatedLinkRates fields */
1842 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1843 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1844 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1845 /* link rates used for Negotiated Physical and Logical Link Rate */
1846 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1847 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1848 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1849 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1850 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1851 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1852 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
1853 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1854 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1855 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1856 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
1857
1858
1859 /* values for AttachedPhyInfo fields */
1860 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1861 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1862 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1863
1864 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1865 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1866 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1867 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1868 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1869 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1870 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1871 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1872 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1873 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1874
1875
1876 /* values for PhyInfo fields */
1877 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1878
1879 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1880 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
1881 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1882 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
1883 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
1884
1885 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
1886 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
1887 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
1888 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
1889 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
1890 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
1891
1892 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
1893 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
1894 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
1895 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
1896 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
1897 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
1898 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
1899 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
1900 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
1901 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
1902
1903 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
1904 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
1905 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
1906 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
1907
1908 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
1909 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
1910
1911 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
1912 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
1913 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
1914 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
1915
1916
1917 /* values for SAS ProgrammedLinkRate fields */
1918 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
1919 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
1920 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
1921 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
1922 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
1923 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
1924 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
1925 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
1926 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
1927 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
1928 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
1929 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
1930
1931
1932 /* values for SAS HwLinkRate fields */
1933 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
1934 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
1935 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
1936 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
1937 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
1938 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
1939 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
1940 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
1941 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
1942 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
1943
1944
1945
1946 /****************************************************************************
1947 *   SAS IO Unit Config Pages
1948 ****************************************************************************/
1949
1950 /* SAS IO Unit Page 0 */
1951
1952 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1953 {
1954     U8          Port;                   /* 0x00 */
1955     U8          PortFlags;              /* 0x01 */
1956     U8          PhyFlags;               /* 0x02 */
1957     U8          NegotiatedLinkRate;     /* 0x03 */
1958     U32         ControllerPhyDeviceInfo;/* 0x04 */
1959     U16         AttachedDevHandle;      /* 0x08 */
1960     U16         ControllerDevHandle;    /* 0x0A */
1961     U32         DiscoveryStatus;        /* 0x0C */
1962     U32         Reserved;               /* 0x10 */
1963 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1964   Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1965
1966 /*
1967  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1968  * one and check the value returned for NumPhys at runtime.
1969  */
1970 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1971 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
1972 #endif
1973
1974 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1975 {
1976     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1977     U32                                 Reserved1;                          /* 0x08 */
1978     U8                                  NumPhys;                            /* 0x0C */
1979     U8                                  Reserved2;                          /* 0x0D */
1980     U16                                 Reserved3;                          /* 0x0E */
1981     MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
1982 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1983   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1984   Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1985
1986 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
1987
1988 /* values for SAS IO Unit Page 0 PortFlags */
1989 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
1990 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
1991
1992 /* values for SAS IO Unit Page 0 PhyFlags */
1993 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
1994 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
1995
1996 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1997
1998 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1999
2000 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2001 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
2002 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
2003 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
2004 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
2005 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2006 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2007 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2008 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2009 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2010 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2011 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2012 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2013 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2014 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2015 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2016 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2017 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2018 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2019 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2020 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2021
2022
2023 /* SAS IO Unit Page 1 */
2024
2025 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
2026 {
2027     U8          Port;                       /* 0x00 */
2028     U8          PortFlags;                  /* 0x01 */
2029     U8          PhyFlags;                   /* 0x02 */
2030     U8          MaxMinLinkRate;             /* 0x03 */
2031     U32         ControllerPhyDeviceInfo;    /* 0x04 */
2032     U16         MaxTargetPortConnectTime;   /* 0x08 */
2033     U16         Reserved1;                  /* 0x0A */
2034 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2035   Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
2036
2037 /*
2038  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2039  * one and check the value returned for NumPhys at runtime.
2040  */
2041 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2042 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2043 #endif
2044
2045 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
2046 {
2047     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2048     U16                                 ControlFlags;                       /* 0x08 */
2049     U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
2050     U16                                 AdditionalControlFlags;             /* 0x0C */
2051     U16                                 SASWideMaxQueueDepth;               /* 0x0E */
2052     U8                                  NumPhys;                            /* 0x10 */
2053     U8                                  SATAMaxQDepth;                      /* 0x11 */
2054     U8                                  ReportDeviceMissingDelay;           /* 0x12 */
2055     U8                                  IODeviceMissingDelay;               /* 0x13 */
2056     MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
2057 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2058   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2059   Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
2060
2061 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2062
2063 /* values for SAS IO Unit Page 1 ControlFlags */
2064 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2065 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2066 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2067 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2068
2069 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2070 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2071 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2072 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2073 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2074
2075 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2076 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2077 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2078 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2079 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2080 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2081 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2082 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2083
2084 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2085 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2086 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2087 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2088 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2089 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2090 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2091 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2092 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2093
2094 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2095 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2096 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2097
2098 /* values for SAS IO Unit Page 1 PortFlags */
2099 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2100
2101 /* values for SAS IO Unit Page 1 PhyFlags */
2102 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2103 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2104
2105 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
2106 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2107 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2108 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2109 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2110 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2111 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2112 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2113 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2114 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2115 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2116
2117 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2118
2119
2120 /* SAS IO Unit Page 4 */
2121
2122 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2123 {
2124     U8          MaxTargetSpinup;            /* 0x00 */
2125     U8          SpinupDelay;                /* 0x01 */
2126     U8          SpinupFlags;                /* 0x02 */
2127     U8          Reserved1;                  /* 0x03 */
2128 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2129   Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2130
2131 /* defines for SAS IO Unit Page 4 SpinupFlags */
2132 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2133
2134
2135 /*
2136  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2137  * one and check the value returned for NumPhys at runtime.
2138  */
2139 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2140 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2141 #endif
2142
2143 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2144 {
2145     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2146     MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
2147     U32                                 Reserved1;                      /* 0x18 */
2148     U32                                 Reserved2;                      /* 0x1C */
2149     U32                                 Reserved3;                      /* 0x20 */
2150     U8                                  BootDeviceWaitTime;             /* 0x24 */
2151     U8                                  Reserved4;                      /* 0x25 */
2152     U16                                 Reserved5;                      /* 0x26 */
2153     U8                                  NumPhys;                        /* 0x28 */
2154     U8                                  PEInitialSpinupDelay;           /* 0x29 */
2155     U8                                  PEReplyDelay;                   /* 0x2A */
2156     U8                                  Flags;                          /* 0x2B */
2157     U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
2158 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2159   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2160   Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2161
2162 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2163
2164 /* defines for Flags field */
2165 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2166
2167 /* defines for PHY field */
2168 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2169
2170
2171 /* SAS IO Unit Page 5 */
2172
2173 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2174 {
2175     U8          ControlFlags;               /* 0x00 */
2176     U8          PortWidthModGroup;          /* 0x01 */
2177     U16         InactivityTimerExponent;    /* 0x02 */
2178     U8          SATAPartialTimeout;         /* 0x04 */
2179     U8          Reserved2;                  /* 0x05 */
2180     U8          SATASlumberTimeout;         /* 0x06 */
2181     U8          Reserved3;                  /* 0x07 */
2182     U8          SASPartialTimeout;          /* 0x08 */
2183     U8          Reserved4;                  /* 0x09 */
2184     U8          SASSlumberTimeout;          /* 0x0A */
2185     U8          Reserved5;                  /* 0x0B */
2186 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2187   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2188   Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2189
2190 /* defines for ControlFlags field */
2191 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2192 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2193 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2194 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2195
2196 /* defines for PortWidthModeGroup field */
2197 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2198
2199 /* defines for InactivityTimerExponent field */
2200 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2201 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2202 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2203 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2204 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2205 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2206 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2207 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2208
2209 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2210 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2211 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2212 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2213 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2214 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2215 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2216 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2217
2218 /*
2219  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2220  * one and check the value returned for NumPhys at runtime.
2221  */
2222 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2223 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2224 #endif
2225
2226 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2227 {
2228     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2229     U8                                  NumPhys;                            /* 0x08 */
2230     U8                                  Reserved1;                          /* 0x09 */
2231     U16                                 Reserved2;                          /* 0x0A */
2232     U32                                 Reserved3;                          /* 0x0C */
2233     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
2234 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2235   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2236   Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2237
2238 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2239
2240
2241 /* SAS IO Unit Page 6 */
2242
2243 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2244 {
2245     U8          CurrentStatus;              /* 0x00 */
2246     U8          CurrentModulation;          /* 0x01 */
2247     U8          CurrentUtilization;         /* 0x02 */
2248     U8          Reserved1;                  /* 0x03 */
2249     U32         Reserved2;                  /* 0x04 */
2250 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2251   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2252   Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2253   MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2254
2255 /* defines for CurrentStatus field */
2256 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2257 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2258 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2259 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2260 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2261 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2262 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2263 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2264
2265 /* defines for CurrentModulation field */
2266 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2267 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2268 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2269 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2270
2271 /*
2272  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2273  * one and check the value returned for NumGroups at runtime.
2274  */
2275 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2276 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2277 #endif
2278
2279 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2280 {
2281     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2282     U32                                 Reserved1;                  /* 0x08 */
2283     U32                                 Reserved2;                  /* 0x0C */
2284     U8                                  NumGroups;                  /* 0x10 */
2285     U8                                  Reserved3;                  /* 0x11 */
2286     U16                                 Reserved4;                  /* 0x12 */
2287     MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2288         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2289 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2290   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2291   Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2292
2293 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2294
2295
2296 /* SAS IO Unit Page 7 */
2297
2298 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2299 {
2300     U8          Flags;                      /* 0x00 */
2301     U8          Reserved1;                  /* 0x01 */
2302     U16         Reserved2;                  /* 0x02 */
2303     U8          Threshold75Pct;             /* 0x04 */
2304     U8          Threshold50Pct;             /* 0x05 */
2305     U8          Threshold25Pct;             /* 0x06 */
2306     U8          Reserved3;                  /* 0x07 */
2307 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2308   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2309   Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2310   MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2311
2312 /* defines for Flags field */
2313 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2314
2315
2316 /*
2317  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2318  * one and check the value returned for NumGroups at runtime.
2319  */
2320 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2321 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2322 #endif
2323
2324 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2325 {
2326     MPI2_CONFIG_EXTENDED_PAGE_HEADER            Header;             /* 0x00 */
2327     U8                                          SamplingInterval;   /* 0x08 */
2328     U8                                          WindowLength;       /* 0x09 */
2329     U16                                         Reserved1;          /* 0x0A */
2330     U32                                         Reserved2;          /* 0x0C */
2331     U32                                         Reserved3;          /* 0x10 */
2332     U8                                          NumGroups;          /* 0x14 */
2333     U8                                          Reserved4;          /* 0x15 */
2334     U16                                         Reserved5;          /* 0x16 */
2335     MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2336         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2337 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2338   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2339   Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2340
2341 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2342
2343
2344 /* SAS IO Unit Page 8 */
2345
2346 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2347 {
2348     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2349     U32                                 Reserved1;                      /* 0x08 */
2350     U32                                 PowerManagementCapabilities;    /* 0x0C */
2351     U8                                  TxRxSleepStatus;                /* 0x10 */ /* reserved in MPI 2.0 */
2352     U8                                  Reserved2;                      /* 0x11 */
2353     U16                                 Reserved3;                      /* 0x12 */
2354 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2355   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2356   Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2357
2358 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2359
2360 /* defines for PowerManagementCapabilities field */
2361 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2362 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2363 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2364 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2365 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2366 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2367 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2368 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2369 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2370 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2371
2372 /* defines for TxRxSleepStatus field */
2373 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2374 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2375 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2376 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2377
2378
2379
2380 /* SAS IO Unit Page 16 */
2381
2382 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16
2383 {
2384     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2385     U64                                 TimeStamp;                          /* 0x08 */
2386     U32                                 Reserved1;                          /* 0x10 */
2387     U32                                 Reserved2;                          /* 0x14 */
2388     U32                                 FastPathPendedRequests;             /* 0x18 */
2389     U32                                 FastPathUnPendedRequests;           /* 0x1C */
2390     U32                                 FastPathHostRequestStarts;          /* 0x20 */
2391     U32                                 FastPathFirmwareRequestStarts;      /* 0x24 */
2392     U32                                 FastPathHostCompletions;            /* 0x28 */
2393     U32                                 FastPathFirmwareCompletions;        /* 0x2C */
2394     U32                                 NonFastPathRequestStarts;           /* 0x30 */
2395     U32                                 NonFastPathHostCompletions;         /* 0x30 */
2396 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2397   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2398   Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2399
2400 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2401
2402
2403 /****************************************************************************
2404 *   SAS Expander Config Pages
2405 ****************************************************************************/
2406
2407 /* SAS Expander Page 0 */
2408
2409 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2410 {
2411     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2412     U8                                  PhysicalPort;               /* 0x08 */
2413     U8                                  ReportGenLength;            /* 0x09 */
2414     U16                                 EnclosureHandle;            /* 0x0A */
2415     U64                                 SASAddress;                 /* 0x0C */
2416     U32                                 DiscoveryStatus;            /* 0x14 */
2417     U16                                 DevHandle;                  /* 0x18 */
2418     U16                                 ParentDevHandle;            /* 0x1A */
2419     U16                                 ExpanderChangeCount;        /* 0x1C */
2420     U16                                 ExpanderRouteIndexes;       /* 0x1E */
2421     U8                                  NumPhys;                    /* 0x20 */
2422     U8                                  SASLevel;                   /* 0x21 */
2423     U16                                 Flags;                      /* 0x22 */
2424     U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
2425     U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
2426     U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
2427     U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
2428     U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
2429     U16                                 ZoneLockInactivityLimit;    /* 0x34 */
2430     U16                                 Reserved1;                  /* 0x36 */
2431     U8                                  TimeToReducedFunc;          /* 0x38 */
2432     U8                                  InitialTimeToReducedFunc;   /* 0x39 */
2433     U8                                  MaxReducedFuncTime;         /* 0x3A */
2434     U8                                  Reserved2;                  /* 0x3B */
2435 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2436   Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2437
2438 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2439
2440 /* values for SAS Expander Page 0 DiscoveryStatus field */
2441 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2442 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2443 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2444 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2445 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2446 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2447 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2448 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2449 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2450 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2451 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2452 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2453 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2454 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2455 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2456 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2457 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2458 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2459 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2460 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2461
2462 /* values for SAS Expander Page 0 Flags field */
2463 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2464 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2465 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2466 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2467 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2468 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2469 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2470 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2471 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2472 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2473 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2474
2475
2476 /* SAS Expander Page 1 */
2477
2478 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2479 {
2480     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2481     U8                                  PhysicalPort;               /* 0x08 */
2482     U8                                  Reserved1;                  /* 0x09 */
2483     U16                                 Reserved2;                  /* 0x0A */
2484     U8                                  NumPhys;                    /* 0x0C */
2485     U8                                  Phy;                        /* 0x0D */
2486     U16                                 NumTableEntriesProgrammed;  /* 0x0E */
2487     U8                                  ProgrammedLinkRate;         /* 0x10 */
2488     U8                                  HwLinkRate;                 /* 0x11 */
2489     U16                                 AttachedDevHandle;          /* 0x12 */
2490     U32                                 PhyInfo;                    /* 0x14 */
2491     U32                                 AttachedDeviceInfo;         /* 0x18 */
2492     U16                                 ExpanderDevHandle;          /* 0x1C */
2493     U8                                  ChangeCount;                /* 0x1E */
2494     U8                                  NegotiatedLinkRate;         /* 0x1F */
2495     U8                                  PhyIdentifier;              /* 0x20 */
2496     U8                                  AttachedPhyIdentifier;      /* 0x21 */
2497     U8                                  Reserved3;                  /* 0x22 */
2498     U8                                  DiscoveryInfo;              /* 0x23 */
2499     U32                                 AttachedPhyInfo;            /* 0x24 */
2500     U8                                  ZoneGroup;                  /* 0x28 */
2501     U8                                  SelfConfigStatus;           /* 0x29 */
2502     U16                                 Reserved4;                  /* 0x2A */
2503 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2504   Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2505
2506 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2507
2508 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2509
2510 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2511
2512 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2513
2514 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2515
2516 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2517
2518 /* values for SAS Expander Page 1 DiscoveryInfo field */
2519 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2520 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2521 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2522
2523 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2524
2525
2526 /****************************************************************************
2527 *   SAS Device Config Pages
2528 ****************************************************************************/
2529
2530 /* SAS Device Page 0 */
2531
2532 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2533 {
2534     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2535     U16                                 Slot;                   /* 0x08 */
2536     U16                                 EnclosureHandle;        /* 0x0A */
2537     U64                                 SASAddress;             /* 0x0C */
2538     U16                                 ParentDevHandle;        /* 0x14 */
2539     U8                                  PhyNum;                 /* 0x16 */
2540     U8                                  AccessStatus;           /* 0x17 */
2541     U16                                 DevHandle;              /* 0x18 */
2542     U8                                  AttachedPhyIdentifier;  /* 0x1A */
2543     U8                                  ZoneGroup;              /* 0x1B */
2544     U32                                 DeviceInfo;             /* 0x1C */
2545     U16                                 Flags;                  /* 0x20 */
2546     U8                                  PhysicalPort;           /* 0x22 */
2547     U8                                  MaxPortConnections;     /* 0x23 */
2548     U64                                 DeviceName;             /* 0x24 */
2549     U8                                  PortGroups;             /* 0x2C */
2550     U8                                  DmaGroup;               /* 0x2D */
2551     U8                                  ControlGroup;           /* 0x2E */
2552     U8                                  EnclosureLevel;         /* 0x2F */
2553     U8                                  ConnectorName[4];       /* 0x30 */
2554     U32                                 Reserved3;              /* 0x34 */
2555 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2556   Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2557
2558 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2559
2560 /* values for SAS Device Page 0 AccessStatus field */
2561 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2562 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2563 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2564 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2565 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2566 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2567 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2568 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2569 /* specific values for SATA Init failures */
2570 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2571 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2572 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2573 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2574 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2575 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2576 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2577 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2578 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2579 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2580 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2581
2582 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2583
2584 /* values for SAS Device Page 0 Flags field */
2585 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2586 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2587 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2588 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2589 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2590 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2591 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2592 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2593 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2594 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2595 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2596 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2597 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2598 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2599 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2600
2601
2602 /* SAS Device Page 1 */
2603
2604 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2605 {
2606     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2607     U32                                 Reserved1;              /* 0x08 */
2608     U64                                 SASAddress;             /* 0x0C */
2609     U32                                 Reserved2;              /* 0x14 */
2610     U16                                 DevHandle;              /* 0x18 */
2611     U16                                 Reserved3;              /* 0x1A */
2612     U8                                  InitialRegDeviceFIS[20];/* 0x1C */
2613 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2614   Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2615
2616 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2617
2618
2619 /****************************************************************************
2620 *   SAS PHY Config Pages
2621 ****************************************************************************/
2622
2623 /* SAS PHY Page 0 */
2624
2625 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2626 {
2627     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2628     U16                                 OwnerDevHandle;         /* 0x08 */
2629     U16                                 Reserved1;              /* 0x0A */
2630     U16                                 AttachedDevHandle;      /* 0x0C */
2631     U8                                  AttachedPhyIdentifier;  /* 0x0E */
2632     U8                                  Reserved2;              /* 0x0F */
2633     U32                                 AttachedPhyInfo;        /* 0x10 */
2634     U8                                  ProgrammedLinkRate;     /* 0x14 */
2635     U8                                  HwLinkRate;             /* 0x15 */
2636     U8                                  ChangeCount;            /* 0x16 */
2637     U8                                  Flags;                  /* 0x17 */
2638     U32                                 PhyInfo;                /* 0x18 */
2639     U8                                  NegotiatedLinkRate;     /* 0x1C */
2640     U8                                  Reserved3;              /* 0x1D */
2641     U16                                 Reserved4;              /* 0x1E */
2642 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2643   Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2644
2645 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2646
2647 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2648
2649 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2650
2651 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2652
2653 /* values for SAS PHY Page 0 Flags field */
2654 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2655
2656 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2657
2658 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2659
2660
2661 /* SAS PHY Page 1 */
2662
2663 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2664 {
2665     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2666     U32                                 Reserved1;                  /* 0x08 */
2667     U32                                 InvalidDwordCount;          /* 0x0C */
2668     U32                                 RunningDisparityErrorCount; /* 0x10 */
2669     U32                                 LossDwordSynchCount;        /* 0x14 */
2670     U32                                 PhyResetProblemCount;       /* 0x18 */
2671 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2672   Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2673
2674 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2675
2676
2677 /* SAS PHY Page 2 */
2678
2679 typedef struct _MPI2_SASPHY2_PHY_EVENT
2680 {
2681     U8          PhyEventCode;       /* 0x00 */
2682     U8          Reserved1;          /* 0x01 */
2683     U16         Reserved2;          /* 0x02 */
2684     U32         PhyEventInfo;       /* 0x04 */
2685 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2686   Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2687
2688 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2689
2690
2691 /*
2692  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2693  * one and check the value returned for NumPhyEvents at runtime.
2694  */
2695 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2696 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2697 #endif
2698
2699 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2700 {
2701     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2702     U32                                 Reserved1;                  /* 0x08 */
2703     U8                                  NumPhyEvents;               /* 0x0C */
2704     U8                                  Reserved2;                  /* 0x0D */
2705     U16                                 Reserved3;                  /* 0x0E */
2706     MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2707 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2708   Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2709
2710 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2711
2712
2713 /* SAS PHY Page 3 */
2714
2715 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2716 {
2717     U8          PhyEventCode;       /* 0x00 */
2718     U8          Reserved1;          /* 0x01 */
2719     U16         Reserved2;          /* 0x02 */
2720     U8          CounterType;        /* 0x04 */
2721     U8          ThresholdWindow;    /* 0x05 */
2722     U8          TimeUnits;          /* 0x06 */
2723     U8          Reserved3;          /* 0x07 */
2724     U32         EventThreshold;     /* 0x08 */
2725     U16         ThresholdFlags;     /* 0x0C */
2726     U16         Reserved4;          /* 0x0E */
2727 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2728   Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2729
2730 /* values for PhyEventCode field */
2731 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2732 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2733 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2734 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2735 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2736 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2737 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2738 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2739 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2740 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2741 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2742 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2743 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2744 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2745 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2746 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2747 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2748 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2749 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2750 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2751 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2752 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2753 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2754 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2755 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2756 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2757 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2758 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2759 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2760 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2761 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2762 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2763 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2764 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2765 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2766 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2767 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2768
2769 /* values for the CounterType field */
2770 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2771 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2772 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2773
2774 /* values for the TimeUnits field */
2775 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
2776 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
2777 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
2778 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
2779
2780 /* values for the ThresholdFlags field */
2781 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
2782 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
2783
2784 /*
2785  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2786  * one and check the value returned for NumPhyEvents at runtime.
2787  */
2788 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2789 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
2790 #endif
2791
2792 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
2793 {
2794     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2795     U32                                 Reserved1;                  /* 0x08 */
2796     U8                                  NumPhyEvents;               /* 0x0C */
2797     U8                                  Reserved2;                  /* 0x0D */
2798     U16                                 Reserved3;                  /* 0x0E */
2799     MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2800 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2801   Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2802
2803 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
2804
2805
2806 /* SAS PHY Page 4 */
2807
2808 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
2809 {
2810     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2811     U16                                 Reserved1;                  /* 0x08 */
2812     U8                                  Reserved2;                  /* 0x0A */
2813     U8                                  Flags;                      /* 0x0B */
2814     U8                                  InitialFrame[28];           /* 0x0C */
2815 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2816   Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2817
2818 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
2819
2820 /* values for the Flags field */
2821 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
2822 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
2823
2824
2825
2826
2827 /****************************************************************************
2828 *   SAS Port Config Pages
2829 ****************************************************************************/
2830
2831 /* SAS Port Page 0 */
2832
2833 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2834 {
2835     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2836     U8                                  PortNumber;                 /* 0x08 */
2837     U8                                  PhysicalPort;               /* 0x09 */
2838     U8                                  PortWidth;                  /* 0x0A */
2839     U8                                  PhysicalPortWidth;          /* 0x0B */
2840     U8                                  ZoneGroup;                  /* 0x0C */
2841     U8                                  Reserved1;                  /* 0x0D */
2842     U16                                 Reserved2;                  /* 0x0E */
2843     U64                                 SASAddress;                 /* 0x10 */
2844     U32                                 DeviceInfo;                 /* 0x18 */
2845     U32                                 Reserved3;                  /* 0x1C */
2846     U32                                 Reserved4;                  /* 0x20 */
2847 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2848   Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2849
2850 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
2851
2852 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2853
2854
2855 /****************************************************************************
2856 *   SAS Enclosure Config Pages
2857 ****************************************************************************/
2858
2859 /* SAS Enclosure Page 0 */
2860
2861 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2862 {
2863     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2864     U32                                 Reserved1;                  /* 0x08 */
2865     U64                                 EnclosureLogicalID;         /* 0x0C */
2866     U16                                 Flags;                      /* 0x14 */
2867     U16                                 EnclosureHandle;            /* 0x16 */
2868     U16                                 NumSlots;                   /* 0x18 */
2869     U16                                 StartSlot;                  /* 0x1A */
2870     U8                                  Reserved2;                  /* 0x1C */
2871     U8                                  EnclosureLevel;             /* 0x1D */
2872     U16                                 SEPDevHandle;               /* 0x1E */
2873     U32                                 Reserved3;                  /* 0x20 */
2874     U32                                 Reserved4;                  /* 0x24 */
2875 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2876   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2877   Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2878
2879 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
2880
2881 /* values for SAS Enclosure Page 0 Flags field */
2882 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
2883 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
2884 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
2885 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
2886 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
2887 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
2888 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
2889 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
2890
2891
2892 /****************************************************************************
2893 *   Log Config Page
2894 ****************************************************************************/
2895
2896 /* Log Page 0 */
2897
2898 /*
2899  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2900  * one and check the value returned for NumLogEntries at runtime.
2901  */
2902 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2903 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
2904 #endif
2905
2906 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
2907
2908 typedef struct _MPI2_LOG_0_ENTRY
2909 {
2910     U64         TimeStamp;                          /* 0x00 */
2911     U32         Reserved1;                          /* 0x08 */
2912     U16         LogSequence;                        /* 0x0C */
2913     U16         LogEntryQualifier;                  /* 0x0E */
2914     U8          VP_ID;                              /* 0x10 */
2915     U8          VF_ID;                              /* 0x11 */
2916     U16         Reserved2;                          /* 0x12 */
2917     U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2918 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2919   Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2920
2921 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2922 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
2923 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
2924 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
2925 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
2926 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
2927
2928 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2929 {
2930     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2931     U32                                 Reserved1;                  /* 0x08 */
2932     U32                                 Reserved2;                  /* 0x0C */
2933     U16                                 NumLogEntries;              /* 0x10 */
2934     U16                                 Reserved3;                  /* 0x12 */
2935     MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2936 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2937   Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2938
2939 #define MPI2_LOG_0_PAGEVERSION              (0x02)
2940
2941
2942 /****************************************************************************
2943 *   RAID Config Page
2944 ****************************************************************************/
2945
2946 /* RAID Page 0 */
2947
2948 /*
2949  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2950  * one and check the value returned for NumElements at runtime.
2951  */
2952 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2953 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
2954 #endif
2955
2956 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2957 {
2958     U16                     ElementFlags;               /* 0x00 */
2959     U16                     VolDevHandle;               /* 0x02 */
2960     U8                      HotSparePool;               /* 0x04 */
2961     U8                      PhysDiskNum;                /* 0x05 */
2962     U16                     PhysDiskDevHandle;          /* 0x06 */
2963 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2964   MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2965   Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2966
2967 /* values for the ElementFlags field */
2968 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
2969 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
2970 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
2971 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
2972 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
2973
2974
2975 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2976 {
2977     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2978     U8                                  NumHotSpares;               /* 0x08 */
2979     U8                                  NumPhysDisks;               /* 0x09 */
2980     U8                                  NumVolumes;                 /* 0x0A */
2981     U8                                  ConfigNum;                  /* 0x0B */
2982     U32                                 Flags;                      /* 0x0C */
2983     U8                                  ConfigGUID[24];             /* 0x10 */
2984     U32                                 Reserved1;                  /* 0x28 */
2985     U8                                  NumElements;                /* 0x2C */
2986     U8                                  Reserved2;                  /* 0x2D */
2987     U16                                 Reserved3;                  /* 0x2E */
2988     MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2989 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2990   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2991   Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2992
2993 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
2994
2995 /* values for RAID Configuration Page 0 Flags field */
2996 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
2997
2998
2999 /****************************************************************************
3000 *   Driver Persistent Mapping Config Pages
3001 ****************************************************************************/
3002
3003 /* Driver Persistent Mapping Page 0 */
3004
3005 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
3006 {
3007     U64                                 PhysicalIdentifier;         /* 0x00 */
3008     U16                                 MappingInformation;         /* 0x08 */
3009     U16                                 DeviceIndex;                /* 0x0A */
3010     U32                                 PhysicalBitsMapping;        /* 0x0C */
3011     U32                                 Reserved1;                  /* 0x10 */
3012 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3013   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3014   Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
3015
3016 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
3017 {
3018     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3019     MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
3020 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3021   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3022   Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
3023
3024 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3025
3026 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
3027 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3028 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3029 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3030
3031
3032 /****************************************************************************
3033 *   Ethernet Config Pages
3034 ****************************************************************************/
3035
3036 /* Ethernet Page 0 */
3037
3038 /* IP address (union of IPv4 and IPv6) */
3039 typedef union _MPI2_ETHERNET_IP_ADDR
3040 {
3041     U32     IPv4Addr;
3042     U32     IPv6Addr[4];
3043 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
3044   Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
3045
3046 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3047
3048 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
3049 {
3050     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3051     U8                                  NumInterfaces;          /* 0x08 */
3052     U8                                  Reserved0;              /* 0x09 */
3053     U16                                 Reserved1;              /* 0x0A */
3054     U32                                 Status;                 /* 0x0C */
3055     U8                                  MediaState;             /* 0x10 */
3056     U8                                  Reserved2;              /* 0x11 */
3057     U16                                 Reserved3;              /* 0x12 */
3058     U8                                  MacAddress[6];          /* 0x14 */
3059     U8                                  Reserved4;              /* 0x1A */
3060     U8                                  Reserved5;              /* 0x1B */
3061     MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
3062     MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
3063     MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
3064     MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
3065     MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
3066     MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
3067     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3068 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3069   Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
3070
3071 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3072
3073 /* values for Ethernet Page 0 Status field */
3074 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3075 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3076 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3077 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3078 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3079 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3080 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3081 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3082 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3083 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3084 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3085 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3086
3087 /* values for Ethernet Page 0 MediaState field */
3088 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3089 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3090 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3091
3092 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3093 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3094 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3095 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3096 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3097
3098
3099 /* Ethernet Page 1 */
3100
3101 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
3102 {
3103     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3104     U32                                 Reserved0;              /* 0x08 */
3105     U32                                 Flags;                  /* 0x0C */
3106     U8                                  MediaState;             /* 0x10 */
3107     U8                                  Reserved1;              /* 0x11 */
3108     U16                                 Reserved2;              /* 0x12 */
3109     U8                                  MacAddress[6];          /* 0x14 */
3110     U8                                  Reserved3;              /* 0x1A */
3111     U8                                  Reserved4;              /* 0x1B */
3112     MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
3113     MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
3114     MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
3115     MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
3116     MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
3117     U32                                 Reserved5;              /* 0x6C */
3118     U32                                 Reserved6;              /* 0x70 */
3119     U32                                 Reserved7;              /* 0x74 */
3120     U32                                 Reserved8;              /* 0x78 */
3121     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3122 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3123   Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3124
3125 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3126
3127 /* values for Ethernet Page 1 Flags field */
3128 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3129 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3130 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3131 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3132 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3133 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3134 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3135 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3136 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3137
3138 /* values for Ethernet Page 1 MediaState field */
3139 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3140 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3141 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3142
3143 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3144 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3145 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3146 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3147 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3148
3149
3150 /****************************************************************************
3151 *   Extended Manufacturing Config Pages
3152 ****************************************************************************/
3153
3154 /*
3155  * Generic structure to use for product-specific extended manufacturing pages
3156  * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3157  * Page 60).
3158  */
3159
3160 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
3161 {
3162     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3163     U32                                 ProductSpecificInfo;    /* 0x08 */
3164 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3165   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3166   Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3167
3168 /* PageVersion should be provided by product-specific code */
3169
3170 #endif
3171