sys/dev/mpr/mpi/mpi2_ioc.h

   1 /*-
   2  * Copyright (c) 2012-2015 LSI Corp.
   3  * Copyright (c) 2013-2015 Avago Technologies
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 /*
  36  *  Copyright (c) 2000-2015 LSI Corporation.
  37  *  Copyright (c) 2013-2015 Avago Technologies
  38  *
  39  *
  40  *           Name:  mpi2_ioc.h
  41  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
  42  *  Creation Date:  October 11, 2006
  43  *
  44  *  mpi2_ioc.h Version:  02.00.24
  45  *
  46  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  47  *        prefix are for use only on MPI v2.5 products, and must not be used
  48  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
  49  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  50  *
  51  *  Version History
  52  *  ---------------
  53  *
  54  *  Date      Version   Description
  55  *  --------  --------  ------------------------------------------------------
  56  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  57  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  58  *                      MaxTargets.
  59  *                      Added TotalImageSize field to FWDownload Request.
  60  *                      Added reserved words to FWUpload Request.
  61  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  62  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  63  *                      request and replaced it with
  64  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  65  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  66  *                      reply with MaxReplyDescriptorPostQueueDepth.
  67  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  68  *                      depth for the Reply Descriptor Post Queue.
  69  *                      Added SASAddress field to Initiator Device Table
  70  *                      Overflow Event data.
  71  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  72  *                      for SAS Initiator Device Status Change Event data.
  73  *                      Modified Reason Code defines for SAS Topology Change
  74  *                      List Event data, including adding a bit for PHY Vacant
  75  *                      status, and adding a mask for the Reason Code.
  76  *                      Added define for
  77  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  78  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  79  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  80  *                      the IOCFacts Reply.
  81  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  82  *                      Moved MPI2_VERSION_UNION to mpi2.h.
  83  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  84  *                      instead of enables, and added SASBroadcastPrimitiveMasks
  85  *                      field.
  86  *                      Added Log Entry Added Event and related structure.
  87  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  88  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  89  *                      Added MaxVolumes and MaxPersistentEntries fields to
  90  *                      IOCFacts reply.
  91  *                      Added ProtocalFlags and IOCCapabilities fields to
  92  *                      MPI2_FW_IMAGE_HEADER.
  93  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  94  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  95  *                      a U16 (from a U32).
  96  *                      Removed extra 's' from EventMasks name.
  97  *  06-27-08  02.00.08  Fixed an offset in a comment.
  98  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  99  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
 100  *                      renamed MinReplyFrameSize to ReplyFrameSize.
 101  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
 102  *                      Added two new RAIDOperation values for Integrated RAID
 103  *                      Operations Status Event data.
 104  *                      Added four new IR Configuration Change List Event data
 105  *                      ReasonCode values.
 106  *                      Added two new ReasonCode defines for SAS Device Status
 107  *                      Change Event data.
 108  *                      Added three new DiscoveryStatus bits for the SAS
 109  *                      Discovery event data.
 110  *                      Added Multiplexing Status Change bit to the PhyStatus
 111  *                      field of the SAS Topology Change List event data.
 112  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
 113  *                      BootFlags are now product-specific.
 114  *                      Added defines for the indivdual signature bytes
 115  *                      for MPI2_INIT_IMAGE_FOOTER.
 116  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
 117  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
 118  *                      define.
 119  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
 120  *                      define.
 121  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
 122  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
 123  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
 124  *                      Added two new reason codes for SAS Device Status Change
 125  *                      Event.
 126  *                      Added new event: SAS PHY Counter.
 127  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
 128  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
 129  *                      Added new product id family for 2208.
 130  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
 131  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
 132  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
 133  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
 134  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
 135  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
 136  *                      Added Host Based Discovery Phy Event data.
 137  *                      Added defines for ProductID Product field
 138  *                      (MPI2_FW_HEADER_PID_).
 139  *                      Modified values for SAS ProductID Family
 140  *                      (MPI2_FW_HEADER_PID_FAMILY_).
 141  *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 142  *                      Added PowerManagementControl Request structures and
 143  *                      defines.
 144  *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 145  *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 146  *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 147  *  02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 148  *                      SASNotifyPrimitiveMasks field to
 149  *                      MPI2_EVENT_NOTIFICATION_REQUEST.
 150  *                      Added Temperature Threshold Event.
 151  *                      Added Host Message Event.
 152  *                      Added Send Host Message request and reply.
 153  *  05-25-11  02.00.18  For Extended Image Header, added
 154  *                      MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 155  *                      MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 156  *                      Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 157  *  08-24-11  02.00.19  Added PhysicalPort field to
 158  *                      MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 159  *                      Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 160  *  11-18-11  02.00.20  Incorporating additions for MPI v2.5.
 161  *  03-29-12  02.00.21  Added a product specific range to event values.
 162  *  07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 163  *                      Added ElapsedSeconds field to
 164  *                      MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 165  *  08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
 166  *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
 167  *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
 168  *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
 169  *                      Added Encrypted Hash Extended Image.
 170  *  12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
 171  *  --------------------------------------------------------------------------
 172  */
 173
 174 #ifndef MPI2_IOC_H
 175 #define MPI2_IOC_H
 176
 177 /*****************************************************************************
 178 *
 179 *               IOC Messages
 180 *
 181 *****************************************************************************/
 182
 183 /****************************************************************************
 184 *  IOCInit message
 185 ****************************************************************************/
 186
 187 /* IOCInit Request message */
 188 typedef struct _MPI2_IOC_INIT_REQUEST
 189 {
 190     U8                      WhoInit;                        /* 0x00 */
 191     U8                      Reserved1;                      /* 0x01 */
 192     U8                      ChainOffset;                    /* 0x02 */
 193     U8                      Function;                       /* 0x03 */
 194     U16                     Reserved2;                      /* 0x04 */
 195     U8                      Reserved3;                      /* 0x06 */
 196     U8                      MsgFlags;                       /* 0x07 */
 197     U8                      VP_ID;                          /* 0x08 */
 198     U8                      VF_ID;                          /* 0x09 */
 199     U16                     Reserved4;                      /* 0x0A */
 200     U16                     MsgVersion;                     /* 0x0C */
 201     U16                     HeaderVersion;                  /* 0x0E */
 202     U32                     Reserved5;                      /* 0x10 */
 203     U16                     Reserved6;                      /* 0x14 */
 204     U8                      Reserved7;                      /* 0x16 */
 205     U8                      HostMSIxVectors;                /* 0x17 */
 206     U16                     Reserved8;                      /* 0x18 */
 207     U16                     SystemRequestFrameSize;         /* 0x1A */
 208     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 209     U16                     ReplyFreeQueueDepth;            /* 0x1E */
 210     U32                     SenseBufferAddressHigh;         /* 0x20 */
 211     U32                     SystemReplyAddressHigh;         /* 0x24 */
 212     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 213     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 214     U64                     ReplyFreeQueueAddress;          /* 0x38 */
 215     U64                     TimeStamp;                      /* 0x40 */
 216 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 217   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 218
 219 /* WhoInit values */
 220 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 221 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 222 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 223 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 224 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 225 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 226
 227 /* MsgFlags */
 228 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
 229
 230 /* MsgVersion */
 231 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 232 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 233 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 234 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 235
 236 /* HeaderVersion */
 237 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 238 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 239 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 240 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 241
 242 /* minimum depth for a Reply Descriptor Post Queue */
 243 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 244
 245 /* Reply Descriptor Post Queue Array Entry */
 246 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY
 247 {
 248     U64                 RDPQBaseAddress;                    /* 0x00 */
 249     U32                 Reserved1;                          /* 0x08 */
 250     U32                 Reserved2;                          /* 0x0C */
 251 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 252   MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
 253   Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
 254
 255 /* IOCInit Reply message */
 256 typedef struct _MPI2_IOC_INIT_REPLY
 257 {
 258     U8                      WhoInit;                        /* 0x00 */
 259     U8                      Reserved1;                      /* 0x01 */
 260     U8                      MsgLength;                      /* 0x02 */
 261     U8                      Function;                       /* 0x03 */
 262     U16                     Reserved2;                      /* 0x04 */
 263     U8                      Reserved3;                      /* 0x06 */
 264     U8                      MsgFlags;                       /* 0x07 */
 265     U8                      VP_ID;                          /* 0x08 */
 266     U8                      VF_ID;                          /* 0x09 */
 267     U16                     Reserved4;                      /* 0x0A */
 268     U16                     Reserved5;                      /* 0x0C */
 269     U16                     IOCStatus;                      /* 0x0E */
 270     U32                     IOCLogInfo;                     /* 0x10 */
 271 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 272   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 273
 274
 275 /****************************************************************************
 276 *  IOCFacts message
 277 ****************************************************************************/
 278
 279 /* IOCFacts Request message */
 280 typedef struct _MPI2_IOC_FACTS_REQUEST
 281 {
 282     U16                     Reserved1;                      /* 0x00 */
 283     U8                      ChainOffset;                    /* 0x02 */
 284     U8                      Function;                       /* 0x03 */
 285     U16                     Reserved2;                      /* 0x04 */
 286     U8                      Reserved3;                      /* 0x06 */
 287     U8                      MsgFlags;                       /* 0x07 */
 288     U8                      VP_ID;                          /* 0x08 */
 289     U8                      VF_ID;                          /* 0x09 */
 290     U16                     Reserved4;                      /* 0x0A */
 291 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 292   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 293
 294
 295 /* IOCFacts Reply message */
 296 typedef struct _MPI2_IOC_FACTS_REPLY
 297 {
 298     U16                     MsgVersion;                     /* 0x00 */
 299     U8                      MsgLength;                      /* 0x02 */
 300     U8                      Function;                       /* 0x03 */
 301     U16                     HeaderVersion;                  /* 0x04 */
 302     U8                      IOCNumber;                      /* 0x06 */
 303     U8                      MsgFlags;                       /* 0x07 */
 304     U8                      VP_ID;                          /* 0x08 */
 305     U8                      VF_ID;                          /* 0x09 */
 306     U16                     Reserved1;                      /* 0x0A */
 307     U16                     IOCExceptions;                  /* 0x0C */
 308     U16                     IOCStatus;                      /* 0x0E */
 309     U32                     IOCLogInfo;                     /* 0x10 */
 310     U8                      MaxChainDepth;                  /* 0x14 */
 311     U8                      WhoInit;                        /* 0x15 */
 312     U8                      NumberOfPorts;                  /* 0x16 */
 313     U8                      MaxMSIxVectors;                 /* 0x17 */
 314     U16                     RequestCredit;                  /* 0x18 */
 315     U16                     ProductID;                      /* 0x1A */
 316     U32                     IOCCapabilities;                /* 0x1C */
 317     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 318     U16                     IOCRequestFrameSize;            /* 0x24 */
 319     U16                     IOCMaxChainSegmentSize;         /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */
 320     U16                     MaxInitiators;                  /* 0x28 */
 321     U16                     MaxTargets;                     /* 0x2A */
 322     U16                     MaxSasExpanders;                /* 0x2C */
 323     U16                     MaxEnclosures;                  /* 0x2E */
 324     U16                     ProtocolFlags;                  /* 0x30 */
 325     U16                     HighPriorityCredit;             /* 0x32 */
 326     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 327     U8                      ReplyFrameSize;                 /* 0x36 */
 328     U8                      MaxVolumes;                     /* 0x37 */
 329     U16                     MaxDevHandle;                   /* 0x38 */
 330     U16                     MaxPersistentEntries;           /* 0x3A */
 331     U16                     MinDevHandle;                   /* 0x3C */
 332     U16                     Reserved4;                      /* 0x3E */
 333 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 334   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 335
 336 /* MsgVersion */
 337 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 338 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 339 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 340 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 341
 342 /* HeaderVersion */
 343 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 344 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 345 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 346 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 347
 348 /* IOCExceptions */
 349 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 350 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 351
 352 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 353 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 354 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 355 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 356 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 357
 358 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 359 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 360 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 361 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 362 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 363
 364 /* defines for WhoInit field are after the IOCInit Request */
 365
 366 /* ProductID field uses MPI2_FW_HEADER_PID_ */
 367
 368 /* IOCCapabilities */
 369 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
 370 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
 371 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 372 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 373 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 374 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 375 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 376 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 377 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 378 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 379 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 380 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 381 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 382 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 383 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 384
 385 /* ProtocolFlags */
 386 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 387 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 388
 389
 390 /****************************************************************************
 391 *  PortFacts message
 392 ****************************************************************************/
 393
 394 /* PortFacts Request message */
 395 typedef struct _MPI2_PORT_FACTS_REQUEST
 396 {
 397     U16                     Reserved1;                      /* 0x00 */
 398     U8                      ChainOffset;                    /* 0x02 */
 399     U8                      Function;                       /* 0x03 */
 400     U16                     Reserved2;                      /* 0x04 */
 401     U8                      PortNumber;                     /* 0x06 */
 402     U8                      MsgFlags;                       /* 0x07 */
 403     U8                      VP_ID;                          /* 0x08 */
 404     U8                      VF_ID;                          /* 0x09 */
 405     U16                     Reserved3;                      /* 0x0A */
 406 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 407   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 408
 409 /* PortFacts Reply message */
 410 typedef struct _MPI2_PORT_FACTS_REPLY
 411 {
 412     U16                     Reserved1;                      /* 0x00 */
 413     U8                      MsgLength;                      /* 0x02 */
 414     U8                      Function;                       /* 0x03 */
 415     U16                     Reserved2;                      /* 0x04 */
 416     U8                      PortNumber;                     /* 0x06 */
 417     U8                      MsgFlags;                       /* 0x07 */
 418     U8                      VP_ID;                          /* 0x08 */
 419     U8                      VF_ID;                          /* 0x09 */
 420     U16                     Reserved3;                      /* 0x0A */
 421     U16                     Reserved4;                      /* 0x0C */
 422     U16                     IOCStatus;                      /* 0x0E */
 423     U32                     IOCLogInfo;                     /* 0x10 */
 424     U8                      Reserved5;                      /* 0x14 */
 425     U8                      PortType;                       /* 0x15 */
 426     U16                     Reserved6;                      /* 0x16 */
 427     U16                     MaxPostedCmdBuffers;            /* 0x18 */
 428     U16                     Reserved7;                      /* 0x1A */
 429 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 430   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 431
 432 /* PortType values */
 433 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 434 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 435 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 436 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 437 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 438
 439
 440 /****************************************************************************
 441 *  PortEnable message
 442 ****************************************************************************/
 443
 444 /* PortEnable Request message */
 445 typedef struct _MPI2_PORT_ENABLE_REQUEST
 446 {
 447     U16                     Reserved1;                      /* 0x00 */
 448     U8                      ChainOffset;                    /* 0x02 */
 449     U8                      Function;                       /* 0x03 */
 450     U8                      Reserved2;                      /* 0x04 */
 451     U8                      PortFlags;                      /* 0x05 */
 452     U8                      Reserved3;                      /* 0x06 */
 453     U8                      MsgFlags;                       /* 0x07 */
 454     U8                      VP_ID;                          /* 0x08 */
 455     U8                      VF_ID;                          /* 0x09 */
 456     U16                     Reserved4;                      /* 0x0A */
 457 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 458   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 459
 460
 461 /* PortEnable Reply message */
 462 typedef struct _MPI2_PORT_ENABLE_REPLY
 463 {
 464     U16                     Reserved1;                      /* 0x00 */
 465     U8                      MsgLength;                      /* 0x02 */
 466     U8                      Function;                       /* 0x03 */
 467     U8                      Reserved2;                      /* 0x04 */
 468     U8                      PortFlags;                      /* 0x05 */
 469     U8                      Reserved3;                      /* 0x06 */
 470     U8                      MsgFlags;                       /* 0x07 */
 471     U8                      VP_ID;                          /* 0x08 */
 472     U8                      VF_ID;                          /* 0x09 */
 473     U16                     Reserved4;                      /* 0x0A */
 474     U16                     Reserved5;                      /* 0x0C */
 475     U16                     IOCStatus;                      /* 0x0E */
 476     U32                     IOCLogInfo;                     /* 0x10 */
 477 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 478   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 479
 480
 481 /****************************************************************************
 482 *  EventNotification message
 483 ****************************************************************************/
 484
 485 /* EventNotification Request message */
 486 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 487
 488 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 489 {
 490     U16                     Reserved1;                      /* 0x00 */
 491     U8                      ChainOffset;                    /* 0x02 */
 492     U8                      Function;                       /* 0x03 */
 493     U16                     Reserved2;                      /* 0x04 */
 494     U8                      Reserved3;                      /* 0x06 */
 495     U8                      MsgFlags;                       /* 0x07 */
 496     U8                      VP_ID;                          /* 0x08 */
 497     U8                      VF_ID;                          /* 0x09 */
 498     U16                     Reserved4;                      /* 0x0A */
 499     U32                     Reserved5;                      /* 0x0C */
 500     U32                     Reserved6;                      /* 0x10 */
 501     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 502     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 503     U16                     SASNotifyPrimitiveMasks;        /* 0x26 */
 504     U32                     Reserved8;                      /* 0x28 */
 505 } MPI2_EVENT_NOTIFICATION_REQUEST,
 506   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 507   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 508
 509
 510 /* EventNotification Reply message */
 511 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 512 {
 513     U16                     EventDataLength;                /* 0x00 */
 514     U8                      MsgLength;                      /* 0x02 */
 515     U8                      Function;                       /* 0x03 */
 516     U16                     Reserved1;                      /* 0x04 */
 517     U8                      AckRequired;                    /* 0x06 */
 518     U8                      MsgFlags;                       /* 0x07 */
 519     U8                      VP_ID;                          /* 0x08 */
 520     U8                      VF_ID;                          /* 0x09 */
 521     U16                     Reserved2;                      /* 0x0A */
 522     U16                     Reserved3;                      /* 0x0C */
 523     U16                     IOCStatus;                      /* 0x0E */
 524     U32                     IOCLogInfo;                     /* 0x10 */
 525     U16                     Event;                          /* 0x14 */
 526     U16                     Reserved4;                      /* 0x16 */
 527     U32                     EventContext;                   /* 0x18 */
 528     U32                     EventData[1];                   /* 0x1C */
 529 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 530   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 531
 532 /* AckRequired */
 533 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 534 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 535
 536 /* Event */
 537 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 538 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 539 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 540 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 541 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
 542 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 543 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 544 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 545 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 546 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 547 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 548 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 549 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 550 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 551 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 552 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 553 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 554 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 555 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 556 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 557 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 558 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 559 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 560 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 561 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
 562 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 563 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 564
 565
 566 /* Log Entry Added Event data */
 567
 568 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 569 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 570
 571 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 572 {
 573     U64         TimeStamp;                          /* 0x00 */
 574     U32         Reserved1;                          /* 0x08 */
 575     U16         LogSequence;                        /* 0x0C */
 576     U16         LogEntryQualifier;                  /* 0x0E */
 577     U8          VP_ID;                              /* 0x10 */
 578     U8          VF_ID;                              /* 0x11 */
 579     U16         Reserved2;                          /* 0x12 */
 580     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 581 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 582   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 583   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 584
 585
 586 /* GPIO Interrupt Event data */
 587
 588 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
 589 {
 590     U8          GPIONum;                            /* 0x00 */
 591     U8          Reserved1;                          /* 0x01 */
 592     U16         Reserved2;                          /* 0x02 */
 593 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 594   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 595   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 596
 597
 598 /* Temperature Threshold Event data */
 599
 600 typedef struct _MPI2_EVENT_DATA_TEMPERATURE
 601 {
 602     U16         Status;                             /* 0x00 */
 603     U8          SensorNum;                          /* 0x02 */
 604     U8          Reserved1;                          /* 0x03 */
 605     U16         CurrentTemperature;                 /* 0x04 */
 606     U16         Reserved2;                          /* 0x06 */
 607     U32         Reserved3;                          /* 0x08 */
 608     U32         Reserved4;                          /* 0x0C */
 609 } MPI2_EVENT_DATA_TEMPERATURE,
 610   MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
 611   Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
 612
 613 /* Temperature Threshold Event data Status bits */
 614 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 615 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 616 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 617 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 618
 619
 620 /* Host Message Event data */
 621
 622 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE
 623 {
 624     U8          SourceVF_ID;                        /* 0x00 */
 625     U8          Reserved1;                          /* 0x01 */
 626     U16         Reserved2;                          /* 0x02 */
 627     U32         Reserved3;                          /* 0x04 */
 628     U32         HostData[1];                        /* 0x08 */
 629 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 630   Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
 631
 632
 633 /* Power Performance Change Event */
 634
 635 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
 636 {
 637     U8          CurrentPowerMode;                   /* 0x00 */
 638     U8          PreviousPowerMode;                  /* 0x01 */
 639     U16         Reserved1;                          /* 0x02 */
 640 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 641   MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 642   Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t;
 643
 644 /* defines for CurrentPowerMode and PreviousPowerMode fields */
 645 #define MPI2_EVENT_PM_INIT_MASK              (0xC0)
 646 #define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
 647 #define MPI2_EVENT_PM_INIT_HOST              (0x40)
 648 #define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
 649 #define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
 650
 651 #define MPI2_EVENT_PM_MODE_MASK              (0x07)
 652 #define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
 653 #define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
 654 #define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
 655 #define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
 656 #define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
 657
 658
 659 /* Hard Reset Received Event data */
 660
 661 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 662 {
 663     U8                      Reserved1;                      /* 0x00 */
 664     U8                      Port;                           /* 0x01 */
 665     U16                     Reserved2;                      /* 0x02 */
 666 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 667   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 668   Mpi2EventDataHardResetReceived_t,
 669   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 670
 671
 672 /* Task Set Full Event data */
 673 /*   this event is obsolete */
 674
 675 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 676 {
 677     U16                     DevHandle;                      /* 0x00 */
 678     U16                     CurrentDepth;                   /* 0x02 */
 679 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 680   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 681
 682
 683 /* SAS Device Status Change Event data */
 684
 685 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 686 {
 687     U16                     TaskTag;                        /* 0x00 */
 688     U8                      ReasonCode;                     /* 0x02 */
 689     U8                      PhysicalPort;                   /* 0x03 */
 690     U8                      ASC;                            /* 0x04 */
 691     U8                      ASCQ;                           /* 0x05 */
 692     U16                     DevHandle;                      /* 0x06 */
 693     U32                     Reserved2;                      /* 0x08 */
 694     U64                     SASAddress;                     /* 0x0C */
 695     U8                      LUN[8];                         /* 0x14 */
 696 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 697   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 698   Mpi2EventDataSasDeviceStatusChange_t,
 699   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 700
 701 /* SAS Device Status Change Event data ReasonCode values */
 702 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 703 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 704 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 705 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 706 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 707 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 708 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 709 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 710 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 711 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 712 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 713 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 714 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 715
 716
 717 /* Integrated RAID Operation Status Event data */
 718
 719 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 720 {
 721     U16                     VolDevHandle;               /* 0x00 */
 722     U16                     Reserved1;                  /* 0x02 */
 723     U8                      RAIDOperation;              /* 0x04 */
 724     U8                      PercentComplete;            /* 0x05 */
 725     U16                     Reserved2;                  /* 0x06 */
 726     U32                     ElapsedSeconds;             /* 0x08 */
 727 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 728   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 729   Mpi2EventDataIrOperationStatus_t,
 730   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 731
 732 /* Integrated RAID Operation Status Event data RAIDOperation values */
 733 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 734 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 735 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 736 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 737 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 738
 739
 740 /* Integrated RAID Volume Event data */
 741
 742 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 743 {
 744     U16                     VolDevHandle;               /* 0x00 */
 745     U8                      ReasonCode;                 /* 0x02 */
 746     U8                      Reserved1;                  /* 0x03 */
 747     U32                     NewValue;                   /* 0x04 */
 748     U32                     PreviousValue;              /* 0x08 */
 749 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 750   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 751
 752 /* Integrated RAID Volume Event data ReasonCode values */
 753 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 754 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 755 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 756
 757
 758 /* Integrated RAID Physical Disk Event data */
 759
 760 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 761 {
 762     U16                     Reserved1;                  /* 0x00 */
 763     U8                      ReasonCode;                 /* 0x02 */
 764     U8                      PhysDiskNum;                /* 0x03 */
 765     U16                     PhysDiskDevHandle;          /* 0x04 */
 766     U16                     Reserved2;                  /* 0x06 */
 767     U16                     Slot;                       /* 0x08 */
 768     U16                     EnclosureHandle;            /* 0x0A */
 769     U32                     NewValue;                   /* 0x0C */
 770     U32                     PreviousValue;              /* 0x10 */
 771 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 772   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 773   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 774
 775 /* Integrated RAID Physical Disk Event data ReasonCode values */
 776 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 777 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 778 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 779
 780
 781 /* Integrated RAID Configuration Change List Event data */
 782
 783 /*
 784  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 785  * one and check NumElements at runtime.
 786  */
 787 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 788 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 789 #endif
 790
 791 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 792 {
 793     U16                     ElementFlags;               /* 0x00 */
 794     U16                     VolDevHandle;               /* 0x02 */
 795     U8                      ReasonCode;                 /* 0x04 */
 796     U8                      PhysDiskNum;                /* 0x05 */
 797     U16                     PhysDiskDevHandle;          /* 0x06 */
 798 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 799   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 800
 801 /* IR Configuration Change List Event data ElementFlags values */
 802 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 803 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 804 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 805 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 806
 807 /* IR Configuration Change List Event data ReasonCode values */
 808 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 809 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 810 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 811 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 812 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 813 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 814 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 815 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 816 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 817
 818 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 819 {
 820     U8                              NumElements;        /* 0x00 */
 821     U8                              Reserved1;          /* 0x01 */
 822     U8                              Reserved2;          /* 0x02 */
 823     U8                              ConfigNum;          /* 0x03 */
 824     U32                             Flags;              /* 0x04 */
 825     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 826 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 827   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 828   Mpi2EventDataIrConfigChangeList_t,
 829   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 830
 831 /* IR Configuration Change List Event data Flags values */
 832 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 833
 834
 835 /* SAS Discovery Event data */
 836
 837 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 838 {
 839     U8                      Flags;                      /* 0x00 */
 840     U8                      ReasonCode;                 /* 0x01 */
 841     U8                      PhysicalPort;               /* 0x02 */
 842     U8                      Reserved1;                  /* 0x03 */
 843     U32                     DiscoveryStatus;            /* 0x04 */
 844 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 845   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 846   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 847
 848 /* SAS Discovery Event data Flags values */
 849 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 850 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 851
 852 /* SAS Discovery Event data ReasonCode values */
 853 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 854 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 855
 856 /* SAS Discovery Event data DiscoveryStatus values */
 857 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 858 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 859 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 860 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 861 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 862 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 863 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 864 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 865 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 866 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 867 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 868 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 869 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 870 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 871 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 872 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 873 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 874 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 875 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 876 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 877
 878
 879 /* SAS Broadcast Primitive Event data */
 880
 881 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 882 {
 883     U8                      PhyNum;                     /* 0x00 */
 884     U8                      Port;                       /* 0x01 */
 885     U8                      PortWidth;                  /* 0x02 */
 886     U8                      Primitive;                  /* 0x03 */
 887 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 888   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 889   Mpi2EventDataSasBroadcastPrimitive_t,
 890   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 891
 892 /* defines for the Primitive field */
 893 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 894 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 895 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 896 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 897 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 898 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 899 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 900 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 901
 902
 903 /* SAS Notify Primitive Event data */
 904
 905 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE
 906 {
 907     U8                      PhyNum;                     /* 0x00 */
 908     U8                      Port;                       /* 0x01 */
 909     U8                      Reserved1;                  /* 0x02 */
 910     U8                      Primitive;                  /* 0x03 */
 911 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 912   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 913   Mpi2EventDataSasNotifyPrimitive_t,
 914   MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
 915
 916 /* defines for the Primitive field */
 917 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 918 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 919 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 920 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 921
 922
 923 /* SAS Initiator Device Status Change Event data */
 924
 925 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 926 {
 927     U8                      ReasonCode;                 /* 0x00 */
 928     U8                      PhysicalPort;               /* 0x01 */
 929     U16                     DevHandle;                  /* 0x02 */
 930     U64                     SASAddress;                 /* 0x04 */
 931 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 932   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 933   Mpi2EventDataSasInitDevStatusChange_t,
 934   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 935
 936 /* SAS Initiator Device Status Change event ReasonCode values */
 937 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 938 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 939
 940
 941 /* SAS Initiator Device Table Overflow Event data */
 942
 943 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 944 {
 945     U16                     MaxInit;                    /* 0x00 */
 946     U16                     CurrentInit;                /* 0x02 */
 947     U64                     SASAddress;                 /* 0x04 */
 948 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 949   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 950   Mpi2EventDataSasInitTableOverflow_t,
 951   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 952
 953
 954 /* SAS Topology Change List Event data */
 955
 956 /*
 957  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 958  * one and check NumEntries at runtime.
 959  */
 960 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 961 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 962 #endif
 963
 964 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 965 {
 966     U16                     AttachedDevHandle;          /* 0x00 */
 967     U8                      LinkRate;                   /* 0x02 */
 968     U8                      PhyStatus;                  /* 0x03 */
 969 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 970   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 971
 972 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 973 {
 974     U16                             EnclosureHandle;            /* 0x00 */
 975     U16                             ExpanderDevHandle;          /* 0x02 */
 976     U8                              NumPhys;                    /* 0x04 */
 977     U8                              Reserved1;                  /* 0x05 */
 978     U16                             Reserved2;                  /* 0x06 */
 979     U8                              NumEntries;                 /* 0x08 */
 980     U8                              StartPhyNum;                /* 0x09 */
 981     U8                              ExpStatus;                  /* 0x0A */
 982     U8                              PhysicalPort;               /* 0x0B */
 983     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 984 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 985   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 986   Mpi2EventDataSasTopologyChangeList_t,
 987   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 988
 989 /* values for the ExpStatus field */
 990 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 991 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 992 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 993 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 994 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 995
 996 /* defines for the LinkRate field */
 997 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 998 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 999 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
1000 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
1001
1002 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
1003 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
1004 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
1005 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
1006 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
1007 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
1008 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
1009 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
1010 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
1011 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
1012 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
1013
1014 /* values for the PhyStatus field */
1015 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
1016 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
1017 /* values for the PhyStatus ReasonCode sub-field */
1018 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
1019 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
1020 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
1021 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
1022 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
1023 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
1024
1025
1026 /* SAS Enclosure Device Status Change Event data */
1027
1028 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
1029 {
1030     U16                     EnclosureHandle;            /* 0x00 */
1031     U8                      ReasonCode;                 /* 0x02 */
1032     U8                      PhysicalPort;               /* 0x03 */
1033     U64                     EnclosureLogicalID;         /* 0x04 */
1034     U16                     NumSlots;                   /* 0x0C */
1035     U16                     StartSlot;                  /* 0x0E */
1036     U32                     PhyBits;                    /* 0x10 */
1037 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1038   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1039   Mpi2EventDataSasEnclDevStatusChange_t,
1040   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
1041
1042 /* SAS Enclosure Device Status Change event ReasonCode values */
1043 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
1044 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
1045
1046
1047 /* SAS PHY Counter Event data */
1048
1049 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
1050 {
1051     U64         TimeStamp;          /* 0x00 */
1052     U32         Reserved1;          /* 0x08 */
1053     U8          PhyEventCode;       /* 0x0C */
1054     U8          PhyNum;             /* 0x0D */
1055     U16         Reserved2;          /* 0x0E */
1056     U32         PhyEventInfo;       /* 0x10 */
1057     U8          CounterType;        /* 0x14 */
1058     U8          ThresholdWindow;    /* 0x15 */
1059     U8          TimeUnits;          /* 0x16 */
1060     U8          Reserved3;          /* 0x17 */
1061     U32         EventThreshold;     /* 0x18 */
1062     U16         ThresholdFlags;     /* 0x1C */
1063     U16         Reserved4;          /* 0x1E */
1064 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1065   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1066   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
1067
1068 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
1069
1070 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
1071
1072 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
1073
1074 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
1075
1076
1077 /* SAS Quiesce Event data */
1078
1079 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
1080 {
1081     U8                      ReasonCode;                 /* 0x00 */
1082     U8                      Reserved1;                  /* 0x01 */
1083     U16                     Reserved2;                  /* 0x02 */
1084     U32                     Reserved3;                  /* 0x04 */
1085 } MPI2_EVENT_DATA_SAS_QUIESCE,
1086   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1087   Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1088
1089 /* SAS Quiesce Event data ReasonCode values */
1090 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
1091 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
1092
1093
1094 /* Host Based Discovery Phy Event data */
1095
1096 typedef struct _MPI2_EVENT_HBD_PHY_SAS
1097 {
1098     U8          Flags;                      /* 0x00 */
1099     U8          NegotiatedLinkRate;         /* 0x01 */
1100     U8          PhyNum;                     /* 0x02 */
1101     U8          PhysicalPort;               /* 0x03 */
1102     U32         Reserved1;                  /* 0x04 */
1103     U8          InitialFrame[28];           /* 0x08 */
1104 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1105   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1106
1107 /* values for the Flags field */
1108 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1109 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1110
1111 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
1112
1113 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
1114 {
1115     MPI2_EVENT_HBD_PHY_SAS      Sas;
1116 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1117   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1118
1119 typedef struct _MPI2_EVENT_DATA_HBD_PHY
1120 {
1121     U8                          DescriptorType;     /* 0x00 */
1122     U8                          Reserved1;          /* 0x01 */
1123     U16                         Reserved2;          /* 0x02 */
1124     U32                         Reserved3;          /* 0x04 */
1125     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
1126 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1127   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1128
1129 /* values for the DescriptorType field */
1130 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1131
1132
1133
1134 /****************************************************************************
1135 *  EventAck message
1136 ****************************************************************************/
1137
1138 /* EventAck Request message */
1139 typedef struct _MPI2_EVENT_ACK_REQUEST
1140 {
1141     U16                     Reserved1;                      /* 0x00 */
1142     U8                      ChainOffset;                    /* 0x02 */
1143     U8                      Function;                       /* 0x03 */
1144     U16                     Reserved2;                      /* 0x04 */
1145     U8                      Reserved3;                      /* 0x06 */
1146     U8                      MsgFlags;                       /* 0x07 */
1147     U8                      VP_ID;                          /* 0x08 */
1148     U8                      VF_ID;                          /* 0x09 */
1149     U16                     Reserved4;                      /* 0x0A */
1150     U16                     Event;                          /* 0x0C */
1151     U16                     Reserved5;                      /* 0x0E */
1152     U32                     EventContext;                   /* 0x10 */
1153 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1154   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1155
1156
1157 /* EventAck Reply message */
1158 typedef struct _MPI2_EVENT_ACK_REPLY
1159 {
1160     U16                     Reserved1;                      /* 0x00 */
1161     U8                      MsgLength;                      /* 0x02 */
1162     U8                      Function;                       /* 0x03 */
1163     U16                     Reserved2;                      /* 0x04 */
1164     U8                      Reserved3;                      /* 0x06 */
1165     U8                      MsgFlags;                       /* 0x07 */
1166     U8                      VP_ID;                          /* 0x08 */
1167     U8                      VF_ID;                          /* 0x09 */
1168     U16                     Reserved4;                      /* 0x0A */
1169     U16                     Reserved5;                      /* 0x0C */
1170     U16                     IOCStatus;                      /* 0x0E */
1171     U32                     IOCLogInfo;                     /* 0x10 */
1172 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1173   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1174
1175
1176 /****************************************************************************
1177 *  SendHostMessage message
1178 ****************************************************************************/
1179
1180 /* SendHostMessage Request message */
1181 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST
1182 {
1183     U16                     HostDataLength;                 /* 0x00 */
1184     U8                      ChainOffset;                    /* 0x02 */
1185     U8                      Function;                       /* 0x03 */
1186     U16                     Reserved1;                      /* 0x04 */
1187     U8                      Reserved2;                      /* 0x06 */
1188     U8                      MsgFlags;                       /* 0x07 */
1189     U8                      VP_ID;                          /* 0x08 */
1190     U8                      VF_ID;                          /* 0x09 */
1191     U16                     Reserved3;                      /* 0x0A */
1192     U8                      Reserved4;                      /* 0x0C */
1193     U8                      DestVF_ID;                      /* 0x0D */
1194     U16                     Reserved5;                      /* 0x0E */
1195     U32                     Reserved6;                      /* 0x10 */
1196     U32                     Reserved7;                      /* 0x14 */
1197     U32                     Reserved8;                      /* 0x18 */
1198     U32                     Reserved9;                      /* 0x1C */
1199     U32                     Reserved10;                     /* 0x20 */
1200     U32                     HostData[1];                    /* 0x24 */
1201 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1202   MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1203   Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1204
1205
1206 /* SendHostMessage Reply message */
1207 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY
1208 {
1209     U16                     HostDataLength;                 /* 0x00 */
1210     U8                      MsgLength;                      /* 0x02 */
1211     U8                      Function;                       /* 0x03 */
1212     U16                     Reserved1;                      /* 0x04 */
1213     U8                      Reserved2;                      /* 0x06 */
1214     U8                      MsgFlags;                       /* 0x07 */
1215     U8                      VP_ID;                          /* 0x08 */
1216     U8                      VF_ID;                          /* 0x09 */
1217     U16                     Reserved3;                      /* 0x0A */
1218     U16                     Reserved4;                      /* 0x0C */
1219     U16                     IOCStatus;                      /* 0x0E */
1220     U32                     IOCLogInfo;                     /* 0x10 */
1221 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1222   Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1223
1224
1225 /****************************************************************************
1226 *  FWDownload message
1227 ****************************************************************************/
1228
1229 /* MPI v2.0 FWDownload Request message */
1230 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1231 {
1232     U8                      ImageType;                  /* 0x00 */
1233     U8                      Reserved1;                  /* 0x01 */
1234     U8                      ChainOffset;                /* 0x02 */
1235     U8                      Function;                   /* 0x03 */
1236     U16                     Reserved2;                  /* 0x04 */
1237     U8                      Reserved3;                  /* 0x06 */
1238     U8                      MsgFlags;                   /* 0x07 */
1239     U8                      VP_ID;                      /* 0x08 */
1240     U8                      VF_ID;                      /* 0x09 */
1241     U16                     Reserved4;                  /* 0x0A */
1242     U32                     TotalImageSize;             /* 0x0C */
1243     U32                     Reserved5;                  /* 0x10 */
1244     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1245 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1246   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1247
1248 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1249
1250 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1251 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1252 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1253 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1254 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1255 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1256 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1257 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1258 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C) /* MPI v2.5 and newer */
1259 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1260
1261 /* MPI v2.0 FWDownload TransactionContext Element */
1262 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1263 {
1264     U8                      Reserved1;                  /* 0x00 */
1265     U8                      ContextSize;                /* 0x01 */
1266     U8                      DetailsLength;              /* 0x02 */
1267     U8                      Flags;                      /* 0x03 */
1268     U32                     Reserved2;                  /* 0x04 */
1269     U32                     ImageOffset;                /* 0x08 */
1270     U32                     ImageSize;                  /* 0x0C */
1271 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1272   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1273
1274
1275 /* MPI v2.5 FWDownload Request message */
1276 typedef struct _MPI25_FW_DOWNLOAD_REQUEST
1277 {
1278     U8                      ImageType;                  /* 0x00 */
1279     U8                      Reserved1;                  /* 0x01 */
1280     U8                      ChainOffset;                /* 0x02 */
1281     U8                      Function;                   /* 0x03 */
1282     U16                     Reserved2;                  /* 0x04 */
1283     U8                      Reserved3;                  /* 0x06 */
1284     U8                      MsgFlags;                   /* 0x07 */
1285     U8                      VP_ID;                      /* 0x08 */
1286     U8                      VF_ID;                      /* 0x09 */
1287     U16                     Reserved4;                  /* 0x0A */
1288     U32                     TotalImageSize;             /* 0x0C */
1289     U32                     Reserved5;                  /* 0x10 */
1290     U32                     Reserved6;                  /* 0x14 */
1291     U32                     ImageOffset;                /* 0x18 */
1292     U32                     ImageSize;                  /* 0x1C */
1293     MPI25_SGE_IO_UNION      SGL;                        /* 0x20 */
1294 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
1295   Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
1296
1297
1298 /* FWDownload Reply message */
1299 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1300 {
1301     U8                      ImageType;                  /* 0x00 */
1302     U8                      Reserved1;                  /* 0x01 */
1303     U8                      MsgLength;                  /* 0x02 */
1304     U8                      Function;                   /* 0x03 */
1305     U16                     Reserved2;                  /* 0x04 */
1306     U8                      Reserved3;                  /* 0x06 */
1307     U8                      MsgFlags;                   /* 0x07 */
1308     U8                      VP_ID;                      /* 0x08 */
1309     U8                      VF_ID;                      /* 0x09 */
1310     U16                     Reserved4;                  /* 0x0A */
1311     U16                     Reserved5;                  /* 0x0C */
1312     U16                     IOCStatus;                  /* 0x0E */
1313     U32                     IOCLogInfo;                 /* 0x10 */
1314 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1315   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1316
1317
1318 /****************************************************************************
1319 *  FWUpload message
1320 ****************************************************************************/
1321
1322 /* MPI v2.0 FWUpload Request message */
1323 typedef struct _MPI2_FW_UPLOAD_REQUEST
1324 {
1325     U8                      ImageType;                  /* 0x00 */
1326     U8                      Reserved1;                  /* 0x01 */
1327     U8                      ChainOffset;                /* 0x02 */
1328     U8                      Function;                   /* 0x03 */
1329     U16                     Reserved2;                  /* 0x04 */
1330     U8                      Reserved3;                  /* 0x06 */
1331     U8                      MsgFlags;                   /* 0x07 */
1332     U8                      VP_ID;                      /* 0x08 */
1333     U8                      VF_ID;                      /* 0x09 */
1334     U16                     Reserved4;                  /* 0x0A */
1335     U32                     Reserved5;                  /* 0x0C */
1336     U32                     Reserved6;                  /* 0x10 */
1337     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1338 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1339   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1340
1341 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1342 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1343 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1344 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1345 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1346 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1347 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1348 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1349 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1350 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1351
1352 /* MPI v2.0 FWUpload TransactionContext Element */
1353 typedef struct _MPI2_FW_UPLOAD_TCSGE
1354 {
1355     U8                      Reserved1;                  /* 0x00 */
1356     U8                      ContextSize;                /* 0x01 */
1357     U8                      DetailsLength;              /* 0x02 */
1358     U8                      Flags;                      /* 0x03 */
1359     U32                     Reserved2;                  /* 0x04 */
1360     U32                     ImageOffset;                /* 0x08 */
1361     U32                     ImageSize;                  /* 0x0C */
1362 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1363   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1364
1365
1366 /* MPI v2.5 FWUpload Request message */
1367 typedef struct _MPI25_FW_UPLOAD_REQUEST
1368 {
1369     U8                      ImageType;                  /* 0x00 */
1370     U8                      Reserved1;                  /* 0x01 */
1371     U8                      ChainOffset;                /* 0x02 */
1372     U8                      Function;                   /* 0x03 */
1373     U16                     Reserved2;                  /* 0x04 */
1374     U8                      Reserved3;                  /* 0x06 */
1375     U8                      MsgFlags;                   /* 0x07 */
1376     U8                      VP_ID;                      /* 0x08 */
1377     U8                      VF_ID;                      /* 0x09 */
1378     U16                     Reserved4;                  /* 0x0A */
1379     U32                     Reserved5;                  /* 0x0C */
1380     U32                     Reserved6;                  /* 0x10 */
1381     U32                     Reserved7;                  /* 0x14 */
1382     U32                     ImageOffset;                /* 0x18 */
1383     U32                     ImageSize;                  /* 0x1C */
1384     MPI25_SGE_IO_UNION      SGL;                        /* 0x20 */
1385 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
1386   Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
1387
1388
1389 /* FWUpload Reply message */
1390 typedef struct _MPI2_FW_UPLOAD_REPLY
1391 {
1392     U8                      ImageType;                  /* 0x00 */
1393     U8                      Reserved1;                  /* 0x01 */
1394     U8                      MsgLength;                  /* 0x02 */
1395     U8                      Function;                   /* 0x03 */
1396     U16                     Reserved2;                  /* 0x04 */
1397     U8                      Reserved3;                  /* 0x06 */
1398     U8                      MsgFlags;                   /* 0x07 */
1399     U8                      VP_ID;                      /* 0x08 */
1400     U8                      VF_ID;                      /* 0x09 */
1401     U16                     Reserved4;                  /* 0x0A */
1402     U16                     Reserved5;                  /* 0x0C */
1403     U16                     IOCStatus;                  /* 0x0E */
1404     U32                     IOCLogInfo;                 /* 0x10 */
1405     U32                     ActualImageSize;            /* 0x14 */
1406 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1407   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1408
1409
1410 /* FW Image Header */
1411 typedef struct _MPI2_FW_IMAGE_HEADER
1412 {
1413     U32                     Signature;                  /* 0x00 */
1414     U32                     Signature0;                 /* 0x04 */
1415     U32                     Signature1;                 /* 0x08 */
1416     U32                     Signature2;                 /* 0x0C */
1417     MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1418     MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1419     MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1420     MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1421     U16                     VendorID;                   /* 0x20 */
1422     U16                     ProductID;                  /* 0x22 */
1423     U16                     ProtocolFlags;              /* 0x24 */
1424     U16                     Reserved26;                 /* 0x26 */
1425     U32                     IOCCapabilities;            /* 0x28 */
1426     U32                     ImageSize;                  /* 0x2C */
1427     U32                     NextImageHeaderOffset;      /* 0x30 */
1428     U32                     Checksum;                   /* 0x34 */
1429     U32                     Reserved38;                 /* 0x38 */
1430     U32                     Reserved3C;                 /* 0x3C */
1431     U32                     Reserved40;                 /* 0x40 */
1432     U32                     Reserved44;                 /* 0x44 */
1433     U32                     Reserved48;                 /* 0x48 */
1434     U32                     Reserved4C;                 /* 0x4C */
1435     U32                     Reserved50;                 /* 0x50 */
1436     U32                     Reserved54;                 /* 0x54 */
1437     U32                     Reserved58;                 /* 0x58 */
1438     U32                     Reserved5C;                 /* 0x5C */
1439     U32                     Reserved60;                 /* 0x60 */
1440     U32                     FirmwareVersionNameWhat;    /* 0x64 */
1441     U8                      FirmwareVersionName[32];    /* 0x68 */
1442     U32                     VendorNameWhat;             /* 0x88 */
1443     U8                      VendorName[32];             /* 0x8C */
1444     U32                     PackageNameWhat;            /* 0x88 */
1445     U8                      PackageName[32];            /* 0x8C */
1446     U32                     ReservedD0;                 /* 0xD0 */
1447     U32                     ReservedD4;                 /* 0xD4 */
1448     U32                     ReservedD8;                 /* 0xD8 */
1449     U32                     ReservedDC;                 /* 0xDC */
1450     U32                     ReservedE0;                 /* 0xE0 */
1451     U32                     ReservedE4;                 /* 0xE4 */
1452     U32                     ReservedE8;                 /* 0xE8 */
1453     U32                     ReservedEC;                 /* 0xEC */
1454     U32                     ReservedF0;                 /* 0xF0 */
1455     U32                     ReservedF4;                 /* 0xF4 */
1456     U32                     ReservedF8;                 /* 0xF8 */
1457     U32                     ReservedFC;                 /* 0xFC */
1458 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1459   Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1460
1461 /* Signature field */
1462 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1463 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1464 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1465
1466 /* Signature0 field */
1467 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1468 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1469
1470 /* Signature1 field */
1471 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1472 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1473
1474 /* Signature2 field */
1475 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1476 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1477
1478
1479 /* defines for using the ProductID field */
1480 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1481 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1482
1483 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1484 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1485 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1486 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1487
1488
1489 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1490 /* SAS ProductID Family bits */
1491 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1492 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1493 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS     (0x0021)
1494
1495 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1496
1497 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1498
1499
1500 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1501 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1502 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1503
1504 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1505
1506 #define MPI2_FW_HEADER_SIZE                     (0x100)
1507
1508
1509 /* Extended Image Header */
1510 typedef struct _MPI2_EXT_IMAGE_HEADER
1511
1512 {
1513     U8                      ImageType;                  /* 0x00 */
1514     U8                      Reserved1;                  /* 0x01 */
1515     U16                     Reserved2;                  /* 0x02 */
1516     U32                     Checksum;                   /* 0x04 */
1517     U32                     ImageSize;                  /* 0x08 */
1518     U32                     NextImageHeaderOffset;      /* 0x0C */
1519     U32                     PackageVersion;             /* 0x10 */
1520     U32                     Reserved3;                  /* 0x14 */
1521     U32                     Reserved4;                  /* 0x18 */
1522     U32                     Reserved5;                  /* 0x1C */
1523     U8                      IdentifyString[32];         /* 0x20 */
1524 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1525   Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1526
1527 /* useful offsets */
1528 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1529 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1530 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1531
1532 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1533
1534 /* defines for the ImageType field */
1535 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1536 #define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1537 #define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1538 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1539 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1540 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1541 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1542 #define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1543 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09) /* MPI v2.5 and newer */
1544 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1545 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1546
1547 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)  /* deprecated */
1548
1549
1550
1551 /* FLASH Layout Extended Image Data */
1552
1553 /*
1554  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1555  * one and check RegionsPerLayout at runtime.
1556  */
1557 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1558 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1559 #endif
1560
1561 /*
1562  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1563  * one and check NumberOfLayouts at runtime.
1564  */
1565 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1566 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1567 #endif
1568
1569 typedef struct _MPI2_FLASH_REGION
1570 {
1571     U8                      RegionType;                 /* 0x00 */
1572     U8                      Reserved1;                  /* 0x01 */
1573     U16                     Reserved2;                  /* 0x02 */
1574     U32                     RegionOffset;               /* 0x04 */
1575     U32                     RegionSize;                 /* 0x08 */
1576     U32                     Reserved3;                  /* 0x0C */
1577 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1578   Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1579
1580 typedef struct _MPI2_FLASH_LAYOUT
1581 {
1582     U32                     FlashSize;                  /* 0x00 */
1583     U32                     Reserved1;                  /* 0x04 */
1584     U32                     Reserved2;                  /* 0x08 */
1585     U32                     Reserved3;                  /* 0x0C */
1586     MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1587 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1588   Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1589
1590 typedef struct _MPI2_FLASH_LAYOUT_DATA
1591 {
1592     U8                      ImageRevision;              /* 0x00 */
1593     U8                      Reserved1;                  /* 0x01 */
1594     U8                      SizeOfRegion;               /* 0x02 */
1595     U8                      Reserved2;                  /* 0x03 */
1596     U16                     NumberOfLayouts;            /* 0x04 */
1597     U16                     RegionsPerLayout;           /* 0x06 */
1598     U16                     MinimumSectorAlignment;     /* 0x08 */
1599     U16                     Reserved3;                  /* 0x0A */
1600     U32                     Reserved4;                  /* 0x0C */
1601     MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1602 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1603   Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1604
1605 /* defines for the RegionType field */
1606 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1607 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1608 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1609 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1610 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1611 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1612 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1613 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1614 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1615 #define MPI2_FLASH_REGION_INIT                  (0x0A)
1616
1617 /* ImageRevision */
1618 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1619
1620
1621
1622 /* Supported Devices Extended Image Data */
1623
1624 /*
1625  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1626  * one and check NumberOfDevices at runtime.
1627  */
1628 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1629 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1630 #endif
1631
1632 typedef struct _MPI2_SUPPORTED_DEVICE
1633 {
1634     U16                     DeviceID;                   /* 0x00 */
1635     U16                     VendorID;                   /* 0x02 */
1636     U16                     DeviceIDMask;               /* 0x04 */
1637     U16                     Reserved1;                  /* 0x06 */
1638     U8                      LowPCIRev;                  /* 0x08 */
1639     U8                      HighPCIRev;                 /* 0x09 */
1640     U16                     Reserved2;                  /* 0x0A */
1641     U32                     Reserved3;                  /* 0x0C */
1642 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1643   Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1644
1645 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1646 {
1647     U8                      ImageRevision;              /* 0x00 */
1648     U8                      Reserved1;                  /* 0x01 */
1649     U8                      NumberOfDevices;            /* 0x02 */
1650     U8                      Reserved2;                  /* 0x03 */
1651     U32                     Reserved3;                  /* 0x04 */
1652     MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1653 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1654   Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1655
1656 /* ImageRevision */
1657 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1658
1659
1660 /* Init Extended Image Data */
1661
1662 typedef struct _MPI2_INIT_IMAGE_FOOTER
1663
1664 {
1665     U32                     BootFlags;                  /* 0x00 */
1666     U32                     ImageSize;                  /* 0x04 */
1667     U32                     Signature0;                 /* 0x08 */
1668     U32                     Signature1;                 /* 0x0C */
1669     U32                     Signature2;                 /* 0x10 */
1670     U32                     ResetVector;                /* 0x14 */
1671 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1672   Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1673
1674 /* defines for the BootFlags field */
1675 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1676
1677 /* defines for the ImageSize field */
1678 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1679
1680 /* defines for the Signature0 field */
1681 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1682 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1683
1684 /* defines for the Signature1 field */
1685 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1686 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1687
1688 /* defines for the Signature2 field */
1689 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1690 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1691
1692 /* Signature fields as individual bytes */
1693 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1694 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1695 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1696 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1697
1698 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1699 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1700 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1701 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1702
1703 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1704 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1705 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1706 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1707
1708 /* defines for the ResetVector field */
1709 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1710
1711
1712 /* Encrypted Hash Extended Image Data */
1713
1714 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY
1715 {
1716     U8                  HashImageType;          /* 0x00 */
1717     U8                  HashAlgorithm;          /* 0x01 */
1718     U8                  EncryptionAlgorithm;    /* 0x02 */
1719     U8                  Reserved1;              /* 0x03 */
1720     U32                 Reserved2;              /* 0x04 */
1721     U32                 EncryptedHash[1];       /* 0x08 */ /* variable length */
1722 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1723   Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t;
1724
1725 /* values for HashImageType */
1726 #define MPI25_HASH_IMAGE_TYPE_UNUSED            (0x00)
1727 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE          (0x01)
1728 #define MPI25_HASH_IMAGE_TYPE_BIOS              (0x02)
1729
1730 /* values for HashAlgorithm */
1731 #define MPI25_HASH_ALGORITHM_UNUSED             (0x00)
1732 #define MPI25_HASH_ALGORITHM_SHA256             (0x01)
1733
1734 /* values for EncryptionAlgorithm */
1735 #define MPI25_ENCRYPTION_ALG_UNUSED             (0x00)
1736 #define MPI25_ENCRYPTION_ALG_RSA256             (0x01)
1737
1738 typedef struct _MPI25_ENCRYPTED_HASH_DATA
1739 {
1740     U8                              ImageVersion;           /* 0x00 */
1741     U8                              NumHash;                /* 0x01 */
1742     U16                             Reserved1;              /* 0x02 */
1743     U32                             Reserved2;              /* 0x04 */
1744     MPI25_ENCRYPTED_HASH_ENTRY      EncryptedHashEntry[1];  /* 0x08 */ /* variable number of entries */
1745 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA,
1746   Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t;
1747
1748 /****************************************************************************
1749 *  PowerManagementControl message
1750 ****************************************************************************/
1751
1752 /* PowerManagementControl Request message */
1753 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
1754 {
1755     U8                      Feature;                    /* 0x00 */
1756     U8                      Reserved1;                  /* 0x01 */
1757     U8                      ChainOffset;                /* 0x02 */
1758     U8                      Function;                   /* 0x03 */
1759     U16                     Reserved2;                  /* 0x04 */
1760     U8                      Reserved3;                  /* 0x06 */
1761     U8                      MsgFlags;                   /* 0x07 */
1762     U8                      VP_ID;                      /* 0x08 */
1763     U8                      VF_ID;                      /* 0x09 */
1764     U16                     Reserved4;                  /* 0x0A */
1765     U8                      Parameter1;                 /* 0x0C */
1766     U8                      Parameter2;                 /* 0x0D */
1767     U8                      Parameter3;                 /* 0x0E */
1768     U8                      Parameter4;                 /* 0x0F */
1769     U32                     Reserved5;                  /* 0x10 */
1770     U32                     Reserved6;                  /* 0x14 */
1771 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1772   Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1773
1774 /* defines for the Feature field */
1775 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1776 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1777 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03) /* obsolete */
1778 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1779 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05) /* reserved in MPI 2.0 */
1780 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1781 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1782
1783 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1784 /* Parameter1 contains a PHY number */
1785 /* Parameter2 indicates power condition action using these defines */
1786 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1787 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1788 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1789 /* Parameter3 and Parameter4 are reserved */
1790
1791 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
1792 /* Parameter1 contains SAS port width modulation group number */
1793 /* Parameter2 indicates IOC action using these defines */
1794 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1795 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1796 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1797 /* Parameter3 indicates desired modulation level using these defines */
1798 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1799 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1800 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1801 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1802 /* Parameter4 is reserved */
1803
1804 /* this next set (_PCIE_LINK) is obsolete */
1805 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1806 /* Parameter1 indicates desired PCIe link speed using these defines */
1807 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00) /* obsolete */
1808 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01) /* obsolete */
1809 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02) /* obsolete */
1810 /* Parameter2 indicates desired PCIe link width using these defines */
1811 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01) /* obsolete */
1812 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02) /* obsolete */
1813 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04) /* obsolete */
1814 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08) /* obsolete */
1815 /* Parameter3 and Parameter4 are reserved */
1816
1817 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1818 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1819 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1820 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1821 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1822 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1823 /* Parameter2, Parameter3, and Parameter4 are reserved */
1824
1825 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */
1826 /* Parameter1 indicates host action regarding global power management mode */
1827 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1828 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1829 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1830 /* Parameter2 indicates the requested global power management mode */
1831 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1832 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1833 #define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1834 /* Parameter3 and Parameter4 are reserved */
1835
1836
1837 /* PowerManagementControl Reply message */
1838 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
1839 {
1840     U8                      Feature;                    /* 0x00 */
1841     U8                      Reserved1;                  /* 0x01 */
1842     U8                      MsgLength;                  /* 0x02 */
1843     U8                      Function;                   /* 0x03 */
1844     U16                     Reserved2;                  /* 0x04 */
1845     U8                      Reserved3;                  /* 0x06 */
1846     U8                      MsgFlags;                   /* 0x07 */
1847     U8                      VP_ID;                      /* 0x08 */
1848     U8                      VF_ID;                      /* 0x09 */
1849     U16                     Reserved4;                  /* 0x0A */
1850     U16                     Reserved5;                  /* 0x0C */
1851     U16                     IOCStatus;                  /* 0x0E */
1852     U32                     IOCLogInfo;                 /* 0x10 */
1853 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1854   Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1855
1856
1857 #endif
1858