sys/dev/mrsas/mrsas.h

   1 /*
   2  * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy
   3  * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy
   4  * Support: freebsdraid@avagotech.com
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  * this list of conditions and the following disclaimer. 2. Redistributions
  12  * in binary form must reproduce the above copyright notice, this list of
  13  * conditions and the following disclaimer in the documentation and/or other
  14  * materials provided with the distribution. 3. Neither the name of the
  15  * <ORGANIZATION> nor the names of its contributors may be used to endorse or
  16  * promote products derived from this software without specific prior written
  17  * permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * The views and conclusions contained in the software and documentation are
  32  * those of the authors and should not be interpreted as representing
  33  * official policies,either expressed or implied, of the FreeBSD Project.
  34  *
  35  * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621
  36  * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD
  37  *
  38  */
  39
  40 #include <sys/cdefs.h>
  41 __FBSDID("$FreeBSD$");
  42
  43 #ifndef MRSAS_H
  44 #define MRSAS_H
  45
  46 #include <sys/param.h>                  /* defines used in kernel.h */
  47 #include <sys/module.h>
  48 #include <sys/systm.h>
  49 #include <sys/proc.h>
  50 #include <sys/errno.h>
  51 #include <sys/kernel.h>                 /* types used in module initialization */
  52 #include <sys/conf.h>                   /* cdevsw struct */
  53 #include <sys/uio.h>                    /* uio struct */
  54 #include <sys/malloc.h>
  55 #include <sys/bus.h>                    /* structs, prototypes for pci bus
  56                                          * stuff */
  57 #include <sys/rman.h>
  58 #include <sys/types.h>
  59 #include <sys/lock.h>
  60 #include <sys/sema.h>
  61 #include <sys/sysctl.h>
  62 #include <sys/stat.h>
  63 #include <sys/taskqueue.h>
  64 #include <sys/poll.h>
  65 #include <sys/selinfo.h>
  66
  67 #include <machine/bus.h>
  68 #include <machine/resource.h>
  69 #include <machine/atomic.h>
  70
  71 #include <dev/pci/pcivar.h>             /* For pci_get macros! */
  72 #include <dev/pci/pcireg.h>
  73
  74
  75 #define IOCTL_SEMA_DESCRIPTION  "mrsas semaphore for MFI pool"
  76
  77 /*
  78  * Device IDs and PCI
  79  */
  80 #define MRSAS_TBOLT                     0x005b
  81 #define MRSAS_INVADER           0x005d
  82 #define MRSAS_FURY                      0x005f
  83 #define MRSAS_PCI_BAR0          0x10
  84 #define MRSAS_PCI_BAR1          0x14
  85 #define MRSAS_PCI_BAR2          0x1C
  86
  87 /*
  88  * Firmware State Defines
  89  */
  90 #define MRSAS_FWSTATE_MAXCMD_MASK               0x0000FFFF
  91 #define MRSAS_FWSTATE_SGE_MASK                  0x00FF0000
  92 #define MRSAS_FW_STATE_CHNG_INTERRUPT   1
  93
  94 /*
  95  * Message Frame Defines
  96  */
  97 #define MRSAS_SENSE_LEN                                 96
  98 #define MRSAS_FUSION_MAX_RESET_TRIES    3
  99
 100 /*
 101  * Miscellaneous Defines
 102  */
 103 #define BYTE_ALIGNMENT                                  1
 104 #define MRSAS_MAX_NAME_LENGTH                   32
 105 #define MRSAS_VERSION                                   "06.707.04.03-fbsd"
 106 #define MRSAS_ULONG_MAX                                 0xFFFFFFFFFFFFFFFF
 107 #define MRSAS_DEFAULT_TIMEOUT                   0x14    /* Temporarily set */
 108 #define DONE                                                    0
 109 #define MRSAS_PAGE_SIZE                                 4096
 110 #define MRSAS_RESET_NOTICE_INTERVAL             5
 111 #define MRSAS_IO_TIMEOUT                                180000  /* 180 second timeout */
 112 #define MRSAS_LDIO_QUEUE_DEPTH                  70      /* 70 percent as default */
 113 #define THRESHOLD_REPLY_COUNT                   50
 114 #define MAX_MSIX_COUNT                                  128
 115
 116 /*
 117  * Boolean types
 118  */
 119 #if (__FreeBSD_version < 901000)
 120 typedef enum _boolean {
 121         false, true
 122 }       boolean;
 123
 124 #endif
 125 enum err {
 126         SUCCESS, FAIL
 127 };
 128
 129 MALLOC_DECLARE(M_MRSAS);
 130 SYSCTL_DECL(_hw_mrsas);
 131
 132 #define MRSAS_INFO              (1 << 0)
 133 #define MRSAS_TRACE             (1 << 1)
 134 #define MRSAS_FAULT             (1 << 2)
 135 #define MRSAS_OCR               (1 << 3)
 136 #define MRSAS_TOUT              MRSAS_OCR
 137 #define MRSAS_AEN               (1 << 4)
 138 #define MRSAS_PRL11             (1 << 5)
 139
 140 #define mrsas_dprint(sc, level, msg, args...)       \
 141 do {                                                \
 142     if (sc->mrsas_debug & level)                    \
 143         device_printf(sc->mrsas_dev, msg, ##args);  \
 144 } while (0)
 145
 146
 147 /****************************************************************************
 148  * Raid Context structure which describes MegaRAID specific IO Paramenters
 149  * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
 150  ****************************************************************************/
 151
 152 typedef struct _RAID_CONTEXT {
 153         u_int8_t Type:4;
 154         u_int8_t nseg:4;
 155         u_int8_t resvd0;
 156         u_int16_t timeoutValue;
 157         u_int8_t regLockFlags;
 158         u_int8_t resvd1;
 159         u_int16_t VirtualDiskTgtId;
 160         u_int64_t regLockRowLBA;
 161         u_int32_t regLockLength;
 162         u_int16_t nextLMId;
 163         u_int8_t exStatus;
 164         u_int8_t status;
 165         u_int8_t RAIDFlags;
 166         u_int8_t numSGE;
 167         u_int16_t configSeqNum;
 168         u_int8_t spanArm;
 169         u_int8_t resvd2[3];
 170 }       RAID_CONTEXT;
 171
 172
 173 /*************************************************************************
 174  * MPI2 Defines
 175  ************************************************************************/
 176
 177 #define MPI2_FUNCTION_IOC_INIT                                  (0x02)  /* IOC Init */
 178 #define MPI2_WHOINIT_HOST_DRIVER                                (0x04)
 179 #define MPI2_VERSION_MAJOR                                              (0x02)
 180 #define MPI2_VERSION_MINOR                                              (0x00)
 181 #define MPI2_VERSION_MAJOR_MASK                                 (0xFF00)
 182 #define MPI2_VERSION_MAJOR_SHIFT                                (8)
 183 #define MPI2_VERSION_MINOR_MASK                                 (0x00FF)
 184 #define MPI2_VERSION_MINOR_SHIFT                                (0)
 185 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
 186                       MPI2_VERSION_MINOR)
 187 #define MPI2_HEADER_VERSION_UNIT                                (0x10)
 188 #define MPI2_HEADER_VERSION_DEV                                 (0x00)
 189 #define MPI2_HEADER_VERSION_UNIT_MASK                   (0xFF00)
 190 #define MPI2_HEADER_VERSION_UNIT_SHIFT                  (8)
 191 #define MPI2_HEADER_VERSION_DEV_MASK                    (0x00FF)
 192 #define MPI2_HEADER_VERSION_DEV_SHIFT                   (0)
 193 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
 194 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR              (0x03)
 195 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG    (0x8000)
 196 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG              (0x0400)
 197 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP   (0x0003)
 198 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG              (0x0200)
 199 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD               (0x0100)
 200 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP                 (0x0004)
 201 #define MPI2_FUNCTION_SCSI_IO_REQUEST                   (0x00)  /* SCSI IO */
 202 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY   (0x06)
 203 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO                 (0x00)
 204 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING                (0x02)
 205 #define MPI2_SCSIIO_CONTROL_WRITE                               (0x01000000)
 206 #define MPI2_SCSIIO_CONTROL_READ                                (0x02000000)
 207 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK               (0x0E)
 208 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED                  (0x0F)
 209 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
 210 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK               (0x0F)
 211 #define MPI2_WRSEQ_FLUSH_KEY_VALUE                              (0x0)
 212 #define MPI2_WRITE_SEQUENCE_OFFSET                              (0x00000004)
 213 #define MPI2_WRSEQ_1ST_KEY_VALUE                                (0xF)
 214 #define MPI2_WRSEQ_2ND_KEY_VALUE                                (0x4)
 215 #define MPI2_WRSEQ_3RD_KEY_VALUE                                (0xB)
 216 #define MPI2_WRSEQ_4TH_KEY_VALUE                                (0x2)
 217 #define MPI2_WRSEQ_5TH_KEY_VALUE                                (0x7)
 218 #define MPI2_WRSEQ_6TH_KEY_VALUE                                (0xD)
 219
 220 #ifndef MPI2_POINTER
 221 #define MPI2_POINTER    *
 222 #endif
 223
 224
 225 /***************************************
 226  * MPI2 Structures
 227  ***************************************/
 228
 229 typedef struct _MPI25_IEEE_SGE_CHAIN64 {
 230         u_int64_t Address;
 231         u_int32_t Length;
 232         u_int16_t Reserved1;
 233         u_int8_t NextChainOffset;
 234         u_int8_t Flags;
 235 }       MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
 236 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
 237
 238 typedef struct _MPI2_SGE_SIMPLE_UNION {
 239         u_int32_t FlagsLength;
 240         union {
 241                 u_int32_t Address32;
 242                 u_int64_t Address64;
 243         }       u;
 244 }       MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
 245 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
 246
 247 typedef struct {
 248         u_int8_t CDB[20];               /* 0x00 */
 249         u_int32_t PrimaryReferenceTag;  /* 0x14 */
 250         u_int16_t PrimaryApplicationTag;/* 0x18 */
 251         u_int16_t PrimaryApplicationTagMask;    /* 0x1A */
 252         u_int32_t TransferLength;       /* 0x1C */
 253 }       MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
 254 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
 255
 256 typedef struct _MPI2_SGE_CHAIN_UNION {
 257         u_int16_t Length;
 258         u_int8_t NextChainOffset;
 259         u_int8_t Flags;
 260         union {
 261                 u_int32_t Address32;
 262                 u_int64_t Address64;
 263         }       u;
 264 }       MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
 265 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
 266
 267 typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
 268         u_int32_t Address;
 269         u_int32_t FlagsLength;
 270 }       MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
 271 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
 272 typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
 273         u_int64_t Address;
 274         u_int32_t Length;
 275         u_int16_t Reserved1;
 276         u_int8_t Reserved2;
 277         u_int8_t Flags;
 278 }       MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
 279 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
 280
 281 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
 282         MPI2_IEEE_SGE_SIMPLE32 Simple32;
 283         MPI2_IEEE_SGE_SIMPLE64 Simple64;
 284 }       MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
 285 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
 286
 287 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
 288 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
 289
 290 typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
 291         MPI2_IEEE_SGE_CHAIN32 Chain32;
 292         MPI2_IEEE_SGE_CHAIN64 Chain64;
 293 }       MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
 294 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
 295
 296 typedef union _MPI2_SGE_IO_UNION {
 297         MPI2_SGE_SIMPLE_UNION MpiSimple;
 298         MPI2_SGE_CHAIN_UNION MpiChain;
 299         MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
 300         MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
 301 }       MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
 302 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
 303
 304 typedef union {
 305         u_int8_t CDB32[32];
 306         MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
 307         MPI2_SGE_SIMPLE_UNION SGE;
 308 }       MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
 309 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
 310
 311 /*
 312  * RAID SCSI IO Request Message Total SGE count will be one less than
 313  * _MPI2_SCSI_IO_REQUEST
 314  */
 315 typedef struct _MPI2_RAID_SCSI_IO_REQUEST {
 316         u_int16_t DevHandle;            /* 0x00 */
 317         u_int8_t ChainOffset;           /* 0x02 */
 318         u_int8_t Function;              /* 0x03 */
 319         u_int16_t Reserved1;            /* 0x04 */
 320         u_int8_t Reserved2;             /* 0x06 */
 321         u_int8_t MsgFlags;              /* 0x07 */
 322         u_int8_t VP_ID;                 /* 0x08 */
 323         u_int8_t VF_ID;                 /* 0x09 */
 324         u_int16_t Reserved3;            /* 0x0A */
 325         u_int32_t SenseBufferLowAddress;/* 0x0C */
 326         u_int16_t SGLFlags;             /* 0x10 */
 327         u_int8_t SenseBufferLength;     /* 0x12 */
 328         u_int8_t Reserved4;             /* 0x13 */
 329         u_int8_t SGLOffset0;            /* 0x14 */
 330         u_int8_t SGLOffset1;            /* 0x15 */
 331         u_int8_t SGLOffset2;            /* 0x16 */
 332         u_int8_t SGLOffset3;            /* 0x17 */
 333         u_int32_t SkipCount;            /* 0x18 */
 334         u_int32_t DataLength;           /* 0x1C */
 335         u_int32_t BidirectionalDataLength;      /* 0x20 */
 336         u_int16_t IoFlags;              /* 0x24 */
 337         u_int16_t EEDPFlags;            /* 0x26 */
 338         u_int32_t EEDPBlockSize;        /* 0x28 */
 339         u_int32_t SecondaryReferenceTag;/* 0x2C */
 340         u_int16_t SecondaryApplicationTag;      /* 0x30 */
 341         u_int16_t ApplicationTagTranslationMask;        /* 0x32 */
 342         u_int8_t LUN[8];                /* 0x34 */
 343         u_int32_t Control;              /* 0x3C */
 344         MPI2_SCSI_IO_CDB_UNION CDB;     /* 0x40 */
 345         RAID_CONTEXT RaidContext;       /* 0x60 */
 346         MPI2_SGE_IO_UNION SGL;          /* 0x80 */
 347 }       MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST,
 348 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t;
 349
 350 /*
 351  * MPT RAID MFA IO Descriptor.
 352  */
 353 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR {
 354         u_int32_t RequestFlags:8;
 355         u_int32_t MessageAddress1:24;   /* bits 31:8 */
 356         u_int32_t MessageAddress2;      /* bits 61:32 */
 357 }       MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR;
 358
 359 /* Default Request Descriptor */
 360 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
 361         u_int8_t RequestFlags;          /* 0x00 */
 362         u_int8_t MSIxIndex;             /* 0x01 */
 363         u_int16_t SMID;                 /* 0x02 */
 364         u_int16_t LMID;                 /* 0x04 */
 365         u_int16_t DescriptorTypeDependent;      /* 0x06 */
 366 }       MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 367
 368         MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
 369 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
 370
 371 /* High Priority Request Descriptor */
 372 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
 373         u_int8_t RequestFlags;          /* 0x00 */
 374         u_int8_t MSIxIndex;             /* 0x01 */
 375         u_int16_t SMID;                 /* 0x02 */
 376         u_int16_t LMID;                 /* 0x04 */
 377         u_int16_t Reserved1;            /* 0x06 */
 378 }       MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 379
 380         MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
 381 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
 382
 383 /* SCSI IO Request Descriptor */
 384 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
 385         u_int8_t RequestFlags;          /* 0x00 */
 386         u_int8_t MSIxIndex;             /* 0x01 */
 387         u_int16_t SMID;                 /* 0x02 */
 388         u_int16_t LMID;                 /* 0x04 */
 389         u_int16_t DevHandle;            /* 0x06 */
 390 }       MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 391
 392         MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
 393 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
 394
 395 /* SCSI Target Request Descriptor */
 396 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
 397         u_int8_t RequestFlags;          /* 0x00 */
 398         u_int8_t MSIxIndex;             /* 0x01 */
 399         u_int16_t SMID;                 /* 0x02 */
 400         u_int16_t LMID;                 /* 0x04 */
 401         u_int16_t IoIndex;              /* 0x06 */
 402 }       MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 403
 404         MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
 405 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
 406
 407 /* RAID Accelerator Request Descriptor */
 408 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
 409         u_int8_t RequestFlags;          /* 0x00 */
 410         u_int8_t MSIxIndex;             /* 0x01 */
 411         u_int16_t SMID;                 /* 0x02 */
 412         u_int16_t LMID;                 /* 0x04 */
 413         u_int16_t Reserved;             /* 0x06 */
 414 }       MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 415
 416         MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
 417 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
 418
 419 /* union of Request Descriptors */
 420 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION {
 421         MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
 422         MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
 423         MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
 424         MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
 425         MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
 426         MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
 427         union {
 428                 struct {
 429                         u_int32_t low;
 430                         u_int32_t high;
 431                 }       u;
 432                 u_int64_t Words;
 433         }       addr;
 434 }       MRSAS_REQUEST_DESCRIPTOR_UNION;
 435
 436 /* Default Reply Descriptor */
 437 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
 438         u_int8_t ReplyFlags;            /* 0x00 */
 439         u_int8_t MSIxIndex;             /* 0x01 */
 440         u_int16_t DescriptorTypeDependent1;     /* 0x02 */
 441         u_int32_t DescriptorTypeDependent2;     /* 0x04 */
 442 }       MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
 443 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
 444
 445 /* Address Reply Descriptor */
 446 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
 447         u_int8_t ReplyFlags;            /* 0x00 */
 448         u_int8_t MSIxIndex;             /* 0x01 */
 449         u_int16_t SMID;                 /* 0x02 */
 450         u_int32_t ReplyFrameAddress;    /* 0x04 */
 451 }       MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
 452 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
 453
 454 /* SCSI IO Success Reply Descriptor */
 455 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
 456         u_int8_t ReplyFlags;            /* 0x00 */
 457         u_int8_t MSIxIndex;             /* 0x01 */
 458         u_int16_t SMID;                 /* 0x02 */
 459         u_int16_t TaskTag;              /* 0x04 */
 460         u_int16_t Reserved1;            /* 0x06 */
 461 }       MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 462
 463         MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
 464 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
 465
 466 /* TargetAssist Success Reply Descriptor */
 467 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
 468         u_int8_t ReplyFlags;            /* 0x00 */
 469         u_int8_t MSIxIndex;             /* 0x01 */
 470         u_int16_t SMID;                 /* 0x02 */
 471         u_int8_t SequenceNumber;        /* 0x04 */
 472         u_int8_t Reserved1;             /* 0x05 */
 473         u_int16_t IoIndex;              /* 0x06 */
 474 }       MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 475
 476         MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
 477 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
 478
 479 /* Target Command Buffer Reply Descriptor */
 480 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
 481         u_int8_t ReplyFlags;            /* 0x00 */
 482         u_int8_t MSIxIndex;             /* 0x01 */
 483         u_int8_t VP_ID;                 /* 0x02 */
 484         u_int8_t Flags;                 /* 0x03 */
 485         u_int16_t InitiatorDevHandle;   /* 0x04 */
 486         u_int16_t IoIndex;              /* 0x06 */
 487 }       MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 488
 489         MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
 490 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
 491
 492 /* RAID Accelerator Success Reply Descriptor */
 493 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
 494         u_int8_t ReplyFlags;            /* 0x00 */
 495         u_int8_t MSIxIndex;             /* 0x01 */
 496         u_int16_t SMID;                 /* 0x02 */
 497         u_int32_t Reserved;             /* 0x04 */
 498 }       MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 499
 500         MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
 501 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
 502
 503 /* union of Reply Descriptors */
 504 typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
 505         MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
 506         MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
 507         MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
 508         MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
 509         MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
 510         MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
 511         u_int64_t Words;
 512 }       MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
 513 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
 514
 515 typedef union {
 516         volatile unsigned int val;
 517         unsigned int val_rdonly;
 518 } mrsas_atomic_t;
 519
 520 #define mrsas_atomic_read(v)    atomic_load_acq_int(&(v)->val)
 521 #define mrsas_atomic_set(v,i)   atomic_store_rel_int(&(v)->val, i)
 522 #define mrsas_atomic_dec(v)     atomic_fetchadd_int(&(v)->val, -1)
 523 #define mrsas_atomic_inc(v)     atomic_fetchadd_int(&(v)->val, 1)
 524
 525 /* IOCInit Request message */
 526 typedef struct _MPI2_IOC_INIT_REQUEST {
 527         u_int8_t WhoInit;               /* 0x00 */
 528         u_int8_t Reserved1;             /* 0x01 */
 529         u_int8_t ChainOffset;           /* 0x02 */
 530         u_int8_t Function;              /* 0x03 */
 531         u_int16_t Reserved2;            /* 0x04 */
 532         u_int8_t Reserved3;             /* 0x06 */
 533         u_int8_t MsgFlags;              /* 0x07 */
 534         u_int8_t VP_ID;                 /* 0x08 */
 535         u_int8_t VF_ID;                 /* 0x09 */
 536         u_int16_t Reserved4;            /* 0x0A */
 537         u_int16_t MsgVersion;           /* 0x0C */
 538         u_int16_t HeaderVersion;        /* 0x0E */
 539         u_int32_t Reserved5;            /* 0x10 */
 540         u_int16_t Reserved6;            /* 0x14 */
 541         u_int8_t Reserved7;             /* 0x16 */
 542         u_int8_t HostMSIxVectors;       /* 0x17 */
 543         u_int16_t Reserved8;            /* 0x18 */
 544         u_int16_t SystemRequestFrameSize;       /* 0x1A */
 545         u_int16_t ReplyDescriptorPostQueueDepth;        /* 0x1C */
 546         u_int16_t ReplyFreeQueueDepth;  /* 0x1E */
 547         u_int32_t SenseBufferAddressHigh;       /* 0x20 */
 548         u_int32_t SystemReplyAddressHigh;       /* 0x24 */
 549         u_int64_t SystemRequestFrameBaseAddress;        /* 0x28 */
 550         u_int64_t ReplyDescriptorPostQueueAddress;      /* 0x30 */
 551         u_int64_t ReplyFreeQueueAddress;/* 0x38 */
 552         u_int64_t TimeStamp;            /* 0x40 */
 553 }       MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 554 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 555
 556 /*
 557  * MR private defines
 558  */
 559 #define MR_PD_INVALID                   0xFFFF
 560 #define MAX_SPAN_DEPTH                  8
 561 #define MAX_QUAD_DEPTH                  MAX_SPAN_DEPTH
 562 #define MAX_RAIDMAP_SPAN_DEPTH  (MAX_SPAN_DEPTH)
 563 #define MAX_ROW_SIZE                    32
 564 #define MAX_RAIDMAP_ROW_SIZE    (MAX_ROW_SIZE)
 565 #define MAX_LOGICAL_DRIVES              64
 566 #define MAX_LOGICAL_DRIVES_EXT  256
 567
 568 #define MAX_RAIDMAP_LOGICAL_DRIVES      (MAX_LOGICAL_DRIVES)
 569 #define MAX_RAIDMAP_VIEWS                       (MAX_LOGICAL_DRIVES)
 570
 571 #define MAX_ARRAYS                              128
 572 #define MAX_RAIDMAP_ARRAYS              (MAX_ARRAYS)
 573
 574 #define MAX_ARRAYS_EXT                  256
 575 #define MAX_API_ARRAYS_EXT              MAX_ARRAYS_EXT
 576
 577 #define MAX_PHYSICAL_DEVICES    256
 578 #define MAX_RAIDMAP_PHYSICAL_DEVICES    (MAX_PHYSICAL_DEVICES)
 579 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
 580
 581
 582 #define MRSAS_MAX_PD_CHANNELS           1
 583 #define MRSAS_MAX_LD_CHANNELS           1
 584 #define MRSAS_MAX_DEV_PER_CHANNEL       256
 585 #define MRSAS_DEFAULT_INIT_ID           -1
 586 #define MRSAS_MAX_LUN                           8
 587 #define MRSAS_DEFAULT_CMD_PER_LUN       256
 588 #define MRSAS_MAX_PD                            (MRSAS_MAX_PD_CHANNELS * \
 589                         MRSAS_MAX_DEV_PER_CHANNEL)
 590 #define MRSAS_MAX_LD_IDS                        (MRSAS_MAX_LD_CHANNELS * \
 591                         MRSAS_MAX_DEV_PER_CHANNEL)
 592
 593
 594 #define VD_EXT_DEBUG    0
 595
 596
 597 /*******************************************************************
 598  * RAID map related structures
 599  ********************************************************************/
 600 #pragma pack(1)
 601 typedef struct _MR_DEV_HANDLE_INFO {
 602         u_int16_t curDevHdl;
 603         u_int8_t validHandles;
 604         u_int8_t reserved;
 605         u_int16_t devHandle[2];
 606 }       MR_DEV_HANDLE_INFO;
 607
 608 #pragma pack()
 609
 610 typedef struct _MR_ARRAY_INFO {
 611         u_int16_t pd[MAX_RAIDMAP_ROW_SIZE];
 612 }       MR_ARRAY_INFO;
 613
 614 typedef struct _MR_QUAD_ELEMENT {
 615         u_int64_t logStart;
 616         u_int64_t logEnd;
 617         u_int64_t offsetInSpan;
 618         u_int32_t diff;
 619         u_int32_t reserved1;
 620 }       MR_QUAD_ELEMENT;
 621
 622 typedef struct _MR_SPAN_INFO {
 623         u_int32_t noElements;
 624         u_int32_t reserved1;
 625         MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
 626 }       MR_SPAN_INFO;
 627
 628 typedef struct _MR_LD_SPAN_ {
 629         u_int64_t startBlk;
 630         u_int64_t numBlks;
 631         u_int16_t arrayRef;
 632         u_int8_t spanRowSize;
 633         u_int8_t spanRowDataSize;
 634         u_int8_t reserved[4];
 635 }       MR_LD_SPAN;
 636
 637 typedef struct _MR_SPAN_BLOCK_INFO {
 638         u_int64_t num_rows;
 639         MR_LD_SPAN span;
 640         MR_SPAN_INFO block_span_info;
 641 }       MR_SPAN_BLOCK_INFO;
 642
 643 typedef struct _MR_LD_RAID {
 644         struct {
 645                 u_int32_t fpCapable:1;
 646                 u_int32_t reserved5:3;
 647                 u_int32_t ldPiMode:4;
 648                 u_int32_t pdPiMode:4;
 649                 u_int32_t encryptionType:8;
 650                 u_int32_t fpWriteCapable:1;
 651                 u_int32_t fpReadCapable:1;
 652                 u_int32_t fpWriteAcrossStripe:1;
 653                 u_int32_t fpReadAcrossStripe:1;
 654                 u_int32_t fpNonRWCapable:1;
 655                 u_int32_t reserved4:7;
 656         }       capability;
 657         u_int32_t reserved6;
 658         u_int64_t size;
 659
 660         u_int8_t spanDepth;
 661         u_int8_t level;
 662         u_int8_t stripeShift;
 663         u_int8_t rowSize;
 664
 665         u_int8_t rowDataSize;
 666         u_int8_t writeMode;
 667         u_int8_t PRL;
 668         u_int8_t SRL;
 669
 670         u_int16_t targetId;
 671         u_int8_t ldState;
 672         u_int8_t regTypeReqOnWrite;
 673         u_int8_t modFactor;
 674         u_int8_t regTypeReqOnRead;
 675         u_int16_t seqNum;
 676
 677         struct {
 678                 u_int32_t ldSyncRequired:1;
 679                 u_int32_t regTypeReqOnReadLsValid:1;
 680                 u_int32_t reserved:30;
 681         }       flags;
 682
 683         u_int8_t LUN[8];
 684         u_int8_t fpIoTimeoutForLd;
 685         u_int8_t reserved2[3];
 686         u_int32_t logicalBlockLength;
 687         struct {
 688                 u_int32_t LdPiExp:4;
 689                 u_int32_t LdLogicalBlockExp:4;
 690                 u_int32_t reserved1:24;
 691         }       exponent;
 692         u_int8_t reserved3[0x80 - 0x38];
 693 }       MR_LD_RAID;
 694
 695 typedef struct _MR_LD_SPAN_MAP {
 696         MR_LD_RAID ldRaid;
 697         u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE];
 698         MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
 699 }       MR_LD_SPAN_MAP;
 700
 701 typedef struct _MR_FW_RAID_MAP {
 702         u_int32_t totalSize;
 703         union {
 704                 struct {
 705                         u_int32_t maxLd;
 706                         u_int32_t maxSpanDepth;
 707                         u_int32_t maxRowSize;
 708                         u_int32_t maxPdCount;
 709                         u_int32_t maxArrays;
 710                 }       validationInfo;
 711                 u_int32_t version[5];
 712                 u_int32_t reserved1[5];
 713         }       raid_desc;
 714         u_int32_t ldCount;
 715         u_int32_t Reserved1;
 716
 717         /*
 718          * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For
 719          * example: if tgt Id is 4 and FW LD is 2, and there is only one LD,
 720          * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF,
 721          * 0x0,.....]. This is to help reduce the entire strcture size if
 722          * there are few LDs or driver is looking info for 1 LD only.
 723          */
 724         u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS];
 725         u_int8_t fpPdIoTimeoutSec;
 726         u_int8_t reserved2[7];
 727         MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
 728         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 729         MR_LD_SPAN_MAP ldSpanMap[1];
 730 }       MR_FW_RAID_MAP;
 731
 732
 733 typedef struct _MR_FW_RAID_MAP_EXT {
 734         /* Not used in new map */
 735         u_int32_t reserved;
 736
 737         union {
 738                 struct {
 739                         u_int32_t maxLd;
 740                         u_int32_t maxSpanDepth;
 741                         u_int32_t maxRowSize;
 742                         u_int32_t maxPdCount;
 743                         u_int32_t maxArrays;
 744                 }       validationInfo;
 745                 u_int32_t version[5];
 746                 u_int32_t reserved1[5];
 747         }       fw_raid_desc;
 748
 749         u_int8_t fpPdIoTimeoutSec;
 750         u_int8_t reserved2[7];
 751
 752         u_int16_t ldCount;
 753         u_int16_t arCount;
 754         u_int16_t spanCount;
 755         u_int16_t reserve3;
 756
 757         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 758         u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 759         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
 760         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
 761 }       MR_FW_RAID_MAP_EXT;
 762
 763
 764 typedef struct _MR_DRV_RAID_MAP {
 765         /*
 766          * Total size of this structure, including this field. This feild
 767          * will be manupulated by driver for ext raid map, else pick the
 768          * value from firmware raid map.
 769          */
 770         u_int32_t totalSize;
 771
 772         union {
 773                 struct {
 774                         u_int32_t maxLd;
 775                         u_int32_t maxSpanDepth;
 776                         u_int32_t maxRowSize;
 777                         u_int32_t maxPdCount;
 778                         u_int32_t maxArrays;
 779                 }       validationInfo;
 780                 u_int32_t version[5];
 781                 u_int32_t reserved1[5];
 782         }       drv_raid_desc;
 783
 784         /* timeout value used by driver in FP IOs */
 785         u_int8_t fpPdIoTimeoutSec;
 786         u_int8_t reserved2[7];
 787
 788         u_int16_t ldCount;
 789         u_int16_t arCount;
 790         u_int16_t spanCount;
 791         u_int16_t reserve3;
 792
 793         MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
 794         u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
 795         MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
 796         MR_LD_SPAN_MAP ldSpanMap[1];
 797
 798 }       MR_DRV_RAID_MAP;
 799
 800 /*
 801  * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is
 802  * created to sync with old raid. And it is mainly for code re-use purpose.
 803  */
 804
 805 #pragma pack(1)
 806 typedef struct _MR_DRV_RAID_MAP_ALL {
 807
 808         MR_DRV_RAID_MAP raidMap;
 809         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
 810 }       MR_DRV_RAID_MAP_ALL;
 811
 812 #pragma pack()
 813
 814 typedef struct _LD_LOAD_BALANCE_INFO {
 815         u_int8_t loadBalanceFlag;
 816         u_int8_t reserved1;
 817         mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
 818         u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES];
 819 }       LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO;
 820
 821 /* SPAN_SET is info caclulated from span info from Raid map per ld */
 822 typedef struct _LD_SPAN_SET {
 823         u_int64_t log_start_lba;
 824         u_int64_t log_end_lba;
 825         u_int64_t span_row_start;
 826         u_int64_t span_row_end;
 827         u_int64_t data_strip_start;
 828         u_int64_t data_strip_end;
 829         u_int64_t data_row_start;
 830         u_int64_t data_row_end;
 831         u_int8_t strip_offset[MAX_SPAN_DEPTH];
 832         u_int32_t span_row_data_width;
 833         u_int32_t diff;
 834         u_int32_t reserved[2];
 835 }       LD_SPAN_SET, *PLD_SPAN_SET;
 836
 837 typedef struct LOG_BLOCK_SPAN_INFO {
 838         LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
 839 }       LD_SPAN_INFO, *PLD_SPAN_INFO;
 840
 841 #pragma pack(1)
 842 typedef struct _MR_FW_RAID_MAP_ALL {
 843         MR_FW_RAID_MAP raidMap;
 844         MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
 845 }       MR_FW_RAID_MAP_ALL;
 846
 847 #pragma pack()
 848
 849 struct IO_REQUEST_INFO {
 850         u_int64_t ldStartBlock;
 851         u_int32_t numBlocks;
 852         u_int16_t ldTgtId;
 853         u_int8_t isRead;
 854         u_int16_t devHandle;
 855         u_int64_t pdBlock;
 856         u_int8_t fpOkForIo;
 857         u_int8_t IoforUnevenSpan;
 858         u_int8_t start_span;
 859         u_int8_t reserved;
 860         u_int64_t start_row;
 861         /* span[7:5], arm[4:0] */
 862         u_int8_t span_arm;
 863         u_int8_t pd_after_lb;
 864 };
 865
 866 typedef struct _MR_LD_TARGET_SYNC {
 867         u_int8_t targetId;
 868         u_int8_t reserved;
 869         u_int16_t seqNum;
 870 }       MR_LD_TARGET_SYNC;
 871
 872 #define IEEE_SGE_FLAGS_ADDR_MASK                (0x03)
 873 #define IEEE_SGE_FLAGS_SYSTEM_ADDR              (0x00)
 874 #define IEEE_SGE_FLAGS_IOCDDR_ADDR              (0x01)
 875 #define IEEE_SGE_FLAGS_IOCPLB_ADDR              (0x02)
 876 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR   (0x03)
 877 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT    (0x80)
 878 #define IEEE_SGE_FLAGS_END_OF_LIST              (0x40)
 879
 880 union desc_value {
 881         u_int64_t word;
 882         struct {
 883                 u_int32_t low;
 884                 u_int32_t high;
 885         }       u;
 886 };
 887
 888 /*******************************************************************
 889  * Temporary command
 890  ********************************************************************/
 891 struct mrsas_tmp_dcmd {
 892         bus_dma_tag_t tmp_dcmd_tag;
 893         bus_dmamap_t tmp_dcmd_dmamap;
 894         void   *tmp_dcmd_mem;
 895         bus_addr_t tmp_dcmd_phys_addr;
 896 };
 897
 898 /*******************************************************************
 899  * Register set, included legacy controllers 1068 and 1078,
 900  * structure extended for 1078 registers
 901  *******************************************************************/
 902 #pragma pack(1)
 903 typedef struct _mrsas_register_set {
 904         u_int32_t doorbell;             /* 0000h */
 905         u_int32_t fusion_seq_offset;    /* 0004h */
 906         u_int32_t fusion_host_diag;     /* 0008h */
 907         u_int32_t reserved_01;          /* 000Ch */
 908
 909         u_int32_t inbound_msg_0;        /* 0010h */
 910         u_int32_t inbound_msg_1;        /* 0014h */
 911         u_int32_t outbound_msg_0;       /* 0018h */
 912         u_int32_t outbound_msg_1;       /* 001Ch */
 913
 914         u_int32_t inbound_doorbell;     /* 0020h */
 915         u_int32_t inbound_intr_status;  /* 0024h */
 916         u_int32_t inbound_intr_mask;    /* 0028h */
 917
 918         u_int32_t outbound_doorbell;    /* 002Ch */
 919         u_int32_t outbound_intr_status; /* 0030h */
 920         u_int32_t outbound_intr_mask;   /* 0034h */
 921
 922         u_int32_t reserved_1[2];        /* 0038h */
 923
 924         u_int32_t inbound_queue_port;   /* 0040h */
 925         u_int32_t outbound_queue_port;  /* 0044h */
 926
 927         u_int32_t reserved_2[9];        /* 0048h */
 928         u_int32_t reply_post_host_index;/* 006Ch */
 929         u_int32_t reserved_2_2[12];     /* 0070h */
 930
 931         u_int32_t outbound_doorbell_clear;      /* 00A0h */
 932
 933         u_int32_t reserved_3[3];        /* 00A4h */
 934
 935         u_int32_t outbound_scratch_pad; /* 00B0h */
 936         u_int32_t outbound_scratch_pad_2;       /* 00B4h */
 937
 938         u_int32_t reserved_4[2];        /* 00B8h */
 939
 940         u_int32_t inbound_low_queue_port;       /* 00C0h */
 941
 942         u_int32_t inbound_high_queue_port;      /* 00C4h */
 943
 944         u_int32_t reserved_5;           /* 00C8h */
 945         u_int32_t res_6[11];            /* CCh */
 946         u_int32_t host_diag;
 947         u_int32_t seq_offset;
 948         u_int32_t index_registers[807]; /* 00CCh */
 949 }       mrsas_reg_set;
 950
 951 #pragma pack()
 952
 953 /*******************************************************************
 954  * Firmware Interface Defines
 955  *******************************************************************
 956  * MFI stands for MegaRAID SAS FW Interface. This is just a moniker
 957  * for protocol between the software and firmware. Commands are
 958  * issued using "message frames".
 959  ******************************************************************/
 960 /*
 961  * FW posts its state in upper 4 bits of outbound_msg_0 register
 962  */
 963 #define MFI_STATE_MASK                                  0xF0000000
 964 #define MFI_STATE_UNDEFINED                             0x00000000
 965 #define MFI_STATE_BB_INIT                               0x10000000
 966 #define MFI_STATE_FW_INIT                               0x40000000
 967 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 968 #define MFI_STATE_FW_INIT_2                             0x70000000
 969 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 970 #define MFI_STATE_BOOT_MESSAGE_PENDING  0x90000000
 971 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 972 #define MFI_STATE_READY                                 0xB0000000
 973 #define MFI_STATE_OPERATIONAL                   0xC0000000
 974 #define MFI_STATE_FAULT                                 0xF0000000
 975 #define MFI_RESET_REQUIRED                              0x00000001
 976 #define MFI_RESET_ADAPTER                               0x00000002
 977 #define MEGAMFI_FRAME_SIZE                              64
 978 #define MRSAS_MFI_FRAME_SIZE                    1024
 979 #define MRSAS_MFI_SENSE_SIZE                    128
 980
 981 /*
 982  * During FW init, clear pending cmds & reset state using inbound_msg_0
 983  *
 984  * ABORT        : Abort all pending cmds READY        : Move from OPERATIONAL to
 985  * READY state; discard queue info MFIMODE      : Discard (possible) low MFA
 986  * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from
 987  * BIOS or Driver HOTPLUG      : Resume from Hotplug MFI_STOP_ADP : Send
 988  * signal to FW to stop processing
 989  */
 990
 991 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC)
 992 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)
 993 #define DIAG_WRITE_ENABLE                       (0x00000080)
 994 #define DIAG_RESET_ADAPTER                      (0x00000004)
 995
 996 #define MFI_ADP_RESET                           0x00000040
 997 #define MFI_INIT_ABORT                          0x00000001
 998 #define MFI_INIT_READY                          0x00000002
 999 #define MFI_INIT_MFIMODE                        0x00000004
1000 #define MFI_INIT_CLEAR_HANDSHAKE        0x00000008
1001 #define MFI_INIT_HOTPLUG                        0x00000010
1002 #define MFI_STOP_ADP                            0x00000020
1003 #define MFI_RESET_FLAGS                         MFI_INIT_READY|         \
1004                                                                         MFI_INIT_MFIMODE|       \
1005                                                                         MFI_INIT_ABORT
1006
1007 /*
1008  * MFI frame flags
1009  */
1010 #define MFI_FRAME_POST_IN_REPLY_QUEUE                   0x0000
1011 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE              0x0001
1012 #define MFI_FRAME_SGL32                                                 0x0000
1013 #define MFI_FRAME_SGL64                                                 0x0002
1014 #define MFI_FRAME_SENSE32                                               0x0000
1015 #define MFI_FRAME_SENSE64                                               0x0004
1016 #define MFI_FRAME_DIR_NONE                                              0x0000
1017 #define MFI_FRAME_DIR_WRITE                                             0x0008
1018 #define MFI_FRAME_DIR_READ                                              0x0010
1019 #define MFI_FRAME_DIR_BOTH                                              0x0018
1020 #define MFI_FRAME_IEEE                                                  0x0020
1021
1022 /*
1023  * Definition for cmd_status
1024  */
1025 #define MFI_CMD_STATUS_POLL_MODE                                0xFF
1026
1027 /*
1028  * MFI command opcodes
1029  */
1030 #define MFI_CMD_INIT                                                    0x00
1031 #define MFI_CMD_LD_READ                                                 0x01
1032 #define MFI_CMD_LD_WRITE                                                0x02
1033 #define MFI_CMD_LD_SCSI_IO                                              0x03
1034 #define MFI_CMD_PD_SCSI_IO                                              0x04
1035 #define MFI_CMD_DCMD                                                    0x05
1036 #define MFI_CMD_ABORT                                                   0x06
1037 #define MFI_CMD_SMP                                                             0x07
1038 #define MFI_CMD_STP                                                             0x08
1039 #define MFI_CMD_INVALID                                                 0xff
1040
1041 #define MR_DCMD_CTRL_GET_INFO                                   0x01010000
1042 #define MR_DCMD_LD_GET_LIST                                             0x03010000
1043 #define MR_DCMD_CTRL_CACHE_FLUSH                                0x01101000
1044 #define MR_FLUSH_CTRL_CACHE                                             0x01
1045 #define MR_FLUSH_DISK_CACHE                                             0x02
1046
1047 #define MR_DCMD_CTRL_SHUTDOWN                                   0x01050000
1048 #define MR_DCMD_HIBERNATE_SHUTDOWN                              0x01060000
1049 #define MR_ENABLE_DRIVE_SPINDOWN                                0x01
1050
1051 #define MR_DCMD_CTRL_EVENT_GET_INFO                             0x01040100
1052 #define MR_DCMD_CTRL_EVENT_GET                                  0x01040300
1053 #define MR_DCMD_CTRL_EVENT_WAIT                                 0x01040500
1054 #define MR_DCMD_LD_GET_PROPERTIES                               0x03030000
1055
1056 #define MR_DCMD_CLUSTER                                                 0x08000000
1057 #define MR_DCMD_CLUSTER_RESET_ALL                               0x08010100
1058 #define MR_DCMD_CLUSTER_RESET_LD                                0x08010200
1059 #define MR_DCMD_PD_LIST_QUERY                                   0x02010100
1060
1061 #define MR_DCMD_CTRL_MISC_CPX                                   0x0100e200
1062 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET             0x0100e201
1063 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA                0x0100e202
1064 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER                0x0100e203
1065 #define MAX_MR_ROW_SIZE                                                 32
1066 #define MR_CPX_DIR_WRITE                                                1
1067 #define MR_CPX_DIR_READ                                                 0
1068 #define MR_CPX_VERSION                                                  1
1069
1070 #define MR_DCMD_CTRL_IO_METRICS_GET                             0x01170200
1071
1072 #define MR_EVT_CFG_CLEARED                                              0x0004
1073
1074 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1075 #define MR_EVT_PD_INSERTED                                              0x005b
1076 #define MR_EVT_PD_REMOVED                                               0x0070
1077 #define MR_EVT_LD_CREATED                                               0x008a
1078 #define MR_EVT_LD_DELETED                                               0x008b
1079 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1080 #define MR_EVT_LD_OFFLINE                                               0x00fc
1081 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1082 #define MR_EVT_CTRL_PERF_COLLECTION                             0x017e
1083
1084 /*
1085  * MFI command completion codes
1086  */
1087 enum MFI_STAT {
1088         MFI_STAT_OK = 0x00,
1089         MFI_STAT_INVALID_CMD = 0x01,
1090         MFI_STAT_INVALID_DCMD = 0x02,
1091         MFI_STAT_INVALID_PARAMETER = 0x03,
1092         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
1093         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
1094         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
1095         MFI_STAT_APP_IN_USE = 0x07,
1096         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
1097         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
1098         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
1099         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
1100         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
1101         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
1102         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
1103         MFI_STAT_FLASH_BUSY = 0x0f,
1104         MFI_STAT_FLASH_ERROR = 0x10,
1105         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
1106         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
1107         MFI_STAT_FLASH_NOT_OPEN = 0x13,
1108         MFI_STAT_FLASH_NOT_STARTED = 0x14,
1109         MFI_STAT_FLUSH_FAILED = 0x15,
1110         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
1111         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
1112         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
1113         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
1114         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
1115         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
1116         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
1117         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
1118         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
1119         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
1120         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
1121         MFI_STAT_MFC_HW_ERROR = 0x21,
1122         MFI_STAT_NO_HW_PRESENT = 0x22,
1123         MFI_STAT_NOT_FOUND = 0x23,
1124         MFI_STAT_NOT_IN_ENCL = 0x24,
1125         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
1126         MFI_STAT_PD_TYPE_WRONG = 0x26,
1127         MFI_STAT_PR_DISABLED = 0x27,
1128         MFI_STAT_ROW_INDEX_INVALID = 0x28,
1129         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
1130         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
1131         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
1132         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
1133         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
1134         MFI_STAT_SCSI_IO_FAILED = 0x2e,
1135         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
1136         MFI_STAT_SHUTDOWN_FAILED = 0x30,
1137         MFI_STAT_TIME_NOT_SET = 0x31,
1138         MFI_STAT_WRONG_STATE = 0x32,
1139         MFI_STAT_LD_OFFLINE = 0x33,
1140         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
1141         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
1142         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
1143         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
1144         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
1145         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
1146
1147         MFI_STAT_INVALID_STATUS = 0xFF
1148 };
1149
1150 /*
1151  * Number of mailbox bytes in DCMD message frame
1152  */
1153 #define MFI_MBOX_SIZE   12
1154
1155 enum MR_EVT_CLASS {
1156
1157         MR_EVT_CLASS_DEBUG = -2,
1158         MR_EVT_CLASS_PROGRESS = -1,
1159         MR_EVT_CLASS_INFO = 0,
1160         MR_EVT_CLASS_WARNING = 1,
1161         MR_EVT_CLASS_CRITICAL = 2,
1162         MR_EVT_CLASS_FATAL = 3,
1163         MR_EVT_CLASS_DEAD = 4,
1164
1165 };
1166
1167 enum MR_EVT_LOCALE {
1168
1169         MR_EVT_LOCALE_LD = 0x0001,
1170         MR_EVT_LOCALE_PD = 0x0002,
1171         MR_EVT_LOCALE_ENCL = 0x0004,
1172         MR_EVT_LOCALE_BBU = 0x0008,
1173         MR_EVT_LOCALE_SAS = 0x0010,
1174         MR_EVT_LOCALE_CTRL = 0x0020,
1175         MR_EVT_LOCALE_CONFIG = 0x0040,
1176         MR_EVT_LOCALE_CLUSTER = 0x0080,
1177         MR_EVT_LOCALE_ALL = 0xffff,
1178
1179 };
1180
1181 enum MR_EVT_ARGS {
1182
1183         MR_EVT_ARGS_NONE,
1184         MR_EVT_ARGS_CDB_SENSE,
1185         MR_EVT_ARGS_LD,
1186         MR_EVT_ARGS_LD_COUNT,
1187         MR_EVT_ARGS_LD_LBA,
1188         MR_EVT_ARGS_LD_OWNER,
1189         MR_EVT_ARGS_LD_LBA_PD_LBA,
1190         MR_EVT_ARGS_LD_PROG,
1191         MR_EVT_ARGS_LD_STATE,
1192         MR_EVT_ARGS_LD_STRIP,
1193         MR_EVT_ARGS_PD,
1194         MR_EVT_ARGS_PD_ERR,
1195         MR_EVT_ARGS_PD_LBA,
1196         MR_EVT_ARGS_PD_LBA_LD,
1197         MR_EVT_ARGS_PD_PROG,
1198         MR_EVT_ARGS_PD_STATE,
1199         MR_EVT_ARGS_PCI,
1200         MR_EVT_ARGS_RATE,
1201         MR_EVT_ARGS_STR,
1202         MR_EVT_ARGS_TIME,
1203         MR_EVT_ARGS_ECC,
1204         MR_EVT_ARGS_LD_PROP,
1205         MR_EVT_ARGS_PD_SPARE,
1206         MR_EVT_ARGS_PD_INDEX,
1207         MR_EVT_ARGS_DIAG_PASS,
1208         MR_EVT_ARGS_DIAG_FAIL,
1209         MR_EVT_ARGS_PD_LBA_LBA,
1210         MR_EVT_ARGS_PORT_PHY,
1211         MR_EVT_ARGS_PD_MISSING,
1212         MR_EVT_ARGS_PD_ADDRESS,
1213         MR_EVT_ARGS_BITMAP,
1214         MR_EVT_ARGS_CONNECTOR,
1215         MR_EVT_ARGS_PD_PD,
1216         MR_EVT_ARGS_PD_FRU,
1217         MR_EVT_ARGS_PD_PATHINFO,
1218         MR_EVT_ARGS_PD_POWER_STATE,
1219         MR_EVT_ARGS_GENERIC,
1220 };
1221
1222
1223 /*
1224  * Thunderbolt (and later) Defines
1225  */
1226 #define MRSAS_MAX_SZ_CHAIN_FRAME                                        1024
1227 #define MFI_FUSION_ENABLE_INTERRUPT_MASK                        (0x00000009)
1228 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE           256
1229 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST         0xF0
1230 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST                       0xF1
1231 #define MRSAS_LOAD_BALANCE_FLAG                                         0x1
1232 #define MRSAS_DCMD_MBOX_PEND_FLAG                                       0x1
1233 #define HOST_DIAG_WRITE_ENABLE                                          0x80
1234 #define HOST_DIAG_RESET_ADAPTER                                         0x4
1235 #define MRSAS_TBOLT_MAX_RESET_TRIES                                     3
1236 #define MRSAS_MAX_MFI_CMDS                                                      32
1237
1238 /*
1239  * Invader Defines
1240  */
1241 #define MPI2_TYPE_CUDA                                                          0x2
1242 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH       0x4000
1243 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0                      0x00
1244 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1                      0x10
1245 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA                      0x80
1246 #define MR_RL_FLAGS_SEQ_NUM_ENABLE                                      0x8
1247
1248 /*
1249  * T10 PI defines
1250  */
1251 #define MR_PROT_INFO_TYPE_CONTROLLER                            0x8
1252 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD                          0x7f
1253 #define MRSAS_SCSI_SERVICE_ACTION_READ32                        0x9
1254 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32                       0xB
1255 #define MRSAS_SCSI_ADDL_CDB_LEN                                         0x18
1256 #define MRSAS_RD_WR_PROTECT_CHECK_ALL                           0x20
1257 #define MRSAS_RD_WR_PROTECT_CHECK_NONE                          0x60
1258 #define MRSAS_SCSIBLOCKSIZE                                                     512
1259
1260 /*
1261  * Raid context flags
1262  */
1263 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT        0x4
1264 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK         0x30
1265 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
1266         MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
1267         MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
1268 }       MR_RAID_FLAGS_IO_SUB_TYPE;
1269
1270 /*
1271  * Request descriptor types
1272  */
1273 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO          0x7
1274 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA            0x1
1275 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK        0x2
1276 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT     1
1277 #define MRSAS_FP_CMD_LEN                                        16
1278 #define MRSAS_FUSION_IN_RESET                           0
1279
1280 #define RAID_CTX_SPANARM_ARM_SHIFT                      (0)
1281 #define RAID_CTX_SPANARM_ARM_MASK                       (0x1f)
1282 #define RAID_CTX_SPANARM_SPAN_SHIFT                     (5)
1283 #define RAID_CTX_SPANARM_SPAN_MASK                      (0xE0)
1284
1285 /*
1286  * Define region lock types
1287  */
1288 typedef enum _REGION_TYPE {
1289         REGION_TYPE_UNUSED = 0,
1290         REGION_TYPE_SHARED_READ = 1,
1291         REGION_TYPE_SHARED_WRITE = 2,
1292         REGION_TYPE_EXCLUSIVE = 3,
1293 }       REGION_TYPE;
1294
1295
1296 /*
1297  * SCSI-CAM Related Defines
1298  */
1299 #define MRSAS_SCSI_MAX_LUNS                             0
1300 #define MRSAS_SCSI_INITIATOR_ID                 255
1301 #define MRSAS_SCSI_MAX_CMDS                             8
1302 #define MRSAS_SCSI_MAX_CDB_LEN                  16
1303 #define MRSAS_SCSI_SENSE_BUFFERSIZE             96
1304 #define MRSAS_MAX_SGL                                   70
1305 #define MRSAS_MAX_IO_SIZE                               (256 * 1024)
1306 #define MRSAS_INTERNAL_CMDS                             32
1307
1308 /* Request types */
1309 #define MRSAS_REQ_TYPE_INTERNAL_CMD             0x0
1310 #define MRSAS_REQ_TYPE_AEN_FETCH                0x1
1311 #define MRSAS_REQ_TYPE_PASSTHRU                 0x2
1312 #define MRSAS_REQ_TYPE_GETSET_PARAM             0x3
1313 #define MRSAS_REQ_TYPE_SCSI_IO                  0x4
1314
1315 /* Request states */
1316 #define MRSAS_REQ_STATE_FREE                    0
1317 #define MRSAS_REQ_STATE_BUSY                    1
1318 #define MRSAS_REQ_STATE_TRAN                    2
1319 #define MRSAS_REQ_STATE_COMPLETE                3
1320
1321 typedef enum _MR_SCSI_CMD_TYPE {
1322         READ_WRITE_LDIO = 0,
1323         NON_READ_WRITE_LDIO = 1,
1324         READ_WRITE_SYSPDIO = 2,
1325         NON_READ_WRITE_SYSPDIO = 3,
1326 }       MR_SCSI_CMD_TYPE;
1327
1328 enum mrsas_req_flags {
1329         MRSAS_DIR_UNKNOWN = 0x1,
1330         MRSAS_DIR_IN = 0x2,
1331         MRSAS_DIR_OUT = 0x4,
1332         MRSAS_DIR_NONE = 0x8,
1333 };
1334
1335 /*
1336  * Adapter Reset States
1337  */
1338 enum {
1339         MRSAS_HBA_OPERATIONAL = 0,
1340         MRSAS_ADPRESET_SM_INFAULT = 1,
1341         MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1342         MRSAS_ADPRESET_SM_OPERATIONAL = 3,
1343         MRSAS_HW_CRITICAL_ERROR = 4,
1344         MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1345 };
1346
1347 /*
1348  * MPT Command Structure
1349  */
1350 struct mrsas_mpt_cmd {
1351         MRSAS_RAID_SCSI_IO_REQUEST *io_request;
1352         bus_addr_t io_request_phys_addr;
1353         MPI2_SGE_IO_UNION *chain_frame;
1354         bus_addr_t chain_frame_phys_addr;
1355         u_int32_t sge_count;
1356         u_int8_t *sense;
1357         bus_addr_t sense_phys_addr;
1358         u_int8_t retry_for_fw_reset;
1359         MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1360         u_int32_t sync_cmd_idx;
1361         u_int32_t index;
1362         u_int8_t flags;
1363         u_int8_t pd_r1_lb;
1364         u_int8_t load_balance;
1365         bus_size_t length;
1366         u_int32_t error_code;
1367         bus_dmamap_t data_dmamap;
1368         void   *data;
1369         union ccb *ccb_ptr;
1370         struct callout cm_callout;
1371         struct mrsas_softc *sc;
1372         TAILQ_ENTRY(mrsas_mpt_cmd) next;
1373 };
1374
1375 /*
1376  * MFI Command Structure
1377  */
1378 struct mrsas_mfi_cmd {
1379         union mrsas_frame *frame;
1380         bus_dmamap_t frame_dmamap;
1381         void   *frame_mem;
1382         bus_addr_t frame_phys_addr;
1383         u_int8_t *sense;
1384         bus_dmamap_t sense_dmamap;
1385         void   *sense_mem;
1386         bus_addr_t sense_phys_addr;
1387         u_int32_t index;
1388         u_int8_t sync_cmd;
1389         u_int8_t cmd_status;
1390         u_int8_t abort_aen;
1391         u_int8_t retry_for_fw_reset;
1392         struct mrsas_softc *sc;
1393         union ccb *ccb_ptr;
1394         union {
1395                 struct {
1396                         u_int16_t smid;
1397                         u_int16_t resvd;
1398                 }       context;
1399                 u_int32_t frame_count;
1400         }       cmd_id;
1401         TAILQ_ENTRY(mrsas_mfi_cmd) next;
1402 };
1403
1404
1405 /*
1406  * define constants for device list query options
1407  */
1408 enum MR_PD_QUERY_TYPE {
1409         MR_PD_QUERY_TYPE_ALL = 0,
1410         MR_PD_QUERY_TYPE_STATE = 1,
1411         MR_PD_QUERY_TYPE_POWER_STATE = 2,
1412         MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
1413         MR_PD_QUERY_TYPE_SPEED = 4,
1414         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
1415 };
1416
1417 #define MR_EVT_CFG_CLEARED                                              0x0004
1418 #define MR_EVT_LD_STATE_CHANGE                                  0x0051
1419 #define MR_EVT_PD_INSERTED                                              0x005b
1420 #define MR_EVT_PD_REMOVED                                               0x0070
1421 #define MR_EVT_LD_CREATED                                               0x008a
1422 #define MR_EVT_LD_DELETED                                               0x008b
1423 #define MR_EVT_FOREIGN_CFG_IMPORTED                             0x00db
1424 #define MR_EVT_LD_OFFLINE                                               0x00fc
1425 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
1426
1427 enum MR_PD_STATE {
1428         MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1429         MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
1430         MR_PD_STATE_HOT_SPARE = 0x02,
1431         MR_PD_STATE_OFFLINE = 0x10,
1432         MR_PD_STATE_FAILED = 0x11,
1433         MR_PD_STATE_REBUILD = 0x14,
1434         MR_PD_STATE_ONLINE = 0x18,
1435         MR_PD_STATE_COPYBACK = 0x20,
1436         MR_PD_STATE_SYSTEM = 0x40,
1437 };
1438
1439 /*
1440  * defines the physical drive address structure
1441  */
1442 #pragma pack(1)
1443 struct MR_PD_ADDRESS {
1444         u_int16_t deviceId;
1445         u_int16_t enclDeviceId;
1446
1447         union {
1448                 struct {
1449                         u_int8_t enclIndex;
1450                         u_int8_t slotNumber;
1451                 }       mrPdAddress;
1452                 struct {
1453                         u_int8_t enclPosition;
1454                         u_int8_t enclConnectorIndex;
1455                 }       mrEnclAddress;
1456         }       u1;
1457         u_int8_t scsiDevType;
1458         union {
1459                 u_int8_t connectedPortBitmap;
1460                 u_int8_t connectedPortNumbers;
1461         }       u2;
1462         u_int64_t sasAddr[2];
1463 };
1464
1465 #pragma pack()
1466
1467 /*
1468  * defines the physical drive list structure
1469  */
1470 #pragma pack(1)
1471 struct MR_PD_LIST {
1472         u_int32_t size;
1473         u_int32_t count;
1474         struct MR_PD_ADDRESS addr[1];
1475 };
1476
1477 #pragma pack()
1478
1479 #pragma pack(1)
1480 struct mrsas_pd_list {
1481         u_int16_t tid;
1482         u_int8_t driveType;
1483         u_int8_t driveState;
1484 };
1485
1486 #pragma pack()
1487
1488 /*
1489  * defines the logical drive reference structure
1490  */
1491 typedef union _MR_LD_REF {
1492         struct {
1493                 u_int8_t targetId;
1494                 u_int8_t reserved;
1495                 u_int16_t seqNum;
1496         }       ld_context;
1497         u_int32_t ref;
1498 }       MR_LD_REF;
1499
1500
1501 /*
1502  * defines the logical drive list structure
1503  */
1504 #pragma pack(1)
1505 struct MR_LD_LIST {
1506         u_int32_t ldCount;
1507         u_int32_t reserved;
1508         struct {
1509                 MR_LD_REF ref;
1510                 u_int8_t state;
1511                 u_int8_t reserved[3];
1512                 u_int64_t size;
1513         }       ldList[MAX_LOGICAL_DRIVES_EXT];
1514 };
1515
1516 #pragma pack()
1517
1518 /*
1519  * SAS controller properties
1520  */
1521 #pragma pack(1)
1522 struct mrsas_ctrl_prop {
1523         u_int16_t seq_num;
1524         u_int16_t pred_fail_poll_interval;
1525         u_int16_t intr_throttle_count;
1526         u_int16_t intr_throttle_timeouts;
1527         u_int8_t rebuild_rate;
1528         u_int8_t patrol_read_rate;
1529         u_int8_t bgi_rate;
1530         u_int8_t cc_rate;
1531         u_int8_t recon_rate;
1532         u_int8_t cache_flush_interval;
1533         u_int8_t spinup_drv_count;
1534         u_int8_t spinup_delay;
1535         u_int8_t cluster_enable;
1536         u_int8_t coercion_mode;
1537         u_int8_t alarm_enable;
1538         u_int8_t disable_auto_rebuild;
1539         u_int8_t disable_battery_warn;
1540         u_int8_t ecc_bucket_size;
1541         u_int16_t ecc_bucket_leak_rate;
1542         u_int8_t restore_hotspare_on_insertion;
1543         u_int8_t expose_encl_devices;
1544         u_int8_t maintainPdFailHistory;
1545         u_int8_t disallowHostRequestReordering;
1546         u_int8_t abortCCOnError;
1547         u_int8_t loadBalanceMode;
1548         u_int8_t disableAutoDetectBackplane;
1549         u_int8_t snapVDSpace;
1550         /*
1551          * Add properties that can be controlled by a bit in the following
1552          * structure.
1553          */
1554         struct {
1555                 u_int32_t copyBackDisabled:1;
1556                 u_int32_t SMARTerEnabled:1;
1557                 u_int32_t prCorrectUnconfiguredAreas:1;
1558                 u_int32_t useFdeOnly:1;
1559                 u_int32_t disableNCQ:1;
1560                 u_int32_t SSDSMARTerEnabled:1;
1561                 u_int32_t SSDPatrolReadEnabled:1;
1562                 u_int32_t enableSpinDownUnconfigured:1;
1563                 u_int32_t autoEnhancedImport:1;
1564                 u_int32_t enableSecretKeyControl:1;
1565                 u_int32_t disableOnlineCtrlReset:1;
1566                 u_int32_t allowBootWithPinnedCache:1;
1567                 u_int32_t disableSpinDownHS:1;
1568                 u_int32_t enableJBOD:1;
1569                 u_int32_t disableCacheBypass:1;
1570                 u_int32_t useDiskActivityForLocate:1;
1571                 u_int32_t enablePI:1;
1572                 u_int32_t preventPIImport:1;
1573                 u_int32_t useGlobalSparesForEmergency:1;
1574                 u_int32_t useUnconfGoodForEmergency:1;
1575                 u_int32_t useEmergencySparesforSMARTer:1;
1576                 u_int32_t forceSGPIOForQuadOnly:1;
1577                 u_int32_t enableConfigAutoBalance:1;
1578                 u_int32_t enableVirtualCache:1;
1579                 u_int32_t enableAutoLockRecovery:1;
1580                 u_int32_t disableImmediateIO:1;
1581                 u_int32_t disableT10RebuildAssist:1;
1582                 u_int32_t ignore64ldRestriction:1;
1583                 u_int32_t enableSwZone:1;
1584                 u_int32_t limitMaxRateSATA3G:1;
1585                 u_int32_t reserved:2;
1586         }       OnOffProperties;
1587         u_int8_t autoSnapVDSpace;
1588         u_int8_t viewSpace;
1589         u_int16_t spinDownTime;
1590         u_int8_t reserved[24];
1591
1592 };
1593
1594 #pragma pack()
1595
1596
1597 /*
1598  * SAS controller information
1599  */
1600 struct mrsas_ctrl_info {
1601         /*
1602          * PCI device information
1603          */
1604         struct {
1605                 u_int16_t vendor_id;
1606                 u_int16_t device_id;
1607                 u_int16_t sub_vendor_id;
1608                 u_int16_t sub_device_id;
1609                 u_int8_t reserved[24];
1610         } __packed pci;
1611         /*
1612          * Host interface information
1613          */
1614         struct {
1615                 u_int8_t PCIX:1;
1616                 u_int8_t PCIE:1;
1617                 u_int8_t iSCSI:1;
1618                 u_int8_t SAS_3G:1;
1619                 u_int8_t reserved_0:4;
1620                 u_int8_t reserved_1[6];
1621                 u_int8_t port_count;
1622                 u_int64_t port_addr[8];
1623         } __packed host_interface;
1624         /*
1625          * Device (backend) interface information
1626          */
1627         struct {
1628                 u_int8_t SPI:1;
1629                 u_int8_t SAS_3G:1;
1630                 u_int8_t SATA_1_5G:1;
1631                 u_int8_t SATA_3G:1;
1632                 u_int8_t reserved_0:4;
1633                 u_int8_t reserved_1[6];
1634                 u_int8_t port_count;
1635                 u_int64_t port_addr[8];
1636         } __packed device_interface;
1637
1638         u_int32_t image_check_word;
1639         u_int32_t image_component_count;
1640
1641         struct {
1642                 char    name[8];
1643                 char    version[32];
1644                 char    build_date[16];
1645                 char    built_time[16];
1646         } __packed image_component[8];
1647
1648         u_int32_t pending_image_component_count;
1649
1650         struct {
1651                 char    name[8];
1652                 char    version[32];
1653                 char    build_date[16];
1654                 char    build_time[16];
1655         } __packed pending_image_component[8];
1656
1657         u_int8_t max_arms;
1658         u_int8_t max_spans;
1659         u_int8_t max_arrays;
1660         u_int8_t max_lds;
1661         char    product_name[80];
1662         char    serial_no[32];
1663
1664         /*
1665          * Other physical/controller/operation information. Indicates the
1666          * presence of the hardware
1667          */
1668         struct {
1669                 u_int32_t bbu:1;
1670                 u_int32_t alarm:1;
1671                 u_int32_t nvram:1;
1672                 u_int32_t uart:1;
1673                 u_int32_t reserved:28;
1674         } __packed hw_present;
1675
1676         u_int32_t current_fw_time;
1677
1678         /*
1679          * Maximum data transfer sizes
1680          */
1681         u_int16_t max_concurrent_cmds;
1682         u_int16_t max_sge_count;
1683         u_int32_t max_request_size;
1684
1685         /*
1686          * Logical and physical device counts
1687          */
1688         u_int16_t ld_present_count;
1689         u_int16_t ld_degraded_count;
1690         u_int16_t ld_offline_count;
1691
1692         u_int16_t pd_present_count;
1693         u_int16_t pd_disk_present_count;
1694         u_int16_t pd_disk_pred_failure_count;
1695         u_int16_t pd_disk_failed_count;
1696
1697         /*
1698          * Memory size information
1699          */
1700         u_int16_t nvram_size;
1701         u_int16_t memory_size;
1702         u_int16_t flash_size;
1703
1704         /*
1705          * Error counters
1706          */
1707         u_int16_t mem_correctable_error_count;
1708         u_int16_t mem_uncorrectable_error_count;
1709
1710         /*
1711          * Cluster information
1712          */
1713         u_int8_t cluster_permitted;
1714         u_int8_t cluster_active;
1715
1716         /*
1717          * Additional max data transfer sizes
1718          */
1719         u_int16_t max_strips_per_io;
1720
1721         /*
1722          * Controller capabilities structures
1723          */
1724         struct {
1725                 u_int32_t raid_level_0:1;
1726                 u_int32_t raid_level_1:1;
1727                 u_int32_t raid_level_5:1;
1728                 u_int32_t raid_level_1E:1;
1729                 u_int32_t raid_level_6:1;
1730                 u_int32_t reserved:27;
1731         } __packed raid_levels;
1732
1733         struct {
1734                 u_int32_t rbld_rate:1;
1735                 u_int32_t cc_rate:1;
1736                 u_int32_t bgi_rate:1;
1737                 u_int32_t recon_rate:1;
1738                 u_int32_t patrol_rate:1;
1739                 u_int32_t alarm_control:1;
1740                 u_int32_t cluster_supported:1;
1741                 u_int32_t bbu:1;
1742                 u_int32_t spanning_allowed:1;
1743                 u_int32_t dedicated_hotspares:1;
1744                 u_int32_t revertible_hotspares:1;
1745                 u_int32_t foreign_config_import:1;
1746                 u_int32_t self_diagnostic:1;
1747                 u_int32_t mixed_redundancy_arr:1;
1748                 u_int32_t global_hot_spares:1;
1749                 u_int32_t reserved:17;
1750         } __packed adapter_operations;
1751
1752         struct {
1753                 u_int32_t read_policy:1;
1754                 u_int32_t write_policy:1;
1755                 u_int32_t io_policy:1;
1756                 u_int32_t access_policy:1;
1757                 u_int32_t disk_cache_policy:1;
1758                 u_int32_t reserved:27;
1759         } __packed ld_operations;
1760
1761         struct {
1762                 u_int8_t min;
1763                 u_int8_t max;
1764                 u_int8_t reserved[2];
1765         } __packed stripe_sz_ops;
1766
1767         struct {
1768                 u_int32_t force_online:1;
1769                 u_int32_t force_offline:1;
1770                 u_int32_t force_rebuild:1;
1771                 u_int32_t reserved:29;
1772         } __packed pd_operations;
1773
1774         struct {
1775                 u_int32_t ctrl_supports_sas:1;
1776                 u_int32_t ctrl_supports_sata:1;
1777                 u_int32_t allow_mix_in_encl:1;
1778                 u_int32_t allow_mix_in_ld:1;
1779                 u_int32_t allow_sata_in_cluster:1;
1780                 u_int32_t reserved:27;
1781         } __packed pd_mix_support;
1782
1783         /*
1784          * Define ECC single-bit-error bucket information
1785          */
1786         u_int8_t ecc_bucket_count;
1787         u_int8_t reserved_2[11];
1788
1789         /*
1790          * Include the controller properties (changeable items)
1791          */
1792         struct mrsas_ctrl_prop properties;
1793
1794         /*
1795          * Define FW pkg version (set in envt v'bles on OEM basis)
1796          */
1797         char    package_version[0x60];
1798
1799         u_int64_t deviceInterfacePortAddr2[8];
1800         u_int8_t reserved3[128];
1801
1802         struct {
1803                 u_int16_t minPdRaidLevel_0:4;
1804                 u_int16_t maxPdRaidLevel_0:12;
1805
1806                 u_int16_t minPdRaidLevel_1:4;
1807                 u_int16_t maxPdRaidLevel_1:12;
1808
1809                 u_int16_t minPdRaidLevel_5:4;
1810                 u_int16_t maxPdRaidLevel_5:12;
1811
1812                 u_int16_t minPdRaidLevel_1E:4;
1813                 u_int16_t maxPdRaidLevel_1E:12;
1814
1815                 u_int16_t minPdRaidLevel_6:4;
1816                 u_int16_t maxPdRaidLevel_6:12;
1817
1818                 u_int16_t minPdRaidLevel_10:4;
1819                 u_int16_t maxPdRaidLevel_10:12;
1820
1821                 u_int16_t minPdRaidLevel_50:4;
1822                 u_int16_t maxPdRaidLevel_50:12;
1823
1824                 u_int16_t minPdRaidLevel_60:4;
1825                 u_int16_t maxPdRaidLevel_60:12;
1826
1827                 u_int16_t minPdRaidLevel_1E_RLQ0:4;
1828                 u_int16_t maxPdRaidLevel_1E_RLQ0:12;
1829
1830                 u_int16_t minPdRaidLevel_1E0_RLQ0:4;
1831                 u_int16_t maxPdRaidLevel_1E0_RLQ0:12;
1832
1833                 u_int16_t reserved[6];
1834         }       pdsForRaidLevels;
1835
1836         u_int16_t maxPds;               /* 0x780 */
1837         u_int16_t maxDedHSPs;           /* 0x782 */
1838         u_int16_t maxGlobalHSPs;        /* 0x784 */
1839         u_int16_t ddfSize;              /* 0x786 */
1840         u_int8_t maxLdsPerArray;        /* 0x788 */
1841         u_int8_t partitionsInDDF;       /* 0x789 */
1842         u_int8_t lockKeyBinding;        /* 0x78a */
1843         u_int8_t maxPITsPerLd;          /* 0x78b */
1844         u_int8_t maxViewsPerLd;         /* 0x78c */
1845         u_int8_t maxTargetId;           /* 0x78d */
1846         u_int16_t maxBvlVdSize;         /* 0x78e */
1847
1848         u_int16_t maxConfigurableSSCSize;       /* 0x790 */
1849         u_int16_t currentSSCsize;       /* 0x792 */
1850
1851         char    expanderFwVersion[12];  /* 0x794 */
1852
1853         u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */
1854
1855         u_int16_t cacheMemorySize;      /* 0x7A2 */
1856
1857         struct {                        /* 0x7A4 */
1858                 u_int32_t supportPIcontroller:1;
1859                 u_int32_t supportLdPIType1:1;
1860                 u_int32_t supportLdPIType2:1;
1861                 u_int32_t supportLdPIType3:1;
1862                 u_int32_t supportLdBBMInfo:1;
1863                 u_int32_t supportShieldState:1;
1864                 u_int32_t blockSSDWriteCacheChange:1;
1865                 u_int32_t supportSuspendResumeBGops:1;
1866                 u_int32_t supportEmergencySpares:1;
1867                 u_int32_t supportSetLinkSpeed:1;
1868                 u_int32_t supportBootTimePFKChange:1;
1869                 u_int32_t supportJBOD:1;
1870                 u_int32_t disableOnlinePFKChange:1;
1871                 u_int32_t supportPerfTuning:1;
1872                 u_int32_t supportSSDPatrolRead:1;
1873                 u_int32_t realTimeScheduler:1;
1874
1875                 u_int32_t supportResetNow:1;
1876                 u_int32_t supportEmulatedDrives:1;
1877                 u_int32_t headlessMode:1;
1878                 u_int32_t dedicatedHotSparesLimited:1;
1879
1880
1881                 u_int32_t supportUnevenSpans:1;
1882                 u_int32_t reserved:11;
1883         }       adapterOperations2;
1884
1885         u_int8_t driverVersion[32];     /* 0x7A8 */
1886         u_int8_t maxDAPdCountSpinup60;  /* 0x7C8 */
1887         u_int8_t temperatureROC;        /* 0x7C9 */
1888         u_int8_t temperatureCtrl;       /* 0x7CA */
1889         u_int8_t reserved4;             /* 0x7CB */
1890         u_int16_t maxConfigurablePds;   /* 0x7CC */
1891
1892
1893         u_int8_t reserved5[2];          /* 0x7CD reserved */
1894
1895         struct {
1896                 u_int32_t peerIsPresent:1;
1897                 u_int32_t peerIsIncompatible:1;
1898
1899                 u_int32_t hwIncompatible:1;
1900                 u_int32_t fwVersionMismatch:1;
1901                 u_int32_t ctrlPropIncompatible:1;
1902                 u_int32_t premiumFeatureMismatch:1;
1903                 u_int32_t reserved:26;
1904         }       cluster;
1905
1906         char    clusterId[16];          /* 0x7D4 */
1907
1908         char    reserved6[4];           /* 0x7E4 RESERVED FOR IOV */
1909
1910         struct {                        /* 0x7E8 */
1911                 u_int32_t supportPersonalityChange:2;
1912                 u_int32_t supportThermalPollInterval:1;
1913                 u_int32_t supportDisableImmediateIO:1;
1914                 u_int32_t supportT10RebuildAssist:1;
1915                 u_int32_t supportMaxExtLDs:1;
1916                 u_int32_t supportCrashDump:1;
1917                 u_int32_t supportSwZone:1;
1918                 u_int32_t supportDebugQueue:1;
1919                 u_int32_t supportNVCacheErase:1;
1920                 u_int32_t supportForceTo512e:1;
1921                 u_int32_t supportHOQRebuild:1;
1922                 u_int32_t supportAllowedOpsforDrvRemoval:1;
1923                 u_int32_t supportDrvActivityLEDSetting:1;
1924                 u_int32_t supportNVDRAM:1;
1925                 u_int32_t supportForceFlash:1;
1926                 u_int32_t supportDisableSESMonitoring:1;
1927                 u_int32_t supportCacheBypassModes:1;
1928                 u_int32_t supportSecurityonJBOD:1;
1929                 u_int32_t discardCacheDuringLDDelete:1;
1930                 u_int32_t reserved:12;
1931         }       adapterOperations3;
1932
1933         u_int8_t pad[0x800 - 0x7EC];    /* 0x7EC */
1934 } __packed;
1935
1936 /*
1937  * When SCSI mid-layer calls driver's reset routine, driver waits for
1938  * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1939  * that the driver cannot _actually_ abort or reset pending commands. While
1940  * it is waiting for the commands to complete, it prints a diagnostic message
1941  * every MRSAS_RESET_NOTICE_INTERVAL seconds
1942  */
1943 #define MRSAS_RESET_WAIT_TIME                   180
1944 #define MRSAS_INTERNAL_CMD_WAIT_TIME    180
1945 #define MRSAS_IOC_INIT_WAIT_TIME                60
1946 #define MRSAS_RESET_NOTICE_INTERVAL             5
1947 #define MRSAS_IOCTL_CMD                                 0
1948 #define MRSAS_DEFAULT_CMD_TIMEOUT               90
1949 #define MRSAS_THROTTLE_QUEUE_DEPTH              16
1950
1951 /*
1952  * MSI-x regsiters offset defines
1953  */
1954 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET   (0x0000030C)
1955 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET               (0x0000006C)
1956 #define MR_MAX_REPLY_QUEUES_OFFSET                              (0x0000001F)
1957 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET                  (0x003FC000)
1958 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
1959 #define MR_MAX_MSIX_REG_ARRAY                                   16
1960
1961 /*
1962  * FW reports the maximum of number of commands that it can accept (maximum
1963  * commands that can be outstanding) at any time. The driver must report a
1964  * lower number to the mid layer because it can issue a few internal commands
1965  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1966  * is shown below
1967  */
1968 #define MRSAS_INT_CMDS                  32
1969 #define MRSAS_SKINNY_INT_CMDS   5
1970 #define MRSAS_MAX_MSIX_QUEUES   128
1971
1972 /*
1973  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs
1974  * based on the size of bus_addr_t
1975  */
1976 #define IS_DMA64                                                        (sizeof(bus_addr_t) == 8)
1977
1978 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT        0x00000001
1979 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
1980 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE     0x00000002
1981 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
1982
1983 #define MFI_OB_INTR_STATUS_MASK                         0x00000002
1984 #define MFI_POLL_TIMEOUT_SECS                           60
1985
1986 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
1987 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
1988 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          0x00000001
1989 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
1990 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
1991 #define MFI_1068_PCSR_OFFSET                            0x84
1992 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
1993 #define MFI_1068_FW_READY                                       0xDDDD0000
1994
1995 typedef union _MFI_CAPABILITIES {
1996         struct {
1997                 u_int32_t support_fp_remote_lun:1;
1998                 u_int32_t support_additional_msix:1;
1999                 u_int32_t support_fastpath_wb:1;
2000                 u_int32_t support_max_255lds:1;
2001                 u_int32_t support_ndrive_r1_lb:1;
2002                 u_int32_t support_core_affinity:1;
2003                 u_int32_t security_protocol_cmds_fw:1;
2004                 u_int32_t reserved:25;
2005         }       mfi_capabilities;
2006         u_int32_t reg;
2007 }       MFI_CAPABILITIES;
2008
2009 #pragma pack(1)
2010 struct mrsas_sge32 {
2011         u_int32_t phys_addr;
2012         u_int32_t length;
2013 };
2014
2015 #pragma pack()
2016
2017 #pragma pack(1)
2018 struct mrsas_sge64 {
2019         u_int64_t phys_addr;
2020         u_int32_t length;
2021 };
2022
2023 #pragma pack()
2024
2025 #pragma pack()
2026 union mrsas_sgl {
2027         struct mrsas_sge32 sge32[1];
2028         struct mrsas_sge64 sge64[1];
2029 };
2030
2031 #pragma pack()
2032
2033 #pragma pack(1)
2034 struct mrsas_header {
2035         u_int8_t cmd;                   /* 00e */
2036         u_int8_t sense_len;             /* 01h */
2037         u_int8_t cmd_status;            /* 02h */
2038         u_int8_t scsi_status;           /* 03h */
2039
2040         u_int8_t target_id;             /* 04h */
2041         u_int8_t lun;                   /* 05h */
2042         u_int8_t cdb_len;               /* 06h */
2043         u_int8_t sge_count;             /* 07h */
2044
2045         u_int32_t context;              /* 08h */
2046         u_int32_t pad_0;                /* 0Ch */
2047
2048         u_int16_t flags;                /* 10h */
2049         u_int16_t timeout;              /* 12h */
2050         u_int32_t data_xferlen;         /* 14h */
2051 };
2052
2053 #pragma pack()
2054
2055 #pragma pack(1)
2056 struct mrsas_init_frame {
2057         u_int8_t cmd;                   /* 00h */
2058         u_int8_t reserved_0;            /* 01h */
2059         u_int8_t cmd_status;            /* 02h */
2060
2061         u_int8_t reserved_1;            /* 03h */
2062         MFI_CAPABILITIES driver_operations;     /* 04h */
2063         u_int32_t context;              /* 08h */
2064         u_int32_t pad_0;                /* 0Ch */
2065
2066         u_int16_t flags;                /* 10h */
2067         u_int16_t reserved_3;           /* 12h */
2068         u_int32_t data_xfer_len;        /* 14h */
2069
2070         u_int32_t queue_info_new_phys_addr_lo;  /* 18h */
2071         u_int32_t queue_info_new_phys_addr_hi;  /* 1Ch */
2072         u_int32_t queue_info_old_phys_addr_lo;  /* 20h */
2073         u_int32_t queue_info_old_phys_addr_hi;  /* 24h */
2074         u_int32_t driver_ver_lo;        /* 28h */
2075         u_int32_t driver_ver_hi;        /* 2Ch */
2076         u_int32_t reserved_4[4];        /* 30h */
2077 };
2078
2079 #pragma pack()
2080
2081 #pragma pack(1)
2082 struct mrsas_io_frame {
2083         u_int8_t cmd;                   /* 00h */
2084         u_int8_t sense_len;             /* 01h */
2085         u_int8_t cmd_status;            /* 02h */
2086         u_int8_t scsi_status;           /* 03h */
2087
2088         u_int8_t target_id;             /* 04h */
2089         u_int8_t access_byte;           /* 05h */
2090         u_int8_t reserved_0;            /* 06h */
2091         u_int8_t sge_count;             /* 07h */
2092
2093         u_int32_t context;              /* 08h */
2094         u_int32_t pad_0;                /* 0Ch */
2095
2096         u_int16_t flags;                /* 10h */
2097         u_int16_t timeout;              /* 12h */
2098         u_int32_t lba_count;            /* 14h */
2099
2100         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2101         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2102
2103         u_int32_t start_lba_lo;         /* 20h */
2104         u_int32_t start_lba_hi;         /* 24h */
2105
2106         union mrsas_sgl sgl;            /* 28h */
2107 };
2108
2109 #pragma pack()
2110
2111 #pragma pack(1)
2112 struct mrsas_pthru_frame {
2113         u_int8_t cmd;                   /* 00h */
2114         u_int8_t sense_len;             /* 01h */
2115         u_int8_t cmd_status;            /* 02h */
2116         u_int8_t scsi_status;           /* 03h */
2117
2118         u_int8_t target_id;             /* 04h */
2119         u_int8_t lun;                   /* 05h */
2120         u_int8_t cdb_len;               /* 06h */
2121         u_int8_t sge_count;             /* 07h */
2122
2123         u_int32_t context;              /* 08h */
2124         u_int32_t pad_0;                /* 0Ch */
2125
2126         u_int16_t flags;                /* 10h */
2127         u_int16_t timeout;              /* 12h */
2128         u_int32_t data_xfer_len;        /* 14h */
2129
2130         u_int32_t sense_buf_phys_addr_lo;       /* 18h */
2131         u_int32_t sense_buf_phys_addr_hi;       /* 1Ch */
2132
2133         u_int8_t cdb[16];               /* 20h */
2134         union mrsas_sgl sgl;            /* 30h */
2135 };
2136
2137 #pragma pack()
2138
2139 #pragma pack(1)
2140 struct mrsas_dcmd_frame {
2141         u_int8_t cmd;                   /* 00h */
2142         u_int8_t reserved_0;            /* 01h */
2143         u_int8_t cmd_status;            /* 02h */
2144         u_int8_t reserved_1[4];         /* 03h */
2145         u_int8_t sge_count;             /* 07h */
2146
2147         u_int32_t context;              /* 08h */
2148         u_int32_t pad_0;                /* 0Ch */
2149
2150         u_int16_t flags;                /* 10h */
2151         u_int16_t timeout;              /* 12h */
2152
2153         u_int32_t data_xfer_len;        /* 14h */
2154         u_int32_t opcode;               /* 18h */
2155
2156         union {                         /* 1Ch */
2157                 u_int8_t b[12];
2158                 u_int16_t s[6];
2159                 u_int32_t w[3];
2160         }       mbox;
2161
2162         union mrsas_sgl sgl;            /* 28h */
2163 };
2164
2165 #pragma pack()
2166
2167 #pragma pack(1)
2168 struct mrsas_abort_frame {
2169         u_int8_t cmd;                   /* 00h */
2170         u_int8_t reserved_0;            /* 01h */
2171         u_int8_t cmd_status;            /* 02h */
2172
2173         u_int8_t reserved_1;            /* 03h */
2174         MFI_CAPABILITIES driver_operations;     /* 04h */
2175         u_int32_t context;              /* 08h */
2176         u_int32_t pad_0;                /* 0Ch */
2177
2178         u_int16_t flags;                /* 10h */
2179         u_int16_t reserved_3;           /* 12h */
2180         u_int32_t reserved_4;           /* 14h */
2181
2182         u_int32_t abort_context;        /* 18h */
2183         u_int32_t pad_1;                /* 1Ch */
2184
2185         u_int32_t abort_mfi_phys_addr_lo;       /* 20h */
2186         u_int32_t abort_mfi_phys_addr_hi;       /* 24h */
2187
2188         u_int32_t reserved_5[6];        /* 28h */
2189 };
2190
2191 #pragma pack()
2192
2193 #pragma pack(1)
2194 struct mrsas_smp_frame {
2195         u_int8_t cmd;                   /* 00h */
2196         u_int8_t reserved_1;            /* 01h */
2197         u_int8_t cmd_status;            /* 02h */
2198         u_int8_t connection_status;     /* 03h */
2199
2200         u_int8_t reserved_2[3];         /* 04h */
2201         u_int8_t sge_count;             /* 07h */
2202
2203         u_int32_t context;              /* 08h */
2204         u_int32_t pad_0;                /* 0Ch */
2205
2206         u_int16_t flags;                /* 10h */
2207         u_int16_t timeout;              /* 12h */
2208
2209         u_int32_t data_xfer_len;        /* 14h */
2210         u_int64_t sas_addr;             /* 18h */
2211
2212         union {
2213                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: req */
2214                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: req */
2215         }       sgl;
2216 };
2217
2218 #pragma pack()
2219
2220
2221 #pragma pack(1)
2222 struct mrsas_stp_frame {
2223         u_int8_t cmd;                   /* 00h */
2224         u_int8_t reserved_1;            /* 01h */
2225         u_int8_t cmd_status;            /* 02h */
2226         u_int8_t reserved_2;            /* 03h */
2227
2228         u_int8_t target_id;             /* 04h */
2229         u_int8_t reserved_3[2];         /* 05h */
2230         u_int8_t sge_count;             /* 07h */
2231
2232         u_int32_t context;              /* 08h */
2233         u_int32_t pad_0;                /* 0Ch */
2234
2235         u_int16_t flags;                /* 10h */
2236         u_int16_t timeout;              /* 12h */
2237
2238         u_int32_t data_xfer_len;        /* 14h */
2239
2240         u_int16_t fis[10];              /* 18h */
2241         u_int32_t stp_flags;
2242
2243         union {
2244                 struct mrsas_sge32 sge32[2];    /* [0]: resp [1]: data */
2245                 struct mrsas_sge64 sge64[2];    /* [0]: resp [1]: data */
2246         }       sgl;
2247 };
2248
2249 #pragma pack()
2250
2251 union mrsas_frame {
2252         struct mrsas_header hdr;
2253         struct mrsas_init_frame init;
2254         struct mrsas_io_frame io;
2255         struct mrsas_pthru_frame pthru;
2256         struct mrsas_dcmd_frame dcmd;
2257         struct mrsas_abort_frame abort;
2258         struct mrsas_smp_frame smp;
2259         struct mrsas_stp_frame stp;
2260         u_int8_t raw_bytes[64];
2261 };
2262
2263 #pragma pack(1)
2264 union mrsas_evt_class_locale {
2265
2266         struct {
2267                 u_int16_t locale;
2268                 u_int8_t reserved;
2269                 int8_t  class;
2270         } __packed members;
2271
2272         u_int32_t word;
2273
2274 } __packed;
2275
2276 #pragma pack()
2277
2278
2279 #pragma pack(1)
2280 struct mrsas_evt_log_info {
2281         u_int32_t newest_seq_num;
2282         u_int32_t oldest_seq_num;
2283         u_int32_t clear_seq_num;
2284         u_int32_t shutdown_seq_num;
2285         u_int32_t boot_seq_num;
2286
2287 } __packed;
2288
2289 #pragma pack()
2290
2291 struct mrsas_progress {
2292
2293         u_int16_t progress;
2294         u_int16_t elapsed_seconds;
2295
2296 } __packed;
2297
2298 struct mrsas_evtarg_ld {
2299
2300         u_int16_t target_id;
2301         u_int8_t ld_index;
2302         u_int8_t reserved;
2303
2304 } __packed;
2305
2306 struct mrsas_evtarg_pd {
2307         u_int16_t device_id;
2308         u_int8_t encl_index;
2309         u_int8_t slot_number;
2310
2311 } __packed;
2312
2313 struct mrsas_evt_detail {
2314
2315         u_int32_t seq_num;
2316         u_int32_t time_stamp;
2317         u_int32_t code;
2318         union mrsas_evt_class_locale cl;
2319         u_int8_t arg_type;
2320         u_int8_t reserved1[15];
2321
2322         union {
2323                 struct {
2324                         struct mrsas_evtarg_pd pd;
2325                         u_int8_t cdb_length;
2326                         u_int8_t sense_length;
2327                         u_int8_t reserved[2];
2328                         u_int8_t cdb[16];
2329                         u_int8_t sense[64];
2330                 } __packed cdbSense;
2331
2332                 struct mrsas_evtarg_ld ld;
2333
2334                 struct {
2335                         struct mrsas_evtarg_ld ld;
2336                         u_int64_t count;
2337                 } __packed ld_count;
2338
2339                 struct {
2340                         u_int64_t lba;
2341                         struct mrsas_evtarg_ld ld;
2342                 } __packed ld_lba;
2343
2344                 struct {
2345                         struct mrsas_evtarg_ld ld;
2346                         u_int32_t prevOwner;
2347                         u_int32_t newOwner;
2348                 } __packed ld_owner;
2349
2350                 struct {
2351                         u_int64_t ld_lba;
2352                         u_int64_t pd_lba;
2353                         struct mrsas_evtarg_ld ld;
2354                         struct mrsas_evtarg_pd pd;
2355                 } __packed ld_lba_pd_lba;
2356
2357                 struct {
2358                         struct mrsas_evtarg_ld ld;
2359                         struct mrsas_progress prog;
2360                 } __packed ld_prog;
2361
2362                 struct {
2363                         struct mrsas_evtarg_ld ld;
2364                         u_int32_t prev_state;
2365                         u_int32_t new_state;
2366                 } __packed ld_state;
2367
2368                 struct {
2369                         u_int64_t strip;
2370                         struct mrsas_evtarg_ld ld;
2371                 } __packed ld_strip;
2372
2373                 struct mrsas_evtarg_pd pd;
2374
2375                 struct {
2376                         struct mrsas_evtarg_pd pd;
2377                         u_int32_t err;
2378                 } __packed pd_err;
2379
2380                 struct {
2381                         u_int64_t lba;
2382                         struct mrsas_evtarg_pd pd;
2383                 } __packed pd_lba;
2384
2385                 struct {
2386                         u_int64_t lba;
2387                         struct mrsas_evtarg_pd pd;
2388                         struct mrsas_evtarg_ld ld;
2389                 } __packed pd_lba_ld;
2390
2391                 struct {
2392                         struct mrsas_evtarg_pd pd;
2393                         struct mrsas_progress prog;
2394                 } __packed pd_prog;
2395
2396                 struct {
2397                         struct mrsas_evtarg_pd pd;
2398                         u_int32_t prevState;
2399                         u_int32_t newState;
2400                 } __packed pd_state;
2401
2402                 struct {
2403                         u_int16_t vendorId;
2404                         u_int16_t deviceId;
2405                         u_int16_t subVendorId;
2406                         u_int16_t subDeviceId;
2407                 } __packed pci;
2408
2409                 u_int32_t rate;
2410                 char    str[96];
2411
2412                 struct {
2413                         u_int32_t rtc;
2414                         u_int32_t elapsedSeconds;
2415                 } __packed time;
2416
2417                 struct {
2418                         u_int32_t ecar;
2419                         u_int32_t elog;
2420                         char    str[64];
2421                 } __packed ecc;
2422
2423                 u_int8_t b[96];
2424                 u_int16_t s[48];
2425                 u_int32_t w[24];
2426                 u_int64_t d[12];
2427         }       args;
2428
2429         char    description[128];
2430
2431 } __packed;
2432
2433 struct mrsas_irq_context {
2434         struct mrsas_softc *sc;
2435         uint32_t MSIxIndex;
2436 };
2437
2438 /* Controller management info added to support Linux Emulator */
2439 #define MAX_MGMT_ADAPTERS               1024
2440
2441 struct mrsas_mgmt_info {
2442         u_int16_t count;
2443         struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS];
2444         int     max_index;
2445 };
2446
2447 #define PCI_TYPE0_ADDRESSES             6
2448 #define PCI_TYPE1_ADDRESSES             2
2449 #define PCI_TYPE2_ADDRESSES             5
2450
2451 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
2452         u_int16_t vendorID;
2453               //(ro)
2454         u_int16_t deviceID;
2455               //(ro)
2456         u_int16_t command;
2457               //Device control
2458         u_int16_t status;
2459         u_int8_t revisionID;
2460               //(ro)
2461         u_int8_t progIf;
2462               //(ro)
2463         u_int8_t subClass;
2464               //(ro)
2465         u_int8_t baseClass;
2466               //(ro)
2467         u_int8_t cacheLineSize;
2468               //(ro +)
2469         u_int8_t latencyTimer;
2470               //(ro +)
2471         u_int8_t headerType;
2472               //(ro)
2473         u_int8_t bist;
2474               //Built in self test
2475
2476         union {
2477                 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 {
2478                         u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES];
2479                         u_int32_t cis;
2480                         u_int16_t subVendorID;
2481                         u_int16_t subSystemID;
2482                         u_int32_t romBaseAddress;
2483                         u_int8_t capabilitiesPtr;
2484                         u_int8_t reserved1[3];
2485                         u_int32_t reserved2;
2486                         u_int8_t interruptLine;
2487                         u_int8_t interruptPin;
2488                               //(ro)
2489                         u_int8_t minimumGrant;
2490                               //(ro)
2491                         u_int8_t maximumLatency;
2492                               //(ro)
2493                 }       type0;
2494
2495                 /*
2496                  * PCI to PCI Bridge
2497                  */
2498
2499                 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 {
2500                         u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES];
2501                         u_int8_t primaryBus;
2502                         u_int8_t secondaryBus;
2503                         u_int8_t subordinateBus;
2504                         u_int8_t secondaryLatency;
2505                         u_int8_t ioBase;
2506                         u_int8_t ioLimit;
2507                         u_int16_t secondaryStatus;
2508                         u_int16_t memoryBase;
2509                         u_int16_t memoryLimit;
2510                         u_int16_t prefetchBase;
2511                         u_int16_t prefetchLimit;
2512                         u_int32_t prefetchBaseUpper32;
2513                         u_int32_t prefetchLimitUpper32;
2514                         u_int16_t ioBaseUpper16;
2515                         u_int16_t ioLimitUpper16;
2516                         u_int8_t capabilitiesPtr;
2517                         u_int8_t reserved1[3];
2518                         u_int32_t romBaseAddress;
2519                         u_int8_t interruptLine;
2520                         u_int8_t interruptPin;
2521                         u_int16_t bridgeControl;
2522                 }       type1;
2523
2524                 /*
2525                  * PCI to CARDBUS Bridge
2526                  */
2527
2528                 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 {
2529                         u_int32_t socketRegistersBaseAddress;
2530                         u_int8_t capabilitiesPtr;
2531                         u_int8_t reserved;
2532                         u_int16_t secondaryStatus;
2533                         u_int8_t primaryBus;
2534                         u_int8_t secondaryBus;
2535                         u_int8_t subordinateBus;
2536                         u_int8_t secondaryLatency;
2537                         struct {
2538                                 u_int32_t base;
2539                                 u_int32_t limit;
2540                         }       range [PCI_TYPE2_ADDRESSES - 1];
2541                         u_int8_t interruptLine;
2542                         u_int8_t interruptPin;
2543                         u_int16_t bridgeControl;
2544                 }       type2;
2545         }       u;
2546
2547 }       MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER;
2548
2549 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER)   //64 bytes
2550
2551 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
2552         union {
2553                 struct {
2554                         u_int32_t linkSpeed:4;
2555                         u_int32_t linkWidth:6;
2556                         u_int32_t aspmSupport:2;
2557                         u_int32_t losExitLatency:3;
2558                         u_int32_t l1ExitLatency:3;
2559                         u_int32_t rsvdp:6;
2560                         u_int32_t portNumber:8;
2561                 }       bits;
2562
2563                 u_int32_t asUlong;
2564         }       u;
2565 }       MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY;
2566
2567 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY)
2568
2569 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
2570         union {
2571                 struct {
2572                         u_int16_t linkSpeed:4;
2573                         u_int16_t negotiatedLinkWidth:6;
2574                         u_int16_t linkTrainingError:1;
2575                         u_int16_t linkTraning:1;
2576                         u_int16_t slotClockConfig:1;
2577                         u_int16_t rsvdZ:3;
2578                 }       bits;
2579
2580                 u_int16_t asUshort;
2581         }       u;
2582         u_int16_t reserved;
2583 }       MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY;
2584
2585 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY)
2586
2587
2588 typedef struct _MRSAS_DRV_PCI_CAPABILITIES {
2589         MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability;
2590         MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability;
2591 }       MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES;
2592
2593 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES)
2594
2595 /* PCI information */
2596 typedef struct _MRSAS_DRV_PCI_INFORMATION {
2597         u_int32_t busNumber;
2598         u_int8_t deviceNumber;
2599         u_int8_t functionNumber;
2600         u_int8_t interruptVector;
2601         u_int8_t reserved1;
2602         MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo;
2603         MRSAS_DRV_PCI_CAPABILITIES capability;
2604         u_int32_t domainID;
2605         u_int8_t reserved2[28];
2606 }       MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION;
2607
2608 /*******************************************************************
2609  * per-instance data
2610  ********************************************************************/
2611 struct mrsas_softc {
2612         device_t mrsas_dev;
2613         struct cdev *mrsas_cdev;
2614         uint16_t device_id;
2615         struct resource *reg_res;
2616         int     reg_res_id;
2617         bus_space_tag_t bus_tag;
2618         bus_space_handle_t bus_handle;
2619         bus_dma_tag_t mrsas_parent_tag;
2620         bus_dma_tag_t verbuf_tag;
2621         bus_dmamap_t verbuf_dmamap;
2622         void   *verbuf_mem;
2623         bus_addr_t verbuf_phys_addr;
2624         bus_dma_tag_t sense_tag;
2625         bus_dmamap_t sense_dmamap;
2626         void   *sense_mem;
2627         bus_addr_t sense_phys_addr;
2628         bus_dma_tag_t io_request_tag;
2629         bus_dmamap_t io_request_dmamap;
2630         void   *io_request_mem;
2631         bus_addr_t io_request_phys_addr;
2632         bus_dma_tag_t chain_frame_tag;
2633         bus_dmamap_t chain_frame_dmamap;
2634         void   *chain_frame_mem;
2635         bus_addr_t chain_frame_phys_addr;
2636         bus_dma_tag_t reply_desc_tag;
2637         bus_dmamap_t reply_desc_dmamap;
2638         void   *reply_desc_mem;
2639         bus_addr_t reply_desc_phys_addr;
2640         bus_dma_tag_t ioc_init_tag;
2641         bus_dmamap_t ioc_init_dmamap;
2642         void   *ioc_init_mem;
2643         bus_addr_t ioc_init_phys_mem;
2644         bus_dma_tag_t data_tag;
2645         struct cam_sim *sim_0;
2646         struct cam_sim *sim_1;
2647         struct cam_path *path_0;
2648         struct cam_path *path_1;
2649         struct mtx sim_lock;
2650         struct mtx pci_lock;
2651         struct mtx io_lock;
2652         struct mtx ioctl_lock;
2653         struct mtx mpt_cmd_pool_lock;
2654         struct mtx mfi_cmd_pool_lock;
2655         struct mtx raidmap_lock;
2656         struct mtx aen_lock;
2657         struct selinfo mrsas_select;
2658         uint32_t mrsas_aen_triggered;
2659         uint32_t mrsas_poll_waiting;
2660
2661         struct sema ioctl_count_sema;
2662         uint32_t max_fw_cmds;
2663         uint32_t max_num_sge;
2664         struct resource *mrsas_irq[MAX_MSIX_COUNT];
2665         void   *intr_handle[MAX_MSIX_COUNT];
2666         int     irq_id[MAX_MSIX_COUNT];
2667         struct mrsas_irq_context irq_context[MAX_MSIX_COUNT];
2668         int     msix_vectors;
2669         int     msix_enable;
2670         uint32_t msix_reg_offset[16];
2671         uint8_t mask_interrupts;
2672         struct mrsas_mpt_cmd **mpt_cmd_list;
2673         struct mrsas_mfi_cmd **mfi_cmd_list;
2674         TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head;
2675         TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head;
2676         bus_addr_t req_frames_desc_phys;
2677         u_int8_t *req_frames_desc;
2678         u_int8_t *req_desc;
2679         bus_addr_t io_request_frames_phys;
2680         u_int8_t *io_request_frames;
2681         bus_addr_t reply_frames_desc_phys;
2682         u_int16_t last_reply_idx[MAX_MSIX_COUNT];
2683         u_int32_t reply_q_depth;
2684         u_int32_t request_alloc_sz;
2685         u_int32_t reply_alloc_sz;
2686         u_int32_t io_frames_alloc_sz;
2687         u_int32_t chain_frames_alloc_sz;
2688         u_int16_t max_sge_in_main_msg;
2689         u_int16_t max_sge_in_chain;
2690         u_int8_t chain_offset_io_request;
2691         u_int8_t chain_offset_mfi_pthru;
2692         u_int32_t map_sz;
2693         u_int64_t map_id;
2694         struct mrsas_mfi_cmd *map_update_cmd;
2695         struct mrsas_mfi_cmd *aen_cmd;
2696         u_int8_t fast_path_io;
2697         void   *chan;
2698         void   *ocr_chan;
2699         u_int8_t adprecovery;
2700         u_int8_t remove_in_progress;
2701         u_int8_t ocr_thread_active;
2702         u_int8_t do_timedout_reset;
2703         u_int32_t reset_in_progress;
2704         u_int32_t reset_count;
2705         bus_dma_tag_t raidmap_tag[2];
2706         bus_dmamap_t raidmap_dmamap[2];
2707         void   *raidmap_mem[2];
2708         bus_addr_t raidmap_phys_addr[2];
2709         bus_dma_tag_t mficmd_frame_tag;
2710         bus_dma_tag_t mficmd_sense_tag;
2711         bus_dma_tag_t evt_detail_tag;
2712         bus_dmamap_t evt_detail_dmamap;
2713         struct mrsas_evt_detail *evt_detail_mem;
2714         bus_addr_t evt_detail_phys_addr;
2715         struct mrsas_ctrl_info *ctrl_info;
2716         bus_dma_tag_t ctlr_info_tag;
2717         bus_dmamap_t ctlr_info_dmamap;
2718         void   *ctlr_info_mem;
2719         bus_addr_t ctlr_info_phys_addr;
2720         u_int32_t max_sectors_per_req;
2721         u_int32_t disableOnlineCtrlReset;
2722         mrsas_atomic_t fw_outstanding;
2723         u_int32_t mrsas_debug;
2724         u_int32_t mrsas_io_timeout;
2725         u_int32_t mrsas_fw_fault_check_delay;
2726         u_int32_t io_cmds_highwater;
2727         u_int8_t UnevenSpanSupport;
2728         struct sysctl_ctx_list sysctl_ctx;
2729         struct sysctl_oid *sysctl_tree;
2730         struct proc *ocr_thread;
2731         u_int32_t last_seq_num;
2732         bus_dma_tag_t el_info_tag;
2733         bus_dmamap_t el_info_dmamap;
2734         void   *el_info_mem;
2735         bus_addr_t el_info_phys_addr;
2736         struct mrsas_pd_list pd_list[MRSAS_MAX_PD];
2737         struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD];
2738         u_int8_t ld_ids[MRSAS_MAX_LD_IDS];
2739         struct taskqueue *ev_tq;
2740         struct task ev_task;
2741         u_int32_t CurLdCount;
2742         u_int64_t reset_flags;
2743         int     lb_pending_cmds;
2744         LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
2745         LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
2746
2747         u_int8_t secure_jbod_support;
2748         u_int8_t max256vdSupport;
2749         u_int16_t fw_supported_vd_count;
2750         u_int16_t fw_supported_pd_count;
2751
2752         u_int16_t drv_supported_vd_count;
2753         u_int16_t drv_supported_pd_count;
2754
2755         u_int32_t max_map_sz;
2756         u_int32_t current_map_sz;
2757         u_int32_t old_map_sz;
2758         u_int32_t new_map_sz;
2759         u_int32_t drv_map_sz;
2760
2761         /* Non dma-able memory. Driver local copy. */
2762         MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
2763 };
2764
2765 /* Compatibility shims for different OS versions */
2766 #if __FreeBSD_version >= 800001
2767 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2768     kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2769 #define mrsas_kproc_exit(arg)   kproc_exit(arg)
2770 #else
2771 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
2772     kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
2773 #define mrsas_kproc_exit(arg)   kthread_exit(arg)
2774 #endif
2775
2776 static __inline void
2777 mrsas_clear_bit(int b, volatile void *p)
2778 {
2779         atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2780 }
2781
2782 static __inline void
2783 mrsas_set_bit(int b, volatile void *p)
2784 {
2785         atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f));
2786 }
2787
2788 static __inline int
2789 mrsas_test_bit(int b, volatile void *p)
2790 {
2791         return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f));
2792 }
2793
2794 #endif                                  /* MRSAS_H */