sys/dev/nvme/nvme_private.h

   1 /*-
   2  * Copyright (C) 2012-2014 Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef __NVME_PRIVATE_H__
  30 #define __NVME_PRIVATE_H__
  31
  32 #include <sys/param.h>
  33 #include <sys/bio.h>
  34 #include <sys/bus.h>
  35 #include <sys/kernel.h>
  36 #include <sys/lock.h>
  37 #include <sys/malloc.h>
  38 #include <sys/mutex.h>
  39 #include <sys/rman.h>
  40 #include <sys/systm.h>
  41 #include <sys/taskqueue.h>
  42
  43 #include <vm/uma.h>
  44
  45 #include <machine/bus.h>
  46
  47 #include "nvme.h"
  48
  49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev))
  50
  51 MALLOC_DECLARE(M_NVME);
  52
  53 #define IDT32_PCI_ID            0x80d0111d /* 32 channel board */
  54 #define IDT8_PCI_ID             0x80d2111d /* 8 channel board */
  55
  56 /*
  57  * For commands requiring more than 2 PRP entries, one PRP will be
  58  *  embedded in the command (prp1), and the rest of the PRP entries
  59  *  will be in a list pointed to by the command (prp2).  This means
  60  *  that real max number of PRP entries we support is 32+1, which
  61  *  results in a max xfer size of 32*PAGE_SIZE.
  62  */
  63 #define NVME_MAX_PRP_LIST_ENTRIES       (NVME_MAX_XFER_SIZE / PAGE_SIZE)
  64
  65 #define NVME_ADMIN_TRACKERS     (16)
  66 #define NVME_ADMIN_ENTRIES      (128)
  67 /* min and max are defined in admin queue attributes section of spec */
  68 #define NVME_MIN_ADMIN_ENTRIES  (2)
  69 #define NVME_MAX_ADMIN_ENTRIES  (4096)
  70
  71 /*
  72  * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion
  73  *  queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we
  74  *  will allow outstanding on an I/O qpair at any time.  The only advantage in
  75  *  having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping
  76  *  the contents of the submission and completion queues, it will show a longer
  77  *  history of data.
  78  */
  79 #define NVME_IO_ENTRIES         (256)
  80 #define NVME_IO_TRACKERS        (128)
  81 #define NVME_MIN_IO_TRACKERS    (4)
  82 #define NVME_MAX_IO_TRACKERS    (1024)
  83
  84 /*
  85  * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES
  86  *  for each controller.
  87  */
  88
  89 #define NVME_INT_COAL_TIME      (0)     /* disabled */
  90 #define NVME_INT_COAL_THRESHOLD (0)     /* 0-based */
  91
  92 #define NVME_MAX_NAMESPACES     (16)
  93 #define NVME_MAX_CONSUMERS      (2)
  94 #define NVME_MAX_ASYNC_EVENTS   (8)
  95
  96 #define NVME_DEFAULT_TIMEOUT_PERIOD     (30)    /* in seconds */
  97 #define NVME_MIN_TIMEOUT_PERIOD         (5)
  98 #define NVME_MAX_TIMEOUT_PERIOD         (120)
  99
 100 #define NVME_DEFAULT_RETRY_COUNT        (4)
 101
 102 /* Maximum log page size to fetch for AERs. */
 103 #define NVME_MAX_AER_LOG_SIZE           (4096)
 104
 105 /*
 106  * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define
 107  *  it.
 108  */
 109 #ifndef CACHE_LINE_SIZE
 110 #define CACHE_LINE_SIZE         (64)
 111 #endif
 112
 113 /*
 114  * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O
 115  *  support and the bus_dmamap_load_bio API are available on the target
 116  *  kernel.  This will ease porting back to earlier stable branches at a
 117  *  later point.
 118  */
 119 #ifdef BIO_UNMAPPED
 120 #define NVME_UNMAPPED_BIO_SUPPORT
 121 #endif
 122
 123 extern uma_zone_t       nvme_request_zone;
 124 extern int32_t          nvme_retry_count;
 125
 126 struct nvme_completion_poll_status {
 127
 128         struct nvme_completion  cpl;
 129         boolean_t               done;
 130 };
 131
 132 #define NVME_REQUEST_VADDR      1
 133 #define NVME_REQUEST_NULL       2 /* For requests with no payload. */
 134 #define NVME_REQUEST_UIO        3
 135 #ifdef NVME_UNMAPPED_BIO_SUPPORT
 136 #define NVME_REQUEST_BIO        4
 137 #endif
 138
 139 struct nvme_request {
 140
 141         struct nvme_command             cmd;
 142         struct nvme_qpair               *qpair;
 143         union {
 144                 void                    *payload;
 145                 struct bio              *bio;
 146         } u;
 147         uint32_t                        type;
 148         uint32_t                        payload_size;
 149         boolean_t                       timeout;
 150         nvme_cb_fn_t                    cb_fn;
 151         void                            *cb_arg;
 152         int32_t                         retries;
 153         STAILQ_ENTRY(nvme_request)      stailq;
 154 };
 155
 156 struct nvme_async_event_request {
 157
 158         struct nvme_controller          *ctrlr;
 159         struct nvme_request             *req;
 160         struct nvme_completion          cpl;
 161         uint32_t                        log_page_id;
 162         uint32_t                        log_page_size;
 163         uint8_t                         log_page_buffer[NVME_MAX_AER_LOG_SIZE];
 164 };
 165
 166 struct nvme_tracker {
 167
 168         TAILQ_ENTRY(nvme_tracker)       tailq;
 169         struct nvme_request             *req;
 170         struct nvme_qpair               *qpair;
 171         struct callout                  timer;
 172         bus_dmamap_t                    payload_dma_map;
 173         uint16_t                        cid;
 174
 175         uint64_t                        prp[NVME_MAX_PRP_LIST_ENTRIES];
 176         bus_addr_t                      prp_bus_addr;
 177         bus_dmamap_t                    prp_dma_map;
 178 };
 179
 180 struct nvme_qpair {
 181
 182         struct nvme_controller  *ctrlr;
 183         uint32_t                id;
 184         uint32_t                phase;
 185
 186         uint16_t                vector;
 187         int                     rid;
 188         struct resource         *res;
 189         void                    *tag;
 190
 191         uint32_t                num_entries;
 192         uint32_t                num_trackers;
 193         uint32_t                sq_tdbl_off;
 194         uint32_t                cq_hdbl_off;
 195
 196         uint32_t                sq_head;
 197         uint32_t                sq_tail;
 198         uint32_t                cq_head;
 199
 200         int64_t                 num_cmds;
 201         int64_t                 num_intr_handler_calls;
 202
 203         struct nvme_command     *cmd;
 204         struct nvme_completion  *cpl;
 205
 206         bus_dma_tag_t           dma_tag;
 207         bus_dma_tag_t           dma_tag_payload;
 208
 209         bus_dmamap_t            cmd_dma_map;
 210         uint64_t                cmd_bus_addr;
 211
 212         bus_dmamap_t            cpl_dma_map;
 213         uint64_t                cpl_bus_addr;
 214
 215         TAILQ_HEAD(, nvme_tracker)      free_tr;
 216         TAILQ_HEAD(, nvme_tracker)      outstanding_tr;
 217         STAILQ_HEAD(, nvme_request)     queued_req;
 218
 219         struct nvme_tracker     **act_tr;
 220
 221         boolean_t               is_enabled;
 222
 223         struct mtx              lock __aligned(CACHE_LINE_SIZE);
 224
 225 } __aligned(CACHE_LINE_SIZE);
 226
 227 struct nvme_namespace {
 228
 229         struct nvme_controller          *ctrlr;
 230         struct nvme_namespace_data      data;
 231         uint16_t                        id;
 232         uint16_t                        flags;
 233         struct cdev                     *cdev;
 234         void                            *cons_cookie[NVME_MAX_CONSUMERS];
 235         uint32_t                        stripesize;
 236         struct mtx                      lock;
 237 };
 238
 239 /*
 240  * One of these per allocated PCI device.
 241  */
 242 struct nvme_controller {
 243
 244         device_t                dev;
 245
 246         struct mtx              lock;
 247
 248         uint32_t                ready_timeout_in_ms;
 249
 250         bus_space_tag_t         bus_tag;
 251         bus_space_handle_t      bus_handle;
 252         int                     resource_id;
 253         struct resource         *resource;
 254
 255         /*
 256          * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5,
 257          *  separate from the control registers which are in BAR 0/1.  These
 258          *  members track the mapping of BAR 4/5 for that reason.
 259          */
 260         int                     bar4_resource_id;
 261         struct resource         *bar4_resource;
 262
 263         uint32_t                msix_enabled;
 264         uint32_t                force_intx;
 265         uint32_t                enable_aborts;
 266
 267         uint32_t                num_io_queues;
 268         boolean_t               per_cpu_io_queues;
 269
 270         /* Fields for tracking progress during controller initialization. */
 271         struct intr_config_hook config_hook;
 272         uint32_t                ns_identified;
 273         uint32_t                queues_created;
 274
 275         struct task             reset_task;
 276         struct task             fail_req_task;
 277         struct taskqueue        *taskqueue;
 278
 279         struct resource         *msi_res[MAXCPU + 1];
 280
 281         /* For shared legacy interrupt. */
 282         int                     rid;
 283         struct resource         *res;
 284         void                    *tag;
 285
 286         bus_dma_tag_t           hw_desc_tag;
 287         bus_dmamap_t            hw_desc_map;
 288
 289         /** maximum i/o size in bytes */
 290         uint32_t                max_xfer_size;
 291
 292         /** minimum page size supported by this controller in bytes */
 293         uint32_t                min_page_size;
 294
 295         /** interrupt coalescing time period (in microseconds) */
 296         uint32_t                int_coal_time;
 297
 298         /** interrupt coalescing threshold */
 299         uint32_t                int_coal_threshold;
 300
 301         /** timeout period in seconds */
 302         uint32_t                timeout_period;
 303
 304         struct nvme_qpair       adminq;
 305         struct nvme_qpair       *ioq;
 306
 307         struct nvme_registers           *regs;
 308
 309         struct nvme_controller_data     cdata;
 310         struct nvme_namespace           ns[NVME_MAX_NAMESPACES];
 311
 312         struct cdev                     *cdev;
 313
 314         /** bit mask of warning types currently enabled for async events */
 315         union nvme_critical_warning_state       async_event_config;
 316
 317         uint32_t                        num_aers;
 318         struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS];
 319
 320         void                            *cons_cookie[NVME_MAX_CONSUMERS];
 321
 322         uint32_t                        is_resetting;
 323         uint32_t                        is_initialized;
 324         uint32_t                        notification_sent;
 325
 326         boolean_t                       is_failed;
 327         STAILQ_HEAD(, nvme_request)     fail_req;
 328 };
 329
 330 #define nvme_mmio_offsetof(reg)                                                \
 331         offsetof(struct nvme_registers, reg)
 332
 333 #define nvme_mmio_read_4(sc, reg)                                              \
 334         bus_space_read_4((sc)->bus_tag, (sc)->bus_handle,                      \
 335             nvme_mmio_offsetof(reg))
 336
 337 #define nvme_mmio_write_4(sc, reg, val)                                        \
 338         bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,                     \
 339             nvme_mmio_offsetof(reg), val)
 340
 341 #define nvme_mmio_write_8(sc, reg, val) \
 342         do {                                                                   \
 343                 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,             \
 344                     nvme_mmio_offsetof(reg), val & 0xFFFFFFFF);                \
 345                 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle,             \
 346                     nvme_mmio_offsetof(reg)+4,                                 \
 347                     (val & 0xFFFFFFFF00000000UL) >> 32);                       \
 348         } while (0);
 349
 350 #if __FreeBSD_version < 800054
 351 #define wmb()   __asm volatile("sfence" ::: "memory")
 352 #define mb()    __asm volatile("mfence" ::: "memory")
 353 #endif
 354
 355 #define nvme_printf(ctrlr, fmt, args...)        \
 356     device_printf(ctrlr->dev, fmt, ##args)
 357
 358 void    nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg);
 359
 360 void    nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr,
 361                                            void *payload,
 362                                            nvme_cb_fn_t cb_fn, void *cb_arg);
 363 void    nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr,
 364                                           uint16_t nsid, void *payload,
 365                                           nvme_cb_fn_t cb_fn, void *cb_arg);
 366 void    nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr,
 367                                                 uint32_t microseconds,
 368                                                 uint32_t threshold,
 369                                                 nvme_cb_fn_t cb_fn,
 370                                                 void *cb_arg);
 371 void    nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr,
 372                                       struct nvme_error_information_entry *payload,
 373                                       uint32_t num_entries, /* 0 = max */
 374                                       nvme_cb_fn_t cb_fn,
 375                                       void *cb_arg);
 376 void    nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr,
 377                                                    uint32_t nsid,
 378                                                    struct nvme_health_information_page *payload,
 379                                                    nvme_cb_fn_t cb_fn,
 380                                                    void *cb_arg);
 381 void    nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr,
 382                                          struct nvme_firmware_page *payload,
 383                                          nvme_cb_fn_t cb_fn,
 384                                          void *cb_arg);
 385 void    nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr,
 386                                     struct nvme_qpair *io_que, uint16_t vector,
 387                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 388 void    nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr,
 389                                     struct nvme_qpair *io_que,
 390                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 391 void    nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr,
 392                                     struct nvme_qpair *io_que,
 393                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 394 void    nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr,
 395                                     struct nvme_qpair *io_que,
 396                                     nvme_cb_fn_t cb_fn, void *cb_arg);
 397 void    nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr,
 398                                       uint32_t num_queues, nvme_cb_fn_t cb_fn,
 399                                       void *cb_arg);
 400 void    nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr,
 401                                               union nvme_critical_warning_state state,
 402                                               nvme_cb_fn_t cb_fn, void *cb_arg);
 403 void    nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid,
 404                              uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg);
 405
 406 void    nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl);
 407
 408 int     nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev);
 409 void    nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev);
 410 void    nvme_ctrlr_shutdown(struct nvme_controller *ctrlr);
 411 int     nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr);
 412 void    nvme_ctrlr_reset(struct nvme_controller *ctrlr);
 413 /* ctrlr defined as void * to allow use with config_intrhook. */
 414 void    nvme_ctrlr_start_config_hook(void *ctrlr_arg);
 415 void    nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr,
 416                                         struct nvme_request *req);
 417 void    nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr,
 418                                      struct nvme_request *req);
 419 void    nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr,
 420                                        struct nvme_request *req);
 421
 422 void    nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id,
 423                              uint16_t vector, uint32_t num_entries,
 424                              uint32_t num_trackers,
 425                              struct nvme_controller *ctrlr);
 426 void    nvme_qpair_submit_tracker(struct nvme_qpair *qpair,
 427                                   struct nvme_tracker *tr);
 428 void    nvme_qpair_process_completions(struct nvme_qpair *qpair);
 429 void    nvme_qpair_submit_request(struct nvme_qpair *qpair,
 430                                   struct nvme_request *req);
 431 void    nvme_qpair_reset(struct nvme_qpair *qpair);
 432 void    nvme_qpair_fail(struct nvme_qpair *qpair);
 433 void    nvme_qpair_manual_complete_request(struct nvme_qpair *qpair,
 434                                            struct nvme_request *req,
 435                                            uint32_t sct, uint32_t sc,
 436                                            boolean_t print_on_error);
 437
 438 void    nvme_admin_qpair_enable(struct nvme_qpair *qpair);
 439 void    nvme_admin_qpair_disable(struct nvme_qpair *qpair);
 440 void    nvme_admin_qpair_destroy(struct nvme_qpair *qpair);
 441
 442 void    nvme_io_qpair_enable(struct nvme_qpair *qpair);
 443 void    nvme_io_qpair_disable(struct nvme_qpair *qpair);
 444 void    nvme_io_qpair_destroy(struct nvme_qpair *qpair);
 445
 446 int     nvme_ns_construct(struct nvme_namespace *ns, uint16_t id,
 447                           struct nvme_controller *ctrlr);
 448 void    nvme_ns_destruct(struct nvme_namespace *ns);
 449
 450 void    nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr);
 451
 452 void    nvme_dump_command(struct nvme_command *cmd);
 453 void    nvme_dump_completion(struct nvme_completion *cpl);
 454
 455 static __inline void
 456 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error)
 457 {
 458         uint64_t *bus_addr = (uint64_t *)arg;
 459
 460         if (error != 0)
 461                 printf("nvme_single_map err %d\n", error);
 462         *bus_addr = seg[0].ds_addr;
 463 }
 464
 465 static __inline struct nvme_request *
 466 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg)
 467 {
 468         struct nvme_request *req;
 469
 470         req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO);
 471         if (req != NULL) {
 472                 req->cb_fn = cb_fn;
 473                 req->cb_arg = cb_arg;
 474                 req->timeout = TRUE;
 475         }
 476         return (req);
 477 }
 478
 479 static __inline struct nvme_request *
 480 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size,
 481     nvme_cb_fn_t cb_fn, void *cb_arg)
 482 {
 483         struct nvme_request *req;
 484
 485         req = _nvme_allocate_request(cb_fn, cb_arg);
 486         if (req != NULL) {
 487                 req->type = NVME_REQUEST_VADDR;
 488                 req->u.payload = payload;
 489                 req->payload_size = payload_size;
 490         }
 491         return (req);
 492 }
 493
 494 static __inline struct nvme_request *
 495 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg)
 496 {
 497         struct nvme_request *req;
 498
 499         req = _nvme_allocate_request(cb_fn, cb_arg);
 500         if (req != NULL)
 501                 req->type = NVME_REQUEST_NULL;
 502         return (req);
 503 }
 504
 505 static __inline struct nvme_request *
 506 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg)
 507 {
 508         struct nvme_request *req;
 509
 510         req = _nvme_allocate_request(cb_fn, cb_arg);
 511         if (req != NULL) {
 512 #ifdef NVME_UNMAPPED_BIO_SUPPORT
 513                 req->type = NVME_REQUEST_BIO;
 514                 req->u.bio = bio;
 515 #else
 516                 req->type = NVME_REQUEST_VADDR;
 517                 req->u.payload = bio->bio_data;
 518                 req->payload_size = bio->bio_bcount;
 519 #endif
 520         }
 521         return (req);
 522 }
 523
 524 #define nvme_free_request(req)  uma_zfree(nvme_request_zone, req)
 525
 526 void    nvme_notify_async_consumers(struct nvme_controller *ctrlr,
 527                                     const struct nvme_completion *async_cpl,
 528                                     uint32_t log_page_id, void *log_page_buffer,
 529                                     uint32_t log_page_size);
 530 void    nvme_notify_fail_consumers(struct nvme_controller *ctrlr);
 531 void    nvme_notify_new_controller(struct nvme_controller *ctrlr);
 532
 533 #endif /* __NVME_PRIVATE_H__ */