sys/dev/oce/oce_if.h

   1 /*-
   2  * Copyright (C) 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  *
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * 3. Neither the name of the Emulex Corporation nor the names of its
  16  *    contributors may be used to endorse or promote products derived from
  17  *    this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Contact Information:
  32  * freebsd-drivers@emulex.com
  33  *
  34  * Emulex
  35  * 3333 Susan Street
  36  * Costa Mesa, CA 92626
  37  */
  38
  39 /* $FreeBSD$ */
  40
  41 #include <sys/param.h>
  42 #include <sys/endian.h>
  43 #include <sys/module.h>
  44 #include <sys/kernel.h>
  45 #include <sys/bus.h>
  46 #include <sys/mbuf.h>
  47 #include <sys/rman.h>
  48 #include <sys/socket.h>
  49 #include <sys/sockio.h>
  50 #include <sys/sockopt.h>
  51 #include <sys/queue.h>
  52 #include <sys/taskqueue.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/sysctl.h>
  56 #include <sys/random.h>
  57 #include <sys/firmware.h>
  58 #include <sys/systm.h>
  59 #include <sys/proc.h>
  60
  61 #include <dev/pci/pcireg.h>
  62 #include <dev/pci/pcivar.h>
  63
  64 #include <net/bpf.h>
  65 #include <net/ethernet.h>
  66 #include <net/if.h>
  67 #include <net/if_types.h>
  68 #include <net/if_media.h>
  69 #include <net/if_vlan_var.h>
  70 #include <net/if_dl.h>
  71
  72 #include <netinet/in.h>
  73 #include <netinet/in_systm.h>
  74 #include <netinet/in_var.h>
  75 #include <netinet/if_ether.h>
  76 #include <netinet/ip.h>
  77 #include <netinet/ip6.h>
  78 #include <netinet6/in6_var.h>
  79 #include <netinet6/ip6_mroute.h>
  80
  81 #include <netinet/udp.h>
  82 #include <netinet/tcp.h>
  83 #include <netinet/sctp.h>
  84 #include <netinet/tcp_lro.h>
  85
  86 #include <machine/bus.h>
  87
  88 #include "oce_hw.h"
  89
  90 /* OCE device driver module component revision informaiton */
  91 #define COMPONENT_REVISION "10.0.664.0"
  92
  93 /* OCE devices supported by this driver */
  94 #define PCI_VENDOR_EMULEX               0x10df  /* Emulex */
  95 #define PCI_VENDOR_SERVERENGINES        0x19a2  /* ServerEngines (BE) */
  96 #define PCI_PRODUCT_BE2                 0x0700  /* BE2 network adapter */
  97 #define PCI_PRODUCT_BE3                 0x0710  /* BE3 network adapter */
  98 #define PCI_PRODUCT_XE201               0xe220  /* XE201 network adapter */
  99 #define PCI_PRODUCT_XE201_VF            0xe228  /* XE201 with VF in Lancer */
 100 #define PCI_PRODUCT_SH                  0x0720  /* Skyhawk network adapter */
 101
 102 #define IS_BE(sc)       (((sc->flags & OCE_FLAGS_BE3) | \
 103                          (sc->flags & OCE_FLAGS_BE2))? 1:0)
 104 #define IS_BE3(sc)      (sc->flags & OCE_FLAGS_BE3)
 105 #define IS_BE2(sc)      (sc->flags & OCE_FLAGS_BE2)
 106 #define IS_XE201(sc)    ((sc->flags & OCE_FLAGS_XE201) ? 1:0)
 107 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0)
 108 #define IS_SH(sc)       ((sc->flags & OCE_FLAGS_SH) ? 1 : 0)
 109
 110 #define is_be_mode_mc(sc)       ((sc->function_mode & FNM_FLEX10_MODE) ||       \
 111                                 (sc->function_mode & FNM_UMC_MODE)    ||        \
 112                                 (sc->function_mode & FNM_VNIC_MODE))
 113 #define OCE_FUNCTION_CAPS_SUPER_NIC     0x40
 114 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC)
 115
 116
 117 /* proportion Service Level Interface queues */
 118 #define OCE_MAX_UNITS                   2
 119 #define OCE_MAX_PPORT                   OCE_MAX_UNITS
 120 #define OCE_MAX_VPORT                   OCE_MAX_UNITS
 121
 122 extern int mp_ncpus;                    /* system's total active cpu cores */
 123 #define OCE_NCPUS                       mp_ncpus
 124
 125 /* This should be powers of 2. Like 2,4,8 & 16 */
 126 #define OCE_MAX_RSS                     8
 127 #define OCE_LEGACY_MODE_RSS             4 /* For BE3 Legacy mode*/
 128 #define is_rss_enabled(sc)              ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc))
 129
 130 #define OCE_MIN_RQ                      1
 131 #define OCE_MIN_WQ                      1
 132
 133 #define OCE_MAX_RQ                      OCE_MAX_RSS + 1 /* one default queue */
 134 #define OCE_MAX_WQ                      8
 135
 136 #define OCE_MAX_EQ                      32
 137 #define OCE_MAX_CQ                      OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */
 138 #define OCE_MAX_CQ_EQ                   8 /* Max CQ that can attached to an EQ */
 139
 140 #define OCE_DEFAULT_WQ_EQD              16
 141 #define OCE_MAX_PACKET_Q                16
 142 #define OCE_RQ_BUF_SIZE                 2048
 143 #define OCE_LSO_MAX_SIZE                (64 * 1024)
 144 #define LONG_TIMEOUT                    30
 145 #define OCE_MAX_JUMBO_FRAME_SIZE        9018
 146 #define OCE_MAX_MTU                     (OCE_MAX_JUMBO_FRAME_SIZE - \
 147                                                 ETHER_VLAN_ENCAP_LEN - \
 148                                                 ETHER_HDR_LEN)
 149
 150 #define OCE_MAX_TX_ELEMENTS             29
 151 #define OCE_MAX_TX_DESC                 1024
 152 #define OCE_MAX_TX_SIZE                 65535
 153 #define OCE_MAX_RX_SIZE                 4096
 154 #define OCE_MAX_RQ_POSTS                255
 155 #define OCE_DEFAULT_PROMISCUOUS         0
 156
 157
 158 #define RSS_ENABLE_IPV4                 0x1
 159 #define RSS_ENABLE_TCP_IPV4             0x2
 160 #define RSS_ENABLE_IPV6                 0x4
 161 #define RSS_ENABLE_TCP_IPV6             0x8
 162
 163 #define INDIRECTION_TABLE_ENTRIES       128
 164
 165 /* flow control definitions */
 166 #define OCE_FC_NONE                     0x00000000
 167 #define OCE_FC_TX                       0x00000001
 168 #define OCE_FC_RX                       0x00000002
 169 #define OCE_DEFAULT_FLOW_CONTROL        (OCE_FC_TX | OCE_FC_RX)
 170
 171
 172 /* Interface capabilities to give device when creating interface */
 173 #define  OCE_CAPAB_FLAGS                (MBX_RX_IFACE_FLAGS_BROADCAST    | \
 174                                         MBX_RX_IFACE_FLAGS_UNTAGGED      | \
 175                                         MBX_RX_IFACE_FLAGS_PROMISCUOUS      | \
 176                                         MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS |   \
 177                                         MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS   | \
 178                                         MBX_RX_IFACE_FLAGS_RSS | \
 179                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 180
 181 /* Interface capabilities to enable by default (others set dynamically) */
 182 #define  OCE_CAPAB_ENABLE               (MBX_RX_IFACE_FLAGS_BROADCAST | \
 183                                         MBX_RX_IFACE_FLAGS_UNTAGGED   | \
 184                                         MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR)
 185
 186 #define OCE_IF_HWASSIST                 (CSUM_IP | CSUM_TCP | CSUM_UDP)
 187 #define OCE_IF_CAPABILITIES             (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
 188                                         IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \
 189                                         IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU)
 190 #define OCE_IF_HWASSIST_NONE            0
 191 #define OCE_IF_CAPABILITIES_NONE        0
 192
 193
 194 #define ETH_ADDR_LEN                    6
 195 #define MAX_VLANFILTER_SIZE             64
 196 #define MAX_VLANS                       4096
 197
 198 #define upper_32_bits(n)                ((uint32_t)(((n) >> 16) >> 16))
 199 #define BSWAP_8(x)                      ((x) & 0xff)
 200 #define BSWAP_16(x)                     ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8))
 201 #define BSWAP_32(x)                     ((BSWAP_16(x) << 16) | \
 202                                          BSWAP_16((x) >> 16))
 203 #define BSWAP_64(x)                     ((BSWAP_32(x) << 32) | \
 204                                         BSWAP_32((x) >> 32))
 205
 206 #define for_all_wq_queues(sc, wq, i)    \
 207                 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i])
 208 #define for_all_rq_queues(sc, rq, i)    \
 209                 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i])
 210 #define for_all_rss_queues(sc, rq, i)   \
 211                 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \
 212                      i++, rq = sc->rq[i + 1])
 213 #define for_all_evnt_queues(sc, eq, i)  \
 214                 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i])
 215 #define for_all_cq_queues(sc, cq, i)    \
 216                 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i])
 217
 218
 219 /* Flash specific */
 220 #define IOCTL_COOKIE                    "SERVERENGINES CORP"
 221 #define MAX_FLASH_COMP                  32
 222
 223 #define IMG_ISCSI                       160
 224 #define IMG_REDBOOT                     224
 225 #define IMG_BIOS                        34
 226 #define IMG_PXEBIOS                     32
 227 #define IMG_FCOEBIOS                    33
 228 #define IMG_ISCSI_BAK                   176
 229 #define IMG_FCOE                        162
 230 #define IMG_FCOE_BAK                    178
 231 #define IMG_NCSI                        16
 232 #define IMG_PHY                         192
 233 #define FLASHROM_OPER_FLASH             1
 234 #define FLASHROM_OPER_SAVE              2
 235 #define FLASHROM_OPER_REPORT            4
 236 #define FLASHROM_OPER_FLASH_PHY         9
 237 #define FLASHROM_OPER_SAVE_PHY          10
 238 #define TN_8022                         13
 239
 240 enum {
 241         PHY_TYPE_CX4_10GB = 0,
 242         PHY_TYPE_XFP_10GB,
 243         PHY_TYPE_SFP_1GB,
 244         PHY_TYPE_SFP_PLUS_10GB,
 245         PHY_TYPE_KR_10GB,
 246         PHY_TYPE_KX4_10GB,
 247         PHY_TYPE_BASET_10GB,
 248         PHY_TYPE_BASET_1GB,
 249         PHY_TYPE_BASEX_1GB,
 250         PHY_TYPE_SGMII,
 251         PHY_TYPE_DISABLED = 255
 252 };
 253
 254 /**
 255  * @brief Define and hold all necessary info for a single interrupt
 256  */
 257 #define OCE_MAX_MSI                     32 /* Message Signaled Interrupts */
 258 #define OCE_MAX_MSIX                    2048 /* PCI Express MSI Interrrupts */
 259
 260 typedef struct oce_intr_info {
 261         void *tag;              /* cookie returned by bus_setup_intr */
 262         struct resource *intr_res;      /* PCI resource container */
 263         int irq_rr;             /* resource id for the interrupt */
 264         struct oce_softc *sc;   /* pointer to the parent soft c */
 265         struct oce_eq *eq;      /* pointer to the connected EQ */
 266         struct taskqueue *tq;   /* Associated task queue */
 267         struct task task;       /* task queue task */
 268         char task_name[32];     /* task name */
 269         int vector;             /* interrupt vector number */
 270 } OCE_INTR_INFO, *POCE_INTR_INFO;
 271
 272
 273 /* Ring related */
 274 #define GET_Q_NEXT(_START, _STEP, _END) \
 275         (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \
 276         : (((_START) + (_STEP)) - (_END)))
 277
 278 #define DBUF_PA(obj)                    ((obj)->addr)
 279 #define DBUF_VA(obj)                    ((obj)->ptr)
 280 #define DBUF_TAG(obj)                   ((obj)->tag)
 281 #define DBUF_MAP(obj)                   ((obj)->map)
 282 #define DBUF_SYNC(obj, flags)           \
 283                 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags))
 284
 285 #define RING_NUM_PENDING(ring)          ring->num_used
 286 #define RING_FULL(ring)                 (ring->num_used == ring->num_items)
 287 #define RING_EMPTY(ring)                (ring->num_used == 0)
 288 #define RING_NUM_FREE(ring)             \
 289                 (uint32_t)(ring->num_items - ring->num_used)
 290 #define RING_GET(ring, n)               \
 291                 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items)
 292 #define RING_PUT(ring, n)               \
 293                 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items)
 294
 295 #define RING_GET_CONSUMER_ITEM_VA(ring, type)   \
 296         (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx)
 297 #define RING_GET_CONSUMER_ITEM_PA(ring, type)           \
 298         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx)
 299 #define RING_GET_PRODUCER_ITEM_VA(ring, type)           \
 300         (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx)
 301 #define RING_GET_PRODUCER_ITEM_PA(ring, type)           \
 302         (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx)
 303
 304 #define OCE_DMAPTR(o, c)                ((c *)(o)->ptr)
 305
 306 struct oce_packet_desc {
 307         struct mbuf *mbuf;
 308         bus_dmamap_t map;
 309         int nsegs;
 310         uint32_t wqe_idx;
 311 };
 312
 313 typedef struct oce_dma_mem {
 314         bus_dma_tag_t tag;
 315         bus_dmamap_t map;
 316         void *ptr;
 317         bus_addr_t paddr;
 318 } OCE_DMA_MEM, *POCE_DMA_MEM;
 319
 320 typedef struct oce_ring_buffer_s {
 321         uint16_t cidx;  /* Get ptr */
 322         uint16_t pidx;  /* Put Ptr */
 323         size_t item_size;
 324         size_t num_items;
 325         uint32_t num_used;
 326         OCE_DMA_MEM dma;
 327 } oce_ring_buffer_t;
 328
 329 /* Stats */
 330 #define OCE_UNICAST_PACKET      0
 331 #define OCE_MULTICAST_PACKET    1
 332 #define OCE_BROADCAST_PACKET    2
 333 #define OCE_RSVD_PACKET         3
 334
 335 struct oce_rx_stats {
 336         /* Total Receive Stats*/
 337         uint64_t t_rx_pkts;
 338         uint64_t t_rx_bytes;
 339         uint32_t t_rx_frags;
 340         uint32_t t_rx_mcast_pkts;
 341         uint32_t t_rx_ucast_pkts;
 342         uint32_t t_rxcp_errs;
 343 };
 344 struct oce_tx_stats {
 345         /*Total Transmit Stats */
 346         uint64_t t_tx_pkts;
 347         uint64_t t_tx_bytes;
 348         uint32_t t_tx_reqs;
 349         uint32_t t_tx_stops;
 350         uint32_t t_tx_wrbs;
 351         uint32_t t_tx_compl;
 352         uint32_t t_ipv6_ext_hdr_tx_drop;
 353 };
 354
 355 struct oce_be_stats {
 356         uint8_t  be_on_die_temperature;
 357         uint32_t be_tx_events;
 358         uint32_t eth_red_drops;
 359         uint32_t rx_drops_no_pbuf;
 360         uint32_t rx_drops_no_txpb;
 361         uint32_t rx_drops_no_erx_descr;
 362         uint32_t rx_drops_no_tpre_descr;
 363         uint32_t rx_drops_too_many_frags;
 364         uint32_t rx_drops_invalid_ring;
 365         uint32_t forwarded_packets;
 366         uint32_t rx_drops_mtu;
 367         uint32_t rx_crc_errors;
 368         uint32_t rx_alignment_symbol_errors;
 369         uint32_t rx_pause_frames;
 370         uint32_t rx_priority_pause_frames;
 371         uint32_t rx_control_frames;
 372         uint32_t rx_in_range_errors;
 373         uint32_t rx_out_range_errors;
 374         uint32_t rx_frame_too_long;
 375         uint32_t rx_address_match_errors;
 376         uint32_t rx_dropped_too_small;
 377         uint32_t rx_dropped_too_short;
 378         uint32_t rx_dropped_header_too_small;
 379         uint32_t rx_dropped_tcp_length;
 380         uint32_t rx_dropped_runt;
 381         uint32_t rx_ip_checksum_errs;
 382         uint32_t rx_tcp_checksum_errs;
 383         uint32_t rx_udp_checksum_errs;
 384         uint32_t rx_switched_unicast_packets;
 385         uint32_t rx_switched_multicast_packets;
 386         uint32_t rx_switched_broadcast_packets;
 387         uint32_t tx_pauseframes;
 388         uint32_t tx_priority_pauseframes;
 389         uint32_t tx_controlframes;
 390         uint32_t rxpp_fifo_overflow_drop;
 391         uint32_t rx_input_fifo_overflow_drop;
 392         uint32_t pmem_fifo_overflow_drop;
 393         uint32_t jabber_events;
 394 };
 395
 396 struct oce_xe201_stats {
 397         uint64_t tx_pkts;
 398         uint64_t tx_unicast_pkts;
 399         uint64_t tx_multicast_pkts;
 400         uint64_t tx_broadcast_pkts;
 401         uint64_t tx_bytes;
 402         uint64_t tx_unicast_bytes;
 403         uint64_t tx_multicast_bytes;
 404         uint64_t tx_broadcast_bytes;
 405         uint64_t tx_discards;
 406         uint64_t tx_errors;
 407         uint64_t tx_pause_frames;
 408         uint64_t tx_pause_on_frames;
 409         uint64_t tx_pause_off_frames;
 410         uint64_t tx_internal_mac_errors;
 411         uint64_t tx_control_frames;
 412         uint64_t tx_pkts_64_bytes;
 413         uint64_t tx_pkts_65_to_127_bytes;
 414         uint64_t tx_pkts_128_to_255_bytes;
 415         uint64_t tx_pkts_256_to_511_bytes;
 416         uint64_t tx_pkts_512_to_1023_bytes;
 417         uint64_t tx_pkts_1024_to_1518_bytes;
 418         uint64_t tx_pkts_1519_to_2047_bytes;
 419         uint64_t tx_pkts_2048_to_4095_bytes;
 420         uint64_t tx_pkts_4096_to_8191_bytes;
 421         uint64_t tx_pkts_8192_to_9216_bytes;
 422         uint64_t tx_lso_pkts;
 423         uint64_t rx_pkts;
 424         uint64_t rx_unicast_pkts;
 425         uint64_t rx_multicast_pkts;
 426         uint64_t rx_broadcast_pkts;
 427         uint64_t rx_bytes;
 428         uint64_t rx_unicast_bytes;
 429         uint64_t rx_multicast_bytes;
 430         uint64_t rx_broadcast_bytes;
 431         uint32_t rx_unknown_protos;
 432         uint64_t rx_discards;
 433         uint64_t rx_errors;
 434         uint64_t rx_crc_errors;
 435         uint64_t rx_alignment_errors;
 436         uint64_t rx_symbol_errors;
 437         uint64_t rx_pause_frames;
 438         uint64_t rx_pause_on_frames;
 439         uint64_t rx_pause_off_frames;
 440         uint64_t rx_frames_too_long;
 441         uint64_t rx_internal_mac_errors;
 442         uint32_t rx_undersize_pkts;
 443         uint32_t rx_oversize_pkts;
 444         uint32_t rx_fragment_pkts;
 445         uint32_t rx_jabbers;
 446         uint64_t rx_control_frames;
 447         uint64_t rx_control_frames_unknown_opcode;
 448         uint32_t rx_in_range_errors;
 449         uint32_t rx_out_of_range_errors;
 450         uint32_t rx_address_match_errors;
 451         uint32_t rx_vlan_mismatch_errors;
 452         uint32_t rx_dropped_too_small;
 453         uint32_t rx_dropped_too_short;
 454         uint32_t rx_dropped_header_too_small;
 455         uint32_t rx_dropped_invalid_tcp_length;
 456         uint32_t rx_dropped_runt;
 457         uint32_t rx_ip_checksum_errors;
 458         uint32_t rx_tcp_checksum_errors;
 459         uint32_t rx_udp_checksum_errors;
 460         uint32_t rx_non_rss_pkts;
 461         uint64_t rx_ipv4_pkts;
 462         uint64_t rx_ipv6_pkts;
 463         uint64_t rx_ipv4_bytes;
 464         uint64_t rx_ipv6_bytes;
 465         uint64_t rx_nic_pkts;
 466         uint64_t rx_tcp_pkts;
 467         uint64_t rx_iscsi_pkts;
 468         uint64_t rx_management_pkts;
 469         uint64_t rx_switched_unicast_pkts;
 470         uint64_t rx_switched_multicast_pkts;
 471         uint64_t rx_switched_broadcast_pkts;
 472         uint64_t num_forwards;
 473         uint32_t rx_fifo_overflow;
 474         uint32_t rx_input_fifo_overflow;
 475         uint64_t rx_drops_too_many_frags;
 476         uint32_t rx_drops_invalid_queue;
 477         uint64_t rx_drops_mtu;
 478         uint64_t rx_pkts_64_bytes;
 479         uint64_t rx_pkts_65_to_127_bytes;
 480         uint64_t rx_pkts_128_to_255_bytes;
 481         uint64_t rx_pkts_256_to_511_bytes;
 482         uint64_t rx_pkts_512_to_1023_bytes;
 483         uint64_t rx_pkts_1024_to_1518_bytes;
 484         uint64_t rx_pkts_1519_to_2047_bytes;
 485         uint64_t rx_pkts_2048_to_4095_bytes;
 486         uint64_t rx_pkts_4096_to_8191_bytes;
 487         uint64_t rx_pkts_8192_to_9216_bytes;
 488 };
 489
 490 struct oce_drv_stats {
 491         struct oce_rx_stats rx;
 492         struct oce_tx_stats tx;
 493         union {
 494                 struct oce_be_stats be;
 495                 struct oce_xe201_stats xe201;
 496         } u0;
 497 };
 498
 499 #define INTR_RATE_HWM                   15000
 500 #define INTR_RATE_LWM                   10000
 501
 502 #define OCE_MAX_EQD 128u
 503 #define OCE_MIN_EQD 50u
 504
 505 struct oce_set_eqd {
 506         uint32_t eq_id;
 507         uint32_t phase;
 508         uint32_t delay_multiplier;
 509 };
 510
 511 struct oce_aic_obj {             /* Adaptive interrupt coalescing (AIC) info */
 512         boolean_t enable;
 513         uint32_t  min_eqd;            /* in usecs */
 514         uint32_t  max_eqd;            /* in usecs */
 515         uint32_t  cur_eqd;            /* in usecs */
 516         uint32_t  et_eqd;             /* configured value when aic is off */
 517         uint64_t  ticks;
 518         uint64_t  intr_prev;
 519 };
 520
 521 #define MAX_LOCK_DESC_LEN                       32
 522 struct oce_lock {
 523         struct mtx mutex;
 524         char name[MAX_LOCK_DESC_LEN+1];
 525 };
 526 #define OCE_LOCK                                struct oce_lock
 527
 528 #define LOCK_CREATE(lock, desc)                 { \
 529         strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \
 530         (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \
 531         mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \
 532 }
 533 #define LOCK_DESTROY(lock)                      \
 534                 if (mtx_initialized(&(lock)->mutex))\
 535                         mtx_destroy(&(lock)->mutex)
 536 #define TRY_LOCK(lock)                          mtx_trylock(&(lock)->mutex)
 537 #define LOCK(lock)                              mtx_lock(&(lock)->mutex)
 538 #define LOCKED(lock)                            mtx_owned(&(lock)->mutex)
 539 #define UNLOCK(lock)                            mtx_unlock(&(lock)->mutex)
 540
 541 #define DEFAULT_MQ_MBOX_TIMEOUT                 (5 * 1000 * 1000)
 542 #define MBX_READY_TIMEOUT                       (1 * 1000 * 1000)
 543 #define DEFAULT_DRAIN_TIME                      200
 544 #define MBX_TIMEOUT_SEC                         5
 545 #define STAT_TIMEOUT                            2000000
 546
 547 /* size of the packet descriptor array in a transmit queue */
 548 #define OCE_TX_RING_SIZE                        2048
 549 #define OCE_RX_RING_SIZE                        1024
 550 #define OCE_WQ_PACKET_ARRAY_SIZE                (OCE_TX_RING_SIZE/2)
 551 #define OCE_RQ_PACKET_ARRAY_SIZE                (OCE_RX_RING_SIZE)
 552
 553 struct oce_dev;
 554
 555 enum eq_len {
 556         EQ_LEN_256  = 256,
 557         EQ_LEN_512  = 512,
 558         EQ_LEN_1024 = 1024,
 559         EQ_LEN_2048 = 2048,
 560         EQ_LEN_4096 = 4096
 561 };
 562
 563 enum eqe_size {
 564         EQE_SIZE_4  = 4,
 565         EQE_SIZE_16 = 16
 566 };
 567
 568 enum qtype {
 569         QTYPE_EQ,
 570         QTYPE_MQ,
 571         QTYPE_WQ,
 572         QTYPE_RQ,
 573         QTYPE_CQ,
 574         QTYPE_RSS
 575 };
 576
 577 typedef enum qstate_e {
 578         QDELETED = 0x0,
 579         QCREATED = 0x1
 580 } qstate_t;
 581
 582 struct eq_config {
 583         enum eq_len q_len;
 584         enum eqe_size item_size;
 585         uint32_t q_vector_num;
 586         uint8_t min_eqd;
 587         uint8_t max_eqd;
 588         uint8_t cur_eqd;
 589         uint8_t pad;
 590 };
 591
 592 struct oce_eq {
 593         uint32_t eq_id;
 594         void *parent;
 595         void *cb_context;
 596         oce_ring_buffer_t *ring;
 597         uint32_t ref_count;
 598         qstate_t qstate;
 599         struct oce_cq *cq[OCE_MAX_CQ_EQ];
 600         int cq_valid;
 601         struct eq_config eq_cfg;
 602         int vector;
 603         uint64_t intr;
 604 };
 605
 606 enum cq_len {
 607         CQ_LEN_256  = 256,
 608         CQ_LEN_512  = 512,
 609         CQ_LEN_1024 = 1024
 610 };
 611
 612 struct cq_config {
 613         enum cq_len q_len;
 614         uint32_t item_size;
 615         boolean_t is_eventable;
 616         boolean_t sol_eventable;
 617         boolean_t nodelay;
 618         uint16_t dma_coalescing;
 619 };
 620
 621 typedef uint16_t(*cq_handler_t) (void *arg1);
 622
 623 struct oce_cq {
 624         uint32_t cq_id;
 625         void *parent;
 626         struct oce_eq *eq;
 627         cq_handler_t cq_handler;
 628         void *cb_arg;
 629         oce_ring_buffer_t *ring;
 630         qstate_t qstate;
 631         struct cq_config cq_cfg;
 632         uint32_t ref_count;
 633 };
 634
 635
 636 struct mq_config {
 637         uint32_t eqd;
 638         uint8_t q_len;
 639         uint8_t pad[3];
 640 };
 641
 642
 643 struct oce_mq {
 644         void *parent;
 645         oce_ring_buffer_t *ring;
 646         uint32_t mq_id;
 647         struct oce_cq *cq;
 648         struct oce_cq *async_cq;
 649         uint32_t mq_free;
 650         qstate_t qstate;
 651         struct mq_config cfg;
 652 };
 653
 654 struct oce_mbx_ctx {
 655         struct oce_mbx *mbx;
 656         void (*cb) (void *ctx);
 657         void *cb_ctx;
 658 };
 659
 660 struct wq_config {
 661         uint8_t wq_type;
 662         uint16_t buf_size;
 663         uint8_t pad[1];
 664         uint32_t q_len;
 665         uint16_t pd_id;
 666         uint16_t pci_fn_num;
 667         uint32_t eqd;   /* interrupt delay */
 668         uint32_t nbufs;
 669         uint32_t nhdl;
 670 };
 671
 672 struct oce_tx_queue_stats {
 673         uint64_t tx_pkts;
 674         uint64_t tx_bytes;
 675         uint32_t tx_reqs;
 676         uint32_t tx_stops; /* number of times TX Q was stopped */
 677         uint32_t tx_wrbs;
 678         uint32_t tx_compl;
 679         uint32_t tx_rate;
 680         uint32_t ipv6_ext_hdr_tx_drop;
 681 };
 682
 683 struct oce_wq {
 684         OCE_LOCK tx_lock;
 685         void *parent;
 686         oce_ring_buffer_t *ring;
 687         struct oce_cq *cq;
 688         bus_dma_tag_t tag;
 689         struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE];
 690         uint32_t pkt_desc_tail;
 691         uint32_t pkt_desc_head;
 692         uint32_t wqm_used;
 693         boolean_t resched;
 694         uint32_t wq_free;
 695         uint32_t tx_deferd;
 696         uint32_t pkt_drops;
 697         qstate_t qstate;
 698         uint16_t wq_id;
 699         struct wq_config cfg;
 700         int queue_index;
 701         struct oce_tx_queue_stats tx_stats;
 702         struct buf_ring *br;
 703         struct task txtask;
 704         uint32_t db_offset;
 705 };
 706
 707 struct rq_config {
 708         uint32_t q_len;
 709         uint32_t frag_size;
 710         uint32_t mtu;
 711         uint32_t if_id;
 712         uint32_t is_rss_queue;
 713         uint32_t eqd;
 714         uint32_t nbufs;
 715 };
 716
 717 struct oce_rx_queue_stats {
 718         uint32_t rx_post_fail;
 719         uint32_t rx_ucast_pkts;
 720         uint32_t rx_compl;
 721         uint64_t rx_bytes;
 722         uint64_t rx_bytes_prev;
 723         uint64_t rx_pkts;
 724         uint32_t rx_rate;
 725         uint32_t rx_mcast_pkts;
 726         uint32_t rxcp_err;
 727         uint32_t rx_frags;
 728         uint32_t prev_rx_frags;
 729         uint32_t rx_fps;
 730 };
 731
 732
 733 struct oce_rq {
 734         struct rq_config cfg;
 735         uint32_t rq_id;
 736         int queue_index;
 737         uint32_t rss_cpuid;
 738         void *parent;
 739         oce_ring_buffer_t *ring;
 740         struct oce_cq *cq;
 741         void *pad1;
 742         bus_dma_tag_t tag;
 743         struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE];
 744         uint32_t packets_in;
 745         uint32_t packets_out;
 746         uint32_t pending;
 747 #ifdef notdef
 748         struct mbuf *head;
 749         struct mbuf *tail;
 750         int fragsleft;
 751 #endif
 752         qstate_t qstate;
 753         OCE_LOCK rx_lock;
 754         struct oce_rx_queue_stats rx_stats;
 755         struct lro_ctrl lro;
 756         int lro_pkts_queued;
 757
 758 };
 759
 760 struct link_status {
 761         uint8_t phys_port_speed;
 762         uint8_t logical_link_status;
 763         uint16_t qos_link_speed;
 764 };
 765
 766
 767
 768 #define OCE_FLAGS_PCIX                  0x00000001
 769 #define OCE_FLAGS_PCIE                  0x00000002
 770 #define OCE_FLAGS_MSI_CAPABLE           0x00000004
 771 #define OCE_FLAGS_MSIX_CAPABLE          0x00000008
 772 #define OCE_FLAGS_USING_MSI             0x00000010
 773 #define OCE_FLAGS_USING_MSIX            0x00000020
 774 #define OCE_FLAGS_FUNCRESET_RQD         0x00000040
 775 #define OCE_FLAGS_VIRTUAL_PORT          0x00000080
 776 #define OCE_FLAGS_MBOX_ENDIAN_RQD       0x00000100
 777 #define OCE_FLAGS_BE3                   0x00000200
 778 #define OCE_FLAGS_XE201                 0x00000400
 779 #define OCE_FLAGS_BE2                   0x00000800
 780 #define OCE_FLAGS_SH                    0x00001000
 781
 782 #define OCE_DEV_BE2_CFG_BAR             1
 783 #define OCE_DEV_CFG_BAR                 0
 784 #define OCE_PCI_CSR_BAR                 2
 785 #define OCE_PCI_DB_BAR                  4
 786
 787 typedef struct oce_softc {
 788         device_t dev;
 789         OCE_LOCK dev_lock;
 790
 791         uint32_t flags;
 792
 793         uint32_t pcie_link_speed;
 794         uint32_t pcie_link_width;
 795
 796         uint8_t fn; /* PCI function number */
 797
 798         struct resource *devcfg_res;
 799         bus_space_tag_t devcfg_btag;
 800         bus_space_handle_t devcfg_bhandle;
 801         void *devcfg_vhandle;
 802
 803         struct resource *csr_res;
 804         bus_space_tag_t csr_btag;
 805         bus_space_handle_t csr_bhandle;
 806         void *csr_vhandle;
 807
 808         struct resource *db_res;
 809         bus_space_tag_t db_btag;
 810         bus_space_handle_t db_bhandle;
 811         void *db_vhandle;
 812
 813         OCE_INTR_INFO intrs[OCE_MAX_EQ];
 814         int intr_count;
 815
 816         struct ifnet *ifp;
 817
 818         struct ifmedia media;
 819         uint8_t link_status;
 820         uint8_t link_speed;
 821         uint8_t duplex;
 822         uint32_t qos_link_speed;
 823         uint32_t speed;
 824
 825         char fw_version[32];
 826         struct mac_address_format macaddr;
 827
 828         OCE_DMA_MEM bsmbx;
 829         OCE_LOCK bmbx_lock;
 830
 831         uint32_t config_number;
 832         uint32_t asic_revision;
 833         uint32_t port_id;
 834         uint32_t function_mode;
 835         uint32_t function_caps;
 836         uint32_t max_tx_rings;
 837         uint32_t max_rx_rings;
 838
 839         struct oce_wq *wq[OCE_MAX_WQ];  /* TX work queues */
 840         struct oce_rq *rq[OCE_MAX_RQ];  /* RX work queues */
 841         struct oce_cq *cq[OCE_MAX_CQ];  /* Completion queues */
 842         struct oce_eq *eq[OCE_MAX_EQ];  /* Event queues */
 843         struct oce_mq *mq;              /* Mailbox queue */
 844
 845         uint32_t neqs;
 846         uint32_t ncqs;
 847         uint32_t nrqs;
 848         uint32_t nwqs;
 849         uint32_t nrssqs;
 850
 851         uint32_t tx_ring_size;
 852         uint32_t rx_ring_size;
 853         uint32_t rq_frag_size;
 854
 855         uint32_t if_id;         /* interface ID */
 856         uint32_t nifs;          /* number of adapter interfaces, 0 or 1 */
 857         uint32_t pmac_id;       /* PMAC id */
 858
 859         uint32_t if_cap_flags;
 860
 861         uint32_t flow_control;
 862         uint8_t  promisc;
 863
 864         struct oce_aic_obj aic_obj[OCE_MAX_EQ];
 865
 866         /*Vlan Filtering related */
 867         eventhandler_tag vlan_attach;
 868         eventhandler_tag vlan_detach;
 869         uint16_t vlans_added;
 870         uint8_t vlan_tag[MAX_VLANS];
 871         /*stats */
 872         OCE_DMA_MEM stats_mem;
 873         struct oce_drv_stats oce_stats_info;
 874         struct callout  timer;
 875         int8_t be3_native;
 876         uint8_t hw_error;
 877         uint16_t qnq_debug_event;
 878         uint16_t qnqid;
 879         uint32_t pvid;
 880         uint32_t max_vlans;
 881
 882 } OCE_SOFTC, *POCE_SOFTC;
 883
 884
 885
 886 /**************************************************
 887  * BUS memory read/write macros
 888  * BE3: accesses three BAR spaces (CFG, CSR, DB)
 889  * Lancer: accesses one BAR space (CFG)
 890  **************************************************/
 891 #define OCE_READ_CSR_MPU(sc, space, o) \
 892         ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 893                                         (sc)->space##_bhandle,o)) \
 894                                 : (bus_space_read_4((sc)->devcfg_btag, \
 895                                         (sc)->devcfg_bhandle,o)))
 896 #define OCE_READ_REG32(sc, space, o) \
 897         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \
 898                                         (sc)->space##_bhandle,o)) \
 899                                 : (bus_space_read_4((sc)->devcfg_btag, \
 900                                         (sc)->devcfg_bhandle,o)))
 901 #define OCE_READ_REG16(sc, space, o) \
 902         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \
 903                                         (sc)->space##_bhandle,o)) \
 904                                 : (bus_space_read_2((sc)->devcfg_btag, \
 905                                         (sc)->devcfg_bhandle,o)))
 906 #define OCE_READ_REG8(sc, space, o) \
 907         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \
 908                                         (sc)->space##_bhandle,o)) \
 909                                 : (bus_space_read_1((sc)->devcfg_btag, \
 910                                         (sc)->devcfg_bhandle,o)))
 911
 912 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \
 913         ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 914                                        (sc)->space##_bhandle,o,v)) \
 915                                 : (bus_space_write_4((sc)->devcfg_btag, \
 916                                         (sc)->devcfg_bhandle,o,v)))
 917 #define OCE_WRITE_REG32(sc, space, o, v) \
 918         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \
 919                                        (sc)->space##_bhandle,o,v)) \
 920                                 : (bus_space_write_4((sc)->devcfg_btag, \
 921                                         (sc)->devcfg_bhandle,o,v)))
 922 #define OCE_WRITE_REG16(sc, space, o, v) \
 923         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \
 924                                        (sc)->space##_bhandle,o,v)) \
 925                                 : (bus_space_write_2((sc)->devcfg_btag, \
 926                                         (sc)->devcfg_bhandle,o,v)))
 927 #define OCE_WRITE_REG8(sc, space, o, v) \
 928         ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \
 929                                        (sc)->space##_bhandle,o,v)) \
 930                                 : (bus_space_write_1((sc)->devcfg_btag, \
 931                                         (sc)->devcfg_bhandle,o,v)))
 932
 933
 934 /***********************************************************
 935  * DMA memory functions
 936  ***********************************************************/
 937 #define oce_dma_sync(d, f)              bus_dmamap_sync((d)->tag, (d)->map, f)
 938 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags);
 939 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma);
 940 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error);
 941 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring);
 942 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc,
 943                                           uint32_t q_len, uint32_t num_entries);
 944 /************************************************************
 945  * oce_hw_xxx functions
 946  ************************************************************/
 947 int oce_clear_rx_buf(struct oce_rq *rq);
 948 int oce_hw_pci_alloc(POCE_SOFTC sc);
 949 int oce_hw_init(POCE_SOFTC sc);
 950 int oce_hw_start(POCE_SOFTC sc);
 951 int oce_create_nw_interface(POCE_SOFTC sc);
 952 int oce_pci_soft_reset(POCE_SOFTC sc);
 953 int oce_hw_update_multicast(POCE_SOFTC sc);
 954 void oce_delete_nw_interface(POCE_SOFTC sc);
 955 void oce_hw_shutdown(POCE_SOFTC sc);
 956 void oce_hw_intr_enable(POCE_SOFTC sc);
 957 void oce_hw_intr_disable(POCE_SOFTC sc);
 958 void oce_hw_pci_free(POCE_SOFTC sc);
 959
 960 /***********************************************************
 961  * oce_queue_xxx functions
 962  ***********************************************************/
 963 int oce_queue_init_all(POCE_SOFTC sc);
 964 int oce_start_rq(struct oce_rq *rq);
 965 int oce_start_wq(struct oce_wq *wq);
 966 int oce_start_mq(struct oce_mq *mq);
 967 int oce_start_rx(POCE_SOFTC sc);
 968 void oce_arm_eq(POCE_SOFTC sc,
 969                 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint);
 970 void oce_queue_release_all(POCE_SOFTC sc);
 971 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm);
 972 void oce_drain_eq(struct oce_eq *eq);
 973 void oce_drain_mq_cq(void *arg);
 974 void oce_drain_rq_cq(struct oce_rq *rq);
 975 void oce_drain_wq_cq(struct oce_wq *wq);
 976
 977 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list);
 978
 979 /***********************************************************
 980  * cleanup  functions
 981  ***********************************************************/
 982 void oce_stop_rx(POCE_SOFTC sc);
 983 void oce_intr_free(POCE_SOFTC sc);
 984 void oce_free_posted_rxbuf(struct oce_rq *rq);
 985 #if defined(INET6) || defined(INET)
 986 void oce_free_lro(POCE_SOFTC sc);
 987 #endif
 988
 989
 990 /************************************************************
 991  * Mailbox functions
 992  ************************************************************/
 993 int oce_fw_clean(POCE_SOFTC sc);
 994 int oce_reset_fun(POCE_SOFTC sc);
 995 int oce_mbox_init(POCE_SOFTC sc);
 996 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec);
 997 int oce_get_fw_version(POCE_SOFTC sc);
 998 int oce_first_mcc_cmd(POCE_SOFTC sc);
 999
1000 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm,
1001                         uint8_t type, struct mac_address_format *mac);
1002 int oce_get_fw_config(POCE_SOFTC sc);
1003 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags,
1004                 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id);
1005 int oce_if_del(POCE_SOFTC sc, uint32_t if_id);
1006 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id,
1007                 struct normal_vlan *vtag_arr, uint8_t vtag_cnt,
1008                 uint32_t untagged, uint32_t enable_promisc);
1009 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control);
1010 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss);
1011 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable);
1012 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl);
1013 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link);
1014 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1015 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem);
1016 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1017                                 uint32_t reset_stats);
1018 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem,
1019                                 uint32_t req_size, uint32_t reset_stats);
1020 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem);
1021 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size);
1022 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id);
1023 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr,
1024                 uint32_t if_id, uint32_t *pmac_id);
1025 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num,
1026         uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts,
1027         uint64_t pattern);
1028
1029 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num,
1030         uint8_t loopback_type, uint8_t enable);
1031
1032 int oce_mbox_check_native_mode(POCE_SOFTC sc);
1033 int oce_mbox_post(POCE_SOFTC sc,
1034                   struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx);
1035 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode,
1036                                 POCE_DMA_MEM pdma_mem, uint32_t num_bytes);
1037 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size,
1038                         uint32_t data_offset,POCE_DMA_MEM pdma_mem,
1039                         uint32_t *written_data, uint32_t *additional_status);
1040
1041 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc,
1042                                 uint32_t offset, uint32_t optype);
1043 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info);
1044 int oce_mbox_create_rq(struct oce_rq *rq);
1045 int oce_mbox_create_wq(struct oce_wq *wq);
1046 int oce_mbox_create_eq(struct oce_eq *eq);
1047 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce,
1048                          uint32_t is_eventable);
1049 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num);
1050 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd,
1051                                         int num);
1052 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss);
1053 int oce_get_func_config(POCE_SOFTC sc);
1054 void mbx_common_req_hdr_init(struct mbx_hdr *hdr,
1055                              uint8_t dom,
1056                              uint8_t port,
1057                              uint8_t subsys,
1058                              uint8_t opcode,
1059                              uint32_t timeout, uint32_t pyld_len,
1060                              uint8_t version);
1061
1062
1063 uint16_t oce_mq_handler(void *arg);
1064
1065 /************************************************************
1066  * Transmit functions
1067  ************************************************************/
1068 uint16_t oce_wq_handler(void *arg);
1069 void     oce_start(struct ifnet *ifp);
1070 void     oce_tx_task(void *arg, int npending);
1071
1072 /************************************************************
1073  * Receive functions
1074  ************************************************************/
1075 int      oce_alloc_rx_bufs(struct oce_rq *rq, int count);
1076 uint16_t oce_rq_handler(void *arg);
1077
1078
1079 /* Sysctl functions */
1080 void oce_add_sysctls(POCE_SOFTC sc);
1081 void oce_refresh_queue_stats(POCE_SOFTC sc);
1082 int  oce_refresh_nic_stats(POCE_SOFTC sc);
1083 int  oce_stats_init(POCE_SOFTC sc);
1084 void oce_stats_free(POCE_SOFTC sc);
1085
1086 /* Capabilities */
1087 #define OCE_MODCAP_RSS                  1
1088 #define OCE_MAX_RSP_HANDLED             64
1089 extern uint32_t oce_max_rsp_handled;    /* max responses */
1090
1091 #define OCE_MAC_LOOPBACK                0x0
1092 #define OCE_PHY_LOOPBACK                0x1
1093 #define OCE_ONE_PORT_EXT_LOOPBACK       0x2
1094 #define OCE_NO_LOOPBACK                 0xff
1095
1096 #undef IFM_40G_SR4
1097 #define IFM_40G_SR4                     28
1098
1099 #define atomic_inc_32(x)                atomic_add_32(x, 1)
1100 #define atomic_dec_32(x)                atomic_subtract_32(x, 1)
1101
1102 #define LE_64(x)                        htole64(x)
1103 #define LE_32(x)                        htole32(x)
1104 #define LE_16(x)                        htole16(x)
1105 #define HOST_64(x)                      le64toh(x)
1106 #define HOST_32(x)                      le32toh(x)
1107 #define HOST_16(x)                      le16toh(x)
1108 #define DW_SWAP(x, l)
1109 #define IS_ALIGNED(x,a)                 ((x % a) == 0)
1110 #define ADDR_HI(x)                      ((uint32_t)((uint64_t)(x) >> 32))
1111 #define ADDR_LO(x)                      ((uint32_t)((uint64_t)(x) & 0xffffffff));
1112
1113 #define IF_LRO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0)
1114 #define IF_LSO_ENABLED(sc)  (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0)
1115 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0)
1116
1117 #define OCE_LOG2(x)                     (oce_highbit(x))
1118 static inline uint32_t oce_highbit(uint32_t x)
1119 {
1120         int i;
1121         int c;
1122         int b;
1123
1124         c = 0;
1125         b = 0;
1126
1127         for (i = 0; i < 32; i++) {
1128                 if ((1 << i) & x) {
1129                         c++;
1130                         b = i;
1131                 }
1132         }
1133
1134         if (c == 1)
1135                 return b;
1136
1137         return 0;
1138 }
1139
1140 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc)
1141 {
1142         if (IS_BE(sc))
1143                 return MPU_EP_SEMAPHORE_BE3;
1144         else if (IS_SH(sc))
1145                 return MPU_EP_SEMAPHORE_SH;
1146         else
1147                 return MPU_EP_SEMAPHORE_XE201;
1148 }
1149
1150 #define TRANSCEIVER_DATA_NUM_ELE 64
1151 #define TRANSCEIVER_DATA_SIZE 256
1152 #define TRANSCEIVER_A0_SIZE 128
1153 #define TRANSCEIVER_A2_SIZE 128
1154 #define PAGE_NUM_A0 0xa0
1155 #define PAGE_NUM_A2 0xa2
1156 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\
1157                      || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE)))
1158