2 * Copyright (c) 2002-2004 M. Warner Losh.
3 * Copyright (c) 2000-2001 Jonathan Chen.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Copyright (c) 1998, 1999 and 2000
31 * HAYAKAWA Koichi. All rights reserved.
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. All advertising materials mentioning features or use of this software
42 * must display the following acknowledgement:
43 * This product includes software developed by HAYAKAWA Koichi.
44 * 4. The name of the author may not be used to endorse or promote products
45 * derived from this software without specific prior written permission.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
60 * Driver for PCI to CardBus Bridge chips
64 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
66 * Written by Jonathan Chen <jon@freebsd.org>
67 * The author would like to acknowledge:
68 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
69 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things
70 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
71 * * David Cross: Author of the initial ugly hack for a specific cardbus card
74 #include <sys/cdefs.h>
75 __FBSDID("$FreeBSD$");
77 #include <sys/param.h>
78 #include <sys/systm.h>
80 #include <sys/condvar.h>
81 #include <sys/errno.h>
82 #include <sys/kernel.h>
84 #include <sys/malloc.h>
85 #include <sys/mutex.h>
86 #include <sys/sysctl.h>
87 #include <sys/kthread.h>
89 #include <machine/bus.h>
91 #include <machine/resource.h>
92 #include <sys/module.h>
94 #include <dev/pci/pcireg.h>
95 #include <dev/pci/pcivar.h>
96 #include <dev/pci/pcib_private.h>
98 #include <dev/pccard/pccardreg.h>
99 #include <dev/pccard/pccardvar.h>
101 #include <dev/exca/excareg.h>
102 #include <dev/exca/excavar.h>
104 #include <dev/pccbb/pccbbreg.h>
105 #include <dev/pccbb/pccbbvar.h>
107 #include "power_if.h"
111 #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0)
112 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
114 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
115 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
116 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
117 pci_write_config(DEV, REG, ( \
118 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
120 static void cbb_chipinit(struct cbb_softc *sc);
121 static int cbb_pci_filt(void *arg);
123 static struct yenta_chipinfo {
128 /* Texas Instruments chips */
129 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
130 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
131 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
133 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
134 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
135 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
136 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
137 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
138 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
139 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
140 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
141 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
142 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
143 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
144 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
145 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
146 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
147 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
148 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
149 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
150 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
151 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
152 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
153 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
154 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
155 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
156 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
157 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
158 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
159 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
160 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
161 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
162 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
165 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
166 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
167 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
168 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
169 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
170 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
173 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
174 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
175 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
176 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
177 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
178 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
180 /* Toshiba products */
181 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
182 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
183 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
184 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
187 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
188 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
189 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
192 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
193 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
194 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
195 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
196 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
197 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
198 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
199 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
200 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
201 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
202 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
203 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
206 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
209 {0 /* null id */, "unknown", CB_UNKNOWN},
212 /************************************************************************/
214 /************************************************************************/
217 cbb_chipset(uint32_t pci_id, const char **namep)
219 struct yenta_chipinfo *ycp;
221 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
224 *namep = ycp->yc_name;
225 return (ycp->yc_chiptype);
229 cbb_pci_probe(device_t brdev)
237 * Do we know that we support the chipset? If so, then we
240 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
241 device_set_desc(brdev, name);
242 return (BUS_PROBE_DEFAULT);
246 * We do support generic CardBus bridges. All that we've seen
247 * to date have progif 0 (the Yenta spec, and successors mandate
250 baseclass = pci_get_class(brdev);
251 subclass = pci_get_subclass(brdev);
252 progif = pci_get_progif(brdev);
253 if (baseclass == PCIC_BRIDGE &&
254 subclass == PCIS_BRIDGE_CARDBUS && progif == 0) {
255 device_set_desc(brdev, "PCI-CardBus Bridge");
256 return (BUS_PROBE_GENERIC);
262 * Still need this because the pci code only does power for type 0
266 cbb_powerstate_d0(device_t dev)
268 u_int32_t membase, irq;
270 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
271 /* Save important PCI config data. */
272 membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
273 irq = pci_read_config(dev, PCIR_INTLINE, 4);
275 /* Reset the power state. */
276 device_printf(dev, "chip is in D%d power mode "
277 "-- setting to D0\n", pci_get_powerstate(dev));
279 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
281 /* Restore PCI config data. */
282 pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
283 pci_write_config(dev, PCIR_INTLINE, irq, 4);
288 * Print out the config space
291 cbb_print_config(device_t dev)
295 device_printf(dev, "PCI Configuration space:");
296 for (i = 0; i < 256; i += 4) {
298 printf("\n 0x%02x: ", i);
299 printf("0x%08x ", pci_read_config(dev, i, 4));
305 cbb_pci_attach(device_t brdev)
307 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
308 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
311 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
312 struct sysctl_ctx_list *sctx;
313 struct sysctl_oid *soid;
317 parent = device_get_parent(brdev);
318 mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF);
319 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
322 sc->exca[0].pccarddev = NULL;
323 sc->domain = pci_get_domain(brdev);
324 sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1);
325 sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
326 sc->pribus = pcib_get_bus(parent);
327 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
328 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
329 pcib_setup_secbus(brdev, &sc->bus, 1);
332 cbb_powerstate_d0(brdev);
335 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
338 device_printf(brdev, "Could not map register memory\n");
339 mtx_destroy(&sc->mtx);
342 DEVPRINTF((brdev, "Found memory at %08lx\n",
343 rman_get_start(sc->base_res)));
346 sc->bst = rman_get_bustag(sc->base_res);
347 sc->bsh = rman_get_bushandle(sc->base_res);
348 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
349 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
350 sc->exca[0].chipset = EXCA_CARDBUS;
351 sc->chipinit = cbb_chipinit;
355 sctx = device_get_sysctl_ctx(brdev);
356 soid = device_get_sysctl_tree(brdev);
357 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
358 CTLFLAG_RD, &sc->domain, 0, "Domain number");
359 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
360 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
361 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
362 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
363 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
364 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
366 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory",
367 CTLFLAG_RD, &sc->subbus, 0, "Memory window open");
368 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem",
369 CTLFLAG_RD, &sc->subbus, 0, "Prefetch memroy window open");
370 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1",
371 CTLFLAG_RD, &sc->subbus, 0, "io range 1 open");
372 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2",
373 CTLFLAG_RD, &sc->subbus, 0, "io range 2 open");
376 #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS))
378 * This is a gross hack. We should be scanning the entire pci
379 * tree, assigning bus numbers in a way such that we (1) can
380 * reserve 1 extra bus just in case and (2) all sub busses
381 * are in an appropriate range.
383 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec));
384 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
385 if (sc->bus.sec == 0 || sc->pribus != pribus) {
386 if (curr_bus_number <= sc->pribus)
387 curr_bus_number = sc->pribus + 1;
388 if (pribus != sc->pribus) {
389 DEVPRINTF((brdev, "Setting primary bus to %d\n",
391 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
393 sc->bus.sec = curr_bus_number++;
394 sc->bus.sub = curr_bus_number++;
395 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
396 sc->bus.sec, sc->bus.sub));
397 pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1);
398 pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1);
402 /* attach children */
403 sc->cbdev = device_add_child(brdev, "cardbus", -1);
404 if (sc->cbdev == NULL)
405 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
406 else if (device_probe_and_attach(sc->cbdev) != 0)
407 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
409 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
410 if (sc->exca[0].pccarddev == NULL)
411 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
412 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
413 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
415 /* Map and establish the interrupt. */
417 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
418 RF_SHAREABLE | RF_ACTIVE);
419 if (sc->irq_res == NULL) {
420 device_printf(brdev, "Unable to map IRQ...\n");
424 if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE,
425 cbb_pci_filt, NULL, sc, &sc->intrhand)) {
426 device_printf(brdev, "couldn't establish interrupt\n");
430 /* reset 16-bit pcmcia bus */
431 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
434 cbb_power(brdev, CARD_OFF);
436 /* CSC Interrupt: Card detect interrupt on */
437 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
439 /* reset interrupt */
440 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
443 cbb_print_config(brdev);
445 /* Start the thread */
446 if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
447 "%s event thread", device_get_nameunit(brdev))) {
448 device_printf(brdev, "unable to create event thread.\n");
449 panic("cbb_create_event_thread");
451 sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev));
455 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
457 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
460 mtx_destroy(&sc->mtx);
465 cbb_chipinit(struct cbb_softc *sc)
467 uint32_t mux, sysctrl, reg;
469 /* Set CardBus latency timer */
470 if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20)
471 pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1);
473 /* Set PCI latency timer */
474 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
475 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
477 /* Restore bus configuration */
478 pci_write_config(sc->dev, PCIR_PRIBUS_2, sc->pribus, 1);
479 pci_write_config(sc->dev, PCIR_SECBUS_2, sc->bus.sec, 1);
480 pci_write_config(sc->dev, PCIR_SUBBUS_2, sc->bus.sub, 1);
482 /* Enable DMA, memory access for this card and I/O acces for children */
483 pci_enable_busmaster(sc->dev);
484 pci_enable_io(sc->dev, SYS_RES_IOPORT);
485 pci_enable_io(sc->dev, SYS_RES_MEMORY);
487 /* disable Legacy IO */
488 switch (sc->chipset) {
490 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
491 & ~(CBBM_BRIDGECTRL_RL_3E0_EN |
492 CBBM_BRIDGECTRL_RL_3E2_EN), 2);
495 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
499 /* Use PCI interrupt for interrupt routing */
500 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
501 & ~(CBBM_BRIDGECTRL_MASTER_ABORT |
502 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN),
503 | CBBM_BRIDGECTRL_WRITE_POST_EN,
507 * XXX this should be a function table, ala OLDCARD. This means
508 * that we could more easily support ISA interrupts for pccard
509 * cards if we had to.
511 switch (sc->chipset) {
514 * The TI 1031, TI 1130 and TI 1131 all require another bit
515 * be set to enable PCI routing of interrupts, and then
516 * a bit for each of the CSC and Function interrupts we
519 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
520 | CBBM_CBCTRL_113X_PCI_INTR |
521 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
523 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
524 & ~(CBBM_DEVCTRL_INT_SERIAL |
525 CBBM_DEVCTRL_INT_PCI), 1);
529 * Some TI 12xx (and [14][45]xx) based pci cards
530 * sometimes have issues with the MFUNC register not
531 * being initialized due to a bad EEPROM on board.
532 * Laptops that this matters on have this register
533 * properly initialized.
535 * The TI125X parts have a different register.
537 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
538 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
540 mux = (mux & ~CBBM_MFUNC_PIN0) |
541 CBBM_MFUNC_PIN0_INTA;
542 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
543 mux = (mux & ~CBBM_MFUNC_PIN1) |
544 CBBM_MFUNC_PIN1_INTB;
545 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
550 * Disable zoom video. Some machines initialize this
551 * improperly and exerpience has shown that this helps
552 * prevent strange behavior.
554 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
558 * Issue #1: INT# generated at the same time as
559 * selected ISA IRQ. When IREQ# or STSCHG# is active,
560 * in addition to the ISA IRQ being generated, INT#
561 * will also be generated at the same time.
563 * Some of the older controllers have an issue in
564 * which the slot's PCI INT# will be asserted whenever
565 * IREQ# or STSCGH# is asserted even if ExCA registers
566 * 03h or 05h have an ISA IRQ selected.
568 * The fix for this issue, which will work for any
569 * controller (old or new), is to set ExCA registers
570 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
571 * These bits are undocumented. By setting this
572 * register (of each slot) to '1010xxxxb' a routing of
573 * IREQ# to INTC# and STSCHG# to INTC# is selected.
574 * Since INTC# isn't connected there will be no
575 * unexpected PCI INT when IREQ# or STSCHG# is active.
576 * However, INTA# (slot 0) or INTB# (slot 1) will
577 * still be correctly generated if NO ISA IRQ is
578 * selected (ExCA regs 03h or 05h are cleared).
580 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
582 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
583 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
587 * Disable Zoom Video, ToPIC 97, 100.
589 pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1);
592 * At offset 0xa1: INTERRUPT CONTROL register
593 * 0x1: Turn on INT interrupts.
595 PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL,
596 | TOPIC97_INTCTRL_INTIRQSEL, 1);
599 * Need to assert support for low voltage cards
601 exca_setb(&sc->exca[0], EXCA_TOPIC97_CTRL,
602 EXCA_TOPIC97_CTRL_LV_MASK);
606 * SOCKETCTRL appears to be TOPIC 95/B specific
608 PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL,
609 | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4);
613 * At offset 0xa0: SLOT CONTROL
614 * 0x80 Enable CardBus Functionality
615 * 0x40 Enable CardBus and PC Card registers
616 * 0x20 Lock ID in exca regs
617 * 0x10 Write protect ID in config regs
618 * Clear the rest of the bits, which defaults the slot
619 * in legacy mode to 0x3e0 and offset 0. (legacy
620 * mode is determined elsewhere)
622 pci_write_config(sc->dev, TOPIC_SLOTCTRL,
623 TOPIC_SLOTCTRL_SLOTON |
624 TOPIC_SLOTCTRL_SLOTEN |
625 TOPIC_SLOTCTRL_ID_LOCK |
626 TOPIC_SLOTCTRL_ID_WP, 1);
629 * At offset 0xa3 Card Detect Control Register
630 * 0x80 CARDBUS enbale
631 * 0x01 Cleared for hardware change detect
633 PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC,
634 | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4);
639 * Need to tell ExCA registers to CSC interrupts route via PCI
640 * interrupts. There are two ways to do this. One is to set
641 * INTR_ENABLE and the other is to set CSC to 0. Since both
642 * methods are mutually compatible, we do both.
644 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
645 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
647 cbb_disable_func_intr(sc);
649 /* close all memory and io windows */
650 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
651 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
652 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
653 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
654 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
655 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
656 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
657 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
661 cbb_route_interrupt(device_t pcib, device_t dev, int pin)
663 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib);
665 return (rman_get_start(sc->irq_res));
669 cbb_pci_shutdown(device_t brdev)
671 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
674 * We're about to pull the rug out from the card, so mark it as
675 * gone to prevent harm.
680 * Place the cards in reset, turn off the interrupts and power
683 PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2);
684 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
685 cbb_set(sc, CBB_SOCKET_MASK, 0);
686 cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff);
687 cbb_power(brdev, CARD_OFF);
690 * For paranoia, turn off all address decoding. Really not needed,
691 * it seems, but it can't hurt
693 exca_putb(&sc->exca[0], EXCA_ADDRWIN_ENABLE, 0);
694 pci_write_config(brdev, CBBR_MEMBASE0, 0, 4);
695 pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4);
696 pci_write_config(brdev, CBBR_MEMBASE1, 0, 4);
697 pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4);
698 pci_write_config(brdev, CBBR_IOBASE0, 0, 4);
699 pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4);
700 pci_write_config(brdev, CBBR_IOBASE1, 0, 4);
701 pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4);
706 cbb_pci_filt(void *arg)
708 struct cbb_softc *sc = arg;
711 int retval = FILTER_STRAY;
714 * Some chips also require us to read the old ExCA registe for card
715 * status change when we route CSC vis PCI. This isn't supposed to be
716 * required, but it clears the interrupt state on some chipsets.
717 * Maybe there's a setting that would obviate its need. Maybe we
718 * should test the status bits and deal with them, but so far we've
719 * not found any machines that don't also give us the socket status
722 * This call used to be unconditional. However, further research
723 * suggests that we hit this condition when the card READY interrupt
724 * fired. So now we only read it for 16-bit cards, and we only claim
725 * the interrupt if READY is set. If this still causes problems, then
726 * the next step would be to read this if we have a 16-bit card *OR*
727 * we have no card. We treat the READY signal as if it were the power
728 * completion signal. Some bridges may double signal things here, bit
729 * signalling twice should be OK since we only sleep on the powerintr
730 * in one place and a double wakeup would be benign there.
732 if (sc->flags & CBB_16BIT_CARD) {
733 csc = exca_getb(&sc->exca[0], EXCA_CSC);
734 if (csc & EXCA_CSC_READY) {
735 atomic_add_int(&sc->powerintr, 1);
736 wakeup((void *)&sc->powerintr);
737 retval = FILTER_HANDLED;
742 * Read the socket event. Sometimes, the theory goes, the PCI bus is
743 * so loaded that it cannot satisfy the read request, so we get
744 * garbage back from the following read. We have to filter out the
745 * garbage so that we don't spontaneously reset the card under high
746 * load. PCI isn't supposed to act like this. No doubt this is a bug
747 * in the PCI bridge chipset (or cbb brige) that's being used in
748 * certain amd64 laptops today. Work around the issue by assuming
749 * that any bits we don't know about being set means that we got
752 sockevent = cbb_get(sc, CBB_SOCKET_EVENT);
753 if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) {
755 * If anything has happened to the socket, we assume that the
756 * card is no longer OK, and we shouldn't call its ISR. We
757 * set cardok as soon as we've attached the card. This helps
758 * in a noisy eject, which happens all too often when users
759 * are ejecting their PC Cards.
761 * We use this method in preference to checking to see if the
762 * card is still there because the check suffers from a race
763 * condition in the bouncing case.
765 #define DELTA (CBB_SOCKET_MASK_CD)
766 if (sockevent & DELTA) {
767 cbb_clrb(sc, CBB_SOCKET_MASK, DELTA);
768 cbb_set(sc, CBB_SOCKET_EVENT, DELTA);
770 cbb_disable_func_intr(sc);
771 wakeup(&sc->intrhand);
776 * Wakeup anybody waiting for a power interrupt. We have to
777 * use atomic_add_int for wakups on other cores.
779 if (sockevent & CBB_SOCKET_EVENT_POWER) {
780 cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER);
781 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER);
782 atomic_add_int(&sc->powerintr, 1);
783 wakeup((void *)&sc->powerintr);
787 * Status change interrupts aren't presently used in the
788 * rest of the driver. For now, just ACK them.
790 if (sockevent & CBB_SOCKET_EVENT_CSTS)
791 cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS);
792 retval = FILTER_HANDLED;
797 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
798 static struct resource *
799 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
800 u_long start, u_long end, u_long count, u_int flags)
802 struct cbb_softc *sc;
804 sc = device_get_softc(bus);
805 if (type == PCI_RES_BUS)
806 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
808 return (cbb_alloc_resource(bus, child, type, rid, start, end, count,
813 cbb_pci_adjust_resource(device_t bus, device_t child, int type,
814 struct resource *r, u_long start, u_long end)
816 struct cbb_softc *sc;
818 sc = device_get_softc(bus);
819 if (type == PCI_RES_BUS) {
820 if (!rman_is_region_manager(r, &sc->bus.rman))
822 return (rman_adjust_resource(r, start, end));
824 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
828 cbb_pci_release_resource(device_t bus, device_t child, int type, int rid,
831 struct cbb_softc *sc;
834 sc = device_get_softc(bus);
835 if (type == PCI_RES_BUS) {
836 if (!rman_is_region_manager(r, &sc->bus.rman))
838 if (rman_get_flags(r) & RF_ACTIVE) {
839 error = bus_deactivate_resource(child, type, rid, r);
843 return (rman_release_resource(r));
845 return (cbb_release_resource(bus, child, type, rid, r));
849 /************************************************************************/
850 /* PCI compat methods */
851 /************************************************************************/
854 cbb_maxslots(device_t brdev)
860 cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width)
863 * Pass through to the next ppb up the chain (i.e. our grandparent).
865 return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)),
866 b, s, f, reg, width));
870 cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val,
874 * Pass through to the next ppb up the chain (i.e. our grandparent).
876 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)),
877 b, s, f, reg, val, width);
881 cbb_pci_suspend(device_t brdev)
884 struct cbb_softc *sc = device_get_softc(brdev);
886 error = bus_generic_suspend(brdev);
889 cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */
890 sc->cardok = 0; /* Card is bogus now */
895 cbb_pci_resume(device_t brdev)
898 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev);
902 * In the APM and early ACPI era, BIOSes saved the PCI config
903 * registers. As chips became more complicated, that functionality moved
904 * into the ACPI code / tables. We must therefore, restore the settings
905 * we made here to make sure the device come back. Transitions to Dx
906 * from D0 and back to D0 cause the bridge to lose its config space, so
907 * all the bus mappings and such are preserved.
909 * For most drivers, the PCI layer handles this saving. However, since
910 * there's much black magic and arcane art hidden in these few lines of
911 * code that would be difficult to transition into the PCI
912 * layer. chipinit was several years of trial and error to write.
914 pci_write_config(brdev, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4);
915 DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n",
916 rman_get_start(sc->base_res)));
920 /* reset interrupt -- Do we really need to do this? */
921 tmp = cbb_get(sc, CBB_SOCKET_EVENT);
922 cbb_set(sc, CBB_SOCKET_EVENT, tmp);
924 /* CSC Interrupt: Card detect interrupt on */
925 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
927 /* Signal the thread to wakeup. */
928 wakeup(&sc->intrhand);
930 error = bus_generic_resume(brdev);
935 static device_method_t cbb_methods[] = {
936 /* Device interface */
937 DEVMETHOD(device_probe, cbb_pci_probe),
938 DEVMETHOD(device_attach, cbb_pci_attach),
939 DEVMETHOD(device_detach, cbb_detach),
940 DEVMETHOD(device_shutdown, cbb_pci_shutdown),
941 DEVMETHOD(device_suspend, cbb_pci_suspend),
942 DEVMETHOD(device_resume, cbb_pci_resume),
945 DEVMETHOD(bus_read_ivar, cbb_read_ivar),
946 DEVMETHOD(bus_write_ivar, cbb_write_ivar),
947 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
948 DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource),
949 DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource),
950 DEVMETHOD(bus_release_resource, cbb_pci_release_resource),
952 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
953 DEVMETHOD(bus_release_resource, cbb_release_resource),
955 DEVMETHOD(bus_activate_resource, cbb_activate_resource),
956 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
957 DEVMETHOD(bus_driver_added, cbb_driver_added),
958 DEVMETHOD(bus_child_detached, cbb_child_detached),
959 DEVMETHOD(bus_setup_intr, cbb_setup_intr),
960 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
961 DEVMETHOD(bus_child_present, cbb_child_present),
963 /* 16-bit card interface */
964 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
965 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
967 /* power interface */
968 DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
969 DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
971 /* pcib compatibility interface */
972 DEVMETHOD(pcib_maxslots, cbb_maxslots),
973 DEVMETHOD(pcib_read_config, cbb_read_config),
974 DEVMETHOD(pcib_write_config, cbb_write_config),
975 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt),
980 static driver_t cbb_driver = {
983 sizeof(struct cbb_softc)
986 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0);
987 MODULE_DEPEND(cbb, exca, 1, 1, 1);