1 /*******************************************************************************
2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
4 *Redistribution and use in source and binary forms, with or without modification, are permitted provided
5 *that the following conditions are met:
6 *1. Redistributions of source code must retain the above copyright notice, this list of conditions and the
8 *2. Redistributions in binary form must reproduce the above copyright notice,
9 *this list of conditions and the following disclaimer in the documentation and/or other materials provided
10 *with the distribution.
12 *THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 *WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
14 *FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
15 *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 *NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
17 *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18 *LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
19 *SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
23 ********************************************************************************/
24 /*******************************************************************************/
26 * \brief The file defines the constants, data structure, and functions defined by LL API
28 /******************************************************************************/
33 #include <dev/pms/RefTisa/sallsdk/api/sa_spec.h>
34 #include <dev/pms/RefTisa/sallsdk/api/sa_err.h>
36 /* TestBase needed to have the 'Multi-Data fetch disable' feature */
37 #define SA_CONFIG_MDFD_REGISTRY
39 #define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \
40 (bitptr)&(((STRUCT_TYPE *)0)->FEILD)
42 #if defined(SA_CPU_LITTLE_ENDIAN)
44 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
45 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
47 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
48 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
50 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
51 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
53 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
54 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))))
56 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
57 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
58 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF);
60 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
61 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
62 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
63 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
64 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF);
66 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
67 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
68 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
70 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
71 (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
72 (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
73 (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
74 (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
76 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
77 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
80 #elif defined(SA_CPU_BIG_ENDIAN)
82 #define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
83 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \
84 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF);
86 #define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
87 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \
88 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \
89 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \
90 (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF);
92 #define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
93 (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
94 (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1)));
96 #define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
97 (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \
98 (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \
99 (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \
100 (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3)));
102 #define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \
103 (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16);
105 #define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \
106 (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32);
108 #define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \
109 (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
111 #define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \
112 (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET))));
114 #define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \
115 si_memcpy(DEST_ADDR, SRC_ADDR, LEN);
119 #error (Host CPU endianess undefined!!)
123 #define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \
124 OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \
125 OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \
126 OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \
127 OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved);
130 /**************************************************************************
131 * define byte swap macro *
132 **************************************************************************/
133 /*! \def AGSA_FLIP_2_BYTES(_x)
134 * \brief AGSA_FLIP_2_BYTES macro
136 * use to flip two bytes
138 #define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \
139 ((((bit16)(_x))&0xFF00)>>8)))
141 /*! \def AGSA_FLIP_4_BYTES(_x)
142 * \brief AGSA_FLIP_4_BYTES macro
144 * use to flip four bytes
146 #define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \
147 ((((bit32)(_x))&0x0000FF00)<<8)| \
148 ((((bit32)(_x))&0x00FF0000)>>8)| \
149 ((((bit32)(_x))&0xFF000000)>>24)))
152 #if defined(SA_CPU_LITTLE_ENDIAN)
154 /*! \def LEBIT16_TO_BIT16(_x)
155 * \brief LEBIT16_TO_BIT16 macro
157 * use to convert little endian bit16 to host bit16
159 #ifndef LEBIT16_TO_BIT16
160 #define LEBIT16_TO_BIT16(_x) (_x)
163 /*! \def BIT16_TO_LEBIT16(_x)
164 * \brief BIT16_TO_LEBIT16 macro
166 * use to convert host bit16 to little endian bit16
168 #ifndef BIT16_TO_LEBIT16
169 #define BIT16_TO_LEBIT16(_x) (_x)
172 /*! \def BEBIT16_TO_BIT16(_x)
173 * \brief BEBIT16_TO_BIT16 macro
175 * use to convert big endian bit16 to host bit16
177 #ifndef BEBIT16_TO_BIT16
178 #define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
181 /*! \def BIT16_TO_BEBIT16(_x)
182 * \brief BIT16_TO_BEBIT16 macro
184 * use to convert host bit16 to big endian bit16
186 #ifndef BIT16_TO_BEBIT16
187 #define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
190 /*! \def LEBIT32_TO_BIT32(_x)
191 * \brief LEBIT32_TO_BIT32 macro
193 * use to convert little endian bit32 to host bit32
195 #ifndef LEBIT32_TO_BIT32
196 #define LEBIT32_TO_BIT32(_x) (_x)
199 /*! \def BIT32_TO_LEBIT32(_x)
200 * \brief BIT32_TO_LEBIT32 macro
202 * use to convert host bit32 to little endian bit32
204 #ifndef BIT32_TO_LEBIT32
205 #define BIT32_TO_LEBIT32(_x) (_x)
208 /*! \def BEBIT32_TO_BIT32(_x)
209 * \brief BEBIT32_TO_BIT32 macro
211 * use to convert big endian bit32 to host bit32
213 #ifndef BEBIT32_TO_BIT32
214 #define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
217 /*! \def BIT32_TO_BEBIT32(_x)
218 * \brief BIT32_TO_BEBIT32 macro
220 * use to convert host bit32 to big endian bit32
222 #ifndef BIT32_TO_BEBIT32
223 #define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
228 * bit8 to Byte[x] of bit32
230 #ifndef BIT8_TO_BIT32_B0
231 #define BIT8_TO_BIT32_B0(_x) ((bit32)(_x))
234 #ifndef BIT8_TO_BIT32_B1
235 #define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8)
238 #ifndef BIT8_TO_BIT32_B2
239 #define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16)
242 #ifndef BIT8_TO_BIT32_B3
243 #define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24)
247 * Byte[x] of bit32 to bit8
249 #ifndef BIT32_B0_TO_BIT8
250 #define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
253 #ifndef BIT32_B1_TO_BIT8
254 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
257 #ifndef BIT32_B2_TO_BIT8
258 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
261 #ifndef BIT32_B3_TO_BIT8
262 #define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
265 #elif defined(SA_CPU_BIG_ENDIAN)
267 /*! \def LEBIT16_TO_BIT16(_x)
268 * \brief LEBIT16_TO_BIT16 macro
270 * use to convert little endian bit16 to host bit16
272 #ifndef LEBIT16_TO_BIT16
273 #define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
276 /*! \def BIT16_TO_LEBIT16(_x)
277 * \brief BIT16_TO_LEBIT16 macro
279 * use to convert host bit16 to little endian bit16
281 #ifndef BIT16_TO_LEBIT16
282 #define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
285 /*! \def BEBIT16_TO_BIT16(_x)
286 * \brief BEBIT16_TO_BIT16 macro
288 * use to convert big endian bit16 to host bit16
290 #ifndef BEBIT16_TO_BIT16
291 #define BEBIT16_TO_BIT16(_x) (_x)
294 /*! \def BIT16_TO_BEBIT16(_x)
295 * \brief BIT16_TO_BEBIT16 macro
297 * use to convert host bit16 to big endian bit16
299 #ifndef BIT16_TO_BEBIT16
300 #define BIT16_TO_BEBIT16(_x) (_x)
303 /*! \def LEBIT32_TO_BIT32(_x)
304 * \brief LEBIT32_TO_BIT32 macro
306 * use to convert little endian bit32 to host bit32
308 #ifndef LEBIT32_TO_BIT32
309 #define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
312 /*! \def BIT32_TO_LEBIT32(_x)
313 * \brief BIT32_TO_LEBIT32 macro
315 * use to convert host bit32 to little endian bit32
317 #ifndef BIT32_TO_LEBIT32
318 #define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
321 /*! \def BEBIT32_TO_BIT32(_x)
322 * \brief BEBIT32_TO_BIT32 macro
324 * use to convert big endian bit32 to host bit32
326 #ifndef BEBIT32_TO_BIT32
327 #define BEBIT32_TO_BIT32(_x) (_x)
330 /*! \def BIT32_TO_BEBIT32(_x)
331 * \brief BIT32_TO_BEBIT32 macro
333 * use to convert host bit32 to big endian bit32
335 #ifndef BIT32_TO_BEBIT32
336 #define BIT32_TO_BEBIT32(_x) (_x)
341 * bit8 to Byte[x] of bit32
343 #ifndef BIT8_TO_BIT32_B0
344 #define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24)
347 #ifndef BIT8_TO_BIT32_B1
348 #define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16)
351 #ifndef BIT8_TO_BIT32_B2
352 #define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8)
355 #ifndef BIT8_TO_BIT32_B3
356 #define BIT8_TO_BIT32_B3(_x) ((bit32)(_x))
360 * Byte[x] of bit32 to bit8
362 #ifndef BIT32_B0_TO_BIT8
363 #define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
366 #ifndef BIT32_B1_TO_BIT8
367 #define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
370 #ifndef BIT32_B2_TO_BIT8
371 #define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
374 #ifndef BIT32_B3_TO_BIT8
375 #define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
380 #error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN
385 #if defined(SA_DMA_LITTLE_ENDIAN)
390 #ifndef DMA_BIT32_TO_BIT32
391 #define DMA_BIT32_TO_BIT32(_x) (_x)
394 #ifndef DMA_LEBIT32_TO_BIT32
395 #define DMA_LEBIT32_TO_BIT32(_x) (_x)
398 #ifndef DMA_BEBIT32_TO_BIT32
399 #define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
402 #ifndef BIT32_TO_DMA_BIT32
403 #define BIT32_TO_DMA_BIT32(_x) (_x)
406 #ifndef BIT32_TO_DMA_LEBIT32
407 #define BIT32_TO_DMA_LEBIT32(_x) (_x)
410 #ifndef BIT32_TO_DMA_BEBIT32
411 #define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
418 #ifndef DMA_BIT16_TO_BIT16
419 #define DMA_BIT16_TO_BIT16(_x) (_x)
422 #ifndef DMA_LEBIT16_TO_BIT16
423 #define DMA_LEBIT16_TO_BIT16(_x) (_x)
426 #ifndef DMA_BEBIT16_TO_BIT16
427 #define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
430 #ifndef BIT16_TO_DMA_BIT16
431 #define BIT16_TO_DMA_BIT16(_x) (_x)
434 #ifndef BIT16_TO_DMA_LEBIT16
435 #define BIT16_TO_DMA_LEBIT16(_x) (_x)
438 #ifndef BIT16_TO_DMA_BEBIT16
439 #define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
442 #if defined(SA_CPU_LITTLE_ENDIAN)
444 #ifndef BEBIT32_TO_DMA_BEBIT32
445 #define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
448 #ifndef LEBIT32_TO_DMA_LEBIT32
449 #define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
452 #ifndef DMA_LEBIT32_TO_LEBIT32
453 #define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
456 #ifndef DMA_BEBIT32_TO_BEBIT32
457 #define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
463 #ifndef BEBIT16_TO_DMA_BEBIT16
464 #define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
467 #ifndef LEBIT16_TO_DMA_LEBIT16
468 #define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
471 #ifndef DMA_LEBIT16_TO_LEBIT16
472 #define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
475 #ifndef DMA_BEBIT16_TO_BEBIT16
476 #define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
479 #else /* defined(SA_CPU_BIG_ENDIAN) */
485 #ifndef BEBIT32_TO_DMA_BEBIT32
486 #define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
489 #ifndef LEBIT32_TO_DMA_LEBIT32
490 #define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
493 #ifndef DMA_LEBIT32_TO_LEBIT32
494 #define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
497 #ifndef DMA_BEBIT32_TO_BEBIT32
498 #define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
504 #ifndef BEBIT16_TO_DMA_BEBIT16
505 #define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
508 #ifndef LEBIT16_TO_DMA_LEBIT16
509 #define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
512 #ifndef DMA_LEBIT16_TO_LEBIT16
513 #define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
516 #ifndef DMA_BEBIT16_TO_BEBIT16
517 #define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
523 * bit8 to Byte[x] of bit32
525 #ifndef BIT8_TO_DMA_BIT32_B0
526 #define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x))
529 #ifndef BIT8_TO_DMA_BIT32_B1
530 #define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8)
533 #ifndef BIT8_TO_DMA_BIT32_B2
534 #define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16)
537 #ifndef BIT8_TO_DMA_BIT32_B3
538 #define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24)
542 * Byte[x] of bit32 to bit8
544 #ifndef DMA_BIT32_B0_TO_BIT8
545 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
548 #ifndef DMA_BIT32_B1_TO_BIT8
549 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
552 #ifndef DMA_BIT32_B2_TO_BIT8
553 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
556 #ifndef DMA_BIT32_B3_TO_BIT8
557 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
561 | end of DMA access macros for LITTLE ENDIAN |
562 ---------------------------------------------------------------------
565 #elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */
567 /*--------------------------------------------------------------------
568 | DMA buffer access macros for BIG ENDIAN |
573 #ifndef DMA_BEBIT32_TO_BIT32
574 #define DMA_BEBIT32_TO_BIT32(_x) (_x)
577 #ifndef DMA_LEBIT32_TO_BIT32
578 #define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x)
581 #ifndef BIT32_TO_DMA_BIT32
582 #define BIT32_TO_DMA_BIT32(_x) (_x)
585 #ifndef BIT32_TO_DMA_LEBIT32
586 #define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
589 #ifndef BIT32_TO_DMA_BEBIT32
590 #define BIT32_TO_DMA_BEBIT32(_x) (_x)
594 #ifndef DMA_BEBIT16_TO_BIT16
595 #define DMA_BEBIT16_TO_BIT16(_x) (_x)
598 #ifndef DMA_LEBIT16_TO_BIT16
599 #define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x)
602 #ifndef BIT16_TO_DMA_BIT16
603 #define BIT16_TO_DMA_BIT16(_x) (_x)
606 #ifndef BIT16_TO_DMA_LEBIT16
607 #define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
610 #ifndef BIT16_TO_DMA_BEBIT16
611 #define BIT16_TO_DMA_BEBIT16(_x) (_x)
615 #if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */
618 #ifndef BEBIT32_TO_DMA_BEBIT32
619 #define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
622 #ifndef LEBIT32_TO_DMA_LEBIT32
623 #define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
626 #ifndef DMA_LEBIT32_TO_LEBIT32
627 #define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
630 #ifndef DMA_BEBIT32_TO_BEBIT32
631 #define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x)
635 #ifndef BEBIT16_TO_DMA_BEBIT16
636 #define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
639 #ifndef LEBIT16_TO_DMA_LEBIT16
640 #define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
643 #ifndef DMA_LEBIT16_TO_LEBIT16
644 #define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
647 #ifndef DMA_BEBIT16_TO_BEBIT16
648 #define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x)
652 #else /* defined(SA_CPU_BIG_ENDIAN) */
655 #ifndef BEBIT32_TO_DMA_BEBIT32
656 #define BEBIT32_TO_DMA_BEBIT32(_x) (_x)
659 #ifndef LEBIT32_TO_DMA_LEBIT32
660 #define LEBIT32_TO_DMA_LEBIT32(_x) (_x)
663 #ifndef DMA_LEBIT32_TO_LEBIT32
664 #define DMA_LEBIT32_TO_LEBIT32(_x) (_x)
667 #ifndef DMA_BEBIT32_TO_BEBIT32
668 #define DMA_BEBIT32_TO_BEBIT32(_x) (_x)
672 #ifndef BEBIT16_TO_DMA_BEBIT16
673 #define BEBIT16_TO_DMA_BEBIT16(_x) (_x)
676 #ifndef LEBIT16_TO_DMA_LEBIT16
677 #define LEBIT16_TO_DMA_LEBIT16(_x) (_x)
680 #ifndef DMA_LEBIT16_TO_LEBIT16
681 #define DMA_LEBIT16_TO_LEBIT16(_x) (_x)
684 #ifndef DMA_BEBIT16_TO_BEBIT16
685 #define DMA_BEBIT16_TO_BEBIT16(_x) (_x)
691 * bit8 to Byte[x] of bit32
693 #ifndef BIT8_TO_DMA_BIT32_B0
694 #define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24)
697 #ifndef BIT8_TO_DMA_BIT32_B1
698 #define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16)
701 #ifndef BIT8_TO_DMA_BIT32_B2
702 #define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8)
705 #ifndef BIT8_TO_DMA_BIT32_B3
706 #define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x))
710 * ** Byte[x] of bit32 to bit8
712 #ifndef DMA_BIT32_B0_TO_BIT8
713 #define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24))
716 #ifndef DMA_BIT32_B1_TO_BIT8
717 #define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16))
720 #ifndef DMA_BIT32_B2_TO_BIT8
721 #define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8))
724 #ifndef DMA_BIT32_B3_TO_BIT8
725 #define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF))
729 | end of DMA access macros for BIG ENDIAN |
730 ---------------------------------------------------------------------
734 #error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN
736 #endif /* DMA endian */
738 * End of DMA buffer access macros *
740 **********************************************************************
743 /************************************************************************************
745 * Constants defined for LL Layer starts *
747 ************************************************************************************/
749 /*********************************************************
750 * sTSDK LL revision and Interface revision, FW version
751 *********************************************************/
753 #define FW_THIS_VERSION_SPC12G 0x03060005
755 #define FW_THIS_VERSION_SPC6G 0x02092400
756 #define FW_THIS_VERSION_SPC 0x01110000
759 #define STSDK_LL_INTERFACE_VERSION 0x20A
760 #define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */
761 #define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G /**< current sTSDK version */
762 #define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G /**< FW */
763 #define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G /**< current V matching FW version */
764 #define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */
766 #define STSDK_LL_12G_INTERFACE_VERSION 0x302
767 #define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G /**< current sTSDK version */
768 #define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G /**< FW */
769 #define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G /**< current V matching FW version */
770 #define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */
772 #define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version supported */
773 #define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC /**< current SPC matching FW version */
774 #define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */
776 #define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00
777 /*************************************************
778 * constants for API return values
779 *************************************************/
780 #define AGSA_RC_SUCCESS 0x00 /**< Successful function return value */
781 #define AGSA_RC_FAILURE 0x01 /**< Failed function return value */
782 #define AGSA_RC_BUSY 0x02 /**< Busy function return value */
783 /* current only return from saGetControllerInfo() and saGetControllerStatus() */
784 #define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */
785 #define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */
786 /* current only return from saInitialize() for version checking */
787 #define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */
788 #define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */
789 #define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the current hardware */
790 #define AGSA_RC_COMPLETE 0x08
792 /*************************************************
793 * constants for type field in agsaMem_t
794 *************************************************/
795 #define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */
796 #define AGSA_DMA_MEM 0x01 /**< DMA memory type */
797 #define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */
799 #ifdef SA_ENABLE_TRACE_FUNCTIONS
801 #define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */
803 #define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */
807 #define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */
809 #define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */
811 #endif /* END SA_ENABLE_TRACE_FUNCTIONS */
814 /**********************************
815 * default constant for phy count
816 **********************************/
817 #define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */ /**< max # of phys supported by the hardware */
819 /************************************
820 * default constant for Esgl entries
821 ************************************/
822 #define MAX_ESGL_ENTRIES 10 /**< max # of extended SG list entry */
824 /*******************************************
825 * constant for max inbound/outbound queues
826 *******************************************/
827 #define AGSA_MAX_INBOUND_Q 64 /**< max # of inbound queue */
828 #define AGSA_MAX_OUTBOUND_Q 64 /**< max # of outbound queue */
829 #define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */
831 /****************************
832 * Phy Control constants
833 ****************************/
834 #define AGSA_PHY_LINK_RESET 0x01
835 #define AGSA_PHY_HARD_RESET 0x02
836 #define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */
837 #define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */
838 #define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */
839 #define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10
840 #define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12
841 #define AGSA_PHY_COMINIT_OOB 0x20
843 #define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */
844 #define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */
845 #define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */
846 #define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */
847 #define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */
848 #define AGSA_PHY_SNW3_PAGE 0x06
849 #define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */
850 #define AGSA_SAS_PHY_MISC_PAGE 0x08
851 #define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */
856 #define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */
857 #define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip */
859 /***************************************
861 ***************************************/
862 #define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */
863 #define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */
865 /***************************************
867 ***************************************/
868 #define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */
869 #define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discovery */
870 #define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */
872 /****************************************************************
873 * SSP/SMP/SATA Request type
874 ****************************************************************/
875 /* bit31-28 - request type
883 bit3-0 - Initiator, target or task mode (1 to 8)
885 #define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */
886 #define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */
887 #define AGSA_SSP_REQTYPE 0x80000000
888 #define AGSA_SMP_REQTYPE 0x40000000
889 #define AGSA_SATA_REQTYPE 0x20000000
891 #define AGSA_DIR_MASK 0x00000300
892 #define AGSA_AUTO_MASK 0x00000080
893 #define AGSA_SATA_ATAP_MASK 0x0000FC00
895 #define AGSA_DIR_NONE 0x00000000
896 #define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_READ */
897 #define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRITE */
899 /* bit definition - AUTO mode */
900 #define AGSA_AUTO_GOOD_RESPONSE 0x00000080
902 /* request type - not bit difination */
903 #define AGSA_SSP_INIT 0x00000001
904 #define AGSA_SSP_TGT_MODE 0x00000003
905 #define AGSA_SSP_TASK_MGNT 0x00000005
906 #define AGSA_SSP_TGT_RSP 0x00000006
907 #define AGSA_SMP_INIT 0x00000007
908 #define AGSA_SMP_TGT 0x00000008
910 /* request type for SSP Initiator and extend */
911 #define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT)
913 /* request type for SSP Initiator and indirect */
914 #define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT)
917 #define AGSA_MSG 0x00000010
918 #define AGSA_SSP_EXT_BIT 0x00000020
919 #define AGSA_SSP_INDIRECT_BIT 0x00000040
920 #define AGSA_MSG_BIT AGSA_MSG >> 2
922 /* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/
923 #define AGSA_INDIRECT_CDB_BIT 0x00000008
924 #define AGSA_SKIP_MASK_BIT 0x00000010
925 #define AGSA_ENCRYPT_BIT 0x00000020
926 #define AGSA_DIF_BIT 0x00000040
927 #define AGSA_DIF_LA_BIT 0x00000080
928 #define AGSA_DIRECTION_BITS 0x00000300
929 #define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000
930 #define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000
932 /* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */
933 #define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */
934 #define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */
935 #define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */
936 #define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */
937 #define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */
938 #define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */
939 #define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */
940 #define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */
941 #define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */
942 #define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */
943 #define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */
944 #define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */
945 #define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */
948 /* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */
949 #define AGSA_DIF_UPDATE_BITS 0xFC000000
950 #define AGSA_DIF_VERIFY_BITS 0x03F00000
951 #define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000
952 #define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040
953 #define AGSA_DIF_CRC_SEED_BIT 0x00000020
954 #define AGSA_DIF_CRC_INVERT_BIT 0x00000010
955 #define AGSA_DIF_CRC_VERIFY_BIT 0x00000008
956 #define AGSA_DIF_OP_BITS 0x00000007
958 #define AGSA_DIF_OP_INSERT 0x00000000
959 #define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001
960 #define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002
961 #define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003
962 #define AGSA_DIF_OP_RESERVED2 0x00000004
963 #define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005
964 #define AGSA_DIF_OP_RESERVED3 0x00000006
965 #define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007
968 /* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */
969 #define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000
970 #define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010
971 #define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C
972 #define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002
974 /* Cipher mode to be used for this I/O. */
975 #define AGSA_ENCRYPT_ECB_Mode 0
976 #define AGSA_ENCRYPT_XTS_Mode 0x6
978 /* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */
979 #define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0
980 #define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F
982 /* defined in the sTSDK spec. */
983 #define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT) /**< SSP initiator non data request type */
984 #define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT) /**< SSP initiator read request type */
985 #define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT) /**< SSP initiator write request type */
986 #define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */
987 #define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */
988 #define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target read data with automatic good response request type */
989 #define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */
990 #define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */
991 #define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target write data request type with automatic good response request type*/
992 #define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT) /**< SSP task management request type */
993 #define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP) /**< SSP command or task management response request type */
994 #define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT) /**< SMP initiator request type */
995 #define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT) /**< SMP target response request type */
996 #define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG)
997 #define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG)
998 #define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG)
999 #define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT) /**< SSP initiator read request Ext type */
1000 #define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT) /**< SSP initiator write request Ext type */
1002 #define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator read request indirect type */
1003 #define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator write request indirect type */
1005 #define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator read request indirect type */
1006 #define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator write request indirect type */
1007 #define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG)
1008 #define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG)
1010 #define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF
1012 #define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400
1013 #define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800
1014 #define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00
1015 #define AGSA_SATA_ATAP_NON_DATA 0x00001000
1016 #define AGSA_SATA_ATAP_PIO 0x00001400
1017 #define AGSA_SATA_ATAP_DMA 0x00001800
1018 #define AGSA_SATA_ATAP_NCQ 0x00001C00
1019 #define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000
1020 #define AGSA_SATA_ATAP_PKT 0x00002400
1022 #define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA)
1023 #define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */
1024 #define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */
1025 #define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */
1026 #define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */
1027 #define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */
1028 #define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */
1029 #define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET) /**< SATA device reset request type */
1030 #define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT) /**< SATA device reset assert */
1031 #define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT) /**< SATA device reset deassert */
1032 #define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT)
1033 #define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT)
1034 #define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT)
1037 #define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG)
1038 #define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */
1039 #define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */
1040 #define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */
1041 #define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */
1042 #define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */
1043 #define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */
1044 #define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1045 #define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1046 #define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG)
1048 #define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG) /**< SATA device reset request type */
1052 #define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles interrupts for all channles */
1054 /****************************************************************************
1055 ** INBOUND Queue related macros
1056 ****************************************************************************/
1057 #define AGSA_IBQ_PRIORITY_NORMAL 0x0
1058 #define AGSA_IBQ_PRIORITY_HIGH 0x1
1060 /****************************************************************************
1061 ** Phy properties related macros
1062 ****************************************************************************/
1064 #define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */
1065 #define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */
1066 #define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */
1067 #define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */
1068 #define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */
1071 #define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */
1072 #define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */
1073 #define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */
1075 /* control spin-up hold */
1076 #define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */
1077 #define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */
1078 #define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */
1080 /****************************************************************************
1081 ** Device Info related macros
1082 ****************************************************************************/
1084 #define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */
1085 #define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */
1086 #define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */
1088 /* Rate (link-rate) */
1089 #define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */
1090 #define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */
1091 #define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */
1092 #define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */
1093 #define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */
1096 #define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */
1097 #define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */
1098 #define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */
1099 #define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */
1101 /*****************************************************************************
1102 ** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7)
1103 *****************************************************************************/
1104 #define AGSA_ABORT_TASK 0x01
1105 #define AGSA_ABORT_TASK_SET 0x02
1106 #define AGSA_CLEAR_TASK_SET 0x04
1107 #define AGSA_LOGICAL_UNIT_RESET 0x08
1108 #define AGSA_IT_NEXUS_RESET 0x10
1109 #define AGSA_CLEAR_ACA 0x40
1110 #define AGSA_QUERY_TASK 0x80
1111 #define AGSA_QUERY_TASK_SET 0x81
1112 #define AGSA_QUERY_UNIT_ATTENTION 0x82
1114 /*****************************************************************************
1115 ** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7)
1116 *****************************************************************************/
1117 #define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0
1118 #define AGSA_INVALID_FRAME 0x2
1119 #define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4
1120 #define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5
1121 #define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8
1122 #define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9
1123 /* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */
1124 #define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA
1126 #define AGSA_SATA_BSY_OVERRIDE 0x00080000
1127 #define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000
1129 #define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40
1130 #define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36
1132 /* SATA Initiator Request option field defintion */
1133 #define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001
1134 #define AGSA_SATA_ENABLE_ENCRYPTION 0x000004
1135 #define AGSA_SATA_ENABLE_DIF 0x000008
1136 #define AGSA_SATA_SKIP_QWORD 0xFFFF00
1138 /* SAS Initiator Request flag definitions */
1139 /* Bits 0,1 use TLR_MASK */
1141 #define AGSA_SAS_ENABLE_ENCRYPTION 0x0004
1142 #define AGSA_SAS_ENABLE_DIF 0x0008
1144 #ifdef SAFLAG_USE_DIF_ENC_IOMB
1145 #define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010
1146 #endif /* SAFLAG_USE_DIF_ENC_IOMB */
1148 #define AGSA_SAS_ENABLE_SKIP_MASK 0x0010
1149 #define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0
1151 /****************************************************************************
1152 ** SMP Phy control Phy Operation field
1153 ****************************************************************************/
1154 #define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1
1155 #define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2
1156 #define AGSA_PHY_CONTROL_DISABLE 0x3
1157 #define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5
1158 #define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6
1159 #define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7
1161 /****************************************************************************
1162 ** SAS Diagnostic Operation code
1163 ****************************************************************************/
1164 #define AGSA_SAS_DIAG_START 0x1
1165 #define AGSA_SAS_DIAG_END 0x0
1167 /****************************************************************************
1168 ** Port Control constants
1169 ****************************************************************************/
1170 #define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1
1171 #define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2
1172 #define AGSA_PORT_IO_ABORT 0x3
1173 #define AGSA_PORT_SET_PORT_RESET_TIME 0x4
1174 #define AGSA_PORT_HARD_RESET 0x5
1175 #define AGSA_PORT_CLEAN_UP 0x6
1176 #define AGSA_STOP_PORT_RECOVERY_TIMER 0x7
1179 #define SA_DS_OPERATIONAL 0x1
1180 #define SA_DS_PORT_IN_RESET 0x2
1181 #define SA_DS_IN_RECOVERY 0x3
1182 #define SA_DS_IN_ERROR 0x4
1183 #define SA_DS_NON_OPERATIONAL 0x7
1185 /************************************************************************************
1187 * Constants defined for LL Layer ends *
1189 ************************************************************************************/
1191 /************************************************************************************
1193 * Constants defined for OS Layer starts *
1195 ************************************************************************************/
1196 /*****************************************
1197 * ossaXXX return values
1198 ******************************************/
1199 /* common for all ossaXXX CB */
1200 #define OSSA_SUCCESS 0x00 /**< flag indicates successful callback status */
1201 #define OSSA_FAILURE 0x01 /**< flag indicates failed callback status */
1204 #define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callback status */
1205 #define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback status */
1206 #define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callback status */
1208 /* ossaLocalPhyControl() */
1209 #define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operation failure */
1211 /* ossaDeviceRegisterCB() */
1212 #define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback status */
1213 #define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback status */
1214 #define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback status */
1215 #define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback status */
1216 #define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback status */
1217 #define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback status */
1218 #define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback status */
1219 #define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020
1220 #define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021
1221 #define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022
1223 #define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/
1225 #define OSSA_ERR_PORT_INVALID 0x1041
1226 #define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042
1228 #define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045
1230 #define OSSA_ERR_PHY_ID_INVALID 0x1061
1231 #define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062
1235 /* ossaDeregisterDeviceCB() */
1236 #define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback status */
1237 #define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */
1238 #define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */
1241 #define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the callback function */
1242 #define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the callback function */
1244 /* ossaSetDeviceStateCB() */
1245 #define OSSA_INVALID_STATE 0x0001
1246 #define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025
1247 #define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026
1248 #define OSSA_ERR_DEVICE_STATE_INVALID 0x0049
1250 /* status of ossaSASDiagExecuteCB() */
1251 #define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */
1252 #define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */
1253 #define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */
1254 #define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */
1255 #define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */
1256 #define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */
1257 #define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */
1260 /* status of ossaSASDiagStartEndCB() */
1261 #define OSSA_DIAG_SE_SUCCESS 0x00
1262 #define OSSA_DIAG_SE_INVALID_PHY_ID 0x01
1263 #define OSSA_DIAG_PHY_NOT_DISABLED 0x02
1264 #define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */
1265 #define OSSA_DIAG_OPCODE_INVALID 0x03
1267 /* status of ossaPortControlCB() */
1268 #define OSSA_PORT_CONTROL_FAILURE 0x03
1270 #define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004
1271 #define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/
1272 #define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/
1273 #define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/
1274 #define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/
1275 #define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/
1277 /*regDumpNum of agsaRegDumpInfo_t */
1278 #define GET_GSM_SM_INFO 0x02
1279 #define GET_IOST_RB_INFO 0x03
1281 /************************************************************************************
1283 ************************************************************************************/
1284 #define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event */
1285 #define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed event */
1286 #define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event status */
1287 #define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */
1288 #define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */
1289 #define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold event */
1290 #define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */
1292 #define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change event */
1293 /* not used spcv 0x0A*/
1294 #define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */
1295 #define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SES) event */
1296 #define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C
1297 #define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset received event */
1298 /* not used spcv 0x0E*/
1299 #define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error */
1300 #define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout event */
1301 #define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER) event */
1302 /* not used spcv 0x11*/
1303 #define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event status */
1304 #define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid DWORD */
1305 #define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity */
1306 #define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code violation */
1307 #define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of DWORD synch */
1308 #define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset failed */
1309 #define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeout */
1310 #define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */
1311 #define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out */
1312 #define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete */
1313 #define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Event */
1314 #define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss */
1316 #define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25
1318 #define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that an encryption event occurred */
1319 #define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that a controller mode page operation completed */
1320 #define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that saEncryptSetMode() completed */
1324 #define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not established */
1325 #define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */
1326 #define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communication */
1327 #define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state */
1328 #define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party reset state */
1329 #define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */
1331 /* status for agsaHWEventMode_t */
1332 #define OSSA_CTL_SUCCESS 0x0000
1333 #define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001
1334 #define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002
1335 #define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1336 #define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004
1337 #define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005
1338 // #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B
1339 #define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX
1343 /************************************************************************************
1344 * General Events value
1345 ************************************************************************************/
1346 #define OSSA_INBOUND_V_BIT_NOT_SET 0x01
1347 #define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02
1348 #define OSSA_INBOUND_IOMB_INVALID_OBID 0x03
1350 /************************************************************************************
1351 * FW Flash Update status values
1352 ************************************************************************************/
1353 #define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update completed */
1354 #define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in progress */
1355 #define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header error */
1356 #define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset error */
1357 #define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */
1358 #define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length error */
1359 #define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */
1360 #define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware image HMAC authentication failure.*/
1362 #define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load not supported */
1363 #define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disabled */
1364 #define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disabled */
1366 /************************************************************************************
1367 * Discovery status values
1368 ************************************************************************************/
1369 #define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */
1370 #define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a new device */
1371 #define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a device removed */
1372 #define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */
1373 #define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */
1374 #define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */
1375 #define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */
1376 #define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */
1377 #define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */
1378 #define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */
1379 #define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */
1380 #define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */
1381 #define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */
1382 #define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */
1384 /***********************************************************************************
1386 ***********************************************************************************/
1387 #define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */
1388 #define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */
1389 #define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */
1390 #define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */
1391 #define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */
1393 #define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */
1395 #define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SSP command */
1396 #define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SSP task management */
1398 /* Event Source Type of saRegisterEventCallback() */
1399 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00
1400 #define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01
1402 /* Status of Get Device Info CB */
1403 #define OSSA_DEV_INFO_INVALID_HANDLE 0x01
1404 #define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02
1405 #define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03
1406 #define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04
1408 /* Diagnostic Command Type */
1409 #define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00
1410 #define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01
1411 #define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02
1412 #define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03
1413 #define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04
1414 #define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05
1416 /* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */
1417 #define AGSA_CMD_DESC_PRBS 0x00
1418 #define AGSA_CMD_DESC_CJTPAT 0x01
1419 #define AGSA_CMD_DESC_USR_PATTERNS 0x02
1420 #define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08
1421 #define AGSA_CMD_DESC_PRBS_INVERT 0x09
1422 #define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A
1423 #define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B
1424 #define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C
1425 #define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E
1426 #define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10
1427 #define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11
1428 #define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12
1430 /* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */
1431 #define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00
1432 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01
1433 #define AGSA_CMD_DESC_DISP_ERR_CNT 0x02
1434 #define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05
1435 #define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06
1436 #define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09
1437 #define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A
1438 #define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B
1439 #define AGSA_CMD_DESC_PHY_RST_CNT 0x0C
1440 #define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E
1442 #define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19
1443 #define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A
1444 #define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B
1445 #define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C
1446 #define AGSA_CMD_DESC_ALL 0x1F
1448 /* NVMDevice type */
1449 #define AGSA_NVMD_TWI_DEVICES 0x00
1450 #define AGSA_NVMD_CONFIG_SEEPROM 0x01
1451 #define AGSA_NVMD_VPD_FLASH 0x04
1452 #define AGSA_NVMD_AAP1_REG_FLASH 0x05
1453 #define AGSA_NVMD_IOP_REG_FLASH 0x06
1454 #define AGSA_NVMD_EXPANSION_ROM 0x07
1455 #define AGSA_NVMD_REG_FLASH 0x05
1458 /* GET/SET NVMD Data Response errors */
1459 #define OSSA_NVMD_SUCCESS 0x0000
1460 #define OSSA_NVMD_MODE_ERROR 0x0001
1461 #define OSSA_NVMD_LENGTH_ERROR 0x0002
1462 #define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005
1463 #define OSSA_NVMD_TWI_NACK_ERROR 0x2001
1464 #define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002
1465 #define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021
1466 #define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081
1467 #define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082
1468 #define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF
1469 #define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001
1470 #define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002
1471 #define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003
1472 #define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004
1473 #define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005
1474 #define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006
1475 #define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007
1476 #define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008
1477 #define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009
1478 #define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A
1479 #define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B
1480 #define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C
1481 #define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D
1482 #define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E
1484 /************************************************************
1485 * ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t
1486 ************************************************************/
1487 #define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000
1488 #define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001
1489 #define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002
1490 #define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003
1491 #define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004
1492 #define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005
1493 #define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006
1494 #define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007
1495 #define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008
1498 /************************************************************
1499 * ossaHwCB Encryption status of agsaHWEventEncrypt_t
1500 ************************************************************/
1501 /* KEK and DEK managment status from PM */
1502 #define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003
1503 #define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/
1504 #define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000
1505 #define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001
1506 #define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002
1507 #define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021
1508 #define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022
1509 #define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023
1511 /*encrypt operator management response status */
1512 #define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060
1513 #define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061
1514 #define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062
1515 #define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063
1516 #define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064
1518 /*encrypt saSetOperator() response status */
1519 #define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005
1520 #define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B
1522 /* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/
1523 /* Make sure all definitions are unique bits */
1524 #define agsaEncryptSMF 0x00000000
1525 #define agsaEncryptSMA 0x00000100
1526 #define agsaEncryptSMB 0x00000200
1527 #define agsaEncryptReturnSMF (1 << 12)
1528 #define agsaEncryptAuthorize (1 << 13)
1531 Bits 16-23: Allowable Cipher Mode(ACM)
1532 Bit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled.
1533 Bit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled.
1535 #define agsaEncryptAcmMask 0x00ff0000
1536 #define agsaEncryptEnableAES_ECB (1 << 16)
1537 #define agsaEncryptEnableAES_XTS (1 << 22)
1541 #define agsaEncryptCipherModeECB 0x00000001
1542 #define agsaEncryptCipherModeXTS 0x00000002
1546 #define agsaEncryptStatusNoNVRAM 0x00000001
1547 #define agsaEncryptStatusNVRAMErr 0x00000002
1551 Bin Hex Sector Total
1555 00011 :0x3 4K+64B 4160
1556 00100 :0x4 4K+128B 4224
1558 11000 :0x18 512+8B 520
1559 11001 :0x19 520+8B 528
1560 11010 :0x1A 4K+8B 4104
1561 11011 :0x1B 4K+64B+8B 4168
1562 11100 :0x1C 4K+128B+8B 4232
1566 #define agsaEncryptSectorSize512 0
1567 /* define agsaEncryptSectorSize520 1 Not supported */
1568 #define agsaEncryptSectorSize4096 2
1569 #define agsaEncryptSectorSize4160 3
1570 #define agsaEncryptSectorSize4224 4
1572 #define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18)
1573 #define agsaEncryptDIFSectorSize528 ( 0x19)
1574 #define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18)
1575 #define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18)
1576 #define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18)
1579 #define AGSA_ENCRYPT_STORE_NVRAM 1
1581 /************************************************************
1582 * ossaHwCB Mode page event definitions
1583 ************************************************************/
1584 #define agsaModePageGet 1
1585 #define agsaModePageSet 2
1587 /************************************************************
1588 * saSgpio() SGPIO Function and Register type
1589 ************************************************************/
1590 #define AGSA_READ_SGPIO_REGISTER 0x02
1591 #define AGSA_WRITE_SGPIO_REGISTER 0x82
1593 #define AGSA_SGPIO_CONFIG_REG 0x0
1594 #define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1
1595 #define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2
1596 #define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3
1597 #define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4
1599 /************************************************************
1600 * ossaSGpioCB() Function result
1601 ************************************************************/
1602 #define OSSA_SGPIO_COMMAND_SUCCESS 0x00
1603 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01
1604 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02
1605 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03
1606 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04
1607 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05
1608 #define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06
1609 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19
1610 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81
1611 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A
1612 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82
1613 #define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83
1614 #define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D
1615 #define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D
1617 #define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D
1618 #define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C
1620 /************************************************************
1621 * ossaGetDFEDataCB() status
1622 ************************************************************/
1623 #define OSSA_DFE_MPI_IO_SUCCESS 0x0000
1624 #define OSSA_DFE_DATA_OVERFLOW 0x0002
1625 #define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004
1626 #define OSSA_DFE_CHANNEL_DOWN 0x100E
1627 #define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F
1628 #define OSSA_DFE_CHANNEL_INVALID 0x1010
1629 #define OSSA_DFE_DMA_FAILURE 0x1011
1631 /************************************************************************************
1633 * Constants defined for OS Layer ends *
1635 ************************************************************************************/
1637 /************************************************************************************
1639 * Data Structures Defined for LL API start *
1641 ************************************************************************************/
1642 /** \brief data structure stores OS specific and LL specific context
1644 * The agsaContext_t data structure contains two generic pointers,
1645 * also known as handles, which are used to store OS Layer-specific and
1646 * LL Layer-specific contexts. Only the handle specific to a layer can
1647 * be modified by the layer. The other layer's handle must be returned
1648 * unmodified when communicating between the layers.
1650 * A layer's handle is typically typecast to an instance of a layer-specific
1651 * data structure. The layer can use its handle to point to any data type
1652 * that is to be associated with a function call. A handle provides a way
1653 * to uniquely identify responses when multiple calls to the same function
1657 typedef struct agsaContext_s
1659 void *osData; /**< Pointer-sized value used internally by the OS Layer */
1660 void *sdkData; /**< Pointer-sized value used internally by the LL Layer */
1663 /** \brief hold points to global data strutures used by the LL and OS Layers
1665 * The agsaRoot_t data structure is used to hold pointer-sized values for
1666 * internal use by the LL and OS Layers. It is intended that the
1667 * sdkData element of the agsaRoot_t data structure be used to
1668 * identify an instance of the hardware context. The sdkData
1669 * element is set by the LL Layer in the saHwInitialize()
1670 * function and returned to the OS Layer in the agsaRoot_t data
1673 typedef agsaContext_t agsaRoot_t;
1675 /** \brief holds the pointers to the device data structure used by the LL and OS Layers
1677 * The agsaDevHandle_t data structure is the device instance handle.
1678 * It holds pointer-sized values used internally by each of the LL and
1679 * OS Layers. It is intended that the agsaDevHandle_t data
1680 * structure be used to identify a specific device instance. A
1681 * device instance is uniquely identified by its device handle.
1683 typedef agsaContext_t agsaDevHandle_t;
1685 /** \brief holds the pointers to the port data structure used by the LL and
1688 * The agsaPortContext_t data structure is used to describe an instance of
1689 * SAS port or SATA port. It holds pointer-sized values used
1690 * internally by each of the LL and OS Layers.
1692 * When connected to other SAS end-devices or expanders, each instance of
1693 * agsaPortContext_t represents a SAS local narrow-port or
1696 * When connected to SATA device, each instance of agsaPortContext_t
1697 * represents a local SATA port.
1700 typedef agsaContext_t agsaPortContext_t;
1702 /** \brief data structure pointer to IO request structure
1704 * It is intended that the agsaIORequest_t structure be used to
1705 * uniquely identify each I/O Request for either target or
1706 * initiator. The OS Layer is responsible for allocating and
1707 * managing agsaIORequest_t structures. The LL Layer uses each
1708 * structure only between calls to: saSSPStart() and
1709 * ossaSSPCompleted(), saSATAStart() and ossaSATACompleted(),
1710 * saSMPStart() and ossaSMPCompleted()
1713 typedef agsaContext_t agsaIORequest_t;
1715 /** \brief handle to access frame
1717 * This data structure is the handle to access frame
1719 typedef void *agsaFrameHandle_t;
1721 /** \brief describe a SAS ReCofiguration structure in the SAS/SATA hardware
1723 * Describe a SAS ReConfiguration in the SAS/SATA hardware
1726 typedef struct agsaSASReconfig_s {
1727 bit32 flags; /* flag to indicate a change to the default parameter
1729 bit29: a change to the default SAS/SATA ports is requested
1730 bit28: the OPEN REJECT (RETRY) in command phase is requested
1731 bit27: the OPEN REJECT (RETRY) in data phase is requested
1732 bit26: REJECT will be mapped into OPEN REJECT
1733 bit25: delay for SATA Head-of-Line blocking detection timeout
1734 bit24-00:reserved */
1735 bit16 reserved0; /* reserved */
1736 bit8 reserved1; /* reserved */
1737 bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */
1738 bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */
1739 bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/
1740 bit16 reserved2; /* reserved */
1741 bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */
1742 } agsaSASReconfig_t;
1744 /** \brief describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware
1746 * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware
1749 typedef struct agsaPhyAnalogSetupRegisters_s
1761 } agsaPhyAnalogSetupRegisters_t;
1763 #define MAX_INDEX 10
1768 typedef struct agsaPhyAnalogSetupTable_s
1770 agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX];
1771 } agsaPhyAnalogSetupTable_t;
1773 /** \brief describe a Phy Analog Setting
1775 * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware
1778 typedef struct agsaPhyAnalogSettingsPage_s
1790 } agsaPhyAnalogSettingsPage_t;
1793 /** \brief describe a Open reject retry backoff threshold page
1795 * Describe a Open reject retry backoff threshold registers in the SAS/SATA hardware
1798 typedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s
1804 } agsaSASPhyOpenRejectRetryBackOffThresholdPage_t;
1806 /** \brief describe a Phy Rate Control
1807 * 4.56 agsaPhyRateControlPage_t
1809 * This profile page is used to read or set several rate control
1810 * parameters. The page code for this profile page is 0x07. This page can
1811 * be READ by issuing saGetPhyProfile(). It can be read anytime and there
1812 * is no need to quiesce the I/O to the controller.
1813 * Related parameters can be modified by issuing saSetPhyProfile() before
1814 * calling saPhyStart() to the PHY.
1815 * Note: This page is applicable only to the SPCv controller.
1817 * Initiator and target.
1819 typedef struct agsaPhyRateControlPage_s
1824 } agsaPhyRateControlPage_t;
1827 * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every
1828 * ALIGN_RATE+1 DWord. The default value results in the standard compliant
1829 * value of 2/256. This rate applies to out of connection, SMP and SSP
1830 * connections. The default value is 0x0ff. Other bits are reserved.
1831 * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in
1832 * every ALIGN_RATE+1 DWords. Default value results in standard compliant
1833 * value of 2/256. This rate applies to out of STP connections. The default
1834 * value is 0x0ff. Other bits are reserved.
1835 * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords
1836 * between each SSP frame. 0 means no idle cycles. The default value is
1837 * 0x0. Other bits are reserved.
1840 /** \brief describe a Register Dump information for a Controller in the SAS/SATA hardware
1842 * Describe a register dump information for a controller in the SAS/SATA hardware
1845 typedef struct agsaRegDumpInfo_s
1850 bit32 regDumpOffset;
1853 bit32 indirectAddrUpper32;
1854 bit32 indirectAddrLower32;
1856 } agsaRegDumpInfo_t;
1859 7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000]
1860 8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000]
1861 9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1862 10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1863 11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1864 12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000]
1865 13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1866 14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1867 15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1868 16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000]
1869 17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1870 18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1871 19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000]
1872 20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1873 21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1874 22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000]
1875 23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000]
1876 24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000]
1877 25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000]
1878 26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000]
1881 #define TYPE_GSM_SPACE 1
1882 #define TYPE_QUEUE 2
1883 #define TYPE_FATAL 3
1884 #define TYPE_NON_FATAL 4
1885 #define TYPE_INBOUND_QUEUE 5
1886 #define TYPE_OUTBOUND_QUEUE 6
1889 #define BAR_SHIFT_GSM_OFFSET 0x400000
1891 #define ONE_MEGABYTE 0x100000
1892 #define SIXTYFOURKBYTE (1024 * 64)
1896 #define TYPE_INBOUND 1
1897 #define TYPE_OUTBOUND 2
1928 } agsaForensicData_t;
1930 /** \brief describe a NVMData for a Controller in the SAS/SATA hardware
1932 * Describe a NVMData for a controller in the SAS/SATA hardware
1935 typedef struct agsaNVMDData_s
1937 bit32 indirectPayload :1;
1939 bit32 TWIDeviceAddress :8;
1940 bit32 TWIBusNumber :4;
1941 bit32 TWIDevicePageSize :4;
1942 bit32 TWIDeviceAddressSize :4;
1945 bit32 dataOffsetAddress :24;
1947 bit32 indirectAddrUpper32;
1948 bit32 indirectAddrLower32;
1954 /* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */
1955 #define OSSA_PCIE_DIAG_SUCCESS 0x0000
1956 #define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001
1957 #define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002
1958 #define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006
1959 #define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007
1960 #define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008
1961 #define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009
1962 #define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A
1963 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000
1964 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001
1965 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002
1966 #define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003
1967 #define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042
1968 #define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004
1969 #define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005
1972 typedef struct agsaPCIeDiagExecute_s
1976 bit16 initialIOSeed;
1986 } agsaPCIeDiagExecute_t;
1989 /** \brief agsaPCIeDiagResponse_t
1991 * status of ossaPCIeDiagExecuteCB()
1992 * The agsaPCIeDiagResponse_t structure is a parameter passed to
1993 * ossaPCIeDiagExecuteCB()
1994 * to contain a PCIe Diagnostic command response.
1997 typedef struct agsaPCIeDiagResponse_s {
2005 } agsaPCIeDiagResponse_t;
2008 /** \brief describe a fatal error information for a Controller in the SAS/SATA hardware
2010 * Describe a fatal error information for a controller in the SAS/SATA hardware
2013 typedef struct agsaFatalErrorInfo_s
2019 bit32 regDumpBusBaseNum0;
2020 bit32 regDumpOffset0;
2022 bit32 regDumpBusBaseNum1;
2023 bit32 regDumpOffset1;
2025 } agsaFatalErrorInfo_t;
2027 /** \brief describe a information for a Event in the SAS/SATA hardware
2029 * Describe a general information for a Event in the SAS/SATA hardware
2032 typedef struct agsaEventSource_s
2034 agsaPortContext_t *agPortContext;
2037 } agsaEventSource_t;
2039 /** \brief describe a information for a Controller in the SAS/SATA hardware
2041 * Describe a general information for a controller in the SAS/SATA hardware
2044 typedef struct agsaControllerInfo_s
2046 bit32 signature; /* coherent controller information */
2047 bit32 fwInterfaceRev; /* host and controller interface version */
2048 bit32 hwRevision; /* controller HW Revision number */
2049 bit32 fwRevision; /* controller FW Revision number */
2050 bit32 ilaRevision; /* controller ILA Revision number */
2051 bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */
2052 bit32 maxDevices; /* Maximum Device Supported by controller */
2053 bit32 maxSgElements; /* maximum number of SG elements supported */
2054 bit32 queueSupport; /* maximum number of IQ and OQ supported
2056 bit18 interrupt coalescing
2058 bit16 high priority IQ supported
2059 bit15-08 maximum number of OQ
2060 bit07-00 maximum number of IQ */
2061 bit8 phyCount; /* number of phy available in the controller */
2062 bit8 controllerSetting;/* Controller setting
2064 bit03-00 HDA setting */
2065 bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */
2066 bit8 PCIWidth; /* PCI number of lanes */
2067 bit32 sasSpecsSupport; /* the supported SAS spec. */
2068 bit32 sdkInterfaceRev; /* sdk interface reversion */
2069 bit32 sdkRevision; /* sdk reversion */
2070 } agsaControllerInfo_t;
2072 /** \brief describe a status for a Controller in the SAS/SATA hardware
2074 * Describe a general status for a controller in the SAS/SATA hardware
2077 typedef struct agsaControllerStatus_s
2079 agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */
2080 bit32 interfaceState; /* host and controller interface state
2081 bit02-00 state of host and controller
2083 bit31-16 detail of error based on error state */
2084 bit32 iqFreezeState0; /* freeze state of 1st set of IQ */
2085 bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */
2086 bit32 tickCount0; /* tick count in second for internal CPU-0 */
2087 bit32 tickCount1; /* tick count in second for internal CPU-1 */
2088 bit32 tickCount2; /* tick count in second for internal CPU-2 */
2089 bit32 phyStatus[8]; /* status of phy 0 to phy 15 */
2090 bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */
2092 bit16 bootComponentState[8];
2094 } agsaControllerStatus_t;
2096 /** \brief describe a GPIO Event Setup Infomation in the SAS/SATA hardware
2098 * Describe a configuration for a GPIO Event Setup Infomation in the SAS/SATA hardware
2101 typedef struct agsaGpioEventSetupInfo_s
2104 bit32 gpioEventLevel;
2105 bit32 gpioEventRisingEdge;
2106 bit32 gpioEventFallingEdge;
2107 } agsaGpioEventSetupInfo_t;
2109 /** \brief describe a GPIO Pin Setup Infomation in the SAS/SATA hardware
2111 * Describe a configuration for a GPIO Pin Setup Infomation in the SAS/SATA hardware
2114 typedef struct agsaGpioPinSetupInfo_t
2117 bit32 gpioInputEnabled;
2118 bit32 gpioTypePart1;
2119 bit32 gpioTypePart2;
2120 } agsaGpioPinSetupInfo_t;
2122 /** \brief describe a serial GPIO operation in the SAS/SATA hardware
2124 * Describe a configuration for a GPIO write Setup Infomation in the SAS/SATA hardware
2127 typedef struct agsaGpioWriteSetupInfo_s
2129 bit32 gpioWritemask;
2131 }agsaGpioWriteSetupInfo_t;
2133 /** \brief describe a GPIO Read Infomation in the SAS/SATA hardware
2135 * Describe a configuration for a GPIO read Infomation in the SAS/SATA hardware
2138 typedef struct agsaGpioReadInfo_s
2140 bit32 gpioReadValue;
2141 bit32 gpioInputEnabled; /* GPIOIE */
2142 bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */
2143 bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */
2144 bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */
2145 bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */
2146 bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */
2147 bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */
2148 }agsaGpioReadInfo_t;
2150 /** \brief describe a serial GPIO request and response in the SAS/SATA hardware
2152 * Describe the fields required for serial GPIO request and response in the SAS/SATA hardware
2155 typedef struct agsaSGpioReqResponse_s
2157 bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/
2158 bit8 function; /* 0x02 for read, 0x82 for write */
2159 bit8 registerType; /* used only in request */
2160 bit8 registerIndex; /* used only in request */
2161 bit8 registerCount; /* used only in request */
2162 bit8 functionResult; /* used only in response */
2163 bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */
2164 } agsaSGpioReqResponse_t;
2167 /** \brief describe a serial GPIO operation response in the SAS/SATA hardware
2169 * Describe the fields required for serial GPIO operations response in the SAS/SATA hardware
2172 typedef struct agsaSGpioCfg0
2177 bit8 gpRegisterCount:4;
2178 bit8 cfgRegisterCount:3;
2180 bit8 supportedDriveCount;
2183 /** \brief SGPIO configuration register 1
2185 * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec
2188 typedef struct agsaSGpioCfg1{
2194 bit8 stretchActOn:4;
2195 bit8 stretchActOff:4;
2198 /** \brief describe a configuration for a PHY in the SAS/SATA hardware
2200 * Describe a configuration for a PHY in the SAS/SATA hardware
2203 typedef struct agsaPhyConfig_s
2205 bit32 phyProperties;
2206 /**< b31-b8 reserved */
2207 /**< b16-b19 SSC Disable */
2208 /**< b15-b8 phy analog setup index */
2209 /**< b7 phy analog setup enable */
2210 /**< b6 Control spin up hold */
2211 /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */
2212 /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s,
2213 bit2 - 6.0Gb/s, bit3 - reserved */
2217 /** \brief Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter
2220 * This profile page is used to read or set the SNW-3 PHY capabilities of a
2221 * SAS PHY. This page can be read by calling saGetPhyProfile(). It can be
2222 * read anytime and there is no need to quiesce he I/O to the controller.
2223 * The format of the 32-bit SNW3 is the same as defined in the SAS 2
2225 * Local SNW3 can be modified by calling saSetPhyProfile() before
2226 * saPhyStart() to the PHY. REQUESTED LOGICAL LINK RATE is reserved.
2227 * The SPCv will calculate the PARITY field.
2229 * Note: This page is applicable only to the SPCv controller.
2231 * Initiator and target.
2234 typedef struct agsaPhySNW3Page_s
2238 } agsaPhySNW3Page_t;
2240 /** \brief structure describe error counters of a PHY in the SAS/SATA
2242 * Structure is used as a parameter passed in saLocalPhyControlCB()
2243 * to describe the error counter
2246 typedef struct agsaPhyErrCounters_s
2248 bit32 invalidDword; /* Number of invalid dwords that have been
2249 received outside of phy reset sequences.*/
2250 bit32 runningDisparityError; /* Number of dwords containing running disparity
2251 errors that have been received outside of phy
2253 bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link
2254 reset sequence because it lost dword synchronization.*/
2255 bit32 phyResetProblem; /* Number of times the phy did not obtain dword
2256 synchronization during the final SAS speed
2257 negotiation window.*/
2258 bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity
2259 buffer has overflowed.*/
2260 bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */
2261 bit32 inboundCRCError; /* Number of inbound CRC Error */
2262 bit32 codeViolation; /* Number of code violation */
2263 } agsaPhyErrCounters_t;
2267 * used in saGetPhyProfile
2269 typedef struct agsaPhyErrCountersPage_s
2272 bit32 runningDisparityError;
2273 bit32 codeViolation;
2274 bit32 lossOfDwordSynch;
2275 bit32 phyResetProblem;
2276 bit32 inboundCRCError;
2277 } agsaPhyErrCountersPage_t;
2279 /** \brief structure describes bandwidth counters of a PHY in the SAS/SATA
2281 * Structure is used as a parameter passed in saGetPhyProfile()
2282 * to describe the error counter
2286 typedef struct agsaPhyBWCountersPage_s
2290 } agsaPhyBWCountersPage_t;
2294 /** \brief structure describe hardware configuration
2296 * Structure is used as a parameter passed in saInitialize() to describe the
2297 * configuration used during hardware initialization
2300 typedef struct agsaHwConfig_s
2302 bit32 phyCount; /**< Number of PHYs that are to be configured
2304 bit32 hwInterruptCoalescingTimer; /**< Host Interrupt CoalescingTimer */
2305 bit32 hwInterruptCoalescingControl; /**< Host Interrupt CoalescingControl */
2306 bit32 intReassertionOption; /**< Interrupt Ressertion Option */
2307 bit32 hwOption; /** PCAD64 on 64 bit addressing */
2309 agsaPhyAnalogSetupTable_t phyAnalogConfig; /**< Phy Analog Setting Table */
2312 /** \brief structure describe software configuration
2314 * Structure is used as a parameter passed in saInitialize() to describe the
2315 * configuration used during software initialization
2318 typedef struct agsaSwConfig_s
2320 bit32 maxActiveIOs; /**< Maximum active I/O requests supported */
2321 bit32 numDevHandles; /**< Number of SAS/SATA device handles allocated
2323 bit32 smpReqTimeout; /**< SMP request time out in millisecond */
2324 bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event
2325 registration defined by saRegisterEventCallback() */
2326 bit32 sizefEventLog1; /**< Size of Event Log 1 */
2327 bit32 sizefEventLog2; /**< Size of Event Log 2 */
2328 bit32 eventLog1Option; /**< Option of Event Log 1 */
2329 bit32 eventLog2Option; /**< Option of Event Log 2 */
2331 bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */
2332 bit32 sgpioSupportEnable:1; /**< 1 SGPIO Support Enable */
2333 bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */
2334 bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */
2335 bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */
2336 bit32 legacyInt_X:1; /**< 26 Support Legacy Interrupt */
2337 bit32 hostDirectAccessSupport:1; /**< 27 Support HDA mode */
2338 bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */
2339 bit32 enableDIF:1; /**< 30 */
2340 bit32 enableEncryption:1; /**< 31 */
2341 #ifdef SA_CONFIG_MDFD_REGISTRY
2342 bit32 disableMDF; /*disable MDF*/
2344 bit32 param1; /**< parameter1 */
2345 bit32 param2; /**< parameter2 */
2346 void *param3; /**< parameter3 */
2347 void *param4; /**< paramater4 */
2350 bit32 PortRecoveryResetTimer;
2351 void *mpiContextTable; /** Pointer to a table that contains agsaMPIContext_t
2352 entries. This table is used to fill in MPI table
2353 fields. Values in this table are written to MPI table last.
2354 Any previous values in MPI table are overwritten by values
2357 bit32 mpiContextTablelen; /** Number of agsaMPIContext_t entries in mpiContextTable */
2359 #if defined(SALLSDK_DEBUG)
2360 bit32 sallDebugLevel; /**< Low Layer debug level */
2363 #ifdef SA_ENABLE_PCI_TRIGGER
2365 #endif /* SA_ENABLE_PCI_TRIGGER */
2367 #ifdef SA_ENABLE_TRACE_FUNCTIONS
2368 bit32 TraceDestination;
2369 bit32 TraceBufferSize;
2371 #endif /* SA_ENABLE_TRACE_FUNCTIONS */
2375 typedef struct agsaQueueInbound_s
2377 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth).
2378 A value of zero indicates that the host disabled this queue.*/
2379 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/
2380 bit32 priority:2; /* Queue priority:
2386 } agsaQueueInbound_t;
2388 typedef struct agsaQueueOutbound_s
2390 bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth).
2391 A value of zero indicates that the host disabled
2393 bit32 elementSize:16; /* Size of each element in the queue in bytes.*/
2394 bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host.
2395 Zero means not to delay based on time. An
2396 interrupt is passed to the host when either of
2397 the interruptDelay or interruptCount parameters
2398 is satisfied. Default value is 0.*/
2399 bit32 interruptCount:16; /* Number of interrupts required before passing to
2400 the host. Zero means not to coalesce based on count. */
2401 bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when
2402 Multiple Messages is enabled, this field is the
2403 index to the MSI vectors derived from a single
2404 Message Address and multiple Message Data.
2405 For MSI-X, this field is the index to the
2406 MSI-X Table Structure. */
2407 bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling)
2408 1b: Interrupt enabled */
2411 } agsaQueueOutbound_t;
2413 typedef struct agsaPhyCalibrationTbl_s
2415 bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */
2416 bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/
2417 bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/
2418 bit32 txConfig1; /* transmitter configuration 1 */
2419 bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */
2420 bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */
2421 bit32 rvConfig1; /* reveiver per configuration 1 */
2422 bit32 rvConfig2; /* reveiver per configuration 2 */
2423 bit32 reserved[2]; /* reserved */
2424 } agsaPhyCalibrationTbl_t;
2426 typedef struct agsaQueueConfig_s
2428 bit16 numInboundQueues;
2429 bit16 numOutboundQueues;
2430 bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS];
2431 bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS];
2432 bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS];
2433 bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS];
2434 bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS];
2435 bit8 iqNormalPriorityProcessingDepth;
2436 bit8 iqHighPriorityProcessingDepth;
2437 bit8 generalEventQueue;
2438 bit8 tgtDeviceRemovedEventQueue;
2440 agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q];
2441 agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q];
2442 } agsaQueueConfig_t;
2444 #define OQ_SHARE_PATH_BIT 0x00000001
2446 typedef struct agsaFwImg_s
2448 bit8 *aap1Img; /**< AAP1 Image */
2449 bit32 aap1Len; /**< AAP1 Image Length */
2450 bit8 *ilaImg; /**< ILA Image */
2451 bit32 ilaLen; /**< ILA Image Length */
2452 bit8 *iopImg; /**< IOP Image */
2453 bit32 iopLen; /**< IOP Image Length */
2454 bit8 *istrImg; /**< Init String */
2455 bit32 istrLen; /**< Init String Length */
2458 /** \brief generic memory descriptor
2460 * a generic memory descriptor used for describing a memory requirement in a structure
2463 typedef struct agsaMem_s
2465 void *virtPtr; /**< Virtual pointer to the memory chunk */
2466 void *osHandle; /**< Handle used for OS to free memory */
2467 bit32 phyAddrUpper; /**< Upper 32 bits of physical address */
2468 bit32 phyAddrLower; /**< Lower 32 bits of physical address */
2469 bit32 totalLength; /**< Total length in bytes allocated */
2470 bit32 numElements; /**< Number of elements */
2471 bit32 singleElementLength; /**< Size in bytes of an element */
2472 bit32 alignment; /**< Alignment in bytes needed. A value of one indicates
2473 no specific alignment requirement */
2474 bit32 type; /**< DMA or Cache */
2475 bit32 reserved; /**< reserved */
2478 /** \brief specify the controller Event Log for the SAS/SATA LL Layer
2480 * data structure used in the saGetControllerEventLogInfo() function calls
2483 typedef struct agsaControllerEventLog_s
2485 agsaMem_t eventLog1;
2486 agsaMem_t eventLog2;
2487 bit32 eventLog1Option;
2488 bit32 eventLog2Option;
2489 } agsaControllerEventLog_t;
2491 /* Log Option - bit3-0 */
2492 #define DISABLE_LOGGING 0x0
2493 #define CRITICAL_ERROR 0x1
2496 #define INFORMATION 0x4
2497 #define DEBUGGING 0x5
2499 /** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer
2501 * data structure used in the saGetRequirements() and the saInitialize() function calls
2504 typedef struct agsaSASDiagExecute_s
2513 } agsaSASDiagExecute_t;
2516 /** \brief for the SAS/SATA LL Layer
2518 * This data structure contains the general status of a SAS Phy.
2521 typedef struct agsaSASPhyGeneralStatusPage_s
2525 } agsaSASPhyGeneralStatusPage_t;
2528 /** \brief specify the memory allocation requirement for the SAS/SATA LL Layer
2530 * data structure used in the saGetRequirements() and the saInitialize() function calls
2533 typedef struct agsaMemoryRequirement_s
2535 bit32 count; /**< The number of memory chunks used
2536 in the agMemory table */
2537 agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]; /**< The structure that defines the memory
2538 requirement structure */
2539 } agsaMemoryRequirement_t;
2542 /** \brief describe a SAS address and PHY Identifier
2544 * This structure is used
2547 typedef struct agsaSASAddressID_s
2549 bit8 sasAddressLo[4]; /**< HOST SAS address lower part */
2550 bit8 sasAddressHi[4]; /**< HOST SAS address higher part */
2551 bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */
2552 } agsaSASAddressID_t;
2554 /** \brief data structure provides some information about a SATA device
2556 * data structure provides some information about a SATA device discovered
2557 * following the SATA discovery.
2560 typedef struct agsaDeviceInfo_s
2563 bit16 it_NexusTimeout;
2564 bit16 firstBurstSize;
2567 bit8 devType_S_Rate;
2568 /* Bit 6-7: reserved
2569 Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device
2571 01: SSP or SMP device
2572 10: Direct SATA device
2573 Bit 0-3: Connection Rate field when opening the device.
2580 bit8 sasAddressHi[4];
2581 bit8 sasAddressLo[4];
2586 1b: enable SAS TLR (Transport Layer Retry).
2587 0b: disable SAS TLR (Transport Layer Retry).
2588 When used during device registration, it is recommended that TLR is
2589 enabled, i.e. set the bit to 1.
2590 Bit 1: Priority setting for AWT (Arbitration Wait Time) for this device.
2591 0b: Default setting (recommended). Actual AWT value TBD.
2592 1b: Increase priority. Actual AWT value TBD.
2594 Bit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b
2595 which indicates a directly-attached SATA drive.
2597 Bit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that
2598 can be established with the device concurrently. This field is set to the lowest port width along the pathway
2599 from the controller to the device. This is applicable only to the SPCv controller.
2600 However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller
2601 can establish at least one connection.
2602 Bit 20: Initiator Role
2603 This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller.
2604 0b : The device has no SSP initiator capability.
2605 1b : The device has SSP initiator capability.
2606 Bit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support
2607 0b : Device does not support ATAPI protocol.
2608 1b : Device supports ATAPI protocol.
2614 #define DEV_INFO_MASK 0xFF
2615 #define DEV_INFO_MCN_SHIFT 16
2616 #define DEV_INFO_IR_SHIFT 20
2618 #define RETRY_DEVICE_FLAG (1 << SHIFT0)
2619 #define AWT_DEVICE_FLAG (1 << SHIFT1)
2620 #define SSP_DEVICE_FLAG (1 << SHIFT20)
2621 #define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */
2622 #define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22)
2625 #define DEV_LINK_RATE 0x3F
2627 #define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \
2628 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo)
2630 #define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \
2631 DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi)
2633 #define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \
2634 (((devInfo)->devType_S_Rate & 0xC0) >> 5)
2636 #define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \
2637 *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32)
2639 #define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \
2640 *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32)
2642 /** \brief data structure provides some information about a SATA device
2644 * data structure provides some information about a SATA device discovered
2645 * following the SATA discovery.
2648 typedef struct agsaSATADeviceInfo_s
2650 agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the
2651 SAS/SATA device information */
2652 bit8 connection; /**< How device is connected:
2654 1: Behind Port Multiplier,
2655 portMultiplierField is valid.
2656 2: STP, stpPhyIdentifier is valid */
2658 bit8 portMultiplierField; /**< The first 4 bits indicate that
2659 the Port Multiplier field is defined
2660 by SATA-II. This field is valid only
2661 if the connection field above is
2664 bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if
2665 connection field is set to 2 (STP). */
2668 bit8 signature[8]; /**< The signature of SATA in Task
2669 File registers following power up.
2670 Only five bytes are defined by ATA.
2671 The added three bytes are for
2672 alignment purposes */
2673 } agsaSATADeviceInfo_t;
2675 /** \brief data structure provides some information about a SAS device
2677 * data structure provides some information about a SAS device discovered
2678 * following the SAS discovery
2681 typedef struct agsaSASDeviceInfo_s
2683 agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the SAS/SATA
2684 device information */
2685 bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */
2686 /* b4-7: reserved */
2687 /* b3: SSP initiator port */
2688 /* b2: STP initiator port */
2689 /* b1: SMP initiator port */
2691 bit8 target_ssp_stp_smp; /**< SAS target capabilities */
2692 /* b4-7: reserved */
2693 /* b3: SSP target port */
2694 /* b2: STP target port */
2695 /* b1: SMP target port */
2697 bit32 numOfPhys; /**< Number of PHYs in the device */
2698 bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address
2699 frame as defined by the SAS
2701 } agsaSASDeviceInfo_t;
2703 #define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */
2704 #define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */
2705 #define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */
2706 #define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */
2708 #define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \
2709 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2711 #define SA_SASDEV_IS_STP_INITIATOR(sasDev) \
2712 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2714 #define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \
2715 (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2717 #define SA_SASDEV_IS_SSP_TARGET(sasDev) \
2718 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT)
2720 #define SA_SASDEV_IS_STP_TARGET(sasDev) \
2721 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT)
2723 #define SA_SASDEV_IS_SMP_TARGET(sasDev) \
2724 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT)
2726 #define SA_SASDEV_IS_SATA_DEVICE(sasDev) \
2727 (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT)
2732 /** \brief the data structure describe SG list
2734 * the data structure describe SG list
2737 typedef struct _SASG_DESCRIPTOR
2739 bit32 sgLower; /**< Lower 32 bits of data area physical address */
2740 bit32 sgUpper; /**< Upper 32 bits of data area physical address */
2741 bit32 len; /**< Total data length in bytes */
2742 } SASG_DESCRIPTOR, * PSASG_DESCRIPTOR;
2744 /** \brief data structure used to pass information about the scatter-gather list to the LL Layer
2746 * The ESGL pages are uncached, have a configurable number of SGL
2747 * of (min, max) = (1, 10), and are 16-byte aligned. Although
2748 * the application can configure the page size, the size must be
2749 * incremented in TBD-byte increments. Refer the hardware
2750 * documentation for more detail on the format of ESGL
2754 typedef struct agsaSgl_s
2756 bit32 sgLower; /**< Lower 32 bits of data area physical address */
2757 bit32 sgUpper; /**< Upper 32 bits of data area physical address */
2758 bit32 len; /**< Total data length in bytes */
2759 bit32 extReserved; /**< bit31 is for extended sgl list */
2762 /** \brief data structure is used to pass information about the extended
2763 * scatter-gather list (ESGL) to the LL Layer
2765 * The agsaEsgl_t data structure is used to pass information about the
2766 * extended scatter-gather list (ESGL) to the LL Layer.
2768 * When ESGL is used, its starting address is specified the first descriptor
2769 * entry (i.e. descriptor[0]) in agsaSgl_t structure.
2771 * The ESGL pages are uncached, have a fixed number of SGL of 10, and are
2772 * 16-byte aligned. Refer the hardware documentation for more
2776 typedef struct agsaEsgl_s
2778 agsaSgl_t descriptor[MAX_ESGL_ENTRIES];
2781 /** \brief data structure describes an SSP Command INFORMATION UNIT
2783 * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of
2786 * Currently, Additional CDB length is supported to 16 bytes
2789 #define MAX_CDB_LEN 32
2790 typedef struct agsaSSPCmdInfoUnitExt_s
2794 bit8 efb_tp_taskAttribute;
2796 bit8 additionalCdbLen;
2797 bit8 cdb[MAX_CDB_LEN];
2798 } agsaSSPCmdInfoUnitExt_t ;
2800 #define DIF_UDT_SIZE 6
2802 /* difAction in agsaDif_t */
2803 #define AGSA_DIF_INSERT 0
2804 #define AGSA_DIF_VERIFY_FORWARD 1
2805 #define AGSA_DIF_VERIFY_DELETE 2
2806 #define AGSA_DIF_VERIFY_REPLACE 3
2807 #define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5
2808 #define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7
2810 #define agsaDIFSectorSize512 0
2811 #define agsaDIFSectorSize520 1
2812 #define agsaDIFSectorSize4096 2
2813 #define agsaDIFSectorSize4160 3
2817 typedef struct agsaDif_s
2819 agBOOLEAN enableDIFPerLA;
2821 bit16 initialIOSeed;
2823 bit32 DIFPerLAAddrLo;
2824 bit32 DIFPerLAAddrHi;
2825 bit16 DIFPerLARegion0SecCount;
2827 bit8 udtArray[DIF_UDT_SIZE];
2828 bit8 udrtArray[DIF_UDT_SIZE];
2833 #define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/
2834 #define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */
2835 #define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */
2836 #define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */
2837 #define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */
2838 #define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */
2839 #define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */
2840 #define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */
2841 #define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/
2842 #define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */
2843 #define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/
2844 #define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */
2845 #define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16
2846 #define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */
2847 #define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */
2848 #define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */
2849 #define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */
2850 #define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */
2851 #define DIF_FLAG_BITS_UDTV_SHIFT 20
2852 #define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */
2853 #define DIF_FLAG_BITS_UDTUPSHIFT 26
2855 typedef struct agsaEncryptDek_s
2861 typedef struct agsaEncrypt_s
2863 agsaEncryptDek_t dekInfo;
2865 agBOOLEAN keyTagCheck;
2866 agBOOLEAN enableEncryptionPerLA; /* new */
2867 bit32 sectorSizeIndex;
2875 bit32 EncryptionPerLAAddrLo; /* new */
2876 bit32 EncryptionPerLAAddrHi; /* new */
2877 bit16 EncryptionPerLRegion0SecCount; /* new */
2881 /** \brief data structure describes a SAS SSP command request to be sent to the target device
2883 * data structure describes a SAS SSP command request to be sent to the
2884 * target device. This structure limits the CDB length in SSP
2885 * command up to 16 bytes long.
2887 * This data structure is one instance of the generic request issued to
2888 * saSSPStart() and is passed as an agsaSASRequestBody_t .
2891 typedef struct agsaSSPInitiatorRequest_s
2893 agsaSgl_t agSgl; /**< This structure is used to define either
2894 an ESGL list or a single SGL for the SSP
2895 command operation */
2896 bit32 dataLength; /**< Total data length in bytes */
2897 bit16 firstBurstSize; /**< First Burst Size field as defined by
2898 SAS specification */
2899 bit16 flag; /**< bit1-0 TLR as SAS specification
2901 agsaSSPCmdInfoUnit_t sspCmdIU; /**< Structure containing SSP Command
2904 agsaEncrypt_t encrypt;
2905 #ifdef SA_TESTBASE_EXTRA
2906 /* Added by TestBase */
2908 #endif /* SA_TESTBASE_EXTRA */
2909 } agsaSSPInitiatorRequest_t;
2911 /** \brief data structure describes a SAS SSP command request Ext to be sent to the target device
2913 * data structure describes a SAS SSP command request to be sent to the
2914 * target device. This structure support the CDB length in SSP
2915 * command more than 16 bytes long.
2917 * This data structure is one instance of the generic request issued to
2918 * saSSPStart() and is passed as an agsaSASRequestBody_t .
2921 typedef struct agsaSSPInitiatorRequestExt_s
2923 agsaSgl_t agSgl; /**< This structure is used to define either
2924 an ESGL list or a single SGL for the SSP
2925 command operation */
2927 bit16 firstBurstSize;
2929 agsaSSPCmdInfoUnitExt_t sspCmdIUExt;
2931 agsaEncrypt_t encrypt;
2932 } agsaSSPInitiatorRequestExt_t;
2935 typedef struct agsaSSPInitiatorRequestIndirect_s
2937 agsaSgl_t agSgl; /**< This structure is used to define either
2938 an ESGL list or a single SGL for the SSP
2939 command operation */
2941 bit16 firstBurstSize;
2943 bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */
2944 bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */
2945 bit32 sspInitiatorReqLen; /**< Specifies the length of the SSP initiator request in bytes */
2947 agsaEncrypt_t encrypt;
2949 }agsaSSPInitiatorRequestIndirect_t;
2954 /** \brief data structure describes a SAS SSP target read and write request
2956 * The agsaSSPTargetRequest_t data structure describes a SAS SSP target read
2957 * and write request to be issued on the port. It includes the
2958 * length of the data to be received or sent, an offset into the
2959 * data block where the transfer is to start, and a list of
2960 * scatter-gather buffers.
2962 * This data structure is one instance of the generic request issued
2963 * to saSSPStart() and is passed as an agsaSASRequestBody_t .
2966 /** bit definitions for sspOption
2967 Bit 0-1: Transport Layer Retry setting for other phase:
2969 01b: Retry on ACK/NAK timeout
2970 10b: Retry on NAK received
2971 11b: Retry on both ACK/NAK timeout and NAK received
2972 Bit 2-3: Transport Layer Retry setting for data phase:
2974 01b: Retry on ACK/NAK timeout
2975 10b: Retry on NAK received
2976 11b: Retry on both ACK/NAK timeout and NAK received
2977 Bit 4: Retry Data Frame. Valid only on write command. Indicates whether Target supports RTL for this particular IO.
2980 Bit 5: Auto good response on successful read (data transfer from target to initiator) request.
2983 Bits 6-15 : Reserved.
2985 typedef struct agsaSSPTargetRequest_s
2987 agsaSgl_t agSgl; /**< This structure is used to define either an ESGL list or
2988 a single SGL for the target read or write operation */
2989 bit32 dataLength; /**< Specifies the amount of data to be sent in this data phase */
2990 bit32 offset; /**< Specifies the offset into the overall data block
2991 where this data phase is to begin */
2992 bit16 agTag; /**< Tag from ossaSSPReqReceived(). */
2993 bit16 sspOption; /**< SSP option for retry */
2995 } agsaSSPTargetRequest_t;
2997 #define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */
2998 #define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */
3000 #define SSP_OPTION_OTHR_NO_RETRY 0
3001 #define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1
3002 #define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2
3003 #define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3005 #define SSP_OPTION_DATA_NO_RETRY 0
3006 #define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1
3007 #define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2
3008 #define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3
3010 #define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4)
3011 #define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5)
3012 #define SSP_OPTION_ENCRYPT (1 << SHIFT6)
3013 #define SSP_OPTION_DIF (1 << SHIFT7)
3014 #define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15)
3017 /** \brief data structure describes a SAS SSP target response to be issued
3020 * This data structure is one instance of the generic request issued to
3021 * saSSPStart() and is passed as an agsaSASRequestBody_t
3024 typedef struct agsaSSPTargetResponse_s
3026 bit32 agTag; /**< Tag from ossaSSPReqReceived(). */
3028 bit32 respBufLength; /**< Specifies the length of the Response buffer */
3029 bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer
3030 allocated the Response buffer
3031 (agsaSSPResponseInfoUnit_t).
3032 Valid only when respBufLength is not zero */
3033 bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer
3034 allocated the Response buffer
3035 (agsaSSPResponseInfoUnit_t).
3036 Valid only when respBufLength is not zero */
3037 bit32 respOption; /**< Bit 0-1: ACK and NAK retry option:
3039 01b: Retry on ACK/NAK timeout
3040 10b: Retry on NAK received
3041 11b: Retry on both ACK/NAK timeout and NAK received */
3042 } agsaSSPTargetResponse_t;
3044 #define RESP_OPTION_BITS 0x3 /** bit0-1 */
3045 #define RESP_OPTION_ODS 0x8000 /** bit15 */
3047 /** \brief data structure describes a SMP request or response frame to be sent on the SAS port
3049 * The agsaSMPFrame_t data structure describes a SMP request or response
3050 * frame to be issued or sent on the SAS port.
3052 * This data structure is one instance of the generic request issued to
3053 * saSMPStart() and is passed as an agsaSASRequestBody_t .
3056 typedef struct agsaSMPFrame_s
3058 void *outFrameBuf; /**< if payload is less than 32 bytes,A virtual
3059 frameBuf can be used. instead of physical
3060 address. Set to NULL and use physical
3061 address if payload is > 32 bytes */
3062 bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical
3063 DMA address of the SMP frame buffer */
3064 bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical
3065 DMA address of the SMP frame buffer */
3066 bit32 outFrameLen; /**< Specifies the length of the SMP request
3067 frame excluding the CRC field in bytes */
3068 bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address
3069 of DMA address of response SMP Frame buffer */
3070 bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address
3071 of DMA address of response SMP Frame buffer */
3072 bit32 inFrameLen; /**< Specifies the length of the SMP response
3073 frame excluding the CRC field in bytes */
3074 bit32 expectedRespLen; /**< Specifies the length of SMP Response */
3075 bit32 flag; /** For the SPCv controller:
3076 Bit 0: Indirect Response (IR). This indicates
3077 direct or indirect mode for SMP response frame
3082 Bit 1: Indirect Payload (IP). This indicates
3083 direct or indirect mode for SMP request frame
3089 For the SPC controller: This is not applicable.
3094 #define smpFrameFlagDirectResponse 0
3095 #define smpFrameFlagIndirectResponse 1
3096 #define smpFrameFlagDirectPayload 0
3097 #define smpFrameFlagIndirectPayload 2
3099 /** \brief union data structure specifies a request
3101 * union data structure specifies a request
3103 typedef union agsaSASRequestBody_u
3105 agsaSSPInitiatorRequest_t sspInitiatorReq; /**< Structure containing the SSP initiator request, Support up to 16 bytes CDB */
3106 agsaSSPInitiatorRequestExt_t sspInitiatorReqExt; /**< Structure containing the SSP initiator request for CDB > 16 bytes */
3107 agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect; /**< Structure containing the SSP indirect initiator request */
3108 agsaSSPTargetRequest_t sspTargetReq; /**< Structure containing the SSP Target request */
3109 agsaSSPScsiTaskMgntReq_t sspTaskMgntReq; /**< Structure containing the SSP SCSI Task Management request */
3110 agsaSSPTargetResponse_t sspTargetResponse; /**< Structure containing the SSP Target response. */
3111 agsaSMPFrame_t smpFrame; /**< Structure containing SMP request or response frame */
3112 }agsaSASRequestBody_t;
3117 /** \brief data structure describes an STP or direct connect SATA command
3119 * The agsaSATAInitiatorRequest_t data structure describes an STP or direct
3120 * connect SATA command request to be sent to the device and
3121 * passed as a parameter to saSATAStart() function.
3123 * This structure is an encapsulation of SATA FIS (Frame Information
3124 * Structures), which enables the execution of ATA command
3125 * descriptor using SATA transport
3128 typedef struct agsaSATAInitiatorRequest_s
3130 agsaSgl_t agSgl; /**< This structure is used to define either an ESGL
3131 list or a single SGL for operation that involves
3134 bit32 dataLength; /**< Total data length in bytes */
3136 bit32 option; /**< Operational option, defined using the bit field.
3138 b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */
3140 agsaSATAHostFis_t fis; /**< The FIS request */
3142 agsaEncrypt_t encrypt;
3144 #ifdef SA_TESTBASE_EXTRA
3145 /* Added by TestBase */
3147 #endif /* SA_TESTBASE_EXTRA */
3148 } agsaSATAInitiatorRequest_t;
3151 /* controller Configuration page */
3152 #define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04
3153 #define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05
3154 #define AGSA_IO_GENERAL_CONFIG_PAGE 0x06
3155 #define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20
3156 #define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21
3157 #define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22
3158 #define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23
3160 #ifdef HIALEAH_ENCRYPTION
3161 typedef struct agsaEncryptGeneralPage_s {
3162 bit32 numberOfKeksPageCode; /* 0x20 */
3163 bit32 KeyCardIdKekIndex;
3166 bit32 KeyCardId11_8;
3167 } agsaEncryptGeneralPage_t;
3169 typedef struct agsaEncryptGeneralPage_s {
3170 bit32 pageCode; /* 0x20 */
3172 } agsaEncryptGeneralPage_t;
3173 #endif /* HIALEAH_ENCRYPTION */
3175 #define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00
3176 #define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8
3179 typedef struct agsaEncryptDekConfigPage_s {
3183 bit32 table0Entries;
3187 bit32 table1Entries;
3189 } agsaEncryptDekConfigPage_t;
3191 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000
3192 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28
3193 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000
3194 #define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24
3197 /* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */
3198 /* NAR, CORCAP and USRCAP are valid only when AUT==1 */
3199 typedef struct agsaEncryptControlParamPage_s {
3200 bit32 pageCode; /* 0x22 */
3201 bit32 CORCAP; /* Crypto Officer Role Capabilities */
3202 bit32 USRCAP; /* User Role Capabilities */
3203 bit32 CCS; /* Current Crypto Services */
3204 bit32 NOPR; /* Number of Operators */
3205 } agsaEncryptControlParamPage_t;
3207 typedef struct agsaEncryptInfo_s {
3208 bit32 encryptionCipherMode;
3209 bit32 encryptionSecurityMode;
3212 } agsaEncryptInfo_t;
3215 #define OperatorAuthenticationEnable_AUT 1
3216 #define ReturnToFactoryMode_ARF 2
3219 typedef struct agsaEncryptSelfTestBitMap_s {
3221 bit32 KEY_WRAP_Test;
3223 } agsaEncryptSelfTestBitMap_t;
3225 typedef struct agsaEncryptSelfTestStatusBitMap_s{
3227 bit32 KEY_WRAP_Status;
3229 } agsaEncryptSelfTestStatusBitMap_t;
3231 typedef struct agsaEncryptHMACTestDescriptor_s
3242 } agsaEncryptHMACTestDescriptor_t;
3244 typedef struct agsaEncryptHMACTestResult_s
3248 } agsaEncryptHMACTestResult_t;
3250 typedef struct agsaEncryptSHATestDescriptor_s
3258 } agsaEncryptSHATestDescriptor_t;
3260 typedef struct agsaEncryptSHATestResult_s
3264 } agsaEncryptSHATestResult_t;
3266 /* types of self test */
3267 #define AGSA_BIST_TEST 0x1
3268 #define AGSA_HMAC_TEST 0x2
3269 #define AGSA_SHA_TEST 0x3
3273 typedef struct agsaEncryptDekBlob_s {
3275 } agsaEncryptDekBlob_t;
3277 typedef struct agsaEncryptKekBlob_s {
3279 } agsaEncryptKekBlob_t;
3282 typedef struct agsaEncryptHMACConfigPage_s
3288 } agsaEncryptHMACConfigPage_t;
3291 #define AGSA_ID_SIZE 31
3292 typedef struct agsaID_s {
3293 bit8 ID[AGSA_ID_SIZE];
3297 #define SA_OPR_MGMNT_FLAG_MASK 0x00003000
3298 #define SA_OPR_MGMNT_FLAG_SHIFT 12
3301 typedef struct agsaSASPhyMiscPage_s {
3304 } agsaSASPhyMiscPage_t ;
3307 typedef struct agsaHWEventEncrypt_s {
3308 bit32 encryptOperation;
3310 bit32 eq; /* error qualifier */
3314 } agsaHWEventEncrypt_t;
3317 typedef struct agsaHWEventMode_s {
3318 bit32 modePageOperation;
3323 } agsaHWEventMode_t;
3326 typedef struct agsaInterruptConfigPage_s {
3338 } agsaInterruptConfigPage_t;
3339 typedef struct agsaIoGeneralPage_s {
3340 bit32 pageCode; /* 0x06 */
3343 } agsaIoGeneralPage_t;
3345 /* \brief data structure defines detail information about Agilent Error
3346 * Detection Code (DIF) errors.
3348 * The agsaDifDetails_t data structure defines detail information about
3349 * PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC
3350 * and SPC draft/specification for the definition of the Protection
3353 * This structure is filled by the function saGetDifErrorDetails().
3356 typedef struct agsaDifDetails_s {
3359 bit8 sasAddressHi[4];
3360 bit8 sasAddressLo[4];
3361 bit32 ExpectedCRCUDT01;
3362 bit32 ExpectedUDT2345;
3363 bit32 ActualCRCUDT01;
3364 bit32 ActualUDT2345;
3366 bit32 ErrBoffsetEDataLen;
3370 /** \brief data structure for SAS protocol timer configuration page.
3373 typedef struct agsaSASProtocolTimerConfigurationPage_s{
3374 bit32 pageCode; /* 0 */
3375 bit32 MST_MSI; /* 1 */
3376 bit32 STP_SSP_MCT_TMO; /* 2 */
3377 bit32 STP_FRM_TMO; /* 3 */
3378 bit32 STP_IDLE_TMO; /* 4 */
3379 bit32 OPNRJT_RTRY_INTVL; /* 5 */
3380 bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */
3381 bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */
3382 bit32 MAX_AIP; /* 8 */
3383 } agsaSASProtocolTimerConfigurationPage_t;
3386 /** \brief data structure for firmware flash update saFwFlashUpdate().
3388 * The agsaUpdateFwFlash data structure specifies a request to saFwFlashUpdate()
3390 typedef struct agsaUpdateFwFlash_s
3392 bit32 currentImageOffset;
3393 bit32 currentImageLen;
3394 bit32 totalImageLen;
3396 } agsaUpdateFwFlash_t;
3400 /** \brief data structure for extended firmware flash update saFwFlashExtUpdate().
3402 * The agsaFlashExtExecute_s data structure specifies a request to saFwFlashExtUpdate()
3404 typedef struct agsaFlashExtExecute_s
3410 } agsaFlashExtExecute_t;
3413 /** \brief data structure for firmware flash update saFwFlashUpdate().
3415 * The agsaFlashExtResponse_t data structure specifies a request to ossaFlashExtExecuteCB().()
3417 typedef struct agsaFlashExtResponse_s
3420 bit32 epart_sect_size;
3421 } agsaFlashExtResponse_t;
3424 /** \brief data structure for set fields in MPI table.
3425 * The agsaMPIContext_t data structure is used to set fields in MPI table.
3426 * For details of MPI table, refer to PM8001 Tachyon SPC 8x6G Programmers'
3427 * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual
3428 * PMC-2091148/PMC-2102373.
3432 typedef struct agsaMPIContext_s
3439 #define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1
3440 #define AGSA_MPI_GENERAL_STATUS_TABLE 2
3441 #define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3
3442 #define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4
3443 #define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5
3444 #define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6
3445 #define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7
3446 #define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8
3449 /************************************************************/
3450 /*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/
3451 //#define SPC_ENABLE_PROFILE
3453 #ifdef SPC_ENABLE_PROFILE
3454 typedef struct agsaFwProfile_s
3465 /************************************************************/
3466 /** \brief Callback definition for .ossaDeviceRegistration
3469 typedef void (*ossaDeviceRegistrationCB_t)(
3471 agsaContext_t *agContext,
3473 agsaDevHandle_t *agDevHandle,
3477 /** \brief Callback definition for
3480 typedef void (*ossaDeregisterDeviceHandleCB_t)(
3482 agsaContext_t *agContext,
3483 agsaDevHandle_t *agDevHandle,
3487 /** \brief Callback definition for
3490 typedef void (*ossaGenericCB_t)(void);
3493 /** \brief Callback definition for abort SMP SSP SATA callback
3496 typedef void (*ossaGenericAbortCB_t)(
3498 agsaIORequest_t *agIORequest,
3504 typedef void (*ossaLocalPhyControlCB_t)(
3506 agsaContext_t *agContext,
3514 /** \brief Callback definition for
3517 typedef void (*ossaSATACompletedCB_t)(
3519 agsaIORequest_t *agIORequest,
3527 /** \brief Callback definition for
3530 typedef void (*ossaSMPCompletedCB_t)(
3532 agsaIORequest_t *agIORequest,
3535 agsaFrameHandle_t agFrameHandle
3539 /** \brief Callback definition for
3542 typedef void (*ossaSSPCompletedCB_t)(
3544 agsaIORequest_t *agIORequest,
3552 /** \brief Callback definition for
3555 typedef void (*ossaSetDeviceInfoCB_t) (
3557 agsaContext_t *agContext,
3558 agsaDevHandle_t *agDevHandle,
3564 typedef struct agsaOffloadDifDetails_s
3566 bit32 ExpectedCRCUDT01;
3567 bit32 ExpectedUDT2345;
3568 bit32 ActualCRCUDT01;
3569 bit32 ActualUDT2345;
3572 } agsaOffloadDifDetails_t;
3574 typedef struct agsaDifEncPayload_s
3581 agsaEncrypt_t encrypt;
3582 } agsaDifEncPayload_t;
3584 typedef void (*ossaVhistCaptureCB_t) (
3586 agsaContext_t *agContext,
3590 typedef void (*ossaDIFEncryptionOffloadStartCB_t) (
3592 agsaContext_t *agContext,
3594 agsaOffloadDifDetails_t *agsaOffloadDifDetails
3597 #define SA_RESERVED_REQUEST_COUNT 16
3599 #ifdef SA_FW_TIMER_READS_STATUS
3600 #define SA_FW_TIMER_READS_STATUS_INTERVAL 20
3601 #endif /* SA_FW_TIMER_READS_STATUS */
3603 #define SIZE_DW 4 /**< Size in bytes */
3604 #define SIZE_QW 8 /**< Size in bytes */
3606 #define PCIBAR0 0 /**< PCI Base Address 0 */
3607 #define PCIBAR1 1 /**< PCI Base Address 1 */
3608 #define PCIBAR2 2 /**< PCI Base Address 2 */
3609 #define PCIBAR3 3 /**< PCI Base Address 3 */
3610 #define PCIBAR4 4 /**< PCI Base Address 4 */
3611 #define PCIBAR5 5 /**< PCI Base Address 5 */
3613 /** \brief describe an element of SPC-SPCV converter
3615 * This structure is used
3618 typedef struct agsaBarOffset_s
3620 bit32 Generic; /* */
3626 typedef union agsabit32bit64_U
3633 The agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB().
3634 This data structure contains the number of IO error and event.
3636 typedef struct agsaIOErrorEventStats_s
3638 bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS;
3639 bit32 agOSSA_IO_ABORTED;
3640 bit32 agOSSA_IO_OVERFLOW;
3641 bit32 agOSSA_IO_UNDERFLOW;
3642 bit32 agOSSA_IO_FAILED;
3643 bit32 agOSSA_IO_ABORT_RESET;
3644 bit32 agOSSA_IO_NOT_VALID;
3645 bit32 agOSSA_IO_NO_DEVICE;
3646 bit32 agOSSA_IO_ILLEGAL_PARAMETER;
3647 bit32 agOSSA_IO_LINK_FAILURE;
3648 bit32 agOSSA_IO_PROG_ERROR;
3649 bit32 agOSSA_IO_DIF_IN_ERROR;
3650 bit32 agOSSA_IO_DIF_OUT_ERROR;
3651 bit32 agOSSA_IO_ERROR_HW_TIMEOUT;
3652 bit32 agOSSA_IO_XFER_ERROR_BREAK;
3653 bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY;
3654 bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED;
3655 bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION;
3656 bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK;
3657 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS;
3658 bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION;
3659 bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED;
3660 bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY;
3661 bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION;
3662 bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR;
3663 bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED;
3664 bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT;
3665 bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED;
3666 bit32 agOSSA_IO_XFER_ERROR_RX_FRAME;
3667 bit32 agOSSA_IO_XFER_ERROR_DMA;
3668 bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT;
3669 bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT;
3670 bit32 agOSSA_IO_XFER_ERROR_SATA;
3671 bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST;
3672 bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE;
3673 bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE;
3674 bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT;
3675 bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR;
3676 bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE;
3677 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN;
3678 bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED;
3679 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT;
3680 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK;
3681 bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK;
3682 bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH;
3683 bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN;
3684 bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED;
3685 bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE;
3686 bit32 agOSSA_IO_PORT_IN_RESET;
3687 bit32 agOSSA_IO_DS_NON_OPERATIONAL;
3688 bit32 agOSSA_IO_DS_IN_RECOVERY;
3689 bit32 agOSSA_IO_TM_TAG_NOT_FOUND;
3690 bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR;
3691 bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR;
3692 bit32 agOSSA_IO_DS_IN_ERROR;
3693 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY;
3694 bit32 agOSSA_IO_ABORT_IN_PROGRESS;
3695 bit32 agOSSA_IO_ABORT_DELAYED;
3696 bit32 agOSSA_IO_INVALID_LENGTH;
3697 bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT;
3698 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED;
3699 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO;
3700 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST;
3701 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE;
3702 bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED;
3703 bit32 agOSSA_IO_DS_INVALID;
3704 bit32 agOSSA_IO_XFER_READ_COMPL_ERR;
3705 bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR;
3706 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR;
3707 bit32 agOSSA_MPI_IO_RQE_BUSY_FULL;
3708 bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE;
3709 bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY;
3710 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS;
3711 bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH;
3712 bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID;
3713 bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH;
3714 bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR;
3715 bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM;
3716 bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH;
3717 bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH;
3718 bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH;
3719 bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH;
3720 bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME;
3721 bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN;
3722 bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS;
3723 bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED;
3724 bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE;
3725 bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR;
3726 bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED;
3727 bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT;
3728 bit32 agOSSA_IO_UNKNOWN_ERROR;
3729 } agsaIOErrorEventStats_t;
3732 /************************************************************************************
3734 * Data Structures Defined for LL API ends *
3736 ************************************************************************************/
3737 #ifdef SALL_API_TEST
3738 typedef struct agsaIOCountInfo_s
3740 bit32 numSSPStarted; // saSSPStart()
3741 bit32 numSSPAborted; // saSSPAbort()
3742 bit32 numSSPAbortedCB; // ossaSSPAbortCB()
3743 bit32 numSSPCompleted; // includes success and aborted IOs
3744 bit32 numSMPStarted; // saSMPStart()
3745 bit32 numSMPAborted; // saSMPAbort()
3746 bit32 numSMPAbortedCB; // ossaSMPAbortCB()
3747 bit32 numSMPCompleted; // includes success and aborted IOs
3748 bit32 numSataStarted; // saSATAStart()
3749 bit32 numSataAborted; // saSATAAbort()
3750 bit32 numSataAbortedCB; // ossaSATAAbortCB()
3751 bit32 numSataCompleted; // includes success and aborted IOs
3752 bit32 numEchoSent; // saEchoCommand()
3753 bit32 numEchoCB; // ossaEchoCB()
3754 bit32 numUNKNWRespIOMB; // unknow Response IOMB received
3755 bit32 numOurIntCount; //InterruptHandler() counter
3756 bit32 numSpuriousInt; //spurious interrupts
3757 // bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI)
3758 // bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI)
3759 } agsaIOCountInfo_t;
3761 /* Total IO Counter */
3762 #define LL_COUNTERS 17
3763 /* Counter Bit Map */
3764 #define COUNTER_SSP_START 0x000001
3765 #define COUNTER_SSP_ABORT 0x000002
3766 #define COUNTER_SSPABORT_CB 0x000004
3767 #define COUNTER_SSP_COMPLETEED 0x000008
3768 #define COUNTER_SMP_START 0x000010
3769 #define COUNTER_SMP_ABORT 0x000020
3770 #define COUNTER_SMPABORT_CB 0x000040
3771 #define COUNTER_SMP_COMPLETEED 0x000080
3772 #define COUNTER_SATA_START 0x000100
3773 #define COUNTER_SATA_ABORT 0x000200
3774 #define COUNTER_SATAABORT_CB 0x000400
3775 #define COUNTER_SATA_COMPLETEED 0x000800
3776 #define COUNTER_ECHO_SENT 0x001000
3777 #define COUNTER_ECHO_CB 0x002000
3778 #define COUNTER_UNKWN_IOMB 0x004000
3779 #define COUNTER_OUR_INT 0x008000
3780 #define COUNTER_SPUR_INT 0x010000
3781 #define ALL_COUNTERS 0xFFFFFF
3783 typedef union agsaLLCountInfo_s
3785 agsaIOCountInfo_t IOCounter;
3786 bit32 arrayIOCounter[LL_COUNTERS];
3787 } agsaLLCountInfo_t;
3789 #endif /* SALL_API_TEST */
3791 #define MAX_IO_DEVICE_ENTRIES 4096 /**< Maximum Device Entries */
3794 #ifdef SA_ENABLE_POISION_TLP
3795 #define SA_PTNFE_POISION_TLP 1 /* Enable if one */
3796 #else /* SA_ENABLE_POISION_TLP */
3797 #define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */
3798 #endif /* SA_ENABLE_POISION_TLP */
3800 #ifdef SA_DISABLE_MDFD
3801 #define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */
3802 #else /* SA_DISABLE_MDFD */
3803 #define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */
3804 #endif /* SA_DISABLE_MDFD */
3806 #ifdef SA_ENABLE_ARBTE
3807 #define SA_ARBTE 1 /* Enable if one */
3808 #else /* SA_ENABLE_ARBTE */
3809 #define SA_ARBTE 0 /* Disable if zero default setting */
3810 #endif /* SA_ENABLE_ARBTE */
3812 #ifdef SA_DISABLE_OB_COAL
3813 #define SA_OUTBOUND_COALESCE 0 /* Disable if zero */
3814 #else /* SA_DISABLE_OB_COAL */
3815 #define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */
3816 #endif /* SA_DISABLE_OB_COAL */
3819 /***********************************************************************************
3821 * The OS Layer Functions Declarations start *
3823 ***********************************************************************************/
3824 #include "saosapi.h"
3825 /***********************************************************************************
3827 * The OS Layer Functions Declarations end *
3829 ***********************************************************************************/
3831 /***********************************************************************************
3833 * The LL Layer Functions Declarations start *
3835 ***********************************************************************************/
3838 /* needs to be allocated by the xPrepare() caller, one struct per IO */
3839 typedef struct agsaFastCBBuf_s
3846 void *oneDeviceData; /* tdsaDeviceData_t */
3849 typedef struct agsaFastCommand_s
3853 /* modified by TD tiFastPrepare() */
3854 void *devHandle; /* agsaDevHandle_t* */
3855 void *agSgl; /* agsaSgl_t* */
3857 bit32 extDataLength;
3858 bit8 additionalCdbLen;
3861 /* modified by TD tiFastPrepare() */
3862 bit8 taskAttribute; /* TD_xxx */
3863 bit16 flag; /* TLR_MASK */
3864 bit32 agRequestType;
3866 agsaFastCBBuf_t *safb;
3867 } agsaFastCommand_t;
3872 /* Enable test by setting bits in gFPGA_TEST */
3874 #define EnableFPGA_TEST_ICCcontrol 0x01
3875 #define EnableFPGA_TEST_ReadDEV 0x02
3876 #define EnableFPGA_TEST_WriteCALAll 0x04
3877 #define EnableFPGA_TEST_ReconfigSASParams 0x08
3878 #define EnableFPGA_TEST_LocalPhyControl 0x10
3879 #define EnableFPGA_TEST_PortControl 0x20
3883 PM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification
3885 3.3 Encryption Status Definitions
3886 Encryption engine generated errors.
3887 Table 7 Encryption Engine Generated Errors
3893 section 4.26.12.6 Encryption Errors
3894 Table 51 lists initialization errors related to encryption functionality. For information on errors reported
3895 for inbound IOMB commands, refer to the corresponding outbound response sections. The error codes
3896 listed in Table 51 are reported in the Scratchpad 3 Register.
3898 #define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */
3899 #define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */
3900 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */
3901 #define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */
3902 #define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */
3903 #define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */
3904 #define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */
3905 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */
3906 #define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */
3907 #define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */
3908 #define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */
3909 #define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */
3910 #define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */
3911 #define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */
3913 /* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */
3914 /* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */
3915 /* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */
3916 /* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */
3917 /* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */
3918 /* 0x20:ENC_ERR_FLASH_ACCESS_TMO */
3919 /* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */
3920 /* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */
3921 /* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */
3922 /* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */
3923 /* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */
3924 /* 0x41:ENC_ERR_AES_BIST_FAILURE */
3925 /* 0x42:ENC_ERR_KWP_BIST_FAILURE */
3928 This field indicates self test failure in DIF engine bits [27:24].
3931 #define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */
3933 #define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */
3934 #define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */
3935 #define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */
3936 #define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */
3938 #define SA_ROLE_CAPABILITIES_CSP 0x001
3939 #define SA_ROLE_CAPABILITIES_OPR 0x002
3940 #define SA_ROLE_CAPABILITIES_SCO 0x004
3941 #define SA_ROLE_CAPABILITIES_STS 0x008
3942 #define SA_ROLE_CAPABILITIES_TST 0x010
3943 #define SA_ROLE_CAPABILITIES_KEK 0x020
3944 #define SA_ROLE_CAPABILITIES_DEK 0x040
3945 #define SA_ROLE_CAPABILITIES_IOS 0x080
3946 #define SA_ROLE_CAPABILITIES_FWU 0x100
3947 #define SA_ROLE_CAPABILITIES_PRM 0x200
3951 /***********************************************************************************
3953 * The LL Layer Functions Declarations end *
3955 ***********************************************************************************/
3957 #endif /*__SA_H__ */