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33 /* These structures define the layouts for the TLV items stored in static and
34 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
36 * They contain the same sort of information that was kept in the
37 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
38 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
41 * These are used directly by the MC and should also be usable directly on host
42 * systems which are little-endian and do not do strange things with structure
43 * padding. (Big-endian host systems will require some byte-swapping.)
47 * Please refer to SF-108797-SW for a general overview of the TLV partition
52 * The current tag IDs have a general structure: with the exception of the
53 * special values defined in the document, they are of the form 0xLTTTNNNN,
56 * - L is a location, indicating where this tag is expected to be found:
57 * 0 for static configuration, or 1 for dynamic configuration. Other
58 * values are reserved.
60 * - TTT is a type, which is just a unique value. The same type value
61 * might appear in both locations, indicating a relationship between
62 * the items (e.g. static and dynamic VPD below).
64 * - NNNN is an index of some form. Some item types are per-port, some
65 * are per-PF, some are per-partition-type.
69 * As with the previous Siena structures, each structure here is laid out
70 * carefully: values are aligned to their natural boundary, with explicit
71 * padding fields added where necessary. (No, technically this does not
72 * absolutely guarantee portability. But, in practice, compilers are generally
73 * sensible enough not to introduce completely pointless padding, and it works
78 #ifndef CI_MGMT_TLV_LAYOUT_H
79 #define CI_MGMT_TLV_LAYOUT_H
82 /* ----------------------------------------------------------------------------
83 * General structure (defined by SF-108797-SW)
84 * ----------------------------------------------------------------------------
90 * (Note that this is *not* followed by length or value fields: anything after
91 * the tag itself is irrelevant.)
94 #define TLV_TAG_END (0xEEEEEEEE)
97 /* Other special reserved tag values.
100 #define TLV_TAG_SKIP (0x00000000)
101 #define TLV_TAG_INVALID (0xFFFFFFFF)
104 /* TLV partition header.
106 * In a TLV partition, this must be the first item in the sequence, at offset
110 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
112 struct tlv_partition_header {
118 uint32_t total_length;
122 /* TLV partition trailer.
124 * In a TLV partition, this must be the last item in the sequence, immediately
125 * preceding the TLV_TAG_END word.
128 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
130 struct tlv_partition_trailer {
138 /* Appendable TLV partition header.
140 * In an appendable TLV partition, this must be the first item in the sequence,
141 * at offset 0. (Note that, unlike the configuration partitions, there is no
142 * trailer before the TLV_TAG_END word.)
145 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
147 struct tlv_appendable_partition_header {
155 /* ----------------------------------------------------------------------------
156 * Configuration items
157 * ----------------------------------------------------------------------------
161 /* NIC global capabilities.
164 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
166 struct tlv_global_capabilities {
173 /* Siena-style per-port MAC address allocation.
175 * There are <count> addresses, starting at <base_address> and incrementing
176 * by adding <stride> to the low-order byte(s).
178 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
179 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
182 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
184 struct tlv_port_mac {
187 uint8_t base_address[6];
196 * This is the portion of VPD which is set at manufacturing time and not
197 * expected to change. It is formatted as a standard PCI VPD block.
200 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
202 struct tlv_pf_static_vpd {
211 * This is the portion of VPD which may be changed (e.g. by firmware updates).
212 * It is formatted as a standard PCI VPD block.
215 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
217 struct tlv_pf_dynamic_vpd {
224 /* "DBI" PCI config space changes.
226 * This is a set of edits made to the default PCI config space values before
227 * the device is allowed to enumerate.
230 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
237 uint16_t byte_enables;
243 /* Partition subtype codes.
245 * A subtype may optionally be stored for each type of partition present in
246 * the NVRAM. For example, this may be used to allow a generic firmware update
247 * utility to select a specific variant of firmware for a specific variant of
250 * The description[] field is an optional string which is returned in the
251 * MC_CMD_NVRAM_METADATA response if present.
254 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
256 struct tlv_partition_subtype {
260 uint8_t description[];
264 /* Partition version codes.
266 * A version may optionally be stored for each type of partition present in
267 * the NVRAM. This provides a standard way of tracking the currently stored
268 * version of each of the various component images.
271 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
273 struct tlv_partition_version {
282 /* Global PCIe configuration */
284 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
286 struct tlv_pcie_config {
289 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
290 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
291 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
292 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
293 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
294 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
297 /* Per-PF configuration. Note that not all these fields are necessarily useful
298 * as the apertures are constrained by the BIU settings (the one case we do
299 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
300 * tidy things up later */
302 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
304 struct tlv_per_pf_pcie_config {
308 uint8_t port_allocation;
309 uint16_t vectors_per_pf;
310 uint16_t vectors_per_vf;
311 uint8_t pf_bar0_aperture;
312 uint8_t pf_bar2_aperture;
313 uint8_t vf_bar0_aperture;
315 uint16_t supp_pagesz;
316 uint16_t msix_vec_base;
320 /* Development ONLY. This is a single TLV tag for all the gubbins
321 * that can be set through the MC command-line other than the PCIe
322 * settings. This is a temporary measure. */
323 #define TLV_TAG_TMP_GUBBINS (0x10090000)
325 struct tlv_tmp_gubbins {
328 /* Consumed by dpcpu.c */
329 uint64_t tx0_tags; /* Bitmap */
330 uint64_t tx1_tags; /* Bitmap */
331 uint64_t dl_tags; /* Bitmap */
333 #define TLV_DPCPU_TX_STRIPE (1) /* TX striping is on */
334 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
335 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
336 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
337 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
338 /* Consumed by features.c */
339 uint32_t dut_features; /* All 1s -> leave alone */
340 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
341 /* Consumed by clocks_hunt.c */
342 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
343 /* Consumed by sram.c */
344 int8_t rx_dc_size; /* -1 -> leave alone */
346 int16_t num_q_allocs;
349 /* Global port configuration
351 * This is now deprecated in favour of a platform-provided default
352 * and dynamic config override via tlv_global_port_options.
354 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
356 struct tlv_global_port_config {
359 uint32_t ports_per_core;
360 uint32_t max_port_speed;
366 * This is intended for user-configurable selection of optional firmware
367 * features and variants.
369 * Initially, this consists only of the satellite CPU firmware variant
370 * selection, but this tag could be extended in the future (using the
371 * tag length to determine whether additional fields are present).
374 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
376 struct tlv_firmware_options {
379 uint32_t firmware_variant;
380 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
382 /* These are the values for overriding the driver's choice; the definitions
383 * are taken from MCDI so that they don't get out of step. Include
384 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
385 * you need to use these constants.
387 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
388 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
389 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
390 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
391 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
392 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
397 * Intended for boards with A0 silicon where the core voltage may
398 * need tweaking. Most likely set once when the pass voltage is
401 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
403 struct tlv_0v9_settings {
406 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
407 #define TLV_TAG_0V9_REQUIRES_FAN (1)
408 uint16_t target_voltage; /* In millivolts */
409 /* Since the limits are meant to be centred to the target (and must at least
410 * contain it) they need setting as well. */
411 uint16_t warn_low; /* In millivolts */
412 uint16_t warn_high; /* In millivolts */
413 uint16_t panic_low; /* In millivolts */
414 uint16_t panic_high; /* In millivolts */
418 /* Clock configuration */
420 #define TLV_TAG_CLOCK_CONFIG (0x000d0000)
422 struct tlv_clock_config {
425 uint16_t clk_sys; /* MHz */
426 uint16_t clk_dpcpu; /* MHz */
427 uint16_t clk_icore; /* MHz */
428 uint16_t clk_pcs; /* MHz */
431 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
433 struct tlv_clock_config_medford {
436 uint16_t clk_sys; /* MHz */
437 uint16_t clk_mc; /* MHz */
438 uint16_t clk_rmon; /* MHz */
439 uint16_t clk_vswitch; /* MHz */
440 uint16_t clk_dpcpu; /* MHz */
441 uint16_t clk_pcs; /* MHz */
445 /* EF10-style global pool of MAC addresses.
447 * There are <count> addresses, starting at <base_address>, which are
448 * contiguous. Firmware is responsible for allocating addresses from this
449 * pool to ports / PFs as appropriate.
452 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
454 struct tlv_global_mac {
457 uint8_t base_address[6];
463 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000)
465 /* The target value for the 0v9 power rail measured on-chip at the
466 * analogue test bus */
467 struct tlv_0v9_atb_target {
474 /* Global PCIe configuration, second revision. This represents the visible PFs
475 * by a bitmap rather than having the number of the highest visible one. As such
476 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
477 * can and it should be used in place of that tag in future (but compatibility with
478 * the old tag will be left in the firmware indefinitely). */
480 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
482 struct tlv_pcie_config_r2 {
485 uint16_t visible_pfs; /**< Bitmap of visible PFs */
486 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
487 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
488 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
491 /* Dynamic port mode.
493 * Allows selecting alternate port configuration for platforms that support it
494 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
495 * number of externally visible ports (and, hence, PF to port mapping), so must
496 * be done at boot time.
498 * This tag supercedes tlv_global_port_config.
501 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
503 struct tlv_global_port_mode {
507 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
508 #define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */
509 #define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */
510 #define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
511 #define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
512 #define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
513 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */
514 #define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
515 #define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
516 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */
517 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
520 /* Type of the v-switch created implicitly by the firmware */
522 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
524 struct tlv_vswitch_type {
527 uint32_t vswitch_type;
528 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
529 #define TLV_VSWITCH_TYPE_NONE (0)
530 #define TLV_VSWITCH_TYPE_VLAN (1)
531 #define TLV_VSWITCH_TYPE_VEB (2)
532 #define TLV_VSWITCH_TYPE_VEPA (3)
533 #define TLV_VSWITCH_TYPE_MUX (4)
534 #define TLV_VSWITCH_TYPE_TEST (5)
537 /* A VLAN tag for the v-port created implicitly by the firmware */
539 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
541 struct tlv_vport_vlan_tag {
545 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
548 /* Offset to be applied to the 0v9 setting, wherever it came from */
550 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
552 struct tlv_0v9_atb_offset {
555 int16_t offset_millivolts;
559 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
560 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
561 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
562 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
563 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
565 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
567 struct tlv_privilege_mask { /* legacy structure - do not use */
570 uint32_t privilege_mask;
573 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
575 struct tlv_privilege_mask_add {
578 uint32_t privilege_mask_add;
581 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
583 struct tlv_privilege_mask_rem {
586 uint32_t privilege_mask_rem;
589 /* Additional privileges given to all PFs.
590 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
592 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
594 struct tlv_privilege_mask_add_all_pfs {
597 uint32_t privilege_mask_add;
600 /* Additional privileges given to a selected PF.
601 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
603 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
605 struct tlv_privilege_mask_add_single_pf {
608 uint32_t privilege_mask_add;
611 /* Turning on/off the PFIOV mode.
612 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
614 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
620 #define TLV_PFIOV_OFF (0) /* Default */
621 #define TLV_PFIOV_ON (1)
624 /* Multicast filter chaining mode selection.
626 * When enabled, multicast packets are delivered to all recipients of all
627 * matching multicast filters, with the exception that IP multicast filters
628 * will steal traffic from MAC multicast filters on a per-function basis.
631 * When disabled, multicast packets will always be delivered only to the
632 * recipients of the highest priority matching multicast filter.
633 * (Legacy behaviour.)
635 * The DEFAULT mode (which is the same as the tag not being present at all)
636 * is equivalent to ENABLED in production builds, and DISABLED in eftest
639 * This option is intended to provide run-time control over this feature
640 * while it is being stabilised and may be withdrawn at some point in the
641 * future; the new behaviour is intended to become the standard behaviour.
644 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
646 struct tlv_mcast_filter_chaining {
650 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
651 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
652 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
656 /* Pacer rate limit per PF */
657 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
659 struct tlv_rate_limit {
666 /* OCSD Enable/Disable
668 * This setting allows OCSD to be disabled. This is a requirement for HP
669 * servers to support PCI passthrough for virtualization.
671 * The DEFAULT mode (which is the same as the tag not being present) is
672 * equivalent to ENABLED.
674 * This option is not used by the MCFW, and is entirely handled by the various
675 * drivers that support OCSD, by reading the setting before they attempt
678 * bit0: OCSD Disabled/Enabled
681 #define TLV_TAG_OCSD (0x101C0000)
687 #define TLV_OCSD_DISABLED 0
688 #define TLV_OCSD_ENABLED 1 /* Default */
691 #endif /* CI_MGMT_TLV_LAYOUT_H */