2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
37 #include "efx_phy_ids.h"
43 #define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
47 #define EFX_FIELD_OFFSET(_type, _field) ((size_t) &(((_type *)0)->_field))
49 typedef enum efx_family_e {
53 EFX_FAMILY_HUNTINGTON,
57 extern __checkReturn int
61 __out efx_family_t *efp);
63 extern __checkReturn int
65 __in efsys_bar_t *esbp,
66 __out efx_family_t *efp);
68 #define EFX_PCI_VENID_SFC 0x1924
70 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
72 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
73 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
74 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
76 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
77 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
78 #define EFX_PCI_DEVID_HUNTINGTON 0x0913 /* SFL9122 PF */
79 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
81 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
82 #define EFX_PCI_DEVID_HUNTINGTON_VF 0x1913 /* SFL9122 VF */
83 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
106 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
107 extern __checkReturn uint32_t
109 __in uint32_t crc_init,
110 __in_ecount(length) uint8_t const *input,
114 /* Type prototypes */
116 typedef struct efx_rxq_s efx_rxq_t;
120 typedef struct efx_nic_s efx_nic_t;
122 #define EFX_NIC_FUNC_PRIMARY 0x00000001
123 #define EFX_NIC_FUNC_LINKCTRL 0x00000002
124 #define EFX_NIC_FUNC_TRUSTED 0x00000004
127 extern __checkReturn int
129 __in efx_family_t family,
130 __in efsys_identifier_t *esip,
131 __in efsys_bar_t *esbp,
132 __in efsys_lock_t *eslp,
133 __deref_out efx_nic_t **enpp);
135 extern __checkReturn int
137 __in efx_nic_t *enp);
139 #if EFSYS_OPT_PCIE_TUNE
141 extern __checkReturn int
144 unsigned int nlanes);
146 extern __checkReturn int
147 efx_nic_pcie_extended_sync(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_PCIE_TUNE */
152 extern __checkReturn int
154 __in efx_nic_t *enp);
156 extern __checkReturn int
158 __in efx_nic_t *enp);
162 extern __checkReturn int
163 efx_nic_register_test(
164 __in efx_nic_t *enp);
166 #endif /* EFSYS_OPT_DIAG */
170 __in efx_nic_t *enp);
174 __in efx_nic_t *enp);
178 __in efx_nic_t *enp);
182 #if EFSYS_OPT_HUNTINGTON
183 /* Huntington requires MCDIv2 commands */
184 #define WITH_MCDI_V2 1
187 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
189 typedef enum efx_mcdi_exception_e {
190 EFX_MCDI_EXCEPTION_MC_REBOOT,
191 EFX_MCDI_EXCEPTION_MC_BADASSERT,
192 } efx_mcdi_exception_t;
194 typedef struct efx_mcdi_transport_s {
196 efsys_mem_t *emt_dma_mem;
197 void (*emt_execute)(void *, efx_mcdi_req_t *);
198 void (*emt_ev_cpl)(void *);
199 void (*emt_exception)(void *, efx_mcdi_exception_t);
200 } efx_mcdi_transport_t;
202 extern __checkReturn int
205 __in const efx_mcdi_transport_t *mtp);
207 extern __checkReturn int
209 __in efx_nic_t *enp);
213 __in efx_nic_t *enp);
216 efx_mcdi_request_start(
218 __in efx_mcdi_req_t *emrp,
219 __in boolean_t ev_cpl);
221 extern __checkReturn boolean_t
222 efx_mcdi_request_poll(
223 __in efx_nic_t *enp);
225 extern __checkReturn boolean_t
226 efx_mcdi_request_abort(
227 __in efx_nic_t *enp);
231 __in efx_nic_t *enp);
233 #endif /* EFSYS_OPT_MCDI */
237 #define EFX_NINTR_FALCON 64
238 #define EFX_NINTR_SIENA 1024
240 typedef enum efx_intr_type_e {
241 EFX_INTR_INVALID = 0,
247 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
249 extern __checkReturn int
252 __in efx_intr_type_t type,
253 __in efsys_mem_t *esmp);
257 __in efx_nic_t *enp);
261 __in efx_nic_t *enp);
264 efx_intr_disable_unlocked(
265 __in efx_nic_t *enp);
267 #define EFX_INTR_NEVQS 32
269 extern __checkReturn int
272 __in unsigned int level);
275 efx_intr_status_line(
277 __out boolean_t *fatalp,
278 __out uint32_t *maskp);
281 efx_intr_status_message(
283 __in unsigned int message,
284 __out boolean_t *fatalp);
288 __in efx_nic_t *enp);
292 __in efx_nic_t *enp);
296 #if EFSYS_OPT_MAC_STATS
298 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
299 typedef enum efx_mac_stat_e {
302 EFX_MAC_RX_UNICST_PKTS,
303 EFX_MAC_RX_MULTICST_PKTS,
304 EFX_MAC_RX_BRDCST_PKTS,
305 EFX_MAC_RX_PAUSE_PKTS,
306 EFX_MAC_RX_LE_64_PKTS,
307 EFX_MAC_RX_65_TO_127_PKTS,
308 EFX_MAC_RX_128_TO_255_PKTS,
309 EFX_MAC_RX_256_TO_511_PKTS,
310 EFX_MAC_RX_512_TO_1023_PKTS,
311 EFX_MAC_RX_1024_TO_15XX_PKTS,
312 EFX_MAC_RX_GE_15XX_PKTS,
314 EFX_MAC_RX_FCS_ERRORS,
315 EFX_MAC_RX_DROP_EVENTS,
316 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
317 EFX_MAC_RX_SYMBOL_ERRORS,
318 EFX_MAC_RX_ALIGN_ERRORS,
319 EFX_MAC_RX_INTERNAL_ERRORS,
320 EFX_MAC_RX_JABBER_PKTS,
321 EFX_MAC_RX_LANE0_CHAR_ERR,
322 EFX_MAC_RX_LANE1_CHAR_ERR,
323 EFX_MAC_RX_LANE2_CHAR_ERR,
324 EFX_MAC_RX_LANE3_CHAR_ERR,
325 EFX_MAC_RX_LANE0_DISP_ERR,
326 EFX_MAC_RX_LANE1_DISP_ERR,
327 EFX_MAC_RX_LANE2_DISP_ERR,
328 EFX_MAC_RX_LANE3_DISP_ERR,
329 EFX_MAC_RX_MATCH_FAULT,
330 EFX_MAC_RX_NODESC_DROP_CNT,
333 EFX_MAC_TX_UNICST_PKTS,
334 EFX_MAC_TX_MULTICST_PKTS,
335 EFX_MAC_TX_BRDCST_PKTS,
336 EFX_MAC_TX_PAUSE_PKTS,
337 EFX_MAC_TX_LE_64_PKTS,
338 EFX_MAC_TX_65_TO_127_PKTS,
339 EFX_MAC_TX_128_TO_255_PKTS,
340 EFX_MAC_TX_256_TO_511_PKTS,
341 EFX_MAC_TX_512_TO_1023_PKTS,
342 EFX_MAC_TX_1024_TO_15XX_PKTS,
343 EFX_MAC_TX_GE_15XX_PKTS,
345 EFX_MAC_TX_SGL_COL_PKTS,
346 EFX_MAC_TX_MULT_COL_PKTS,
347 EFX_MAC_TX_EX_COL_PKTS,
348 EFX_MAC_TX_LATE_COL_PKTS,
350 EFX_MAC_TX_EX_DEF_PKTS,
351 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
352 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
353 EFX_MAC_PM_TRUNC_VFIFO_FULL,
354 EFX_MAC_PM_DISCARD_VFIFO_FULL,
355 EFX_MAC_PM_TRUNC_QBB,
356 EFX_MAC_PM_DISCARD_QBB,
357 EFX_MAC_PM_DISCARD_MAPPING,
358 EFX_MAC_RXDP_Q_DISABLED_PKTS,
359 EFX_MAC_RXDP_DI_DROPPED_PKTS,
360 EFX_MAC_RXDP_STREAMING_PKTS,
361 EFX_MAC_RXDP_HLB_FETCH,
362 EFX_MAC_RXDP_HLB_WAIT,
363 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
364 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
365 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
366 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
367 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
368 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
369 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
370 EFX_MAC_VADAPTER_RX_BAD_BYTES,
371 EFX_MAC_VADAPTER_RX_OVERFLOW,
372 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
373 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
374 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
375 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
376 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
377 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
378 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
379 EFX_MAC_VADAPTER_TX_BAD_BYTES,
380 EFX_MAC_VADAPTER_TX_OVERFLOW,
384 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
386 #endif /* EFSYS_OPT_MAC_STATS */
388 typedef enum efx_link_mode_e {
389 EFX_LINK_UNKNOWN = 0,
402 #define EFX_MAC_ADDR_LEN 6
404 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
406 #define EFX_MAC_MULTICAST_LIST_MAX 256
408 #define EFX_MAC_SDU_MAX 9202
410 #define EFX_MAC_PDU(_sdu) \
415 + /* bug16011 */ 16), \
418 #define EFX_MAC_PDU_MIN 60
419 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
421 extern __checkReturn int
426 extern __checkReturn int
431 extern __checkReturn int
434 __in boolean_t all_unicst,
435 __in boolean_t mulcst,
436 __in boolean_t all_mulcst,
437 __in boolean_t brdcst);
439 extern __checkReturn int
440 efx_mac_multicast_list_set(
442 __in_ecount(6*count) uint8_t const *addrs,
445 extern __checkReturn int
446 efx_mac_filter_default_rxq_set(
449 __in boolean_t using_rss);
452 efx_mac_filter_default_rxq_clear(
453 __in efx_nic_t *enp);
455 extern __checkReturn int
458 __in boolean_t enabled);
460 extern __checkReturn int
463 __out boolean_t *mac_upp);
465 #define EFX_FCNTL_RESPOND 0x00000001
466 #define EFX_FCNTL_GENERATE 0x00000002
468 extern __checkReturn int
471 __in unsigned int fcntl,
472 __in boolean_t autoneg);
477 __out unsigned int *fcntl_wantedp,
478 __out unsigned int *fcntl_linkp);
480 #define EFX_MAC_HASH_BITS (1 << 8)
482 extern __checkReturn int
484 __in efx_nic_t *enp);
488 __in efx_nic_t *enp);
490 extern __checkReturn int
493 __in boolean_t unicst,
494 __in boolean_t brdcst);
496 extern __checkReturn int
499 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
501 #if EFSYS_OPT_MCAST_FILTER_LIST
502 extern __checkReturn int
503 efx_pktfilter_mcast_list_set(
505 __in uint8_t const *addrs,
507 #endif /* EFSYS_OPT_MCAST_FILTER_LIST */
509 extern __checkReturn int
510 efx_pktfilter_mcast_all(
511 __in efx_nic_t *enp);
513 #if EFSYS_OPT_MAC_STATS
517 extern __checkReturn const char *
520 __in unsigned int id);
522 #endif /* EFSYS_OPT_NAMES */
524 #define EFX_MAC_STATS_SIZE 0x400
527 * Upload mac statistics supported by the hardware into the given buffer.
529 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
532 * The hardware will only DMA statistics that it understands (of course).
533 * Drivers should not make any assumptions about which statistics are
534 * supported, especially when the statistics are generated by firmware.
536 * Thus, drivers should zero this buffer before use, so that not-understood
537 * statistics read back as zero.
539 extern __checkReturn int
540 efx_mac_stats_upload(
542 __in efsys_mem_t *esmp);
544 extern __checkReturn int
545 efx_mac_stats_periodic(
547 __in efsys_mem_t *esmp,
548 __in uint16_t period_ms,
549 __in boolean_t events);
551 extern __checkReturn int
552 efx_mac_stats_update(
554 __in efsys_mem_t *esmp,
555 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
556 __out_opt uint32_t *generationp);
558 #endif /* EFSYS_OPT_MAC_STATS */
562 typedef enum efx_mon_type_e {
576 __in efx_nic_t *enp);
578 #endif /* EFSYS_OPT_NAMES */
580 extern __checkReturn int
582 __in efx_nic_t *enp);
584 #if EFSYS_OPT_MON_STATS
586 #define EFX_MON_STATS_PAGE_SIZE 0x100
587 #define EFX_MON_MASK_ELEMENT_SIZE 32
589 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
590 typedef enum efx_mon_stat_e {
597 EFX_MON_STAT_EXT_TEMP,
598 EFX_MON_STAT_INT_TEMP,
601 EFX_MON_STAT_INT_COOLING,
602 EFX_MON_STAT_EXT_COOLING,
610 EFX_MON_STAT_AOE_TEMP,
611 EFX_MON_STAT_PSU_AOE_TEMP,
612 EFX_MON_STAT_PSU_TEMP,
618 EFX_MON_STAT_VAOE_IN,
620 EFX_MON_STAT_IAOE_IN,
621 EFX_MON_STAT_NIC_POWER,
625 EFX_MON_STAT_0_9V_ADC,
626 EFX_MON_STAT_INT_TEMP2,
627 EFX_MON_STAT_VREG_TEMP,
628 EFX_MON_STAT_VREG_0_9V_TEMP,
629 EFX_MON_STAT_VREG_1_2V_TEMP,
630 EFX_MON_STAT_INT_VPTAT,
631 EFX_MON_STAT_INT_ADC_TEMP,
632 EFX_MON_STAT_EXT_VPTAT,
633 EFX_MON_STAT_EXT_ADC_TEMP,
634 EFX_MON_STAT_AMBIENT_TEMP,
635 EFX_MON_STAT_AIRFLOW,
636 EFX_MON_STAT_VDD08D_VSS08D_CSR,
637 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
638 EFX_MON_STAT_HOTPOINT_TEMP,
639 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
640 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
641 EFX_MON_STAT_MUM_VCC,
644 EFX_MON_STAT_0V9_A_TEMP,
647 EFX_MON_STAT_0V9_B_TEMP,
648 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
649 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
650 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
651 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
652 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
653 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
654 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
655 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
656 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
657 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
658 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
659 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
663 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
665 typedef enum efx_mon_stat_state_e {
666 EFX_MON_STAT_STATE_OK = 0,
667 EFX_MON_STAT_STATE_WARNING = 1,
668 EFX_MON_STAT_STATE_FATAL = 2,
669 EFX_MON_STAT_STATE_BROKEN = 3,
670 EFX_MON_STAT_STATE_NO_READING = 4,
671 } efx_mon_stat_state_t;
673 typedef struct efx_mon_stat_value_s {
676 } efx_mon_stat_value_t;
683 __in efx_mon_stat_t id);
685 #endif /* EFSYS_OPT_NAMES */
687 extern __checkReturn int
688 efx_mon_stats_update(
690 __in efsys_mem_t *esmp,
691 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
693 #endif /* EFSYS_OPT_MON_STATS */
697 __in efx_nic_t *enp);
701 #define PMA_PMD_MMD 1
706 #define CL22EXT_MMD 29
708 #define MAXMMD ((1 << 5) - 1)
710 extern __checkReturn int
712 __in efx_nic_t *enp);
714 #if EFSYS_OPT_PHY_LED_CONTROL
716 typedef enum efx_phy_led_mode_e {
717 EFX_PHY_LED_DEFAULT = 0,
722 } efx_phy_led_mode_t;
724 extern __checkReturn int
727 __in efx_phy_led_mode_t mode);
729 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
731 extern __checkReturn int
733 __in efx_nic_t *enp);
735 #if EFSYS_OPT_LOOPBACK
737 typedef enum efx_loopback_type_e {
738 EFX_LOOPBACK_OFF = 0,
739 EFX_LOOPBACK_DATA = 1,
740 EFX_LOOPBACK_GMAC = 2,
741 EFX_LOOPBACK_XGMII = 3,
742 EFX_LOOPBACK_XGXS = 4,
743 EFX_LOOPBACK_XAUI = 5,
744 EFX_LOOPBACK_GMII = 6,
745 EFX_LOOPBACK_SGMII = 7,
746 EFX_LOOPBACK_XGBR = 8,
747 EFX_LOOPBACK_XFI = 9,
748 EFX_LOOPBACK_XAUI_FAR = 10,
749 EFX_LOOPBACK_GMII_FAR = 11,
750 EFX_LOOPBACK_SGMII_FAR = 12,
751 EFX_LOOPBACK_XFI_FAR = 13,
752 EFX_LOOPBACK_GPHY = 14,
753 EFX_LOOPBACK_PHY_XS = 15,
754 EFX_LOOPBACK_PCS = 16,
755 EFX_LOOPBACK_PMA_PMD = 17,
756 EFX_LOOPBACK_XPORT = 18,
757 EFX_LOOPBACK_XGMII_WS = 19,
758 EFX_LOOPBACK_XAUI_WS = 20,
759 EFX_LOOPBACK_XAUI_WS_FAR = 21,
760 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
761 EFX_LOOPBACK_GMII_WS = 23,
762 EFX_LOOPBACK_XFI_WS = 24,
763 EFX_LOOPBACK_XFI_WS_FAR = 25,
764 EFX_LOOPBACK_PHYXS_WS = 26,
765 EFX_LOOPBACK_PMA_INT = 27,
766 EFX_LOOPBACK_SD_NEAR = 28,
767 EFX_LOOPBACK_SD_FAR = 29,
768 EFX_LOOPBACK_PMA_INT_WS = 30,
769 EFX_LOOPBACK_SD_FEP2_WS = 31,
770 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
771 EFX_LOOPBACK_SD_FEP_WS = 33,
772 EFX_LOOPBACK_SD_FES_WS = 34,
774 } efx_loopback_type_t;
776 typedef enum efx_loopback_kind_e {
777 EFX_LOOPBACK_KIND_OFF = 0,
778 EFX_LOOPBACK_KIND_ALL,
779 EFX_LOOPBACK_KIND_MAC,
780 EFX_LOOPBACK_KIND_PHY,
782 } efx_loopback_kind_t;
786 __in efx_loopback_kind_t loopback_kind,
787 __out efx_qword_t *maskp);
789 extern __checkReturn int
790 efx_port_loopback_set(
792 __in efx_link_mode_t link_mode,
793 __in efx_loopback_type_t type);
797 extern __checkReturn const char *
798 efx_loopback_type_name(
800 __in efx_loopback_type_t type);
802 #endif /* EFSYS_OPT_NAMES */
804 #endif /* EFSYS_OPT_LOOPBACK */
806 extern __checkReturn int
809 __out_opt efx_link_mode_t *link_modep);
813 __in efx_nic_t *enp);
815 typedef enum efx_phy_cap_type_e {
816 EFX_PHY_CAP_INVALID = 0,
823 EFX_PHY_CAP_10000FDX,
827 EFX_PHY_CAP_40000FDX,
829 } efx_phy_cap_type_t;
832 #define EFX_PHY_CAP_CURRENT 0x00000000
833 #define EFX_PHY_CAP_DEFAULT 0x00000001
834 #define EFX_PHY_CAP_PERM 0x00000002
840 __out uint32_t *maskp);
842 extern __checkReturn int
850 __out uint32_t *maskp);
852 extern __checkReturn int
855 __out uint32_t *ouip);
857 typedef enum efx_phy_media_type_e {
858 EFX_PHY_MEDIA_INVALID = 0,
863 EFX_PHY_MEDIA_SFP_PLUS,
864 EFX_PHY_MEDIA_BASE_T,
865 EFX_PHY_MEDIA_QSFP_PLUS,
867 } efx_phy_media_type_t;
869 /* Get the type of medium currently used. If the board has ports for
870 * modules, a module is present, and we recognise the media type of
871 * the module, then this will be the media type of the module.
872 * Otherwise it will be the media type of the port.
875 efx_phy_media_type_get(
877 __out efx_phy_media_type_t *typep);
879 #if EFSYS_OPT_PHY_STATS
881 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
882 typedef enum efx_phy_stat_e {
884 EFX_PHY_STAT_PMA_PMD_LINK_UP,
885 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
886 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
887 EFX_PHY_STAT_PMA_PMD_REV_A,
888 EFX_PHY_STAT_PMA_PMD_REV_B,
889 EFX_PHY_STAT_PMA_PMD_REV_C,
890 EFX_PHY_STAT_PMA_PMD_REV_D,
891 EFX_PHY_STAT_PCS_LINK_UP,
892 EFX_PHY_STAT_PCS_RX_FAULT,
893 EFX_PHY_STAT_PCS_TX_FAULT,
894 EFX_PHY_STAT_PCS_BER,
895 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
896 EFX_PHY_STAT_PHY_XS_LINK_UP,
897 EFX_PHY_STAT_PHY_XS_RX_FAULT,
898 EFX_PHY_STAT_PHY_XS_TX_FAULT,
899 EFX_PHY_STAT_PHY_XS_ALIGN,
900 EFX_PHY_STAT_PHY_XS_SYNC_A,
901 EFX_PHY_STAT_PHY_XS_SYNC_B,
902 EFX_PHY_STAT_PHY_XS_SYNC_C,
903 EFX_PHY_STAT_PHY_XS_SYNC_D,
904 EFX_PHY_STAT_AN_LINK_UP,
905 EFX_PHY_STAT_AN_MASTER,
906 EFX_PHY_STAT_AN_LOCAL_RX_OK,
907 EFX_PHY_STAT_AN_REMOTE_RX_OK,
908 EFX_PHY_STAT_CL22EXT_LINK_UP,
913 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
914 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
915 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
916 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
917 EFX_PHY_STAT_AN_COMPLETE,
918 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
919 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
920 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
921 EFX_PHY_STAT_PCS_FW_VERSION_0,
922 EFX_PHY_STAT_PCS_FW_VERSION_1,
923 EFX_PHY_STAT_PCS_FW_VERSION_2,
924 EFX_PHY_STAT_PCS_FW_VERSION_3,
925 EFX_PHY_STAT_PCS_FW_BUILD_YY,
926 EFX_PHY_STAT_PCS_FW_BUILD_MM,
927 EFX_PHY_STAT_PCS_FW_BUILD_DD,
928 EFX_PHY_STAT_PCS_OP_MODE,
932 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
939 __in efx_phy_stat_t stat);
941 #endif /* EFSYS_OPT_NAMES */
943 #define EFX_PHY_STATS_SIZE 0x100
945 extern __checkReturn int
946 efx_phy_stats_update(
948 __in efsys_mem_t *esmp,
949 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat);
951 #endif /* EFSYS_OPT_PHY_STATS */
953 #if EFSYS_OPT_PHY_PROPS
960 __in unsigned int id);
962 #endif /* EFSYS_OPT_NAMES */
964 #define EFX_PHY_PROP_DEFAULT 0x00000001
966 extern __checkReturn int
969 __in unsigned int id,
971 __out uint32_t *valp);
973 extern __checkReturn int
976 __in unsigned int id,
979 #endif /* EFSYS_OPT_PHY_PROPS */
983 typedef enum efx_bist_type_e {
984 EFX_BIST_TYPE_UNKNOWN,
985 EFX_BIST_TYPE_PHY_NORMAL,
986 EFX_BIST_TYPE_PHY_CABLE_SHORT,
987 EFX_BIST_TYPE_PHY_CABLE_LONG,
988 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
989 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
990 EFX_BIST_TYPE_REG, /* Test the register memories */
991 EFX_BIST_TYPE_NTYPES,
994 typedef enum efx_bist_result_e {
995 EFX_BIST_RESULT_UNKNOWN,
996 EFX_BIST_RESULT_RUNNING,
997 EFX_BIST_RESULT_PASSED,
998 EFX_BIST_RESULT_FAILED,
1001 typedef enum efx_phy_cable_status_e {
1002 EFX_PHY_CABLE_STATUS_OK,
1003 EFX_PHY_CABLE_STATUS_INVALID,
1004 EFX_PHY_CABLE_STATUS_OPEN,
1005 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1006 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1007 EFX_PHY_CABLE_STATUS_BUSY,
1008 } efx_phy_cable_status_t;
1010 typedef enum efx_bist_value_e {
1011 EFX_BIST_PHY_CABLE_LENGTH_A,
1012 EFX_BIST_PHY_CABLE_LENGTH_B,
1013 EFX_BIST_PHY_CABLE_LENGTH_C,
1014 EFX_BIST_PHY_CABLE_LENGTH_D,
1015 EFX_BIST_PHY_CABLE_STATUS_A,
1016 EFX_BIST_PHY_CABLE_STATUS_B,
1017 EFX_BIST_PHY_CABLE_STATUS_C,
1018 EFX_BIST_PHY_CABLE_STATUS_D,
1019 EFX_BIST_FAULT_CODE,
1020 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1025 EFX_BIST_MEM_EXPECT,
1026 EFX_BIST_MEM_ACTUAL,
1028 EFX_BIST_MEM_ECC_PARITY,
1029 EFX_BIST_MEM_ECC_FATAL,
1033 extern __checkReturn int
1034 efx_bist_enable_offline(
1035 __in efx_nic_t *enp);
1037 extern __checkReturn int
1039 __in efx_nic_t *enp,
1040 __in efx_bist_type_t type);
1042 extern __checkReturn int
1044 __in efx_nic_t *enp,
1045 __in efx_bist_type_t type,
1046 __out efx_bist_result_t *resultp,
1047 __out_opt uint32_t *value_maskp,
1048 __out_ecount_opt(count) unsigned long *valuesp,
1053 __in efx_nic_t *enp,
1054 __in efx_bist_type_t type);
1056 #endif /* EFSYS_OPT_BIST */
1058 #define EFX_FEATURE_IPV6 0x00000001
1059 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1060 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1061 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1062 #define EFX_FEATURE_WOL 0x00000010
1063 #define EFX_FEATURE_MCDI 0x00000020
1064 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1065 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1066 #define EFX_FEATURE_TURBO 0x00000100
1067 #define EFX_FEATURE_MCDI_DMA 0x00000200
1068 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1069 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1070 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1072 typedef struct efx_nic_cfg_s {
1073 uint32_t enc_board_type;
1074 uint32_t enc_phy_type;
1076 char enc_phy_name[21];
1078 char enc_phy_revision[21];
1079 efx_mon_type_t enc_mon_type;
1080 #if EFSYS_OPT_MON_STATS
1081 uint32_t enc_mon_stat_dma_buf_size;
1082 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1084 unsigned int enc_features;
1085 uint8_t enc_mac_addr[6];
1086 uint8_t enc_port; /* PHY port number */
1087 uint32_t enc_func_flags;
1088 uint32_t enc_intr_vec_base;
1089 uint32_t enc_intr_limit;
1090 uint32_t enc_evq_limit;
1091 uint32_t enc_txq_limit;
1092 uint32_t enc_rxq_limit;
1093 uint32_t enc_buftbl_limit;
1094 uint32_t enc_piobuf_limit;
1095 uint32_t enc_piobuf_size;
1096 uint32_t enc_evq_timer_quantum_ns;
1097 uint32_t enc_evq_timer_max_us;
1098 uint32_t enc_clk_mult;
1099 uint32_t enc_rx_prefix_size;
1100 uint32_t enc_rx_buf_align_start;
1101 uint32_t enc_rx_buf_align_end;
1102 #if EFSYS_OPT_LOOPBACK
1103 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1104 #endif /* EFSYS_OPT_LOOPBACK */
1105 #if EFSYS_OPT_PHY_FLAGS
1106 uint32_t enc_phy_flags_mask;
1107 #endif /* EFSYS_OPT_PHY_FLAGS */
1108 #if EFSYS_OPT_PHY_LED_CONTROL
1109 uint32_t enc_led_mask;
1110 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1111 #if EFSYS_OPT_PHY_STATS
1112 uint64_t enc_phy_stat_mask;
1113 #endif /* EFSYS_OPT_PHY_STATS */
1114 #if EFSYS_OPT_PHY_PROPS
1115 unsigned int enc_phy_nprops;
1116 #endif /* EFSYS_OPT_PHY_PROPS */
1118 uint8_t enc_mcdi_mdio_channel;
1119 #if EFSYS_OPT_PHY_STATS
1120 uint32_t enc_mcdi_phy_stat_mask;
1121 #endif /* EFSYS_OPT_PHY_STATS */
1122 #endif /* EFSYS_OPT_SIENA */
1123 #if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
1124 #if EFSYS_OPT_MON_STATS
1125 uint32_t *enc_mcdi_sensor_maskp;
1126 uint32_t enc_mcdi_sensor_mask_size;
1127 #endif /* EFSYS_OPT_MON_STATS */
1128 #endif /* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
1130 uint32_t enc_bist_mask;
1131 #endif /* EFSYS_OPT_BIST */
1132 #if EFSYS_OPT_HUNTINGTON
1135 uint32_t enc_privilege_mask;
1136 #endif /* EFSYS_OPT_HUNTINGTON */
1137 boolean_t enc_bug26807_workaround;
1138 boolean_t enc_bug35388_workaround;
1139 boolean_t enc_bug41750_workaround;
1140 boolean_t enc_rx_batching_enabled;
1141 /* Maximum number of descriptors completed in an rx event. */
1142 uint32_t enc_rx_batch_max;
1143 /* Number of rx descriptors the hardware requires for a push. */
1144 uint32_t enc_rx_push_align;
1146 * Maximum number of bytes into the packet the TCP header can start for
1147 * the hardware to apply TSO packet edits.
1149 uint32_t enc_tx_tso_tcp_header_offset_limit;
1150 boolean_t enc_fw_assisted_tso_enabled;
1151 boolean_t enc_hw_tx_insert_vlan_enabled;
1152 /* Datapath firmware vadapter/vport/vswitch support */
1153 boolean_t enc_datapath_cap_evb;
1154 /* External port identifier */
1155 uint8_t enc_external_port;
1158 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1159 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1161 #define EFX_PCI_FUNCTION(_encp) \
1162 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1164 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1166 extern const efx_nic_cfg_t *
1168 __in efx_nic_t *enp);
1170 /* Driver resource limits (minimum required/maximum usable). */
1171 typedef struct efx_drv_limits_s
1173 uint32_t edl_min_evq_count;
1174 uint32_t edl_max_evq_count;
1176 uint32_t edl_min_rxq_count;
1177 uint32_t edl_max_rxq_count;
1179 uint32_t edl_min_txq_count;
1180 uint32_t edl_max_txq_count;
1182 /* PIO blocks (sub-allocated from piobuf) */
1183 uint32_t edl_min_pio_alloc_size;
1184 uint32_t edl_max_pio_alloc_count;
1187 extern __checkReturn int
1188 efx_nic_set_drv_limits(
1189 __inout efx_nic_t *enp,
1190 __in efx_drv_limits_t *edlp);
1192 typedef enum efx_nic_region_e {
1193 EFX_REGION_VI, /* Memory BAR UC mapping */
1194 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1197 extern __checkReturn int
1198 efx_nic_get_bar_region(
1199 __in efx_nic_t *enp,
1200 __in efx_nic_region_t region,
1201 __out uint32_t *offsetp,
1202 __out size_t *sizep);
1204 extern __checkReturn int
1205 efx_nic_get_vi_pool(
1206 __in efx_nic_t *enp,
1207 __out uint32_t *evq_countp,
1208 __out uint32_t *rxq_countp,
1209 __out uint32_t *txq_countp);
1214 typedef enum efx_vpd_tag_e {
1221 typedef uint16_t efx_vpd_keyword_t;
1223 typedef struct efx_vpd_value_s {
1224 efx_vpd_tag_t evv_tag;
1225 efx_vpd_keyword_t evv_keyword;
1227 uint8_t evv_value[0x100];
1231 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1233 extern __checkReturn int
1235 __in efx_nic_t *enp);
1237 extern __checkReturn int
1239 __in efx_nic_t *enp,
1240 __out size_t *sizep);
1242 extern __checkReturn int
1244 __in efx_nic_t *enp,
1245 __out_bcount(size) caddr_t data,
1248 extern __checkReturn int
1250 __in efx_nic_t *enp,
1251 __in_bcount(size) caddr_t data,
1254 extern __checkReturn int
1256 __in efx_nic_t *enp,
1257 __in_bcount(size) caddr_t data,
1260 extern __checkReturn int
1262 __in efx_nic_t *enp,
1263 __in_bcount(size) caddr_t data,
1265 __inout efx_vpd_value_t *evvp);
1267 extern __checkReturn int
1269 __in efx_nic_t *enp,
1270 __inout_bcount(size) caddr_t data,
1272 __in efx_vpd_value_t *evvp);
1274 extern __checkReturn int
1276 __in efx_nic_t *enp,
1277 __inout_bcount(size) caddr_t data,
1279 __out efx_vpd_value_t *evvp,
1280 __inout unsigned int *contp);
1282 extern __checkReturn int
1284 __in efx_nic_t *enp,
1285 __in_bcount(size) caddr_t data,
1290 __in efx_nic_t *enp);
1292 #endif /* EFSYS_OPT_VPD */
1298 typedef enum efx_nvram_type_e {
1299 EFX_NVRAM_INVALID = 0,
1301 EFX_NVRAM_BOOTROM_CFG,
1302 EFX_NVRAM_MC_FIRMWARE,
1303 EFX_NVRAM_MC_GOLDEN,
1309 EFX_NVRAM_FPGA_BACKUP,
1310 EFX_NVRAM_DYNAMIC_CFG,
1314 extern __checkReturn int
1316 __in efx_nic_t *enp);
1320 extern __checkReturn int
1322 __in efx_nic_t *enp);
1324 #endif /* EFSYS_OPT_DIAG */
1326 extern __checkReturn int
1328 __in efx_nic_t *enp,
1329 __in efx_nvram_type_t type,
1330 __out size_t *sizep);
1332 extern __checkReturn int
1334 __in efx_nic_t *enp,
1335 __in efx_nvram_type_t type,
1336 __out_opt size_t *pref_chunkp);
1339 efx_nvram_rw_finish(
1340 __in efx_nic_t *enp,
1341 __in efx_nvram_type_t type);
1343 extern __checkReturn int
1344 efx_nvram_get_version(
1345 __in efx_nic_t *enp,
1346 __in efx_nvram_type_t type,
1347 __out uint32_t *subtypep,
1348 __out_ecount(4) uint16_t version[4]);
1350 extern __checkReturn int
1351 efx_nvram_read_chunk(
1352 __in efx_nic_t *enp,
1353 __in efx_nvram_type_t type,
1354 __in unsigned int offset,
1355 __out_bcount(size) caddr_t data,
1358 extern __checkReturn int
1359 efx_nvram_set_version(
1360 __in efx_nic_t *enp,
1361 __in efx_nvram_type_t type,
1362 __in_ecount(4) uint16_t version[4]);
1364 /* Validate contents of TLV formatted partition */
1365 extern __checkReturn int
1366 efx_nvram_tlv_validate(
1367 __in efx_nic_t *enp,
1368 __in uint32_t partn,
1369 __in_bcount(partn_size) caddr_t partn_data,
1370 __in size_t partn_size);
1372 extern __checkReturn int
1374 __in efx_nic_t *enp,
1375 __in efx_nvram_type_t type);
1377 extern __checkReturn int
1378 efx_nvram_write_chunk(
1379 __in efx_nic_t *enp,
1380 __in efx_nvram_type_t type,
1381 __in unsigned int offset,
1382 __in_bcount(size) caddr_t data,
1387 __in efx_nic_t *enp);
1389 #endif /* EFSYS_OPT_NVRAM */
1391 #if EFSYS_OPT_BOOTCFG
1395 __in efx_nic_t *enp,
1396 __out_bcount(size) caddr_t data,
1401 __in efx_nic_t *enp,
1402 __in_bcount(size) caddr_t data,
1405 #endif /* EFSYS_OPT_BOOTCFG */
1409 typedef enum efx_wol_type_e {
1410 EFX_WOL_TYPE_INVALID,
1412 EFX_WOL_TYPE_BITMAP,
1417 typedef enum efx_lightsout_offload_type_e {
1418 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1419 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1420 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1421 } efx_lightsout_offload_type_t;
1423 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1424 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1426 typedef union efx_wol_param_u {
1428 uint8_t mac_addr[6];
1431 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1432 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1437 typedef union efx_lightsout_offload_param_u {
1439 uint8_t mac_addr[6];
1443 uint8_t mac_addr[6];
1444 uint32_t solicited_node[4];
1447 } efx_lightsout_offload_param_t;
1449 extern __checkReturn int
1451 __in efx_nic_t *enp);
1453 extern __checkReturn int
1454 efx_wol_filter_clear(
1455 __in efx_nic_t *enp);
1457 extern __checkReturn int
1459 __in efx_nic_t *enp,
1460 __in efx_wol_type_t type,
1461 __in efx_wol_param_t *paramp,
1462 __out uint32_t *filter_idp);
1464 extern __checkReturn int
1465 efx_wol_filter_remove(
1466 __in efx_nic_t *enp,
1467 __in uint32_t filter_id);
1469 extern __checkReturn int
1470 efx_lightsout_offload_add(
1471 __in efx_nic_t *enp,
1472 __in efx_lightsout_offload_type_t type,
1473 __in efx_lightsout_offload_param_t *paramp,
1474 __out uint32_t *filter_idp);
1476 extern __checkReturn int
1477 efx_lightsout_offload_remove(
1478 __in efx_nic_t *enp,
1479 __in efx_lightsout_offload_type_t type,
1480 __in uint32_t filter_id);
1484 __in efx_nic_t *enp);
1486 #endif /* EFSYS_OPT_WOL */
1490 typedef enum efx_pattern_type_t {
1491 EFX_PATTERN_BYTE_INCREMENT = 0,
1492 EFX_PATTERN_ALL_THE_SAME,
1493 EFX_PATTERN_BIT_ALTERNATE,
1494 EFX_PATTERN_BYTE_ALTERNATE,
1495 EFX_PATTERN_BYTE_CHANGING,
1496 EFX_PATTERN_BIT_SWEEP,
1498 } efx_pattern_type_t;
1501 (*efx_sram_pattern_fn_t)(
1503 __in boolean_t negate,
1504 __out efx_qword_t *eqp);
1506 extern __checkReturn int
1508 __in efx_nic_t *enp,
1509 __in efx_pattern_type_t type);
1511 #endif /* EFSYS_OPT_DIAG */
1513 extern __checkReturn int
1514 efx_sram_buf_tbl_set(
1515 __in efx_nic_t *enp,
1517 __in efsys_mem_t *esmp,
1521 efx_sram_buf_tbl_clear(
1522 __in efx_nic_t *enp,
1526 #define EFX_BUF_TBL_SIZE 0x20000
1528 #define EFX_BUF_SIZE 4096
1532 typedef struct efx_evq_s efx_evq_t;
1534 #if EFSYS_OPT_QSTATS
1536 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1537 typedef enum efx_ev_qstat_e {
1543 EV_RX_PAUSE_FRM_ERR,
1544 EV_RX_BUF_OWNER_ID_ERR,
1545 EV_RX_IPV4_HDR_CHKSUM_ERR,
1546 EV_RX_TCP_UDP_CHKSUM_ERR,
1550 EV_RX_MCAST_HASH_MATCH,
1567 EV_DRIVER_SRM_UPD_DONE,
1568 EV_DRIVER_TX_DESCQ_FLS_DONE,
1569 EV_DRIVER_RX_DESCQ_FLS_DONE,
1570 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1571 EV_DRIVER_RX_DSC_ERROR,
1572 EV_DRIVER_TX_DSC_ERROR,
1578 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1580 #endif /* EFSYS_OPT_QSTATS */
1582 extern __checkReturn int
1584 __in efx_nic_t *enp);
1588 __in efx_nic_t *enp);
1590 #define EFX_EVQ_MAXNEVS 32768
1591 #define EFX_EVQ_MINNEVS 512
1593 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1594 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1596 extern __checkReturn int
1598 __in efx_nic_t *enp,
1599 __in unsigned int index,
1600 __in efsys_mem_t *esmp,
1603 __deref_out efx_evq_t **eepp);
1607 __in efx_evq_t *eep,
1608 __in uint16_t data);
1610 typedef __checkReturn boolean_t
1611 (*efx_initialized_ev_t)(
1612 __in_opt void *arg);
1614 #define EFX_PKT_UNICAST 0x0004
1615 #define EFX_PKT_START 0x0008
1617 #define EFX_PKT_VLAN_TAGGED 0x0010
1618 #define EFX_CKSUM_TCPUDP 0x0020
1619 #define EFX_CKSUM_IPV4 0x0040
1620 #define EFX_PKT_CONT 0x0080
1622 #define EFX_CHECK_VLAN 0x0100
1623 #define EFX_PKT_TCP 0x0200
1624 #define EFX_PKT_UDP 0x0400
1625 #define EFX_PKT_IPV4 0x0800
1627 #define EFX_PKT_IPV6 0x1000
1628 #define EFX_PKT_PREFIX_LEN 0x2000
1629 #define EFX_ADDR_MISMATCH 0x4000
1630 #define EFX_DISCARD 0x8000
1632 #define EFX_EV_RX_NLABELS 32
1633 #define EFX_EV_TX_NLABELS 32
1635 typedef __checkReturn boolean_t
1638 __in uint32_t label,
1641 __in uint16_t flags);
1643 typedef __checkReturn boolean_t
1646 __in uint32_t label,
1649 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1650 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1651 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1652 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1653 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1654 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1655 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1656 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1657 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1659 typedef __checkReturn boolean_t
1660 (*efx_exception_ev_t)(
1662 __in uint32_t label,
1663 __in uint32_t data);
1665 typedef __checkReturn boolean_t
1666 (*efx_rxq_flush_done_ev_t)(
1668 __in uint32_t rxq_index);
1670 typedef __checkReturn boolean_t
1671 (*efx_rxq_flush_failed_ev_t)(
1673 __in uint32_t rxq_index);
1675 typedef __checkReturn boolean_t
1676 (*efx_txq_flush_done_ev_t)(
1678 __in uint32_t txq_index);
1680 typedef __checkReturn boolean_t
1681 (*efx_software_ev_t)(
1683 __in uint16_t magic);
1685 typedef __checkReturn boolean_t
1688 __in uint32_t code);
1690 #define EFX_SRAM_CLEAR 0
1691 #define EFX_SRAM_UPDATE 1
1692 #define EFX_SRAM_ILLEGAL_CLEAR 2
1694 typedef __checkReturn boolean_t
1695 (*efx_wake_up_ev_t)(
1697 __in uint32_t label);
1699 typedef __checkReturn boolean_t
1702 __in uint32_t label);
1704 typedef __checkReturn boolean_t
1705 (*efx_link_change_ev_t)(
1707 __in efx_link_mode_t link_mode);
1709 #if EFSYS_OPT_MON_STATS
1711 typedef __checkReturn boolean_t
1712 (*efx_monitor_ev_t)(
1714 __in efx_mon_stat_t id,
1715 __in efx_mon_stat_value_t value);
1717 #endif /* EFSYS_OPT_MON_STATS */
1719 #if EFSYS_OPT_MAC_STATS
1721 typedef __checkReturn boolean_t
1722 (*efx_mac_stats_ev_t)(
1724 __in uint32_t generation
1727 #endif /* EFSYS_OPT_MAC_STATS */
1729 typedef struct efx_ev_callbacks_s {
1730 efx_initialized_ev_t eec_initialized;
1733 efx_exception_ev_t eec_exception;
1734 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1735 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1736 efx_txq_flush_done_ev_t eec_txq_flush_done;
1737 efx_software_ev_t eec_software;
1738 efx_sram_ev_t eec_sram;
1739 efx_wake_up_ev_t eec_wake_up;
1740 efx_timer_ev_t eec_timer;
1741 efx_link_change_ev_t eec_link_change;
1742 #if EFSYS_OPT_MON_STATS
1743 efx_monitor_ev_t eec_monitor;
1744 #endif /* EFSYS_OPT_MON_STATS */
1745 #if EFSYS_OPT_MAC_STATS
1746 efx_mac_stats_ev_t eec_mac_stats;
1747 #endif /* EFSYS_OPT_MAC_STATS */
1748 } efx_ev_callbacks_t;
1750 extern __checkReturn boolean_t
1752 __in efx_evq_t *eep,
1753 __in unsigned int count);
1755 #if EFSYS_OPT_EV_PREFETCH
1759 __in efx_evq_t *eep,
1760 __in unsigned int count);
1762 #endif /* EFSYS_OPT_EV_PREFETCH */
1766 __in efx_evq_t *eep,
1767 __inout unsigned int *countp,
1768 __in const efx_ev_callbacks_t *eecp,
1769 __in_opt void *arg);
1771 extern __checkReturn int
1773 __in efx_evq_t *eep,
1774 __in unsigned int us);
1776 extern __checkReturn int
1778 __in efx_evq_t *eep,
1779 __in unsigned int count);
1781 #if EFSYS_OPT_QSTATS
1787 __in efx_nic_t *enp,
1788 __in unsigned int id);
1790 #endif /* EFSYS_OPT_NAMES */
1793 efx_ev_qstats_update(
1794 __in efx_evq_t *eep,
1795 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1797 #endif /* EFSYS_OPT_QSTATS */
1801 __in efx_evq_t *eep);
1805 extern __checkReturn int
1807 __inout efx_nic_t *enp);
1811 __in efx_nic_t *enp);
1813 #if EFSYS_OPT_RX_HDR_SPLIT
1815 efx_rx_hdr_split_enable(
1816 __in efx_nic_t *enp,
1817 __in unsigned int hdr_buf_size,
1818 __in unsigned int pld_buf_size);
1820 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1822 #if EFSYS_OPT_RX_SCATTER
1824 efx_rx_scatter_enable(
1825 __in efx_nic_t *enp,
1826 __in unsigned int buf_size);
1827 #endif /* EFSYS_OPT_RX_SCATTER */
1829 #if EFSYS_OPT_RX_SCALE
1831 typedef enum efx_rx_hash_alg_e {
1832 EFX_RX_HASHALG_LFSR = 0,
1833 EFX_RX_HASHALG_TOEPLITZ
1834 } efx_rx_hash_alg_t;
1836 typedef enum efx_rx_hash_type_e {
1837 EFX_RX_HASH_IPV4 = 0,
1838 EFX_RX_HASH_TCPIPV4,
1840 EFX_RX_HASH_TCPIPV6,
1841 } efx_rx_hash_type_t;
1843 typedef enum efx_rx_hash_support_e {
1844 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1845 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1846 } efx_rx_hash_support_t;
1848 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1849 #define EFX_MAXRSS 64 /* RX indirection entry range */
1850 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1852 typedef enum efx_rx_scale_support_e {
1853 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1854 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1855 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1856 } efx_rx_scale_support_t;
1858 extern __checkReturn int
1859 efx_rx_hash_support_get(
1860 __in efx_nic_t *enp,
1861 __out efx_rx_hash_support_t *supportp);
1864 extern __checkReturn int
1865 efx_rx_scale_support_get(
1866 __in efx_nic_t *enp,
1867 __out efx_rx_scale_support_t *supportp);
1869 extern __checkReturn int
1870 efx_rx_scale_mode_set(
1871 __in efx_nic_t *enp,
1872 __in efx_rx_hash_alg_t alg,
1873 __in efx_rx_hash_type_t type,
1874 __in boolean_t insert);
1876 extern __checkReturn int
1877 efx_rx_scale_tbl_set(
1878 __in efx_nic_t *enp,
1879 __in_ecount(n) unsigned int *table,
1882 extern __checkReturn int
1883 efx_rx_scale_key_set(
1884 __in efx_nic_t *enp,
1885 __in_ecount(n) uint8_t *key,
1889 efx_psuedo_hdr_hash_get(
1890 __in efx_nic_t *enp,
1891 __in efx_rx_hash_alg_t func,
1892 __in uint8_t *buffer);
1894 #endif /* EFSYS_OPT_RX_SCALE */
1896 extern __checkReturn int
1897 efx_psuedo_hdr_pkt_length_get(
1898 __in efx_nic_t *enp,
1899 __in uint8_t *buffer,
1900 __out uint16_t *pkt_lengthp);
1902 #define EFX_RXQ_MAXNDESCS 4096
1903 #define EFX_RXQ_MINNDESCS 512
1905 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1906 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1907 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1908 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1910 typedef enum efx_rxq_type_e {
1911 EFX_RXQ_TYPE_DEFAULT,
1912 EFX_RXQ_TYPE_SPLIT_HEADER,
1913 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1914 EFX_RXQ_TYPE_SCATTER,
1918 extern __checkReturn int
1920 __in efx_nic_t *enp,
1921 __in unsigned int index,
1922 __in unsigned int label,
1923 __in efx_rxq_type_t type,
1924 __in efsys_mem_t *esmp,
1927 __in efx_evq_t *eep,
1928 __deref_out efx_rxq_t **erpp);
1930 typedef struct efx_buffer_s {
1931 efsys_dma_addr_t eb_addr;
1936 typedef struct efx_desc_s {
1942 __in efx_rxq_t *erp,
1943 __in_ecount(n) efsys_dma_addr_t *addrp,
1945 __in unsigned int n,
1946 __in unsigned int completed,
1947 __in unsigned int added);
1951 __in efx_rxq_t *erp,
1952 __in unsigned int added,
1953 __inout unsigned int *pushedp);
1955 extern __checkReturn int
1957 __in efx_rxq_t *erp);
1961 __in efx_rxq_t *erp);
1965 __in efx_rxq_t *erp);
1969 typedef struct efx_txq_s efx_txq_t;
1971 #if EFSYS_OPT_QSTATS
1973 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1974 typedef enum efx_tx_qstat_e {
1980 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1982 #endif /* EFSYS_OPT_QSTATS */
1984 extern __checkReturn int
1986 __in efx_nic_t *enp);
1990 __in efx_nic_t *enp);
1992 #define EFX_BUG35388_WORKAROUND(_encp) \
1993 (((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1995 #define EFX_TXQ_MAXNDESCS(_encp) \
1996 ((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1998 #define EFX_TXQ_MINNDESCS 512
2000 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2001 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2002 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2003 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2005 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2007 extern __checkReturn int
2009 __in efx_nic_t *enp,
2010 __in unsigned int index,
2011 __in unsigned int label,
2012 __in efsys_mem_t *esmp,
2015 __in uint16_t flags,
2016 __in efx_evq_t *eep,
2017 __deref_out efx_txq_t **etpp,
2018 __out unsigned int *addedp);
2020 extern __checkReturn int
2022 __in efx_txq_t *etp,
2023 __in_ecount(n) efx_buffer_t *eb,
2024 __in unsigned int n,
2025 __in unsigned int completed,
2026 __inout unsigned int *addedp);
2028 extern __checkReturn int
2030 __in efx_txq_t *etp,
2031 __in unsigned int ns);
2035 __in efx_txq_t *etp,
2036 __in unsigned int added,
2037 __in unsigned int pushed);
2039 extern __checkReturn int
2041 __in efx_txq_t *etp);
2045 __in efx_txq_t *etp);
2047 extern __checkReturn int
2049 __in efx_txq_t *etp);
2052 efx_tx_qpio_disable(
2053 __in efx_txq_t *etp);
2055 extern __checkReturn int
2057 __in efx_txq_t *etp,
2058 __in_ecount(buf_length) uint8_t *buffer,
2059 __in size_t buf_length,
2060 __in size_t pio_buf_offset);
2062 extern __checkReturn int
2064 __in efx_txq_t *etp,
2065 __in size_t pkt_length,
2066 __in unsigned int completed,
2067 __inout unsigned int *addedp);
2069 extern __checkReturn int
2071 __in efx_txq_t *etp,
2072 __in_ecount(n) efx_desc_t *ed,
2073 __in unsigned int n,
2074 __in unsigned int completed,
2075 __inout unsigned int *addedp);
2078 efx_tx_qdesc_dma_create(
2079 __in efx_txq_t *etp,
2080 __in efsys_dma_addr_t addr,
2083 __out efx_desc_t *edp);
2086 efx_tx_qdesc_tso_create(
2087 __in efx_txq_t *etp,
2088 __in uint16_t ipv4_id,
2089 __in uint32_t tcp_seq,
2090 __in uint8_t tcp_flags,
2091 __out efx_desc_t *edp);
2094 efx_tx_qdesc_vlantci_create(
2095 __in efx_txq_t *etp,
2097 __out efx_desc_t *edp);
2099 #if EFSYS_OPT_QSTATS
2105 __in efx_nic_t *etp,
2106 __in unsigned int id);
2108 #endif /* EFSYS_OPT_NAMES */
2111 efx_tx_qstats_update(
2112 __in efx_txq_t *etp,
2113 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2115 #endif /* EFSYS_OPT_QSTATS */
2119 __in efx_txq_t *etp);
2124 #if EFSYS_OPT_FILTER
2126 #define EFX_ETHER_TYPE_IPV4 0x0800
2127 #define EFX_ETHER_TYPE_IPV6 0x86DD
2129 #define EFX_IPPROTO_TCP 6
2130 #define EFX_IPPROTO_UDP 17
2132 typedef enum efx_filter_flag_e {
2133 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
2134 * multiple queues */
2135 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
2136 EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04, /* Override an automatic filter
2137 * (priority EFX_FILTER_PRI_AUTO).
2138 * May only be set by the filter
2139 * implementation for each type.
2140 * A removal request will
2141 * restore the automatic filter
2143 EFX_FILTER_FLAG_RX = 0x08, /* Filter is for RX */
2144 EFX_FILTER_FLAG_TX = 0x10, /* Filter is for TX */
2145 } efx_filter_flag_t;
2147 typedef enum efx_filter_match_flags_e {
2148 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2150 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2152 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2153 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2154 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2155 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2156 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2157 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2158 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2159 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2161 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2162 * I/G bit. Used for RX default
2163 * unicast and multicast/
2164 * broadcast filters. */
2165 } efx_filter_match_flags_t;
2167 typedef enum efx_filter_priority_s {
2168 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2169 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2170 * address list or hardware
2171 * requirements. This may only be used
2172 * by the filter implementation for
2174 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2175 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2176 * client (e.g. SR-IOV, HyperV VMQ etc.)
2178 } efx_filter_priority_t;
2181 * FIXME: All these fields are assumed to be in little-endian byte order.
2182 * It may be better for some to be big-endian. See bug42804.
2185 typedef struct efx_filter_spec_s {
2186 uint32_t efs_match_flags:12;
2187 uint32_t efs_priority:2;
2188 uint32_t efs_flags:6;
2189 uint32_t efs_dmaq_id:12;
2190 uint32_t efs_rss_context;
2191 uint16_t efs_outer_vid;
2192 uint16_t efs_inner_vid;
2193 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2194 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2195 uint16_t efs_ether_type;
2196 uint8_t efs_ip_proto;
2197 uint16_t efs_loc_port;
2198 uint16_t efs_rem_port;
2199 efx_oword_t efs_rem_host;
2200 efx_oword_t efs_loc_host;
2201 } efx_filter_spec_t;
2204 /* Default values for use in filter specifications */
2205 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2206 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2207 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2209 extern __checkReturn int
2211 __in efx_nic_t *enp);
2215 __in efx_nic_t *enp);
2217 extern __checkReturn int
2219 __in efx_nic_t *enp,
2220 __inout efx_filter_spec_t *spec);
2222 extern __checkReturn int
2224 __in efx_nic_t *enp,
2225 __inout efx_filter_spec_t *spec);
2227 extern __checkReturn int
2229 __in efx_nic_t *enp);
2231 extern __checkReturn int
2232 efx_filter_supported_filters(
2233 __in efx_nic_t *enp,
2234 __out uint32_t *list,
2235 __out size_t *length);
2238 efx_filter_spec_init_rx(
2239 __inout efx_filter_spec_t *spec,
2240 __in efx_filter_priority_t priority,
2241 __in efx_filter_flag_t flags,
2242 __in efx_rxq_t *erp);
2245 efx_filter_spec_init_tx(
2246 __inout efx_filter_spec_t *spec,
2247 __in efx_txq_t *etp);
2249 extern __checkReturn int
2250 efx_filter_spec_set_ipv4_local(
2251 __inout efx_filter_spec_t *spec,
2254 __in uint16_t port);
2256 extern __checkReturn int
2257 efx_filter_spec_set_ipv4_full(
2258 __inout efx_filter_spec_t *spec,
2260 __in uint32_t lhost,
2261 __in uint16_t lport,
2262 __in uint32_t rhost,
2263 __in uint16_t rport);
2265 extern __checkReturn int
2266 efx_filter_spec_set_eth_local(
2267 __inout efx_filter_spec_t *spec,
2269 __in const uint8_t *addr);
2271 extern __checkReturn int
2272 efx_filter_spec_set_uc_def(
2273 __inout efx_filter_spec_t *spec);
2275 extern __checkReturn int
2276 efx_filter_spec_set_mc_def(
2277 __inout efx_filter_spec_t *spec);
2279 #endif /* EFSYS_OPT_FILTER */
2283 extern __checkReturn uint32_t
2285 __in_ecount(count) uint32_t const *input,
2287 __in uint32_t init);
2289 extern __checkReturn uint32_t
2291 __in_ecount(length) uint8_t const *input,
2293 __in uint32_t init);
2300 #endif /* _SYS_EFX_H */