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31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include "efx_types.h"
41 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
43 static __checkReturn int
44 falconsiena_intr_init(
46 __in efx_intr_type_t type,
47 __in efsys_mem_t *esmp);
50 falconsiena_intr_enable(
54 falconsiena_intr_disable(
58 falconsiena_intr_disable_unlocked(
61 static __checkReturn int
62 falconsiena_intr_trigger(
64 __in unsigned int level);
67 falconsiena_intr_fini(
71 static __checkReturn boolean_t
72 falconsiena_intr_check_fatal(
76 falconsiena_intr_fatal(
79 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
83 static efx_intr_ops_t __efx_intr_falcon_ops = {
84 falconsiena_intr_init, /* eio_init */
85 falconsiena_intr_enable, /* eio_enable */
86 falconsiena_intr_disable, /* eio_disable */
87 falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
88 falconsiena_intr_trigger, /* eio_trigger */
89 falconsiena_intr_fini, /* eio_fini */
91 #endif /* EFSYS_OPT_FALCON */
94 static efx_intr_ops_t __efx_intr_siena_ops = {
95 falconsiena_intr_init, /* eio_init */
96 falconsiena_intr_enable, /* eio_enable */
97 falconsiena_intr_disable, /* eio_disable */
98 falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
99 falconsiena_intr_trigger, /* eio_trigger */
100 falconsiena_intr_fini, /* eio_fini */
102 #endif /* EFSYS_OPT_SIENA */
104 #if EFSYS_OPT_HUNTINGTON
105 static efx_intr_ops_t __efx_intr_hunt_ops = {
106 hunt_intr_init, /* eio_init */
107 hunt_intr_enable, /* eio_enable */
108 hunt_intr_disable, /* eio_disable */
109 hunt_intr_disable_unlocked, /* eio_disable_unlocked */
110 hunt_intr_trigger, /* eio_trigger */
111 hunt_intr_fini, /* eio_fini */
113 #endif /* EFSYS_OPT_HUNTINGTON */
119 __in efx_intr_type_t type,
120 __in efsys_mem_t *esmp)
122 efx_intr_t *eip = &(enp->en_intr);
123 efx_intr_ops_t *eiop;
126 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
127 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
129 if (enp->en_mod_flags & EFX_MOD_INTR) {
138 enp->en_mod_flags |= EFX_MOD_INTR;
140 switch (enp->en_family) {
142 case EFX_FAMILY_FALCON:
143 eiop = (efx_intr_ops_t *)&__efx_intr_falcon_ops;
145 #endif /* EFSYS_OPT_FALCON */
148 case EFX_FAMILY_SIENA:
149 eiop = (efx_intr_ops_t *)&__efx_intr_siena_ops;
151 #endif /* EFSYS_OPT_SIENA */
153 #if EFSYS_OPT_HUNTINGTON
154 case EFX_FAMILY_HUNTINGTON:
155 eiop = (efx_intr_ops_t *)&__efx_intr_hunt_ops;
157 #endif /* EFSYS_OPT_HUNTINGTON */
160 EFSYS_ASSERT(B_FALSE);
165 if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
177 EFSYS_PROBE1(fail1, int, rc);
186 efx_intr_t *eip = &(enp->en_intr);
187 efx_intr_ops_t *eiop = eip->ei_eiop;
189 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
190 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
191 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
195 enp->en_mod_flags &= ~EFX_MOD_INTR;
202 efx_intr_t *eip = &(enp->en_intr);
203 efx_intr_ops_t *eiop = eip->ei_eiop;
205 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
206 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
208 eiop->eio_enable(enp);
215 efx_intr_t *eip = &(enp->en_intr);
216 efx_intr_ops_t *eiop = eip->ei_eiop;
218 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
219 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
221 eiop->eio_disable(enp);
225 efx_intr_disable_unlocked(
228 efx_intr_t *eip = &(enp->en_intr);
229 efx_intr_ops_t *eiop = eip->ei_eiop;
231 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
232 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
234 eiop->eio_disable_unlocked(enp);
241 __in unsigned int level)
243 efx_intr_t *eip = &(enp->en_intr);
244 efx_intr_ops_t *eiop = eip->ei_eiop;
246 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
247 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
249 return (eiop->eio_trigger(enp, level));
253 efx_intr_status_line(
255 __out boolean_t *fatalp,
256 __out uint32_t *qmaskp)
258 efx_intr_t *eip = &(enp->en_intr);
261 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
262 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
264 /* Ensure Huntington and Falcon/Siena ISR at same location */
265 EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST ==
266 ER_DZ_BIU_INT_ISR_REG_OFST);
269 * Read the queue mask and implicitly acknowledge the
272 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
273 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
275 EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
277 #if EFSYS_OPT_HUNTINGTON
278 if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
279 /* Huntington reports fatal errors via events */
284 if (*qmaskp & (1U << eip->ei_level))
285 *fatalp = falconsiena_intr_check_fatal(enp);
291 efx_intr_status_message(
293 __in unsigned int message,
294 __out boolean_t *fatalp)
296 efx_intr_t *eip = &(enp->en_intr);
298 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
299 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
301 #if EFSYS_OPT_HUNTINGTON
302 if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
303 /* Huntington reports fatal errors via events */
308 if (message == eip->ei_level)
309 *fatalp = falconsiena_intr_check_fatal(enp);
318 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
319 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
321 #if EFSYS_OPT_HUNTINGTON
322 if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
323 /* Huntington reports fatal errors via events */
327 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
328 falconsiena_intr_fatal(enp);
333 /* ************************************************************************* */
334 /* ************************************************************************* */
335 /* ************************************************************************* */
337 #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
339 static __checkReturn int
340 falconsiena_intr_init(
342 __in efx_intr_type_t type,
343 __in efsys_mem_t *esmp)
345 efx_intr_t *eip = &(enp->en_intr);
349 * bug17213 workaround.
351 * Under legacy interrupts, don't share a level between fatal
352 * interrupts and event queue interrupts. Under MSI-X, they
353 * must share, or we won't get an interrupt.
355 if (enp->en_family == EFX_FAMILY_SIENA &&
356 eip->ei_type == EFX_INTR_LINE)
357 eip->ei_level = 0x1f;
361 /* Enable all the genuinely fatal interrupts */
362 EFX_SET_OWORD(oword);
363 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
364 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
365 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
366 if (enp->en_family >= EFX_FAMILY_SIENA)
367 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
368 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
370 /* Set up the interrupt address register */
371 EFX_POPULATE_OWORD_3(oword,
372 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
373 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
374 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
375 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
381 falconsiena_intr_enable(
384 efx_intr_t *eip = &(enp->en_intr);
387 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
389 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
390 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
391 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
395 falconsiena_intr_disable(
400 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
401 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
402 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
408 falconsiena_intr_disable_unlocked(
413 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
415 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
416 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
420 static __checkReturn int
421 falconsiena_intr_trigger(
423 __in unsigned int level)
425 efx_intr_t *eip = &(enp->en_intr);
431 /* bug16757: No event queues can be initialized */
432 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
434 switch (enp->en_family) {
435 case EFX_FAMILY_FALCON:
436 if (level >= EFX_NINTR_FALCON) {
442 case EFX_FAMILY_SIENA:
443 if (level >= EFX_NINTR_SIENA) {
450 EFSYS_ASSERT(B_FALSE);
454 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
455 return (ENOTSUP); /* avoid EFSYS_PROBE() */
459 /* Trigger a test interrupt */
460 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
461 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
462 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
463 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
466 * Wait up to 100ms for the interrupt to be raised before restoring
467 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
468 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
472 EFSYS_SPIN(100); /* 100us */
474 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
475 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
477 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
478 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
483 EFSYS_PROBE1(fail1, int, rc);
488 static __checkReturn boolean_t
489 falconsiena_intr_check_fatal(
492 efx_intr_t *eip = &(enp->en_intr);
493 efsys_mem_t *esmp = eip->ei_esmp;
496 /* Read the syndrome */
497 EFSYS_MEM_READO(esmp, 0, &oword);
499 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
502 /* Clear the fatal interrupt condition */
503 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
504 EFSYS_MEM_WRITEO(esmp, 0, &oword);
513 falconsiena_intr_fatal(
516 #if EFSYS_OPT_DECODE_INTR_FATAL
520 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
521 EFX_ZERO_OWORD(mem_per);
523 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
524 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
525 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
527 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
528 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
530 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
531 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
533 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
534 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
535 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
536 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
538 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
539 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
541 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
542 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
544 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
545 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
547 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
548 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
550 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
551 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
553 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
554 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
556 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
557 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
559 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
560 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
561 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
562 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
569 falconsiena_intr_fini(
574 /* Clear the interrupt address register */
575 EFX_ZERO_OWORD(oword);
576 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
579 #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */