2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #include "efx_types.h"
40 #include "falcon_nvram.h"
43 #if EFSYS_OPT_MAC_FALCON_XMAC
44 #include "falcon_xmac.h"
47 #if EFSYS_OPT_MAC_FALCON_GMAC
48 #include "falcon_gmac.h"
51 #if EFSYS_OPT_PHY_NULL
55 #if EFSYS_OPT_PHY_QT2022C2
59 #if EFSYS_OPT_PHY_SFX7101
63 #if EFSYS_OPT_PHY_TXC43128
67 #if EFSYS_OPT_PHY_SFT9001
71 #if EFSYS_OPT_PHY_QT2025C
75 #if EFSYS_OPT_PHY_NULL
76 static efx_phy_ops_t __efx_phy_null_ops = {
78 nullphy_reset, /* epo_reset */
79 nullphy_reconfigure, /* epo_reconfigure */
80 nullphy_verify, /* epo_verify */
81 NULL, /* epo_uplink_check */
82 nullphy_downlink_check, /* epo_downlink_check */
83 nullphy_oui_get, /* epo_oui_get */
84 #if EFSYS_OPT_PHY_STATS
85 nullphy_stats_update, /* epo_stats_update */
86 #endif /* EFSYS_OPT_PHY_STATS */
87 #if EFSYS_OPT_PHY_PROPS
89 nullphy_prop_name, /* epo_prop_name */
91 nullphy_prop_get, /* epo_prop_get */
92 nullphy_prop_set, /* epo_prop_set */
93 #endif /* EFSYS_OPT_PHY_PROPS */
95 NULL, /* epo_bist_enable_offline */
96 NULL, /* epo_bist_start */
97 NULL, /* epo_bist_poll */
98 NULL, /* epo_bist_stop */
99 #endif /* EFSYS_OPT_BIST */
101 #endif /* EFSYS_OPT_PHY_NULL */
103 #if EFSYS_OPT_PHY_QT2022C2
104 static efx_phy_ops_t __efx_phy_qt2022c2_ops = {
105 NULL, /* epo_power */
106 qt2022c2_reset, /* epo_reset */
107 qt2022c2_reconfigure, /* epo_reconfigure */
108 qt2022c2_verify, /* epo_verify */
109 qt2022c2_uplink_check, /* epo_uplink_check */
110 qt2022c2_downlink_check, /* epo_downlink_check */
111 qt2022c2_oui_get, /* epo_oui_get */
112 #if EFSYS_OPT_PHY_STATS
113 qt2022c2_stats_update, /* epo_stats_update */
114 #endif /* EFSYS_OPT_PHY_STATS */
115 #if EFSYS_OPT_PHY_PROPS
117 qt2022c2_prop_name, /* epo_prop_name */
119 qt2022c2_prop_get, /* epo_prop_get */
120 qt2022c2_prop_set, /* epo_prop_set */
121 #endif /* EFSYS_OPT_PHY_PROPS */
123 NULL, /* epo_bist_enable_offline */
124 NULL, /* epo_bist_start */
125 NULL, /* epo_bist_poll */
126 NULL, /* epo_bist_stop */
127 #endif /* EFSYS_OPT_BIST */
129 #endif /* EFSYS_OPT_PHY_QT2022C2 */
131 #if EFSYS_OPT_PHY_SFX7101
132 static efx_phy_ops_t __efx_phy_sfx7101_ops = {
133 sfx7101_power, /* epo_power */
134 sfx7101_reset, /* epo_reset */
135 sfx7101_reconfigure, /* epo_reconfigure */
136 sfx7101_verify, /* epo_verify */
137 sfx7101_uplink_check, /* epo_uplink_check */
138 sfx7101_downlink_check, /* epo_downlink_check */
139 sfx7101_oui_get, /* epo_oui_get */
140 #if EFSYS_OPT_PHY_STATS
141 sfx7101_stats_update, /* epo_stats_update */
142 #endif /* EFSYS_OPT_PHY_STATS */
143 #if EFSYS_OPT_PHY_PROPS
145 sfx7101_prop_name, /* epo_prop_name */
147 sfx7101_prop_get, /* epo_prop_get */
148 sfx7101_prop_set, /* epo_prop_set */
149 #endif /* EFSYS_OPT_PHY_PROPS */
151 NULL, /* epo_bist_enable_offline */
152 NULL, /* epo_bist_start */
153 NULL, /* epo_bist_poll */
154 NULL, /* epo_bist_stop */
155 #endif /* EFSYS_OPT_BIST */
157 #endif /* EFSYS_OPT_PHY_SFX7101 */
159 #if EFSYS_OPT_PHY_TXC43128
160 static efx_phy_ops_t __efx_phy_txc43128_ops = {
161 NULL, /* epo_power */
162 txc43128_reset, /* epo_reset */
163 txc43128_reconfigure, /* epo_reconfigure */
164 txc43128_verify, /* epo_verify */
165 txc43128_uplink_check, /* epo_uplink_check */
166 txc43128_downlink_check, /* epo_downlink_check */
167 txc43128_oui_get, /* epo_oui_get */
168 #if EFSYS_OPT_PHY_STATS
169 txc43128_stats_update, /* epo_stats_update */
170 #endif /* EFSYS_OPT_PHY_STATS */
171 #if EFSYS_OPT_PHY_PROPS
173 txc43128_prop_name, /* epo_prop_name */
175 txc43128_prop_get, /* epo_prop_get */
176 txc43128_prop_set, /* epo_prop_set */
177 #endif /* EFSYS_OPT_PHY_PROPS */
179 NULL, /* epo_bist_enable_offline */
180 NULL, /* epo_bist_start */
181 NULL, /* epo_bist_poll */
182 NULL, /* epo_bist_stop */
183 #endif /* EFSYS_OPT_BIST */
185 #endif /* EFSYS_OPT_PHY_TXC43128 */
187 #if EFSYS_OPT_PHY_SFT9001
188 static efx_phy_ops_t __efx_phy_sft9001_ops = {
189 NULL, /* epo_power */
190 sft9001_reset, /* epo_reset */
191 sft9001_reconfigure, /* epo_reconfigure */
192 sft9001_verify, /* epo_verify */
193 sft9001_uplink_check, /* epo_uplink_check */
194 sft9001_downlink_check, /* epo_downlink_check */
195 sft9001_oui_get, /* epo_oui_get */
196 #if EFSYS_OPT_PHY_STATS
197 sft9001_stats_update, /* epo_stats_update */
198 #endif /* EFSYS_OPT_PHY_STATS */
199 #if EFSYS_OPT_PHY_PROPS
201 sft9001_prop_name, /* epo_prop_name */
203 sft9001_prop_get, /* epo_prop_get */
204 sft9001_prop_set, /* epo_prop_set */
205 #endif /* EFSYS_OPT_PHY_PROPS */
207 NULL, /* epo_bist_enable_offline */
208 sft9001_bist_start, /* epo_bist_start */
209 sft9001_bist_poll, /* epo_bist_poll */
210 sft9001_bist_stop, /* epo_bist_stop */
211 #endif /* EFSYS_OPT_BIST */
213 #endif /* EFSYS_OPT_PHY_SFT9001 */
215 #if EFSYS_OPT_PHY_QT2025C
216 static efx_phy_ops_t __efx_phy_qt2025c_ops = {
217 NULL, /* epo_power */
218 qt2025c_reset, /* epo_reset */
219 qt2025c_reconfigure, /* epo_reconfigure */
220 qt2025c_verify, /* epo_verify */
221 qt2025c_uplink_check, /* epo_uplink_check */
222 qt2025c_downlink_check, /* epo_downlink_check */
223 qt2025c_oui_get, /* epo_oui_get */
224 #if EFSYS_OPT_PHY_STATS
225 qt2025c_stats_update, /* epo_stats_update */
226 #endif /* EFSYS_OPT_PHY_STATS */
227 #if EFSYS_OPT_PHY_PROPS
229 qt2025c_prop_name, /* epo_prop_name */
231 qt2025c_prop_get, /* epo_prop_get */
232 qt2025c_prop_set, /* epo_prop_set */
233 #endif /* EFSYS_OPT_PHY_PROPS */
235 NULL, /* epo_bist_enable_offline */
236 NULL, /* epo_bist_start */
237 NULL, /* epo_bist_poll */
238 NULL, /* epo_bist_stop */
239 #endif /* EFSYS_OPT_BIST */
241 #endif /* EFSYS_OPT_PHY_QT2025C */
244 static efx_phy_ops_t __efx_phy_siena_ops = {
245 siena_phy_power, /* epo_power */
246 NULL, /* epo_reset */
247 siena_phy_reconfigure, /* epo_reconfigure */
248 siena_phy_verify, /* epo_verify */
249 NULL, /* epo_uplink_check */
250 NULL, /* epo_downlink_check */
251 siena_phy_oui_get, /* epo_oui_get */
252 #if EFSYS_OPT_PHY_STATS
253 siena_phy_stats_update, /* epo_stats_update */
254 #endif /* EFSYS_OPT_PHY_STATS */
255 #if EFSYS_OPT_PHY_PROPS
257 siena_phy_prop_name, /* epo_prop_name */
259 siena_phy_prop_get, /* epo_prop_get */
260 siena_phy_prop_set, /* epo_prop_set */
261 #endif /* EFSYS_OPT_PHY_PROPS */
263 NULL, /* epo_bist_enable_offline */
264 siena_phy_bist_start, /* epo_bist_start */
265 siena_phy_bist_poll, /* epo_bist_poll */
266 siena_phy_bist_stop, /* epo_bist_stop */
267 #endif /* EFSYS_OPT_BIST */
269 #endif /* EFSYS_OPT_SIENA */
271 #if EFSYS_OPT_HUNTINGTON
272 static efx_phy_ops_t __efx_phy_hunt_ops = {
273 hunt_phy_power, /* epo_power */
274 NULL, /* epo_reset */
275 hunt_phy_reconfigure, /* epo_reconfigure */
276 hunt_phy_verify, /* epo_verify */
277 NULL, /* epo_uplink_check */
278 NULL, /* epo_downlink_check */
279 hunt_phy_oui_get, /* epo_oui_get */
280 #if EFSYS_OPT_PHY_STATS
281 hunt_phy_stats_update, /* epo_stats_update */
282 #endif /* EFSYS_OPT_PHY_STATS */
283 #if EFSYS_OPT_PHY_PROPS
285 hunt_phy_prop_name, /* epo_prop_name */
287 hunt_phy_prop_get, /* epo_prop_get */
288 hunt_phy_prop_set, /* epo_prop_set */
289 #endif /* EFSYS_OPT_PHY_PROPS */
291 hunt_bist_enable_offline, /* epo_bist_enable_offline */
292 hunt_bist_start, /* epo_bist_start */
293 hunt_bist_poll, /* epo_bist_poll */
294 hunt_bist_stop, /* epo_bist_stop */
295 #endif /* EFSYS_OPT_BIST */
297 #endif /* EFSYS_OPT_HUNTINGTON */
303 efx_port_t *epp = &(enp->en_port);
304 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
308 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
310 epp->ep_port = encp->enc_port;
311 epp->ep_phy_type = encp->enc_phy_type;
313 /* Hook in operations structure */
314 switch (enp->en_family) {
316 case EFX_FAMILY_FALCON:
317 switch (epp->ep_phy_type) {
318 #if EFSYS_OPT_PHY_NULL
319 case PHY_TYPE_NONE_DECODE:
320 epop = (efx_phy_ops_t *)&__efx_phy_null_ops;
323 #if EFSYS_OPT_PHY_QT2022C2
324 case PHY_TYPE_QT2022C2_DECODE:
325 epop = (efx_phy_ops_t *)&__efx_phy_qt2022c2_ops;
328 #if EFSYS_OPT_PHY_SFX7101
329 case PHY_TYPE_SFX7101_DECODE:
330 epop = (efx_phy_ops_t *)&__efx_phy_sfx7101_ops;
333 #if EFSYS_OPT_PHY_TXC43128
334 case PHY_TYPE_TXC43128_DECODE:
335 epop = (efx_phy_ops_t *)&__efx_phy_txc43128_ops;
338 #if EFSYS_OPT_PHY_SFT9001
339 case PHY_TYPE_SFT9001A_DECODE:
340 case PHY_TYPE_SFT9001B_DECODE:
341 epop = (efx_phy_ops_t *)&__efx_phy_sft9001_ops;
344 #if EFSYS_OPT_PHY_QT2025C
345 case EFX_PHY_QT2025C:
346 epop = (efx_phy_ops_t *)&__efx_phy_qt2025c_ops;
354 #endif /* EFSYS_OPT_FALCON */
356 case EFX_FAMILY_SIENA:
357 epop = (efx_phy_ops_t *)&__efx_phy_siena_ops;
359 #endif /* EFSYS_OPT_SIENA */
360 #if EFSYS_OPT_HUNTINGTON
361 case EFX_FAMILY_HUNTINGTON:
362 epop = (efx_phy_ops_t *)&__efx_phy_hunt_ops;
364 #endif /* EFSYS_OPT_HUNTINGTON */
375 EFSYS_PROBE1(fail1, int, rc);
378 epp->ep_phy_type = 0;
387 efx_port_t *epp = &(enp->en_port);
388 efx_phy_ops_t *epop = epp->ep_epop;
390 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
391 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
393 return (epop->epo_verify(enp));
396 #if EFSYS_OPT_PHY_LED_CONTROL
401 __in efx_phy_led_mode_t mode)
403 efx_nic_cfg_t *encp = (&enp->en_nic_cfg);
404 efx_port_t *epp = &(enp->en_port);
405 efx_phy_ops_t *epop = epp->ep_epop;
409 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
410 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
412 if (epp->ep_phy_led_mode == mode)
415 mask = (1 << EFX_PHY_LED_DEFAULT);
416 mask |= encp->enc_led_mask;
418 if (!((1 << mode) & mask)) {
423 EFSYS_ASSERT3U(mode, <, EFX_PHY_LED_NMODES);
424 epp->ep_phy_led_mode = mode;
426 if ((rc = epop->epo_reconfigure(enp)) != 0)
435 EFSYS_PROBE1(fail1, int, rc);
439 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
445 __out uint32_t *maskp)
447 efx_port_t *epp = &(enp->en_port);
449 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
450 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
453 case EFX_PHY_CAP_CURRENT:
454 *maskp = epp->ep_adv_cap_mask;
456 case EFX_PHY_CAP_DEFAULT:
457 *maskp = epp->ep_default_adv_cap_mask;
459 case EFX_PHY_CAP_PERM:
460 *maskp = epp->ep_phy_cap_mask;
463 EFSYS_ASSERT(B_FALSE);
473 efx_port_t *epp = &(enp->en_port);
474 efx_phy_ops_t *epop = epp->ep_epop;
478 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
479 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
481 if ((mask & ~epp->ep_phy_cap_mask) != 0) {
486 if (epp->ep_adv_cap_mask == mask)
489 old_mask = epp->ep_adv_cap_mask;
490 epp->ep_adv_cap_mask = mask;
492 if ((rc = epop->epo_reconfigure(enp)) != 0)
501 epp->ep_adv_cap_mask = old_mask;
502 /* Reconfigure for robustness */
503 if (epop->epo_reconfigure(enp) != 0) {
505 * We may have an inconsistent view of our advertised speed
512 EFSYS_PROBE1(fail1, int, rc);
520 __out uint32_t *maskp)
522 efx_port_t *epp = &(enp->en_port);
524 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
525 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
527 *maskp = epp->ep_lp_cap_mask;
533 __out uint32_t *ouip)
535 efx_port_t *epp = &(enp->en_port);
536 efx_phy_ops_t *epop = epp->ep_epop;
538 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
539 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
541 return (epop->epo_oui_get(enp, ouip));
545 efx_phy_media_type_get(
547 __out efx_phy_media_type_t *typep)
549 efx_port_t *epp = &(enp->en_port);
551 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
552 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
554 if (epp->ep_module_type != EFX_PHY_MEDIA_INVALID)
555 *typep = epp->ep_module_type;
557 *typep = epp->ep_fixed_port_type;
560 #if EFSYS_OPT_PHY_STATS
564 /* START MKCONFIG GENERATED PhyStatNamesBlock d5f79b4bc2c050fe */
565 static const char *__efx_phy_stat_name[] = {
614 /* END MKCONFIG GENERATED PhyStatNamesBlock */
619 __in efx_phy_stat_t type)
621 _NOTE(ARGUNUSED(enp))
622 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
623 EFSYS_ASSERT3U(type, <, EFX_PHY_NSTATS);
625 return (__efx_phy_stat_name[type]);
628 #endif /* EFSYS_OPT_NAMES */
631 efx_phy_stats_update(
633 __in efsys_mem_t *esmp,
634 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat)
636 efx_port_t *epp = &(enp->en_port);
637 efx_phy_ops_t *epop = epp->ep_epop;
639 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
640 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
642 return (epop->epo_stats_update(enp, esmp, stat));
645 #endif /* EFSYS_OPT_PHY_STATS */
647 #if EFSYS_OPT_PHY_PROPS
653 __in unsigned int id)
655 efx_port_t *epp = &(enp->en_port);
656 efx_phy_ops_t *epop = epp->ep_epop;
658 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
659 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
661 return (epop->epo_prop_name(enp, id));
663 #endif /* EFSYS_OPT_NAMES */
668 __in unsigned int id,
670 __out uint32_t *valp)
672 efx_port_t *epp = &(enp->en_port);
673 efx_phy_ops_t *epop = epp->ep_epop;
675 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
676 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
678 return (epop->epo_prop_get(enp, id, flags, valp));
684 __in unsigned int id,
687 efx_port_t *epp = &(enp->en_port);
688 efx_phy_ops_t *epop = epp->ep_epop;
690 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
691 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
693 return (epop->epo_prop_set(enp, id, val));
695 #endif /* EFSYS_OPT_PHY_STATS */
700 efx_bist_enable_offline(
703 efx_port_t *epp = &(enp->en_port);
704 efx_phy_ops_t *epop = epp->ep_epop;
707 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
709 if (epop->epo_bist_enable_offline == NULL) {
714 if ((rc = epop->epo_bist_enable_offline(enp)) != 0)
722 EFSYS_PROBE1(fail1, int, rc);
731 __in efx_bist_type_t type)
733 efx_port_t *epp = &(enp->en_port);
734 efx_phy_ops_t *epop = epp->ep_epop;
737 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
739 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
740 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
741 EFSYS_ASSERT3U(epp->ep_current_bist, ==, EFX_BIST_TYPE_UNKNOWN);
743 if (epop->epo_bist_start == NULL) {
748 if ((rc = epop->epo_bist_start(enp, type)) != 0)
751 epp->ep_current_bist = type;
758 EFSYS_PROBE1(fail1, int, rc);
766 __in efx_bist_type_t type,
767 __out efx_bist_result_t *resultp,
768 __out_opt uint32_t *value_maskp,
769 __out_ecount_opt(count) unsigned long *valuesp,
772 efx_port_t *epp = &(enp->en_port);
773 efx_phy_ops_t *epop = epp->ep_epop;
776 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
778 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
779 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
780 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
782 EFSYS_ASSERT(epop->epo_bist_poll != NULL);
783 if (epop->epo_bist_poll == NULL) {
788 if ((rc = epop->epo_bist_poll(enp, type, resultp, value_maskp,
789 valuesp, count)) != 0)
797 EFSYS_PROBE1(fail1, int, rc);
805 __in efx_bist_type_t type)
807 efx_port_t *epp = &(enp->en_port);
808 efx_phy_ops_t *epop = epp->ep_epop;
810 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
812 EFSYS_ASSERT3U(type, !=, EFX_BIST_TYPE_UNKNOWN);
813 EFSYS_ASSERT3U(type, <, EFX_BIST_TYPE_NTYPES);
814 EFSYS_ASSERT3U(epp->ep_current_bist, ==, type);
816 EFSYS_ASSERT(epop->epo_bist_stop != NULL);
818 if (epop->epo_bist_stop != NULL)
819 epop->epo_bist_stop(enp, type);
821 epp->ep_current_bist = EFX_BIST_TYPE_UNKNOWN;
824 #endif /* EFSYS_OPT_BIST */
829 efx_port_t *epp = &(enp->en_port);
831 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
835 epp->ep_adv_cap_mask = 0;
838 epp->ep_phy_type = 0;