2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
39 #if EFSYS_OPT_HUNTINGTON
42 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
44 (_etp)->et_stat[_stat]++; \
45 _NOTE(CONSTANTCONDITION) \
48 #define EFX_TX_QSTAT_INCR(_etp, _stat)
51 static __checkReturn int
55 __in uint32_t target_evq,
57 __in uint32_t instance,
59 __in efsys_mem_t *esmp)
62 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
63 MC_CMD_INIT_TXQ_OUT_LEN)];
64 efx_qword_t *dma_addr;
70 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
71 EFX_TXQ_NBUFS(EFX_TXQ_MAXNDESCS(&enp->en_nic_cfg)));
73 npages = EFX_TXQ_NBUFS(size);
74 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
79 (void) memset(payload, 0, sizeof (payload));
80 req.emr_cmd = MC_CMD_INIT_TXQ;
81 req.emr_in_buf = payload;
82 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
83 req.emr_out_buf = payload;
84 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
86 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
87 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
88 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
89 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
91 MCDI_IN_POPULATE_DWORD_6(req, INIT_TXQ_IN_FLAGS,
92 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
93 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, (flags & EFX_CKSUM_IPV4) ? 0 : 1,
94 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, (flags & EFX_CKSUM_TCPUDP) ? 0 : 1,
95 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
96 INIT_TXQ_IN_CRC_MODE, 0,
97 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
99 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
100 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
102 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
103 addr = EFSYS_MEM_ADDR(esmp);
105 for (i = 0; i < npages; i++) {
106 EFX_POPULATE_QWORD_2(*dma_addr,
107 EFX_DWORD_1, (uint32_t)(addr >> 32),
108 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
111 addr += EFX_BUF_SIZE;
114 efx_mcdi_execute(enp, &req);
116 if (req.emr_rc != 0) {
126 EFSYS_PROBE1(fail1, int, rc);
131 static __checkReturn int
134 __in uint32_t instance)
137 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
138 MC_CMD_FINI_TXQ_OUT_LEN)];
141 (void) memset(payload, 0, sizeof (payload));
142 req.emr_cmd = MC_CMD_FINI_TXQ;
143 req.emr_in_buf = payload;
144 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
145 req.emr_out_buf = payload;
146 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
148 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
150 efx_mcdi_execute(enp, &req);
152 if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
160 EFSYS_PROBE1(fail1, int, rc);
169 _NOTE(ARGUNUSED(enp))
177 _NOTE(ARGUNUSED(enp))
183 __in unsigned int index,
184 __in unsigned int label,
185 __in efsys_mem_t *esmp,
191 __out unsigned int *addedp)
197 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
202 * A previous user of this TX queue may have written a descriptor to the
203 * TX push collector, but not pushed the doorbell (e.g. after a crash).
204 * The next doorbell write would then push the stale descriptor.
206 * Ensure the (per network port) TX push collector is cleared by writing
207 * a no-op TX option descriptor. See bug29981 for details.
210 EFX_POPULATE_QWORD_4(desc,
211 ESF_DZ_TX_DESC_IS_OPT, 1,
212 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
213 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, (flags & EFX_CKSUM_TCPUDP) ? 1 : 0,
214 ESF_DZ_TX_OPTION_IP_CSUM, (flags & EFX_CKSUM_IPV4) ? 1 : 0);
216 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
217 hunt_tx_qpush(etp, *addedp, 0);
222 EFSYS_PROBE1(fail1, int, rc);
232 _NOTE(ARGUNUSED(etp))
240 efx_nic_t *enp = etp->et_enp;
241 efx_piobuf_handle_t handle;
244 if (etp->et_pio_size != 0) {
249 /* Sub-allocate a PIO block from a piobuf */
250 if ((rc = hunt_nic_pio_alloc(enp,
255 &etp->et_pio_size)) != 0) {
258 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
260 /* Link the piobuf to this TXQ */
261 if ((rc = hunt_nic_pio_link(enp, etp->et_index, handle)) != 0) {
266 * et_pio_offset is the offset of the sub-allocated block within the
267 * hardware PIO buffer. It is used as the buffer address in the PIO
270 * et_pio_write_offset is the offset of the sub-allocated block from the
271 * start of the write-combined memory mapping, and is used for writing
272 * data into the PIO buffer.
274 etp->et_pio_write_offset =
275 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
276 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
282 hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
283 etp->et_pio_size = 0;
287 EFSYS_PROBE1(fail1, int, rc);
293 hunt_tx_qpio_disable(
296 efx_nic_t *enp = etp->et_enp;
298 if (etp->et_pio_size != 0) {
299 /* Unlink the piobuf from this TXQ */
300 hunt_nic_pio_unlink(enp, etp->et_index);
302 /* Free the sub-allocated PIO block */
303 hunt_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
304 etp->et_pio_size = 0;
305 etp->et_pio_write_offset = 0;
312 __in_ecount(length) uint8_t *buffer,
316 efx_nic_t *enp = etp->et_enp;
317 efsys_bar_t *esbp = enp->en_esbp;
318 uint32_t write_offset;
319 uint32_t write_offset_limit;
323 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
325 if (etp->et_pio_size == 0) {
329 if (offset + length > etp->et_pio_size) {
335 * Writes to PIO buffers must be 64 bit aligned, and multiples of
338 write_offset = etp->et_pio_write_offset + offset;
339 write_offset_limit = write_offset + length;
340 eqp = (efx_qword_t *)buffer;
341 while (write_offset < write_offset_limit) {
342 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
344 write_offset += sizeof (efx_qword_t);
352 EFSYS_PROBE1(fail1, int, rc);
360 __in size_t pkt_length,
361 __in unsigned int completed,
362 __inout unsigned int *addedp)
364 efx_qword_t pio_desc;
367 unsigned int added = *addedp;
371 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
376 if (etp->et_pio_size == 0) {
381 id = added++ & etp->et_mask;
382 offset = id * sizeof (efx_qword_t);
384 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
385 unsigned int, id, uint32_t, etp->et_pio_offset,
388 EFX_POPULATE_QWORD_5(pio_desc,
389 ESF_DZ_TX_DESC_IS_OPT, 1,
390 ESF_DZ_TX_OPTION_TYPE, 1,
391 ESF_DZ_TX_PIO_CONT, 0,
392 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
393 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
395 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
397 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
405 EFSYS_PROBE1(fail1, int, rc);
413 __in_ecount(n) efx_buffer_t *eb,
415 __in unsigned int completed,
416 __inout unsigned int *addedp)
418 unsigned int added = *addedp;
422 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
427 for (i = 0; i < n; i++) {
428 efx_buffer_t *ebp = &eb[i];
429 efsys_dma_addr_t addr = ebp->eb_addr;
430 size_t size = ebp->eb_size;
431 boolean_t eop = ebp->eb_eop;
436 /* Fragments must not span 4k boundaries. */
437 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
439 id = added++ & etp->et_mask;
440 offset = id * sizeof (efx_qword_t);
442 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
443 unsigned int, id, efsys_dma_addr_t, addr,
444 size_t, size, boolean_t, eop);
446 EFX_POPULATE_QWORD_5(qword,
447 ESF_DZ_TX_KER_TYPE, 0,
448 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
449 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
450 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
451 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
453 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
456 EFX_TX_QSTAT_INCR(etp, TX_POST);
462 EFSYS_PROBE1(fail1, int, rc);
468 * This improves performance by pushing a TX descriptor at the same time as the
469 * doorbell. The descriptor must be added to the TXQ, so that can be used if the
470 * hardware decides not to use the pushed descriptor.
475 __in unsigned int added,
476 __in unsigned int pushed)
478 efx_nic_t *enp = etp->et_enp;
485 wptr = added & etp->et_mask;
486 id = pushed & etp->et_mask;
487 offset = id * sizeof (efx_qword_t);
489 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
490 EFX_POPULATE_OWORD_3(oword,
491 ERF_DZ_TX_DESC_WPTR, wptr,
492 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
493 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
495 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
496 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id);
497 EFSYS_PIO_WRITE_BARRIER();
498 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index,
505 __in_ecount(n) efx_desc_t *ed,
507 __in unsigned int completed,
508 __inout unsigned int *addedp)
510 unsigned int added = *addedp;
514 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
519 for (i = 0; i < n; i++) {
520 efx_desc_t *edp = &ed[i];
524 id = added++ & etp->et_mask;
525 offset = id * sizeof (efx_desc_t);
527 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
530 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
531 unsigned int, added, unsigned int, n);
533 EFX_TX_QSTAT_INCR(etp, TX_POST);
539 EFSYS_PROBE1(fail1, int, rc);
545 hunt_tx_qdesc_dma_create(
547 __in efsys_dma_addr_t addr,
550 __out efx_desc_t *edp)
552 /* Fragments must not span 4k boundaries. */
553 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
555 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
556 efsys_dma_addr_t, addr,
557 size_t, size, boolean_t, eop);
559 EFX_POPULATE_QWORD_5(edp->ed_eq,
560 ESF_DZ_TX_KER_TYPE, 0,
561 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
562 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
563 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
564 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
568 hunt_tx_qdesc_tso_create(
570 __in uint16_t ipv4_id,
571 __in uint32_t tcp_seq,
572 __in uint8_t tcp_flags,
573 __out efx_desc_t *edp)
575 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
576 uint16_t, ipv4_id, uint32_t, tcp_seq,
579 EFX_POPULATE_QWORD_5(edp->ed_eq,
580 ESF_DZ_TX_DESC_IS_OPT, 1,
581 ESF_DZ_TX_OPTION_TYPE,
582 ESE_DZ_TX_OPTION_DESC_TSO,
583 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
584 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
585 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
589 hunt_tx_qdesc_vlantci_create(
592 __out efx_desc_t *edp)
594 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
597 EFX_POPULATE_QWORD_4(edp->ed_eq,
598 ESF_DZ_TX_DESC_IS_OPT, 1,
599 ESF_DZ_TX_OPTION_TYPE,
600 ESE_DZ_TX_OPTION_DESC_VLAN,
601 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
602 ESF_DZ_TX_VLAN_TAG1, tci);
609 __in unsigned int ns)
614 _NOTE(ARGUNUSED(etp, ns))
624 EFSYS_PROBE1(fail1, int, rc);
633 efx_nic_t *enp = etp->et_enp;
636 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
642 EFSYS_PROBE1(fail1, int, rc);
652 _NOTE(ARGUNUSED(etp))
658 hunt_tx_qstats_update(
660 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
663 * TBD: Consider a common Siena/Huntington function. The code is
664 * essentially identical.
669 for (id = 0; id < TX_NQSTATS; id++) {
670 efsys_stat_t *essp = &stat[id];
672 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
673 etp->et_stat[id] = 0;
677 #endif /* EFSYS_OPT_QSTATS */
679 #endif /* EFSYS_OPT_HUNTINGTON */