2 * Copyright (c) 2009-2015 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
42 __in uint32_t mcdi_cap,
43 __out uint32_t *maskp)
48 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10HDX_LBN))
49 mask |= (1 << EFX_PHY_CAP_10HDX);
50 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10FDX_LBN))
51 mask |= (1 << EFX_PHY_CAP_10FDX);
52 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100HDX_LBN))
53 mask |= (1 << EFX_PHY_CAP_100HDX);
54 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_100FDX_LBN))
55 mask |= (1 << EFX_PHY_CAP_100FDX);
56 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000HDX_LBN))
57 mask |= (1 << EFX_PHY_CAP_1000HDX);
58 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_1000FDX_LBN))
59 mask |= (1 << EFX_PHY_CAP_1000FDX);
60 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_10000FDX_LBN))
61 mask |= (1 << EFX_PHY_CAP_10000FDX);
62 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_PAUSE_LBN))
63 mask |= (1 << EFX_PHY_CAP_PAUSE);
64 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_ASYM_LBN))
65 mask |= (1 << EFX_PHY_CAP_ASYM);
66 if (mcdi_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
67 mask |= (1 << EFX_PHY_CAP_AN);
73 siena_phy_decode_link_mode(
75 __in uint32_t link_flags,
76 __in unsigned int speed,
77 __in unsigned int fcntl,
78 __out efx_link_mode_t *link_modep,
79 __out unsigned int *fcntlp)
81 boolean_t fd = !!(link_flags &
82 (1 << MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN));
83 boolean_t up = !!(link_flags &
84 (1 << MC_CMD_GET_LINK_OUT_LINK_UP_LBN));
89 *link_modep = EFX_LINK_DOWN;
90 else if (speed == 10000 && fd)
91 *link_modep = EFX_LINK_10000FDX;
92 else if (speed == 1000)
93 *link_modep = fd ? EFX_LINK_1000FDX : EFX_LINK_1000HDX;
94 else if (speed == 100)
95 *link_modep = fd ? EFX_LINK_100FDX : EFX_LINK_100HDX;
97 *link_modep = fd ? EFX_LINK_10FDX : EFX_LINK_10HDX;
99 *link_modep = EFX_LINK_UNKNOWN;
101 if (fcntl == MC_CMD_FCNTL_OFF)
103 else if (fcntl == MC_CMD_FCNTL_RESPOND)
104 *fcntlp = EFX_FCNTL_RESPOND;
105 else if (fcntl == MC_CMD_FCNTL_BIDIR)
106 *fcntlp = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
108 EFSYS_PROBE1(mc_pcol_error, int, fcntl);
116 __in efx_qword_t *eqp,
117 __out efx_link_mode_t *link_modep)
119 efx_port_t *epp = &(enp->en_port);
120 unsigned int link_flags;
123 efx_link_mode_t link_mode;
124 uint32_t lp_cap_mask;
127 * Convert the LINKCHANGE speed enumeration into mbit/s, in the
128 * same way as GET_LINK encodes the speed
130 switch (MCDI_EV_FIELD(eqp, LINKCHANGE_SPEED)) {
131 case MCDI_EVENT_LINKCHANGE_SPEED_100M:
134 case MCDI_EVENT_LINKCHANGE_SPEED_1G:
137 case MCDI_EVENT_LINKCHANGE_SPEED_10G:
145 link_flags = MCDI_EV_FIELD(eqp, LINKCHANGE_LINK_FLAGS);
146 siena_phy_decode_link_mode(enp, link_flags, speed,
147 MCDI_EV_FIELD(eqp, LINKCHANGE_FCNTL),
149 siena_phy_decode_cap(MCDI_EV_FIELD(eqp, LINKCHANGE_LP_CAP),
153 * It's safe to update ep_lp_cap_mask without the driver's port lock
154 * because presumably any concurrently running efx_port_poll() is
155 * only going to arrive at the same value.
157 * ep_fcntl has two meanings. It's either the link common fcntl
158 * (if the PHY supports AN), or it's the forced link state. If
159 * the former, it's safe to update the value for the same reason as
160 * for ep_lp_cap_mask. If the latter, then just ignore the value,
161 * because we can race with efx_mac_fcntl_set().
163 epp->ep_lp_cap_mask = lp_cap_mask;
164 if (epp->ep_phy_cap_mask & (1 << EFX_PHY_CAP_AN))
165 epp->ep_fcntl = fcntl;
167 *link_modep = link_mode;
173 __in boolean_t power)
180 /* Check if the PHY is a zombie */
181 if ((rc = siena_phy_verify(enp)) != 0)
184 enp->en_reset_flags |= EFX_RESET_PHY;
189 EFSYS_PROBE1(fail1, int, rc);
197 __out siena_link_state_t *slsp)
200 uint8_t payload[MAX(MC_CMD_GET_LINK_IN_LEN,
201 MC_CMD_GET_LINK_OUT_LEN)];
204 (void) memset(payload, 0, sizeof (payload));
205 req.emr_cmd = MC_CMD_GET_LINK;
206 req.emr_in_buf = payload;
207 req.emr_in_length = MC_CMD_GET_LINK_IN_LEN;
208 req.emr_out_buf = payload;
209 req.emr_out_length = MC_CMD_GET_LINK_OUT_LEN;
211 efx_mcdi_execute(enp, &req);
213 if (req.emr_rc != 0) {
218 if (req.emr_out_length_used < MC_CMD_GET_LINK_OUT_LEN) {
223 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_CAP),
224 &slsp->sls_adv_cap_mask);
225 siena_phy_decode_cap(MCDI_OUT_DWORD(req, GET_LINK_OUT_LP_CAP),
226 &slsp->sls_lp_cap_mask);
228 siena_phy_decode_link_mode(enp, MCDI_OUT_DWORD(req, GET_LINK_OUT_FLAGS),
229 MCDI_OUT_DWORD(req, GET_LINK_OUT_LINK_SPEED),
230 MCDI_OUT_DWORD(req, GET_LINK_OUT_FCNTL),
231 &slsp->sls_link_mode, &slsp->sls_fcntl);
233 #if EFSYS_OPT_LOOPBACK
234 /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespace agree */
235 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_NONE == EFX_LOOPBACK_OFF);
236 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_DATA == EFX_LOOPBACK_DATA);
237 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMAC == EFX_LOOPBACK_GMAC);
238 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGMII == EFX_LOOPBACK_XGMII);
239 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGXS == EFX_LOOPBACK_XGXS);
240 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI == EFX_LOOPBACK_XAUI);
241 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII == EFX_LOOPBACK_GMII);
242 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII == EFX_LOOPBACK_SGMII);
243 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XGBR == EFX_LOOPBACK_XGBR);
244 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI == EFX_LOOPBACK_XFI);
245 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XAUI_FAR == EFX_LOOPBACK_XAUI_FAR);
246 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GMII_FAR == EFX_LOOPBACK_GMII_FAR);
247 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_SGMII_FAR == EFX_LOOPBACK_SGMII_FAR);
248 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_XFI_FAR == EFX_LOOPBACK_XFI_FAR);
249 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_GPHY == EFX_LOOPBACK_GPHY);
250 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PHYXS == EFX_LOOPBACK_PHY_XS);
251 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PCS == EFX_LOOPBACK_PCS);
252 EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_PMAPMD == EFX_LOOPBACK_PMA_PMD);
254 slsp->sls_loopback = MCDI_OUT_DWORD(req, GET_LINK_OUT_LOOPBACK_MODE);
255 #endif /* EFSYS_OPT_LOOPBACK */
257 slsp->sls_mac_up = MCDI_OUT_DWORD(req, GET_LINK_OUT_MAC_FAULT) == 0;
264 EFSYS_PROBE1(fail1, int, rc);
270 siena_phy_reconfigure(
273 efx_port_t *epp = &(enp->en_port);
275 uint8_t payload[MAX(MAX(MC_CMD_SET_ID_LED_IN_LEN,
276 MC_CMD_SET_ID_LED_OUT_LEN),
277 MAX(MC_CMD_SET_LINK_IN_LEN,
278 MC_CMD_SET_LINK_OUT_LEN))];
280 unsigned int led_mode;
284 (void) memset(payload, 0, sizeof (payload));
285 req.emr_cmd = MC_CMD_SET_LINK;
286 req.emr_in_buf = payload;
287 req.emr_in_length = MC_CMD_SET_LINK_IN_LEN;
288 req.emr_out_buf = payload;
289 req.emr_out_length = MC_CMD_SET_LINK_OUT_LEN;
291 cap_mask = epp->ep_adv_cap_mask;
292 MCDI_IN_POPULATE_DWORD_10(req, SET_LINK_IN_CAP,
293 PHY_CAP_10HDX, (cap_mask >> EFX_PHY_CAP_10HDX) & 0x1,
294 PHY_CAP_10FDX, (cap_mask >> EFX_PHY_CAP_10FDX) & 0x1,
295 PHY_CAP_100HDX, (cap_mask >> EFX_PHY_CAP_100HDX) & 0x1,
296 PHY_CAP_100FDX, (cap_mask >> EFX_PHY_CAP_100FDX) & 0x1,
297 PHY_CAP_1000HDX, (cap_mask >> EFX_PHY_CAP_1000HDX) & 0x1,
298 PHY_CAP_1000FDX, (cap_mask >> EFX_PHY_CAP_1000FDX) & 0x1,
299 PHY_CAP_10000FDX, (cap_mask >> EFX_PHY_CAP_10000FDX) & 0x1,
300 PHY_CAP_PAUSE, (cap_mask >> EFX_PHY_CAP_PAUSE) & 0x1,
301 PHY_CAP_ASYM, (cap_mask >> EFX_PHY_CAP_ASYM) & 0x1,
302 PHY_CAP_AN, (cap_mask >> EFX_PHY_CAP_AN) & 0x1);
304 #if EFSYS_OPT_LOOPBACK
305 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE,
306 epp->ep_loopback_type);
307 switch (epp->ep_loopback_link_mode) {
308 case EFX_LINK_100FDX:
311 case EFX_LINK_1000FDX:
314 case EFX_LINK_10000FDX:
321 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_MODE, MC_CMD_LOOPBACK_NONE);
323 #endif /* EFSYS_OPT_LOOPBACK */
324 MCDI_IN_SET_DWORD(req, SET_LINK_IN_LOOPBACK_SPEED, speed);
326 #if EFSYS_OPT_PHY_FLAGS
327 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, epp->ep_phy_flags);
329 MCDI_IN_SET_DWORD(req, SET_LINK_IN_FLAGS, 0);
330 #endif /* EFSYS_OPT_PHY_FLAGS */
332 efx_mcdi_execute(enp, &req);
334 if (req.emr_rc != 0) {
339 /* And set the blink mode */
340 (void) memset(payload, 0, sizeof (payload));
341 req.emr_cmd = MC_CMD_SET_ID_LED;
342 req.emr_in_buf = payload;
343 req.emr_in_length = MC_CMD_SET_ID_LED_IN_LEN;
344 req.emr_out_buf = payload;
345 req.emr_out_length = MC_CMD_SET_ID_LED_OUT_LEN;
347 #if EFSYS_OPT_PHY_LED_CONTROL
348 switch (epp->ep_phy_led_mode) {
349 case EFX_PHY_LED_DEFAULT:
350 led_mode = MC_CMD_LED_DEFAULT;
352 case EFX_PHY_LED_OFF:
353 led_mode = MC_CMD_LED_OFF;
356 led_mode = MC_CMD_LED_ON;
360 led_mode = MC_CMD_LED_DEFAULT;
363 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, led_mode);
365 MCDI_IN_SET_DWORD(req, SET_ID_LED_IN_STATE, MC_CMD_LED_DEFAULT);
366 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
368 efx_mcdi_execute(enp, &req);
370 if (req.emr_rc != 0) {
380 EFSYS_PROBE1(fail1, int, rc);
390 uint8_t payload[MAX(MC_CMD_GET_PHY_STATE_IN_LEN,
391 MC_CMD_GET_PHY_STATE_OUT_LEN)];
395 (void) memset(payload, 0, sizeof (payload));
396 req.emr_cmd = MC_CMD_GET_PHY_STATE;
397 req.emr_in_buf = payload;
398 req.emr_in_length = MC_CMD_GET_PHY_STATE_IN_LEN;
399 req.emr_out_buf = payload;
400 req.emr_out_length = MC_CMD_GET_PHY_STATE_OUT_LEN;
402 efx_mcdi_execute(enp, &req);
404 if (req.emr_rc != 0) {
409 if (req.emr_out_length_used < MC_CMD_GET_PHY_STATE_OUT_LEN) {
414 state = MCDI_OUT_DWORD(req, GET_PHY_STATE_OUT_STATE);
415 if (state != MC_CMD_PHY_STATE_OK) {
416 if (state != MC_CMD_PHY_STATE_ZOMBIE)
417 EFSYS_PROBE1(mc_pcol_error, int, state);
429 EFSYS_PROBE1(fail1, int, rc);
437 __out uint32_t *ouip)
439 _NOTE(ARGUNUSED(enp, ouip))
444 #if EFSYS_OPT_PHY_STATS
446 #define SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
447 _mc_record, _efx_record) \
448 if ((_vmask) & (1ULL << (_mc_record))) { \
449 (_smask) |= (1ULL << (_efx_record)); \
450 if ((_stat) != NULL && !EFSYS_MEM_IS_NULL(_esmp)) { \
452 EFSYS_MEM_READD(_esmp, (_mc_record) * 4, &dword);\
453 (_stat)[_efx_record] = \
454 EFX_DWORD_FIELD(dword, EFX_DWORD_0); \
458 #define SIENA_SIMPLE_STAT_SET2(_vmask, _esmp, _smask, _stat, _record) \
459 SIENA_SIMPLE_STAT_SET(_vmask, _esmp, _smask, _stat, \
460 MC_CMD_ ## _record, \
461 EFX_PHY_STAT_ ## _record)
464 siena_phy_decode_stats(
467 __in_opt efsys_mem_t *esmp,
468 __out_opt uint64_t *smaskp,
469 __out_ecount_opt(EFX_PHY_NSTATS) uint32_t *stat)
473 _NOTE(ARGUNUSED(enp))
475 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, OUI);
476 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_LINK_UP);
477 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_RX_FAULT);
478 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PMA_PMD_TX_FAULT);
480 if (vmask & (1 << MC_CMD_PMA_PMD_SIGNAL)) {
481 smask |= ((1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_A) |
482 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_B) |
483 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_C) |
484 (1ULL << EFX_PHY_STAT_PMA_PMD_SIGNAL_D));
485 if (stat != NULL && esmp != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
488 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PMA_PMD_SIGNAL,
490 sig = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
491 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_A] = (sig >> 1) & 1;
492 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_B] = (sig >> 2) & 1;
493 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_C] = (sig >> 3) & 1;
494 stat[EFX_PHY_STAT_PMA_PMD_SIGNAL_D] = (sig >> 4) & 1;
498 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_A,
500 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_B,
502 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_C,
504 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PMA_PMD_SNR_D,
507 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_LINK_UP);
508 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_RX_FAULT);
509 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_TX_FAULT);
510 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BER);
511 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, PCS_BLOCK_ERRORS);
513 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_LINK_UP,
514 EFX_PHY_STAT_PHY_XS_LINK_UP);
515 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_RX_FAULT,
516 EFX_PHY_STAT_PHY_XS_RX_FAULT);
517 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_TX_FAULT,
518 EFX_PHY_STAT_PHY_XS_TX_FAULT);
519 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_PHYXS_ALIGN,
520 EFX_PHY_STAT_PHY_XS_ALIGN);
522 if (vmask & (1 << MC_CMD_PHYXS_SYNC)) {
523 smask |= ((1 << EFX_PHY_STAT_PHY_XS_SYNC_A) |
524 (1 << EFX_PHY_STAT_PHY_XS_SYNC_B) |
525 (1 << EFX_PHY_STAT_PHY_XS_SYNC_C) |
526 (1 << EFX_PHY_STAT_PHY_XS_SYNC_D));
527 if (stat != NULL && !EFSYS_MEM_IS_NULL(esmp)) {
530 EFSYS_MEM_READD(esmp, 4 * MC_CMD_PHYXS_SYNC, &dword);
531 sync = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
532 stat[EFX_PHY_STAT_PHY_XS_SYNC_A] = (sync >> 0) & 1;
533 stat[EFX_PHY_STAT_PHY_XS_SYNC_B] = (sync >> 1) & 1;
534 stat[EFX_PHY_STAT_PHY_XS_SYNC_C] = (sync >> 2) & 1;
535 stat[EFX_PHY_STAT_PHY_XS_SYNC_D] = (sync >> 3) & 1;
539 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_LINK_UP);
540 SIENA_SIMPLE_STAT_SET2(vmask, esmp, smask, stat, AN_COMPLETE);
542 SIENA_SIMPLE_STAT_SET(vmask, esmp, smask, stat, MC_CMD_CL22_LINK_UP,
543 EFX_PHY_STAT_CL22EXT_LINK_UP);
550 siena_phy_stats_update(
552 __in efsys_mem_t *esmp,
553 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat)
555 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
556 uint32_t vmask = encp->enc_mcdi_phy_stat_mask;
559 uint8_t payload[MAX(MC_CMD_PHY_STATS_IN_LEN,
560 MC_CMD_PHY_STATS_OUT_DMA_LEN)];
563 (void) memset(payload, 0, sizeof (payload));
564 req.emr_cmd = MC_CMD_PHY_STATS;
565 req.emr_in_buf = payload;
566 req.emr_in_length = MC_CMD_PHY_STATS_IN_LEN;
567 req.emr_out_buf = payload;
568 req.emr_out_length = MC_CMD_PHY_STATS_OUT_DMA_LEN;
570 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_LO,
571 EFSYS_MEM_ADDR(esmp) & 0xffffffff);
572 MCDI_IN_SET_DWORD(req, PHY_STATS_IN_DMA_ADDR_HI,
573 EFSYS_MEM_ADDR(esmp) >> 32);
575 efx_mcdi_execute(enp, &req);
577 if (req.emr_rc != 0) {
581 EFSYS_ASSERT3U(req.emr_out_length, ==, MC_CMD_PHY_STATS_OUT_DMA_LEN);
583 siena_phy_decode_stats(enp, vmask, esmp, &smask, stat);
584 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask);
589 EFSYS_PROBE1(fail1, int, rc);
594 #endif /* EFSYS_OPT_PHY_STATS */
596 #if EFSYS_OPT_PHY_PROPS
603 __in unsigned int id)
605 _NOTE(ARGUNUSED(enp, id))
610 #endif /* EFSYS_OPT_NAMES */
612 extern __checkReturn int
615 __in unsigned int id,
617 __out uint32_t *valp)
619 _NOTE(ARGUNUSED(enp, id, flags, valp))
624 extern __checkReturn int
627 __in unsigned int id,
630 _NOTE(ARGUNUSED(enp, id, val))
635 #endif /* EFSYS_OPT_PHY_PROPS */
640 siena_phy_bist_start(
642 __in efx_bist_type_t type)
646 if ((rc = efx_mcdi_bist_start(enp, type)) != 0)
652 EFSYS_PROBE1(fail1, int, rc);
657 static __checkReturn unsigned long
658 siena_phy_sft9001_bist_status(
662 case MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY:
663 return (EFX_PHY_CABLE_STATUS_BUSY);
664 case MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT:
665 return (EFX_PHY_CABLE_STATUS_INTERPAIRSHORT);
666 case MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT:
667 return (EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT);
668 case MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN:
669 return (EFX_PHY_CABLE_STATUS_OPEN);
670 case MC_CMD_POLL_BIST_SFT9001_PAIR_OK:
671 return (EFX_PHY_CABLE_STATUS_OK);
673 return (EFX_PHY_CABLE_STATUS_INVALID);
680 __in efx_bist_type_t type,
681 __out efx_bist_result_t *resultp,
682 __out_opt __drv_when(count > 0, __notnull)
683 uint32_t *value_maskp,
684 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
685 unsigned long *valuesp,
688 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
689 uint8_t payload[MAX(MC_CMD_POLL_BIST_IN_LEN,
690 MCDI_CTL_SDU_LEN_MAX)];
691 uint32_t value_mask = 0;
696 (void) memset(payload, 0, sizeof (payload));
697 req.emr_cmd = MC_CMD_POLL_BIST;
698 req.emr_in_buf = payload;
699 req.emr_in_length = MC_CMD_POLL_BIST_IN_LEN;
700 req.emr_out_buf = payload;
701 req.emr_out_length = MCDI_CTL_SDU_LEN_MAX;
703 efx_mcdi_execute(enp, &req);
705 if (req.emr_rc != 0) {
710 if (req.emr_out_length_used < MC_CMD_POLL_BIST_OUT_RESULT_OFST + 4) {
716 (void) memset(valuesp, '\0', count * sizeof (unsigned long));
718 result = MCDI_OUT_DWORD(req, POLL_BIST_OUT_RESULT);
720 /* Extract PHY specific results */
721 if (result == MC_CMD_POLL_BIST_PASSED &&
722 encp->enc_phy_type == EFX_PHY_SFT9001B &&
723 req.emr_out_length_used >= MC_CMD_POLL_BIST_OUT_SFT9001_LEN &&
724 (type == EFX_BIST_TYPE_PHY_CABLE_SHORT ||
725 type == EFX_BIST_TYPE_PHY_CABLE_LONG)) {
728 if (count > EFX_BIST_PHY_CABLE_LENGTH_A) {
730 valuesp[EFX_BIST_PHY_CABLE_LENGTH_A] =
732 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A);
733 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_A);
736 if (count > EFX_BIST_PHY_CABLE_LENGTH_B) {
738 valuesp[EFX_BIST_PHY_CABLE_LENGTH_B] =
740 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B);
741 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_B);
744 if (count > EFX_BIST_PHY_CABLE_LENGTH_C) {
746 valuesp[EFX_BIST_PHY_CABLE_LENGTH_C] =
748 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C);
749 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_C);
752 if (count > EFX_BIST_PHY_CABLE_LENGTH_D) {
754 valuesp[EFX_BIST_PHY_CABLE_LENGTH_D] =
756 POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D);
757 value_mask |= (1 << EFX_BIST_PHY_CABLE_LENGTH_D);
760 if (count > EFX_BIST_PHY_CABLE_STATUS_A) {
761 if (valuesp != NULL) {
762 word = MCDI_OUT_WORD(req,
763 POLL_BIST_OUT_SFT9001_CABLE_STATUS_A);
764 valuesp[EFX_BIST_PHY_CABLE_STATUS_A] =
765 siena_phy_sft9001_bist_status(word);
767 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_A);
770 if (count > EFX_BIST_PHY_CABLE_STATUS_B) {
771 if (valuesp != NULL) {
772 word = MCDI_OUT_WORD(req,
773 POLL_BIST_OUT_SFT9001_CABLE_STATUS_B);
774 valuesp[EFX_BIST_PHY_CABLE_STATUS_B] =
775 siena_phy_sft9001_bist_status(word);
777 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_B);
780 if (count > EFX_BIST_PHY_CABLE_STATUS_C) {
781 if (valuesp != NULL) {
782 word = MCDI_OUT_WORD(req,
783 POLL_BIST_OUT_SFT9001_CABLE_STATUS_C);
784 valuesp[EFX_BIST_PHY_CABLE_STATUS_C] =
785 siena_phy_sft9001_bist_status(word);
787 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_C);
790 if (count > EFX_BIST_PHY_CABLE_STATUS_D) {
791 if (valuesp != NULL) {
792 word = MCDI_OUT_WORD(req,
793 POLL_BIST_OUT_SFT9001_CABLE_STATUS_D);
794 valuesp[EFX_BIST_PHY_CABLE_STATUS_D] =
795 siena_phy_sft9001_bist_status(word);
797 value_mask |= (1 << EFX_BIST_PHY_CABLE_STATUS_D);
800 } else if (result == MC_CMD_POLL_BIST_FAILED &&
801 encp->enc_phy_type == EFX_PHY_QLX111V &&
802 req.emr_out_length >= MC_CMD_POLL_BIST_OUT_MRSFP_LEN &&
803 count > EFX_BIST_FAULT_CODE) {
805 valuesp[EFX_BIST_FAULT_CODE] =
806 MCDI_OUT_DWORD(req, POLL_BIST_OUT_MRSFP_TEST);
807 value_mask |= 1 << EFX_BIST_FAULT_CODE;
810 if (value_maskp != NULL)
811 *value_maskp = value_mask;
813 EFSYS_ASSERT(resultp != NULL);
814 if (result == MC_CMD_POLL_BIST_RUNNING)
815 *resultp = EFX_BIST_RESULT_RUNNING;
816 else if (result == MC_CMD_POLL_BIST_PASSED)
817 *resultp = EFX_BIST_RESULT_PASSED;
819 *resultp = EFX_BIST_RESULT_FAILED;
826 EFSYS_PROBE1(fail1, int, rc);
834 __in efx_bist_type_t type)
836 /* There is no way to stop BIST on Siena */
837 _NOTE(ARGUNUSED(enp, type))
840 #endif /* EFSYS_OPT_BIST */
842 #endif /* EFSYS_OPT_SIENA */