2 * Copyright (c) 2010-2015 Solarflare Communications Inc.
5 * This software was developed in part by Philip Paeps under contract for
6 * Solarflare Communications, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
19 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
21 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
22 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
27 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * The views and conclusions contained in the software and documentation are
30 * those of the authors and should not be interpreted as representing official
31 * policies, either expressed or implied, of the FreeBSD Project.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/types.h>
38 #include <sys/limits.h>
39 #include <net/ethernet.h>
40 #include <net/if_dl.h>
42 #include "common/efx.h"
46 static int sfxge_phy_cap_mask(struct sfxge_softc *, int, uint32_t *);
49 sfxge_mac_stat_update(struct sfxge_softc *sc)
51 struct sfxge_port *port = &sc->port;
52 efsys_mem_t *esmp = &(port->mac_stats.dma_buf);
57 SFXGE_PORT_LOCK_ASSERT_OWNED(port);
59 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) {
65 if (now - port->mac_stats.update_time < hz) {
70 port->mac_stats.update_time = now;
72 /* If we're unlucky enough to read statistics wduring the DMA, wait
73 * up to 10ms for it to finish (typically takes <500us) */
74 for (count = 0; count < 100; ++count) {
75 EFSYS_PROBE1(wait, unsigned int, count);
77 /* Try to update the cached counters */
78 if ((rc = efx_mac_stats_update(sc->enp, esmp,
79 port->mac_stats.decode_buf, NULL)) != EAGAIN)
91 sfxge_mac_stat_handler(SYSCTL_HANDLER_ARGS)
93 struct sfxge_softc *sc = arg1;
94 unsigned int id = arg2;
98 SFXGE_PORT_LOCK(&sc->port);
99 if ((rc = sfxge_mac_stat_update(sc)) == 0)
100 val = ((uint64_t *)sc->port.mac_stats.decode_buf)[id];
101 SFXGE_PORT_UNLOCK(&sc->port);
104 rc = SYSCTL_OUT(req, &val, sizeof(val));
109 sfxge_mac_stat_init(struct sfxge_softc *sc)
111 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
112 struct sysctl_oid_list *stat_list;
116 stat_list = SYSCTL_CHILDREN(sc->stats_node);
118 /* Initialise the named stats */
119 for (id = 0; id < EFX_MAC_NSTATS; id++) {
120 name = efx_mac_stat_name(sc->enp, id);
123 OID_AUTO, name, CTLTYPE_U64|CTLFLAG_RD,
124 sc, id, sfxge_mac_stat_handler, "Q",
129 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
132 sfxge_port_wanted_fc(struct sfxge_softc *sc)
134 struct ifmedia_entry *ifm = sc->media.ifm_cur;
136 if (ifm->ifm_media == (IFM_ETHER | IFM_AUTO))
137 return (EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE);
138 return (((ifm->ifm_media & IFM_ETH_RXPAUSE) ? EFX_FCNTL_RESPOND : 0) |
139 ((ifm->ifm_media & IFM_ETH_TXPAUSE) ? EFX_FCNTL_GENERATE : 0));
143 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
145 unsigned int wanted_fc, link_fc;
147 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
148 return ((link_fc & EFX_FCNTL_RESPOND) ? IFM_ETH_RXPAUSE : 0) |
149 ((link_fc & EFX_FCNTL_GENERATE) ? IFM_ETH_TXPAUSE : 0);
152 #else /* !SFXGE_HAVE_PAUSE_MEDIAOPTS */
155 sfxge_port_wanted_fc(struct sfxge_softc *sc)
157 return (sc->port.wanted_fc);
161 sfxge_port_link_fc_ifm(struct sfxge_softc *sc)
167 sfxge_port_wanted_fc_handler(SYSCTL_HANDLER_ARGS)
169 struct sfxge_softc *sc;
170 struct sfxge_port *port;
177 if (req->newptr != NULL) {
178 if ((error = SYSCTL_IN(req, &fcntl, sizeof(fcntl))) != 0)
181 SFXGE_PORT_LOCK(port);
183 if (port->wanted_fc != fcntl) {
184 if (port->init_state == SFXGE_PORT_STARTED)
185 error = efx_mac_fcntl_set(sc->enp,
189 port->wanted_fc = fcntl;
192 SFXGE_PORT_UNLOCK(port);
194 SFXGE_PORT_LOCK(port);
195 fcntl = port->wanted_fc;
196 SFXGE_PORT_UNLOCK(port);
198 error = SYSCTL_OUT(req, &fcntl, sizeof(fcntl));
205 sfxge_port_link_fc_handler(SYSCTL_HANDLER_ARGS)
207 struct sfxge_softc *sc;
208 struct sfxge_port *port;
209 unsigned int wanted_fc, link_fc;
214 SFXGE_PORT_LOCK(port);
215 if (__predict_true(port->init_state == SFXGE_PORT_STARTED) &&
217 efx_mac_fcntl_get(sc->enp, &wanted_fc, &link_fc);
220 SFXGE_PORT_UNLOCK(port);
222 return (SYSCTL_OUT(req, &link_fc, sizeof(link_fc)));
225 #endif /* SFXGE_HAVE_PAUSE_MEDIAOPTS */
227 static const uint64_t sfxge_link_baudrate[EFX_LINK_NMODES] = {
228 [EFX_LINK_10HDX] = IF_Mbps(10),
229 [EFX_LINK_10FDX] = IF_Mbps(10),
230 [EFX_LINK_100HDX] = IF_Mbps(100),
231 [EFX_LINK_100FDX] = IF_Mbps(100),
232 [EFX_LINK_1000HDX] = IF_Gbps(1),
233 [EFX_LINK_1000FDX] = IF_Gbps(1),
234 [EFX_LINK_10000FDX] = IF_Gbps(10),
235 [EFX_LINK_40000FDX] = IF_Gbps(40),
239 sfxge_mac_link_update(struct sfxge_softc *sc, efx_link_mode_t mode)
241 struct sfxge_port *port;
246 if (port->link_mode == mode)
249 port->link_mode = mode;
251 /* Push link state update to the OS */
252 link_state = (port->link_mode != EFX_LINK_DOWN ?
253 LINK_STATE_UP : LINK_STATE_DOWN);
254 if_initbaudrate(sc->ifnet, sfxge_link_baudrate[port->link_mode]);
255 if_link_state_change(sc->ifnet, link_state);
259 sfxge_mac_poll_work(void *arg, int npending)
261 struct sfxge_softc *sc;
263 struct sfxge_port *port;
264 efx_link_mode_t mode;
266 sc = (struct sfxge_softc *)arg;
270 SFXGE_PORT_LOCK(port);
272 if (__predict_false(port->init_state != SFXGE_PORT_STARTED))
275 /* This may sleep waiting for MCDI completion */
276 (void)efx_port_poll(enp, &mode);
277 sfxge_mac_link_update(sc, mode);
280 SFXGE_PORT_UNLOCK(port);
284 sfxge_mac_multicast_list_set(struct sfxge_softc *sc)
286 struct ifnet *ifp = sc->ifnet;
287 struct sfxge_port *port = &sc->port;
288 uint8_t *mcast_addr = port->mcast_addrs;
289 struct ifmultiaddr *ifma;
290 struct sockaddr_dl *sa;
293 mtx_assert(&port->lock, MA_OWNED);
295 port->mcast_count = 0;
297 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
298 if (ifma->ifma_addr->sa_family == AF_LINK) {
299 if (port->mcast_count == EFX_MAC_MULTICAST_LIST_MAX) {
300 device_printf(sc->dev,
301 "Too many multicast addresses\n");
306 sa = (struct sockaddr_dl *)ifma->ifma_addr;
307 memcpy(mcast_addr, LLADDR(sa), EFX_MAC_ADDR_LEN);
308 mcast_addr += EFX_MAC_ADDR_LEN;
312 if_maddr_runlock(ifp);
315 rc = efx_mac_multicast_list_set(sc->enp, port->mcast_addrs,
318 device_printf(sc->dev,
319 "Cannot set multicast address list\n");
326 sfxge_mac_filter_set_locked(struct sfxge_softc *sc)
328 struct ifnet *ifp = sc->ifnet;
329 struct sfxge_port *port = &sc->port;
330 boolean_t all_mulcst;
333 mtx_assert(&port->lock, MA_OWNED);
335 all_mulcst = !!(ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI));
337 rc = sfxge_mac_multicast_list_set(sc);
338 /* Fallback to all multicast if cannot set multicast list */
342 rc = efx_mac_filter_set(sc->enp, !!(ifp->if_flags & IFF_PROMISC),
343 (port->mcast_count > 0), all_mulcst, B_TRUE);
349 sfxge_mac_filter_set(struct sfxge_softc *sc)
351 struct sfxge_port *port = &sc->port;
354 SFXGE_PORT_LOCK(port);
356 * The function may be called without softc_lock held in the
357 * case of SIOCADDMULTI and SIOCDELMULTI ioctls. ioctl handler
358 * checks IFF_DRV_RUNNING flag which implies port started, but
359 * it is not guaranteed to remain. softc_lock shared lock can't
360 * be held in the case of these ioctls processing, since it
361 * results in failure where kernel complains that non-sleepable
362 * lock is held in sleeping thread. Both problems are repeatable
363 * on LAG with LACP proto bring up.
365 if (__predict_true(port->init_state == SFXGE_PORT_STARTED))
366 rc = sfxge_mac_filter_set_locked(sc);
369 SFXGE_PORT_UNLOCK(port);
374 sfxge_port_stop(struct sfxge_softc *sc)
376 struct sfxge_port *port;
382 SFXGE_PORT_LOCK(port);
384 KASSERT(port->init_state == SFXGE_PORT_STARTED,
385 ("port not started"));
387 port->init_state = SFXGE_PORT_INITIALIZED;
389 port->mac_stats.update_time = 0;
391 /* This may call MCDI */
392 (void)efx_mac_drain(enp, B_TRUE);
394 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE);
396 port->link_mode = EFX_LINK_UNKNOWN;
398 /* Destroy the common code port object. */
401 efx_filter_fini(enp);
403 SFXGE_PORT_UNLOCK(port);
407 sfxge_port_start(struct sfxge_softc *sc)
409 uint8_t mac_addr[ETHER_ADDR_LEN];
410 struct ifnet *ifp = sc->ifnet;
411 struct sfxge_port *port;
415 uint32_t phy_cap_mask;
420 SFXGE_PORT_LOCK(port);
422 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
423 ("port not initialized"));
425 /* Initialise the required filtering */
426 if ((rc = efx_filter_init(enp)) != 0)
427 goto fail_filter_init;
429 /* Initialize the port object in the common code. */
430 if ((rc = efx_port_init(sc->enp)) != 0)
434 pdu = EFX_MAC_PDU(ifp->if_mtu);
435 if ((rc = efx_mac_pdu_set(enp, pdu)) != 0)
438 if ((rc = efx_mac_fcntl_set(enp, sfxge_port_wanted_fc(sc), B_TRUE))
442 /* Set the unicast address */
444 bcopy(LLADDR((struct sockaddr_dl *)ifp->if_addr->ifa_addr),
445 mac_addr, sizeof(mac_addr));
446 if_addr_runlock(ifp);
447 if ((rc = efx_mac_addr_set(enp, mac_addr)) != 0)
450 sfxge_mac_filter_set_locked(sc);
452 /* Update MAC stats by DMA every second */
453 if ((rc = efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf,
454 1000, B_FALSE)) != 0)
457 if ((rc = efx_mac_drain(enp, B_FALSE)) != 0)
460 if ((rc = sfxge_phy_cap_mask(sc, sc->media.ifm_cur->ifm_media,
461 &phy_cap_mask)) != 0)
464 if ((rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask)) != 0)
467 port->init_state = SFXGE_PORT_STARTED;
469 /* Single poll in case there were missing initial events */
470 SFXGE_PORT_UNLOCK(port);
471 sfxge_mac_poll_work(sc, 0);
477 (void)efx_mac_drain(enp, B_TRUE);
479 (void)efx_mac_stats_periodic(enp, &port->mac_stats.dma_buf, 0, B_FALSE);
487 efx_filter_fini(enp);
489 SFXGE_PORT_UNLOCK(port);
495 sfxge_phy_stat_update(struct sfxge_softc *sc)
497 struct sfxge_port *port = &sc->port;
498 efsys_mem_t *esmp = &port->phy_stats.dma_buf;
503 SFXGE_PORT_LOCK_ASSERT_OWNED(port);
505 if (__predict_false(port->init_state != SFXGE_PORT_STARTED)) {
511 if (now - port->phy_stats.update_time < hz) {
516 port->phy_stats.update_time = now;
518 /* If we're unlucky enough to read statistics wduring the DMA, wait
519 * up to 10ms for it to finish (typically takes <500us) */
520 for (count = 0; count < 100; ++count) {
521 EFSYS_PROBE1(wait, unsigned int, count);
523 /* Synchronize the DMA memory for reading */
524 bus_dmamap_sync(esmp->esm_tag, esmp->esm_map,
525 BUS_DMASYNC_POSTREAD);
527 /* Try to update the cached counters */
528 if ((rc = efx_phy_stats_update(sc->enp, esmp,
529 port->phy_stats.decode_buf)) != EAGAIN)
541 sfxge_phy_stat_handler(SYSCTL_HANDLER_ARGS)
543 struct sfxge_softc *sc = arg1;
544 unsigned int id = arg2;
548 SFXGE_PORT_LOCK(&sc->port);
549 if ((rc = sfxge_phy_stat_update(sc)) == 0)
550 val = ((uint32_t *)sc->port.phy_stats.decode_buf)[id];
551 SFXGE_PORT_UNLOCK(&sc->port);
554 rc = SYSCTL_OUT(req, &val, sizeof(val));
559 sfxge_phy_stat_init(struct sfxge_softc *sc)
561 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->dev);
562 struct sysctl_oid_list *stat_list;
565 uint64_t stat_mask = efx_nic_cfg_get(sc->enp)->enc_phy_stat_mask;
567 stat_list = SYSCTL_CHILDREN(sc->stats_node);
569 /* Initialise the named stats */
570 for (id = 0; id < EFX_PHY_NSTATS; id++) {
571 if (!(stat_mask & ((uint64_t)1 << id)))
573 name = efx_phy_stat_name(sc->enp, id);
576 OID_AUTO, name, CTLTYPE_UINT|CTLFLAG_RD,
577 sc, id, sfxge_phy_stat_handler,
578 id == EFX_PHY_STAT_OUI ? "IX" : "IU",
584 sfxge_port_fini(struct sfxge_softc *sc)
586 struct sfxge_port *port;
590 esmp = &port->mac_stats.dma_buf;
592 KASSERT(port->init_state == SFXGE_PORT_INITIALIZED,
593 ("Port not initialized"));
595 port->init_state = SFXGE_PORT_UNINITIALIZED;
597 port->link_mode = EFX_LINK_UNKNOWN;
599 /* Finish with PHY DMA memory */
600 sfxge_dma_free(&port->phy_stats.dma_buf);
601 free(port->phy_stats.decode_buf, M_SFXGE);
603 sfxge_dma_free(esmp);
604 free(port->mac_stats.decode_buf, M_SFXGE);
606 SFXGE_PORT_LOCK_DESTROY(port);
612 sfxge_port_init(struct sfxge_softc *sc)
614 struct sfxge_port *port;
615 struct sysctl_ctx_list *sysctl_ctx;
616 struct sysctl_oid *sysctl_tree;
617 efsys_mem_t *mac_stats_buf, *phy_stats_buf;
621 mac_stats_buf = &port->mac_stats.dma_buf;
622 phy_stats_buf = &port->phy_stats.dma_buf;
624 KASSERT(port->init_state == SFXGE_PORT_UNINITIALIZED,
625 ("Port already initialized"));
629 SFXGE_PORT_LOCK_INIT(port, device_get_nameunit(sc->dev));
631 DBGPRINT(sc->dev, "alloc PHY stats");
632 port->phy_stats.decode_buf = malloc(EFX_PHY_NSTATS * sizeof(uint32_t),
633 M_SFXGE, M_WAITOK | M_ZERO);
634 if ((rc = sfxge_dma_alloc(sc, EFX_PHY_STATS_SIZE, phy_stats_buf)) != 0)
636 sfxge_phy_stat_init(sc);
638 DBGPRINT(sc->dev, "init sysctl");
639 sysctl_ctx = device_get_sysctl_ctx(sc->dev);
640 sysctl_tree = device_get_sysctl_tree(sc->dev);
642 #ifndef SFXGE_HAVE_PAUSE_MEDIAOPTS
643 /* If flow control cannot be configured or reported through
644 * ifmedia, provide sysctls for it. */
645 port->wanted_fc = EFX_FCNTL_RESPOND | EFX_FCNTL_GENERATE;
646 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
647 "wanted_fc", CTLTYPE_UINT|CTLFLAG_RW, sc, 0,
648 sfxge_port_wanted_fc_handler, "IU", "wanted flow control mode");
649 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), OID_AUTO,
650 "link_fc", CTLTYPE_UINT|CTLFLAG_RD, sc, 0,
651 sfxge_port_link_fc_handler, "IU", "link flow control mode");
654 DBGPRINT(sc->dev, "alloc MAC stats");
655 port->mac_stats.decode_buf = malloc(EFX_MAC_NSTATS * sizeof(uint64_t),
656 M_SFXGE, M_WAITOK | M_ZERO);
657 if ((rc = sfxge_dma_alloc(sc, EFX_MAC_STATS_SIZE, mac_stats_buf)) != 0)
659 sfxge_mac_stat_init(sc);
661 port->init_state = SFXGE_PORT_INITIALIZED;
663 DBGPRINT(sc->dev, "success");
667 free(port->mac_stats.decode_buf, M_SFXGE);
668 sfxge_dma_free(phy_stats_buf);
670 free(port->phy_stats.decode_buf, M_SFXGE);
671 SFXGE_PORT_LOCK_DESTROY(port);
673 DBGPRINT(sc->dev, "failed %d", rc);
677 static const int sfxge_link_mode[EFX_PHY_MEDIA_NTYPES][EFX_LINK_NMODES] = {
678 [EFX_PHY_MEDIA_CX4] = {
679 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_CX4,
681 [EFX_PHY_MEDIA_KX4] = {
682 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_KX4,
684 [EFX_PHY_MEDIA_XFP] = {
685 /* Don't know the module type, but assume SR for now. */
686 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
688 [EFX_PHY_MEDIA_QSFP_PLUS] = {
689 /* Don't know the module type, but assume SR for now. */
690 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
691 [EFX_LINK_40000FDX] = IFM_ETHER | IFM_FDX | IFM_40G_CR4,
693 [EFX_PHY_MEDIA_SFP_PLUS] = {
694 /* Don't know the module type, but assume SX/SR for now. */
695 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_SX,
696 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_SR,
698 [EFX_PHY_MEDIA_BASE_T] = {
699 [EFX_LINK_10HDX] = IFM_ETHER | IFM_HDX | IFM_10_T,
700 [EFX_LINK_10FDX] = IFM_ETHER | IFM_FDX | IFM_10_T,
701 [EFX_LINK_100HDX] = IFM_ETHER | IFM_HDX | IFM_100_TX,
702 [EFX_LINK_100FDX] = IFM_ETHER | IFM_FDX | IFM_100_TX,
703 [EFX_LINK_1000HDX] = IFM_ETHER | IFM_HDX | IFM_1000_T,
704 [EFX_LINK_1000FDX] = IFM_ETHER | IFM_FDX | IFM_1000_T,
705 [EFX_LINK_10000FDX] = IFM_ETHER | IFM_FDX | IFM_10G_T,
710 sfxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
712 struct sfxge_softc *sc;
713 efx_phy_media_type_t medium_type;
714 efx_link_mode_t mode;
717 SFXGE_ADAPTER_LOCK(sc);
719 ifmr->ifm_status = IFM_AVALID;
720 ifmr->ifm_active = IFM_ETHER;
722 if (SFXGE_RUNNING(sc) && SFXGE_LINK_UP(sc)) {
723 ifmr->ifm_status |= IFM_ACTIVE;
725 efx_phy_media_type_get(sc->enp, &medium_type);
726 mode = sc->port.link_mode;
727 ifmr->ifm_active |= sfxge_link_mode[medium_type][mode];
728 ifmr->ifm_active |= sfxge_port_link_fc_ifm(sc);
731 SFXGE_ADAPTER_UNLOCK(sc);
734 static efx_phy_cap_type_t
735 sfxge_link_mode_to_phy_cap(efx_link_mode_t mode)
739 return (EFX_PHY_CAP_10HDX);
741 return (EFX_PHY_CAP_10FDX);
742 case EFX_LINK_100HDX:
743 return (EFX_PHY_CAP_100HDX);
744 case EFX_LINK_100FDX:
745 return (EFX_PHY_CAP_100FDX);
746 case EFX_LINK_1000HDX:
747 return (EFX_PHY_CAP_1000HDX);
748 case EFX_LINK_1000FDX:
749 return (EFX_PHY_CAP_1000FDX);
750 case EFX_LINK_10000FDX:
751 return (EFX_PHY_CAP_10000FDX);
752 case EFX_LINK_40000FDX:
753 return (EFX_PHY_CAP_40000FDX);
755 EFSYS_ASSERT(B_FALSE);
756 return (EFX_PHY_CAP_INVALID);
761 sfxge_phy_cap_mask(struct sfxge_softc *sc, int ifmedia, uint32_t *phy_cap_mask)
763 /* Get global options (duplex), type and subtype bits */
764 int ifmedia_masked = ifmedia & (IFM_GMASK | IFM_NMASK | IFM_TMASK);
765 efx_phy_media_type_t medium_type;
766 boolean_t mode_found = B_FALSE;
767 uint32_t cap_mask, mode_cap_mask;
768 efx_link_mode_t mode;
769 efx_phy_cap_type_t phy_cap;
771 efx_phy_media_type_get(sc->enp, &medium_type);
772 if (medium_type >= nitems(sfxge_link_mode)) {
773 if_printf(sc->ifnet, "unexpected media type %d\n", medium_type);
777 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask);
779 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) {
780 if (ifmedia_masked == sfxge_link_mode[medium_type][mode]) {
788 * If media is not in the table, it must be IFM_AUTO.
790 KASSERT((cap_mask & (1 << EFX_PHY_CAP_AN)) &&
791 ifmedia_masked == (IFM_ETHER | IFM_AUTO),
792 ("%s: no mode for media %#x", __func__, ifmedia));
793 *phy_cap_mask = (cap_mask & ~(1 << EFX_PHY_CAP_ASYM));
797 phy_cap = sfxge_link_mode_to_phy_cap(mode);
798 if (phy_cap == EFX_PHY_CAP_INVALID) {
800 "cannot map link mode %d to phy capability\n",
805 mode_cap_mask = (1 << phy_cap);
806 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_AN);
807 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
808 if (ifmedia & IFM_ETH_RXPAUSE)
809 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE);
810 if (!(ifmedia & IFM_ETH_TXPAUSE))
811 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_ASYM);
813 mode_cap_mask |= cap_mask & (1 << EFX_PHY_CAP_PAUSE);
816 *phy_cap_mask = mode_cap_mask;
821 sfxge_media_change(struct ifnet *ifp)
823 struct sfxge_softc *sc;
824 struct ifmedia_entry *ifm;
826 uint32_t phy_cap_mask;
829 ifm = sc->media.ifm_cur;
831 SFXGE_ADAPTER_LOCK(sc);
833 if (!SFXGE_RUNNING(sc)) {
838 rc = efx_mac_fcntl_set(sc->enp, sfxge_port_wanted_fc(sc), B_TRUE);
842 if ((rc = sfxge_phy_cap_mask(sc, ifm->ifm_media, &phy_cap_mask)) != 0)
845 rc = efx_phy_adv_cap_set(sc->enp, phy_cap_mask);
847 SFXGE_ADAPTER_UNLOCK(sc);
852 int sfxge_port_ifmedia_init(struct sfxge_softc *sc)
854 efx_phy_media_type_t medium_type;
855 uint32_t cap_mask, mode_cap_mask;
856 efx_link_mode_t mode;
857 efx_phy_cap_type_t phy_cap;
858 int mode_ifm, best_mode_ifm = 0;
862 * We need port state to initialise the ifmedia list.
863 * It requires initialized NIC what is already done in
864 * sfxge_create() when resources are estimated.
866 if ((rc = efx_filter_init(sc->enp)) != 0)
868 if ((rc = efx_port_init(sc->enp)) != 0)
872 * Register ifconfig callbacks for querying and setting the
873 * link mode and link status.
875 ifmedia_init(&sc->media, IFM_IMASK, sfxge_media_change,
879 * Map firmware medium type and capabilities to ifmedia types.
880 * ifmedia does not distinguish between forcing the link mode
881 * and disabling auto-negotiation. 1000BASE-T and 10GBASE-T
882 * require AN even if only one link mode is enabled, and for
883 * 100BASE-TX it is useful even if the link mode is forced.
884 * Therefore we never disable auto-negotiation.
886 * Also enable and advertise flow control by default.
889 efx_phy_media_type_get(sc->enp, &medium_type);
890 efx_phy_adv_cap_get(sc->enp, EFX_PHY_CAP_PERM, &cap_mask);
892 for (mode = EFX_LINK_10HDX; mode < EFX_LINK_NMODES; mode++) {
893 phy_cap = sfxge_link_mode_to_phy_cap(mode);
894 if (phy_cap == EFX_PHY_CAP_INVALID)
897 mode_cap_mask = (1 << phy_cap);
898 mode_ifm = sfxge_link_mode[medium_type][mode];
900 if ((cap_mask & mode_cap_mask) && mode_ifm) {
901 /* No flow-control */
902 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
904 #ifdef SFXGE_HAVE_PAUSE_MEDIAOPTS
905 /* Respond-only. If using AN, we implicitly
906 * offer symmetric as well, but that doesn't
907 * mean we *have* to generate pause frames.
909 mode_ifm |= IFM_ETH_RXPAUSE;
910 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
913 mode_ifm |= IFM_ETH_TXPAUSE;
914 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
917 /* Link modes are numbered in order of speed,
918 * so assume the last one available is the best.
920 best_mode_ifm = mode_ifm;
924 if (cap_mask & (1 << EFX_PHY_CAP_AN)) {
925 /* Add autoselect mode. */
926 mode_ifm = IFM_ETHER | IFM_AUTO;
927 ifmedia_add(&sc->media, mode_ifm, 0, NULL);
928 best_mode_ifm = mode_ifm;
931 if (best_mode_ifm != 0)
932 ifmedia_set(&sc->media, best_mode_ifm);
934 /* Now discard port state until interface is started. */
935 efx_port_fini(sc->enp);
937 efx_filter_fini(sc->enp);