sys/dev/sk/if_sk.c

   1 /*      $OpenBSD: if_sk.c,v 2.33 2003/08/12 05:23:06 nate Exp $ */
   2
   3 /*-
   4  * Copyright (c) 1997, 1998, 1999, 2000
   5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement:
  17  *      This product includes software developed by Bill Paul.
  18  * 4. Neither the name of the author nor the names of any co-contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  32  * THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34 /*-
  35  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
  36  *
  37  * Permission to use, copy, modify, and distribute this software for any
  38  * purpose with or without fee is hereby granted, provided that the above
  39  * copyright notice and this permission notice appear in all copies.
  40  *
  41  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  42  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  43  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  44  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  45  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  46  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  47  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  48  */
  49
  50 #include <sys/cdefs.h>
  51 __FBSDID("$FreeBSD$");
  52
  53 /*
  54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
  55  * the SK-984x series adapters, both single port and dual port.
  56  * References:
  57  *      The XaQti XMAC II datasheet,
  58  *  http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
  60  *
  61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
  62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
  63  * convenience to others until Vitesse corrects this problem:
  64  *
  65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
  66  *
  67  * Written by Bill Paul <wpaul@ee.columbia.edu>
  68  * Department of Electrical Engineering
  69  * Columbia University, New York City
  70  */
  71 /*
  72  * The SysKonnect gigabit ethernet adapters consist of two main
  73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
  74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
  75  * components and a PHY while the GEnesis controller provides a PCI
  76  * interface with DMA support. Each card may have between 512K and
  77  * 2MB of SRAM on board depending on the configuration.
  78  *
  79  * The SysKonnect GEnesis controller can have either one or two XMAC
  80  * chips connected to it, allowing single or dual port NIC configurations.
  81  * SysKonnect has the distinction of being the only vendor on the market
  82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
  83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
  84  * XMAC registers. This driver takes advantage of these features to allow
  85  * both XMACs to operate as independent interfaces.
  86  */
  87
  88 #include <sys/param.h>
  89 #include <sys/systm.h>
  90 #include <sys/bus.h>
  91 #include <sys/endian.h>
  92 #include <sys/mbuf.h>
  93 #include <sys/malloc.h>
  94 #include <sys/kernel.h>
  95 #include <sys/module.h>
  96 #include <sys/socket.h>
  97 #include <sys/sockio.h>
  98 #include <sys/queue.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/bpf.h>
 102 #include <net/ethernet.h>
 103 #include <net/if.h>
 104 #include <net/if_arp.h>
 105 #include <net/if_dl.h>
 106 #include <net/if_media.h>
 107 #include <net/if_types.h>
 108 #include <net/if_vlan_var.h>
 109
 110 #include <netinet/in.h>
 111 #include <netinet/in_systm.h>
 112 #include <netinet/ip.h>
 113
 114 #include <machine/bus.h>
 115 #include <machine/in_cksum.h>
 116 #include <machine/resource.h>
 117 #include <sys/rman.h>
 118
 119 #include <dev/mii/mii.h>
 120 #include <dev/mii/miivar.h>
 121 #include <dev/mii/brgphyreg.h>
 122
 123 #include <dev/pci/pcireg.h>
 124 #include <dev/pci/pcivar.h>
 125
 126 #if 0
 127 #define SK_USEIOSPACE
 128 #endif
 129
 130 #include <dev/sk/if_skreg.h>
 131 #include <dev/sk/xmaciireg.h>
 132 #include <dev/sk/yukonreg.h>
 133
 134 MODULE_DEPEND(sk, pci, 1, 1, 1);
 135 MODULE_DEPEND(sk, ether, 1, 1, 1);
 136 MODULE_DEPEND(sk, miibus, 1, 1, 1);
 137
 138 /* "device miibus" required.  See GENERIC if you get errors here. */
 139 #include "miibus_if.h"
 140
 141 static const struct sk_type sk_devs[] = {
 142         {
 143                 VENDORID_SK,
 144                 DEVICEID_SK_V1,
 145                 "SysKonnect Gigabit Ethernet (V1.0)"
 146         },
 147         {
 148                 VENDORID_SK,
 149                 DEVICEID_SK_V2,
 150                 "SysKonnect Gigabit Ethernet (V2.0)"
 151         },
 152         {
 153                 VENDORID_MARVELL,
 154                 DEVICEID_SK_V2,
 155                 "Marvell Gigabit Ethernet"
 156         },
 157         {
 158                 VENDORID_MARVELL,
 159                 DEVICEID_BELKIN_5005,
 160                 "Belkin F5D5005 Gigabit Ethernet"
 161         },
 162         {
 163                 VENDORID_3COM,
 164                 DEVICEID_3COM_3C940,
 165                 "3Com 3C940 Gigabit Ethernet"
 166         },
 167         {
 168                 VENDORID_LINKSYS,
 169                 DEVICEID_LINKSYS_EG1032,
 170                 "Linksys EG1032 Gigabit Ethernet"
 171         },
 172         {
 173                 VENDORID_DLINK,
 174                 DEVICEID_DLINK_DGE530T_A1,
 175                 "D-Link DGE-530T Gigabit Ethernet"
 176         },
 177         {
 178                 VENDORID_DLINK,
 179                 DEVICEID_DLINK_DGE530T_B1,
 180                 "D-Link DGE-530T Gigabit Ethernet"
 181         },
 182         { 0, 0, NULL }
 183 };
 184
 185 static int skc_probe(device_t);
 186 static int skc_attach(device_t);
 187 static int skc_detach(device_t);
 188 static int skc_shutdown(device_t);
 189 static int skc_suspend(device_t);
 190 static int skc_resume(device_t);
 191 static bus_dma_tag_t skc_get_dma_tag(device_t, device_t);
 192 static int sk_detach(device_t);
 193 static int sk_probe(device_t);
 194 static int sk_attach(device_t);
 195 static void sk_tick(void *);
 196 static void sk_yukon_tick(void *);
 197 static void sk_intr(void *);
 198 static void sk_intr_xmac(struct sk_if_softc *);
 199 static void sk_intr_bcom(struct sk_if_softc *);
 200 static void sk_intr_yukon(struct sk_if_softc *);
 201 static __inline void sk_rxcksum(struct ifnet *, struct mbuf *, u_int32_t);
 202 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
 203 static void sk_rxeof(struct sk_if_softc *);
 204 static void sk_jumbo_rxeof(struct sk_if_softc *);
 205 static void sk_txeof(struct sk_if_softc *);
 206 static void sk_txcksum(struct ifnet *, struct mbuf *, struct sk_tx_desc *);
 207 static int sk_encap(struct sk_if_softc *, struct mbuf **);
 208 static void sk_start(struct ifnet *);
 209 static void sk_start_locked(struct ifnet *);
 210 static int sk_ioctl(struct ifnet *, u_long, caddr_t);
 211 static void sk_init(void *);
 212 static void sk_init_locked(struct sk_if_softc *);
 213 static void sk_init_xmac(struct sk_if_softc *);
 214 static void sk_init_yukon(struct sk_if_softc *);
 215 static void sk_stop(struct sk_if_softc *);
 216 static void sk_watchdog(void *);
 217 static int sk_ifmedia_upd(struct ifnet *);
 218 static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 219 static void sk_reset(struct sk_softc *);
 220 static __inline void sk_discard_rxbuf(struct sk_if_softc *, int);
 221 static __inline void sk_discard_jumbo_rxbuf(struct sk_if_softc *, int);
 222 static int sk_newbuf(struct sk_if_softc *, int);
 223 static int sk_jumbo_newbuf(struct sk_if_softc *, int);
 224 static void sk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 225 static int sk_dma_alloc(struct sk_if_softc *);
 226 static int sk_dma_jumbo_alloc(struct sk_if_softc *);
 227 static void sk_dma_free(struct sk_if_softc *);
 228 static void sk_dma_jumbo_free(struct sk_if_softc *);
 229 static int sk_init_rx_ring(struct sk_if_softc *);
 230 static int sk_init_jumbo_rx_ring(struct sk_if_softc *);
 231 static void sk_init_tx_ring(struct sk_if_softc *);
 232 static u_int32_t sk_win_read_4(struct sk_softc *, int);
 233 static u_int16_t sk_win_read_2(struct sk_softc *, int);
 234 static u_int8_t sk_win_read_1(struct sk_softc *, int);
 235 static void sk_win_write_4(struct sk_softc *, int, u_int32_t);
 236 static void sk_win_write_2(struct sk_softc *, int, u_int32_t);
 237 static void sk_win_write_1(struct sk_softc *, int, u_int32_t);
 238
 239 static int sk_miibus_readreg(device_t, int, int);
 240 static int sk_miibus_writereg(device_t, int, int, int);
 241 static void sk_miibus_statchg(device_t);
 242
 243 static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
 244 static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int,
 245                                                 int);
 246 static void sk_xmac_miibus_statchg(struct sk_if_softc *);
 247
 248 static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
 249 static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int,
 250                                                 int);
 251 static void sk_marv_miibus_statchg(struct sk_if_softc *);
 252
 253 static uint32_t sk_xmchash(const uint8_t *);
 254 static void sk_setfilt(struct sk_if_softc *, u_int16_t *, int);
 255 static void sk_rxfilter(struct sk_if_softc *);
 256 static void sk_rxfilter_genesis(struct sk_if_softc *);
 257 static void sk_rxfilter_yukon(struct sk_if_softc *);
 258
 259 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high);
 260 static int sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS);
 261
 262 /* Tunables. */
 263 static int jumbo_disable = 0;
 264 TUNABLE_INT("hw.skc.jumbo_disable", &jumbo_disable);
 265
 266 /*
 267  * It seems that SK-NET GENESIS supports very simple checksum offload
 268  * capability for Tx and I believe it can generate 0 checksum value for
 269  * UDP packets in Tx as the hardware can't differenciate UDP packets from
 270  * TCP packets. 0 chcecksum value for UDP packet is an invalid one as it
 271  * means sender didn't perforam checksum computation. For the safety I
 272  * disabled UDP checksum offload capability at the moment. Alternatively
 273  * we can intrduce a LINK0/LINK1 flag as hme(4) did in its Tx checksum
 274  * offload routine.
 275  */
 276 #define SK_CSUM_FEATURES        (CSUM_TCP)
 277
 278 /*
 279  * Note that we have newbus methods for both the GEnesis controller
 280  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
 281  * the miibus code is a child of the XMACs. We need to do it this way
 282  * so that the miibus drivers can access the PHY registers on the
 283  * right PHY. It's not quite what I had in mind, but it's the only
 284  * design that achieves the desired effect.
 285  */
 286 static device_method_t skc_methods[] = {
 287         /* Device interface */
 288         DEVMETHOD(device_probe,         skc_probe),
 289         DEVMETHOD(device_attach,        skc_attach),
 290         DEVMETHOD(device_detach,        skc_detach),
 291         DEVMETHOD(device_suspend,       skc_suspend),
 292         DEVMETHOD(device_resume,        skc_resume),
 293         DEVMETHOD(device_shutdown,      skc_shutdown),
 294
 295         DEVMETHOD(bus_get_dma_tag,      skc_get_dma_tag),
 296
 297         DEVMETHOD_END
 298 };
 299
 300 static driver_t skc_driver = {
 301         "skc",
 302         skc_methods,
 303         sizeof(struct sk_softc)
 304 };
 305
 306 static devclass_t skc_devclass;
 307
 308 static device_method_t sk_methods[] = {
 309         /* Device interface */
 310         DEVMETHOD(device_probe,         sk_probe),
 311         DEVMETHOD(device_attach,        sk_attach),
 312         DEVMETHOD(device_detach,        sk_detach),
 313         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 314
 315         /* MII interface */
 316         DEVMETHOD(miibus_readreg,       sk_miibus_readreg),
 317         DEVMETHOD(miibus_writereg,      sk_miibus_writereg),
 318         DEVMETHOD(miibus_statchg,       sk_miibus_statchg),
 319
 320         DEVMETHOD_END
 321 };
 322
 323 static driver_t sk_driver = {
 324         "sk",
 325         sk_methods,
 326         sizeof(struct sk_if_softc)
 327 };
 328
 329 static devclass_t sk_devclass;
 330
 331 DRIVER_MODULE(skc, pci, skc_driver, skc_devclass, NULL, NULL);
 332 DRIVER_MODULE(sk, skc, sk_driver, sk_devclass, NULL, NULL);
 333 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
 334
 335 static struct resource_spec sk_res_spec_io[] = {
 336         { SYS_RES_IOPORT,       PCIR_BAR(1),    RF_ACTIVE },
 337         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 338         { -1,                   0,              0 }
 339 };
 340
 341 static struct resource_spec sk_res_spec_mem[] = {
 342         { SYS_RES_MEMORY,       PCIR_BAR(0),    RF_ACTIVE },
 343         { SYS_RES_IRQ,          0,              RF_ACTIVE | RF_SHAREABLE },
 344         { -1,                   0,              0 }
 345 };
 346
 347 #define SK_SETBIT(sc, reg, x)           \
 348         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
 349
 350 #define SK_CLRBIT(sc, reg, x)           \
 351         CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
 352
 353 #define SK_WIN_SETBIT_4(sc, reg, x)     \
 354         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) | x)
 355
 356 #define SK_WIN_CLRBIT_4(sc, reg, x)     \
 357         sk_win_write_4(sc, reg, sk_win_read_4(sc, reg) & ~x)
 358
 359 #define SK_WIN_SETBIT_2(sc, reg, x)     \
 360         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) | x)
 361
 362 #define SK_WIN_CLRBIT_2(sc, reg, x)     \
 363         sk_win_write_2(sc, reg, sk_win_read_2(sc, reg) & ~x)
 364
 365 static u_int32_t
 366 sk_win_read_4(sc, reg)
 367         struct sk_softc         *sc;
 368         int                     reg;
 369 {
 370 #ifdef SK_USEIOSPACE
 371         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 372         return(CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg)));
 373 #else
 374         return(CSR_READ_4(sc, reg));
 375 #endif
 376 }
 377
 378 static u_int16_t
 379 sk_win_read_2(sc, reg)
 380         struct sk_softc         *sc;
 381         int                     reg;
 382 {
 383 #ifdef SK_USEIOSPACE
 384         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 385         return(CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg)));
 386 #else
 387         return(CSR_READ_2(sc, reg));
 388 #endif
 389 }
 390
 391 static u_int8_t
 392 sk_win_read_1(sc, reg)
 393         struct sk_softc         *sc;
 394         int                     reg;
 395 {
 396 #ifdef SK_USEIOSPACE
 397         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 398         return(CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg)));
 399 #else
 400         return(CSR_READ_1(sc, reg));
 401 #endif
 402 }
 403
 404 static void
 405 sk_win_write_4(sc, reg, val)
 406         struct sk_softc         *sc;
 407         int                     reg;
 408         u_int32_t               val;
 409 {
 410 #ifdef SK_USEIOSPACE
 411         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 412         CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), val);
 413 #else
 414         CSR_WRITE_4(sc, reg, val);
 415 #endif
 416         return;
 417 }
 418
 419 static void
 420 sk_win_write_2(sc, reg, val)
 421         struct sk_softc         *sc;
 422         int                     reg;
 423         u_int32_t               val;
 424 {
 425 #ifdef SK_USEIOSPACE
 426         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 427         CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val);
 428 #else
 429         CSR_WRITE_2(sc, reg, val);
 430 #endif
 431         return;
 432 }
 433
 434 static void
 435 sk_win_write_1(sc, reg, val)
 436         struct sk_softc         *sc;
 437         int                     reg;
 438         u_int32_t               val;
 439 {
 440 #ifdef SK_USEIOSPACE
 441         CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
 442         CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), val);
 443 #else
 444         CSR_WRITE_1(sc, reg, val);
 445 #endif
 446         return;
 447 }
 448
 449 static int
 450 sk_miibus_readreg(dev, phy, reg)
 451         device_t                dev;
 452         int                     phy, reg;
 453 {
 454         struct sk_if_softc      *sc_if;
 455         int                     v;
 456
 457         sc_if = device_get_softc(dev);
 458
 459         SK_IF_MII_LOCK(sc_if);
 460         switch(sc_if->sk_softc->sk_type) {
 461         case SK_GENESIS:
 462                 v = sk_xmac_miibus_readreg(sc_if, phy, reg);
 463                 break;
 464         case SK_YUKON:
 465         case SK_YUKON_LITE:
 466         case SK_YUKON_LP:
 467                 v = sk_marv_miibus_readreg(sc_if, phy, reg);
 468                 break;
 469         default:
 470                 v = 0;
 471                 break;
 472         }
 473         SK_IF_MII_UNLOCK(sc_if);
 474
 475         return (v);
 476 }
 477
 478 static int
 479 sk_miibus_writereg(dev, phy, reg, val)
 480         device_t                dev;
 481         int                     phy, reg, val;
 482 {
 483         struct sk_if_softc      *sc_if;
 484         int                     v;
 485
 486         sc_if = device_get_softc(dev);
 487
 488         SK_IF_MII_LOCK(sc_if);
 489         switch(sc_if->sk_softc->sk_type) {
 490         case SK_GENESIS:
 491                 v = sk_xmac_miibus_writereg(sc_if, phy, reg, val);
 492                 break;
 493         case SK_YUKON:
 494         case SK_YUKON_LITE:
 495         case SK_YUKON_LP:
 496                 v = sk_marv_miibus_writereg(sc_if, phy, reg, val);
 497                 break;
 498         default:
 499                 v = 0;
 500                 break;
 501         }
 502         SK_IF_MII_UNLOCK(sc_if);
 503
 504         return (v);
 505 }
 506
 507 static void
 508 sk_miibus_statchg(dev)
 509         device_t                dev;
 510 {
 511         struct sk_if_softc      *sc_if;
 512
 513         sc_if = device_get_softc(dev);
 514
 515         SK_IF_MII_LOCK(sc_if);
 516         switch(sc_if->sk_softc->sk_type) {
 517         case SK_GENESIS:
 518                 sk_xmac_miibus_statchg(sc_if);
 519                 break;
 520         case SK_YUKON:
 521         case SK_YUKON_LITE:
 522         case SK_YUKON_LP:
 523                 sk_marv_miibus_statchg(sc_if);
 524                 break;
 525         }
 526         SK_IF_MII_UNLOCK(sc_if);
 527
 528         return;
 529 }
 530
 531 static int
 532 sk_xmac_miibus_readreg(sc_if, phy, reg)
 533         struct sk_if_softc      *sc_if;
 534         int                     phy, reg;
 535 {
 536         int                     i;
 537
 538         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 539         SK_XM_READ_2(sc_if, XM_PHY_DATA);
 540         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 541                 for (i = 0; i < SK_TIMEOUT; i++) {
 542                         DELAY(1);
 543                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
 544                             XM_MMUCMD_PHYDATARDY)
 545                                 break;
 546                 }
 547
 548                 if (i == SK_TIMEOUT) {
 549                         if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 550                         return(0);
 551                 }
 552         }
 553         DELAY(1);
 554         i = SK_XM_READ_2(sc_if, XM_PHY_DATA);
 555
 556         return(i);
 557 }
 558
 559 static int
 560 sk_xmac_miibus_writereg(sc_if, phy, reg, val)
 561         struct sk_if_softc      *sc_if;
 562         int                     phy, reg, val;
 563 {
 564         int                     i;
 565
 566         SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
 567         for (i = 0; i < SK_TIMEOUT; i++) {
 568                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 569                         break;
 570         }
 571
 572         if (i == SK_TIMEOUT) {
 573                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 574                 return (ETIMEDOUT);
 575         }
 576
 577         SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
 578         for (i = 0; i < SK_TIMEOUT; i++) {
 579                 DELAY(1);
 580                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
 581                         break;
 582         }
 583         if (i == SK_TIMEOUT)
 584                 if_printf(sc_if->sk_ifp, "phy write timed out\n");
 585
 586         return(0);
 587 }
 588
 589 static void
 590 sk_xmac_miibus_statchg(sc_if)
 591         struct sk_if_softc      *sc_if;
 592 {
 593         struct mii_data         *mii;
 594
 595         mii = device_get_softc(sc_if->sk_miibus);
 596
 597         /*
 598          * If this is a GMII PHY, manually set the XMAC's
 599          * duplex mode accordingly.
 600          */
 601         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
 602                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 603                         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 604                 } else {
 605                         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
 606                 }
 607         }
 608 }
 609
 610 static int
 611 sk_marv_miibus_readreg(sc_if, phy, reg)
 612         struct sk_if_softc      *sc_if;
 613         int                     phy, reg;
 614 {
 615         u_int16_t               val;
 616         int                     i;
 617
 618         if (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
 619             sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER) {
 620                 return(0);
 621         }
 622
 623         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 624                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
 625
 626         for (i = 0; i < SK_TIMEOUT; i++) {
 627                 DELAY(1);
 628                 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
 629                 if (val & YU_SMICR_READ_VALID)
 630                         break;
 631         }
 632
 633         if (i == SK_TIMEOUT) {
 634                 if_printf(sc_if->sk_ifp, "phy failed to come ready\n");
 635                 return(0);
 636         }
 637
 638         val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
 639
 640         return(val);
 641 }
 642
 643 static int
 644 sk_marv_miibus_writereg(sc_if, phy, reg, val)
 645         struct sk_if_softc      *sc_if;
 646         int                     phy, reg, val;
 647 {
 648         int                     i;
 649
 650         SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
 651         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
 652                       YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
 653
 654         for (i = 0; i < SK_TIMEOUT; i++) {
 655                 DELAY(1);
 656                 if ((SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY) == 0)
 657                         break;
 658         }
 659         if (i == SK_TIMEOUT)
 660                 if_printf(sc_if->sk_ifp, "phy write timeout\n");
 661
 662         return(0);
 663 }
 664
 665 static void
 666 sk_marv_miibus_statchg(sc_if)
 667         struct sk_if_softc      *sc_if;
 668 {
 669         return;
 670 }
 671
 672 #define HASH_BITS               6
 673
 674 static u_int32_t
 675 sk_xmchash(addr)
 676         const uint8_t *addr;
 677 {
 678         uint32_t crc;
 679
 680         /* Compute CRC for the address value. */
 681         crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 682
 683         return (~crc & ((1 << HASH_BITS) - 1));
 684 }
 685
 686 static void
 687 sk_setfilt(sc_if, addr, slot)
 688         struct sk_if_softc      *sc_if;
 689         u_int16_t               *addr;
 690         int                     slot;
 691 {
 692         int                     base;
 693
 694         base = XM_RXFILT_ENTRY(slot);
 695
 696         SK_XM_WRITE_2(sc_if, base, addr[0]);
 697         SK_XM_WRITE_2(sc_if, base + 2, addr[1]);
 698         SK_XM_WRITE_2(sc_if, base + 4, addr[2]);
 699
 700         return;
 701 }
 702
 703 static void
 704 sk_rxfilter(sc_if)
 705         struct sk_if_softc      *sc_if;
 706 {
 707         struct sk_softc         *sc;
 708
 709         SK_IF_LOCK_ASSERT(sc_if);
 710
 711         sc = sc_if->sk_softc;
 712         if (sc->sk_type == SK_GENESIS)
 713                 sk_rxfilter_genesis(sc_if);
 714         else
 715                 sk_rxfilter_yukon(sc_if);
 716 }
 717
 718 static void
 719 sk_rxfilter_genesis(sc_if)
 720         struct sk_if_softc      *sc_if;
 721 {
 722         struct ifnet            *ifp = sc_if->sk_ifp;
 723         u_int32_t               hashes[2] = { 0, 0 }, mode;
 724         int                     h = 0, i;
 725         struct ifmultiaddr      *ifma;
 726         u_int16_t               dummy[] = { 0, 0, 0 };
 727         u_int16_t               maddr[(ETHER_ADDR_LEN+1)/2];
 728
 729         SK_IF_LOCK_ASSERT(sc_if);
 730
 731         mode = SK_XM_READ_4(sc_if, XM_MODE);
 732         mode &= ~(XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
 733             XM_MODE_RX_USE_PERFECT);
 734         /* First, zot all the existing perfect filters. */
 735         for (i = 1; i < XM_RXFILT_MAX; i++)
 736                 sk_setfilt(sc_if, dummy, i);
 737
 738         /* Now program new ones. */
 739         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 740                 if (ifp->if_flags & IFF_ALLMULTI)
 741                         mode |= XM_MODE_RX_USE_HASH;
 742                 if (ifp->if_flags & IFF_PROMISC)
 743                         mode |= XM_MODE_RX_PROMISC;
 744                 hashes[0] = 0xFFFFFFFF;
 745                 hashes[1] = 0xFFFFFFFF;
 746         } else {
 747                 i = 1;
 748                 if_maddr_rlock(ifp);
 749                 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
 750                     ifma_link) {
 751                         if (ifma->ifma_addr->sa_family != AF_LINK)
 752                                 continue;
 753                         /*
 754                          * Program the first XM_RXFILT_MAX multicast groups
 755                          * into the perfect filter.
 756                          */
 757                         bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 758                             maddr, ETHER_ADDR_LEN);
 759                         if (i < XM_RXFILT_MAX) {
 760                                 sk_setfilt(sc_if, maddr, i);
 761                                 mode |= XM_MODE_RX_USE_PERFECT;
 762                                 i++;
 763                                 continue;
 764                         }
 765                         h = sk_xmchash((const uint8_t *)maddr);
 766                         if (h < 32)
 767                                 hashes[0] |= (1 << h);
 768                         else
 769                                 hashes[1] |= (1 << (h - 32));
 770                         mode |= XM_MODE_RX_USE_HASH;
 771                 }
 772                 if_maddr_runlock(ifp);
 773         }
 774
 775         SK_XM_WRITE_4(sc_if, XM_MODE, mode);
 776         SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
 777         SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
 778 }
 779
 780 static void
 781 sk_rxfilter_yukon(sc_if)
 782         struct sk_if_softc      *sc_if;
 783 {
 784         struct ifnet            *ifp;
 785         u_int32_t               crc, hashes[2] = { 0, 0 }, mode;
 786         struct ifmultiaddr      *ifma;
 787
 788         SK_IF_LOCK_ASSERT(sc_if);
 789
 790         ifp = sc_if->sk_ifp;
 791         mode = SK_YU_READ_2(sc_if, YUKON_RCR);
 792         if (ifp->if_flags & IFF_PROMISC)
 793                 mode &= ~(YU_RCR_UFLEN | YU_RCR_MUFLEN);
 794         else if (ifp->if_flags & IFF_ALLMULTI) {
 795                 mode |= YU_RCR_UFLEN | YU_RCR_MUFLEN;
 796                 hashes[0] = 0xFFFFFFFF;
 797                 hashes[1] = 0xFFFFFFFF;
 798         } else {
 799                 mode |= YU_RCR_UFLEN;
 800                 if_maddr_rlock(ifp);
 801                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 802                         if (ifma->ifma_addr->sa_family != AF_LINK)
 803                                 continue;
 804                         crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 805                             ifma->ifma_addr), ETHER_ADDR_LEN);
 806                         /* Just want the 6 least significant bits. */
 807                         crc &= 0x3f;
 808                         /* Set the corresponding bit in the hash table. */
 809                         hashes[crc >> 5] |= 1 << (crc & 0x1f);
 810                 }
 811                 if_maddr_runlock(ifp);
 812                 if (hashes[0] != 0 || hashes[1] != 0)
 813                         mode |= YU_RCR_MUFLEN;
 814         }
 815
 816         SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
 817         SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
 818         SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
 819         SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
 820         SK_YU_WRITE_2(sc_if, YUKON_RCR, mode);
 821 }
 822
 823 static int
 824 sk_init_rx_ring(sc_if)
 825         struct sk_if_softc      *sc_if;
 826 {
 827         struct sk_ring_data     *rd;
 828         bus_addr_t              addr;
 829         u_int32_t               csum_start;
 830         int                     i;
 831
 832         sc_if->sk_cdata.sk_rx_cons = 0;
 833
 834         csum_start = (ETHER_HDR_LEN + sizeof(struct ip))  << 16 |
 835             ETHER_HDR_LEN;
 836         rd = &sc_if->sk_rdata;
 837         bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
 838         for (i = 0; i < SK_RX_RING_CNT; i++) {
 839                 if (sk_newbuf(sc_if, i) != 0)
 840                         return (ENOBUFS);
 841                 if (i == (SK_RX_RING_CNT - 1))
 842                         addr = SK_RX_RING_ADDR(sc_if, 0);
 843                 else
 844                         addr = SK_RX_RING_ADDR(sc_if, i + 1);
 845                 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 846                 rd->sk_rx_ring[i].sk_csum_start = htole32(csum_start);
 847         }
 848
 849         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
 850             sc_if->sk_cdata.sk_rx_ring_map,
 851             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 852
 853         return(0);
 854 }
 855
 856 static int
 857 sk_init_jumbo_rx_ring(sc_if)
 858         struct sk_if_softc      *sc_if;
 859 {
 860         struct sk_ring_data     *rd;
 861         bus_addr_t              addr;
 862         u_int32_t               csum_start;
 863         int                     i;
 864
 865         sc_if->sk_cdata.sk_jumbo_rx_cons = 0;
 866
 867         csum_start = ((ETHER_HDR_LEN + sizeof(struct ip)) << 16) |
 868             ETHER_HDR_LEN;
 869         rd = &sc_if->sk_rdata;
 870         bzero(rd->sk_jumbo_rx_ring,
 871             sizeof(struct sk_rx_desc) * SK_JUMBO_RX_RING_CNT);
 872         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
 873                 if (sk_jumbo_newbuf(sc_if, i) != 0)
 874                         return (ENOBUFS);
 875                 if (i == (SK_JUMBO_RX_RING_CNT - 1))
 876                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, 0);
 877                 else
 878                         addr = SK_JUMBO_RX_RING_ADDR(sc_if, i + 1);
 879                 rd->sk_jumbo_rx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 880                 rd->sk_jumbo_rx_ring[i].sk_csum_start = htole32(csum_start);
 881         }
 882
 883         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
 884             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
 885             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 886
 887         return (0);
 888 }
 889
 890 static void
 891 sk_init_tx_ring(sc_if)
 892         struct sk_if_softc      *sc_if;
 893 {
 894         struct sk_ring_data     *rd;
 895         struct sk_txdesc        *txd;
 896         bus_addr_t              addr;
 897         int                     i;
 898
 899         STAILQ_INIT(&sc_if->sk_cdata.sk_txfreeq);
 900         STAILQ_INIT(&sc_if->sk_cdata.sk_txbusyq);
 901
 902         sc_if->sk_cdata.sk_tx_prod = 0;
 903         sc_if->sk_cdata.sk_tx_cons = 0;
 904         sc_if->sk_cdata.sk_tx_cnt = 0;
 905
 906         rd = &sc_if->sk_rdata;
 907         bzero(rd->sk_tx_ring, sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
 908         for (i = 0; i < SK_TX_RING_CNT; i++) {
 909                 if (i == (SK_TX_RING_CNT - 1))
 910                         addr = SK_TX_RING_ADDR(sc_if, 0);
 911                 else
 912                         addr = SK_TX_RING_ADDR(sc_if, i + 1);
 913                 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(addr));
 914                 txd = &sc_if->sk_cdata.sk_txdesc[i];
 915                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
 916         }
 917
 918         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
 919             sc_if->sk_cdata.sk_tx_ring_map,
 920             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 921 }
 922
 923 static __inline void
 924 sk_discard_rxbuf(sc_if, idx)
 925         struct sk_if_softc      *sc_if;
 926         int                     idx;
 927 {
 928         struct sk_rx_desc       *r;
 929         struct sk_rxdesc        *rxd;
 930         struct mbuf             *m;
 931
 932
 933         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 934         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 935         m = rxd->rx_m;
 936         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 937 }
 938
 939 static __inline void
 940 sk_discard_jumbo_rxbuf(sc_if, idx)
 941         struct sk_if_softc      *sc_if;
 942         int                     idx;
 943 {
 944         struct sk_rx_desc       *r;
 945         struct sk_rxdesc        *rxd;
 946         struct mbuf             *m;
 947
 948         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
 949         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
 950         m = rxd->rx_m;
 951         r->sk_ctl = htole32(m->m_len | SK_RXSTAT | SK_OPCODE_CSUM);
 952 }
 953
 954 static int
 955 sk_newbuf(sc_if, idx)
 956         struct sk_if_softc      *sc_if;
 957         int                     idx;
 958 {
 959         struct sk_rx_desc       *r;
 960         struct sk_rxdesc        *rxd;
 961         struct mbuf             *m;
 962         bus_dma_segment_t       segs[1];
 963         bus_dmamap_t            map;
 964         int                     nsegs;
 965
 966         m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 967         if (m == NULL)
 968                 return (ENOBUFS);
 969         m->m_len = m->m_pkthdr.len = MCLBYTES;
 970         m_adj(m, ETHER_ALIGN);
 971
 972         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_rx_tag,
 973             sc_if->sk_cdata.sk_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 974                 m_freem(m);
 975                 return (ENOBUFS);
 976         }
 977         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 978
 979         rxd = &sc_if->sk_cdata.sk_rxdesc[idx];
 980         if (rxd->rx_m != NULL) {
 981                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 982                     BUS_DMASYNC_POSTREAD);
 983                 bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap);
 984         }
 985         map = rxd->rx_dmamap;
 986         rxd->rx_dmamap = sc_if->sk_cdata.sk_rx_sparemap;
 987         sc_if->sk_cdata.sk_rx_sparemap = map;
 988         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag, rxd->rx_dmamap,
 989             BUS_DMASYNC_PREREAD);
 990         rxd->rx_m = m;
 991         r = &sc_if->sk_rdata.sk_rx_ring[idx];
 992         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
 993         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
 994         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
 995
 996         return (0);
 997 }
 998
 999 static int
1000 sk_jumbo_newbuf(sc_if, idx)
1001         struct sk_if_softc      *sc_if;
1002         int                     idx;
1003 {
1004         struct sk_rx_desc       *r;
1005         struct sk_rxdesc        *rxd;
1006         struct mbuf             *m;
1007         bus_dma_segment_t       segs[1];
1008         bus_dmamap_t            map;
1009         int                     nsegs;
1010
1011         m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1012         if (m == NULL)
1013                 return (ENOBUFS);
1014         if ((m->m_flags & M_EXT) == 0) {
1015                 m_freem(m);
1016                 return (ENOBUFS);
1017         }
1018         m->m_pkthdr.len = m->m_len = MJUM9BYTES;
1019         /*
1020          * Adjust alignment so packet payload begins on a
1021          * longword boundary. Mandatory for Alpha, useful on
1022          * x86 too.
1023          */
1024         m_adj(m, ETHER_ALIGN);
1025
1026         if (bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_jumbo_rx_tag,
1027             sc_if->sk_cdata.sk_jumbo_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1028                 m_freem(m);
1029                 return (ENOBUFS);
1030         }
1031         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1032
1033         rxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[idx];
1034         if (rxd->rx_m != NULL) {
1035                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1036                     BUS_DMASYNC_POSTREAD);
1037                 bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
1038                     rxd->rx_dmamap);
1039         }
1040         map = rxd->rx_dmamap;
1041         rxd->rx_dmamap = sc_if->sk_cdata.sk_jumbo_rx_sparemap;
1042         sc_if->sk_cdata.sk_jumbo_rx_sparemap = map;
1043         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag, rxd->rx_dmamap,
1044             BUS_DMASYNC_PREREAD);
1045         rxd->rx_m = m;
1046         r = &sc_if->sk_rdata.sk_jumbo_rx_ring[idx];
1047         r->sk_data_lo = htole32(SK_ADDR_LO(segs[0].ds_addr));
1048         r->sk_data_hi = htole32(SK_ADDR_HI(segs[0].ds_addr));
1049         r->sk_ctl = htole32(segs[0].ds_len | SK_RXSTAT | SK_OPCODE_CSUM);
1050
1051         return (0);
1052 }
1053
1054 /*
1055  * Set media options.
1056  */
1057 static int
1058 sk_ifmedia_upd(ifp)
1059         struct ifnet            *ifp;
1060 {
1061         struct sk_if_softc      *sc_if = ifp->if_softc;
1062         struct mii_data         *mii;
1063
1064         mii = device_get_softc(sc_if->sk_miibus);
1065         sk_init(sc_if);
1066         mii_mediachg(mii);
1067
1068         return(0);
1069 }
1070
1071 /*
1072  * Report current media status.
1073  */
1074 static void
1075 sk_ifmedia_sts(ifp, ifmr)
1076         struct ifnet            *ifp;
1077         struct ifmediareq       *ifmr;
1078 {
1079         struct sk_if_softc      *sc_if;
1080         struct mii_data         *mii;
1081
1082         sc_if = ifp->if_softc;
1083         mii = device_get_softc(sc_if->sk_miibus);
1084
1085         mii_pollstat(mii);
1086         ifmr->ifm_active = mii->mii_media_active;
1087         ifmr->ifm_status = mii->mii_media_status;
1088
1089         return;
1090 }
1091
1092 static int
1093 sk_ioctl(ifp, command, data)
1094         struct ifnet            *ifp;
1095         u_long                  command;
1096         caddr_t                 data;
1097 {
1098         struct sk_if_softc      *sc_if = ifp->if_softc;
1099         struct ifreq            *ifr = (struct ifreq *) data;
1100         int                     error, mask;
1101         struct mii_data         *mii;
1102
1103         error = 0;
1104         switch(command) {
1105         case SIOCSIFMTU:
1106                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > SK_JUMBO_MTU)
1107                         error = EINVAL;
1108                 else if (ifp->if_mtu != ifr->ifr_mtu) {
1109                         if (sc_if->sk_jumbo_disable != 0 &&
1110                             ifr->ifr_mtu > SK_MAX_FRAMELEN)
1111                                 error = EINVAL;
1112                         else {
1113                                 SK_IF_LOCK(sc_if);
1114                                 ifp->if_mtu = ifr->ifr_mtu;
1115                                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1116                                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1117                                         sk_init_locked(sc_if);
1118                                 }
1119                                 SK_IF_UNLOCK(sc_if);
1120                         }
1121                 }
1122                 break;
1123         case SIOCSIFFLAGS:
1124                 SK_IF_LOCK(sc_if);
1125                 if (ifp->if_flags & IFF_UP) {
1126                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1127                                 if ((ifp->if_flags ^ sc_if->sk_if_flags)
1128                                     & (IFF_PROMISC | IFF_ALLMULTI))
1129                                         sk_rxfilter(sc_if);
1130                         } else
1131                                 sk_init_locked(sc_if);
1132                 } else {
1133                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1134                                 sk_stop(sc_if);
1135                 }
1136                 sc_if->sk_if_flags = ifp->if_flags;
1137                 SK_IF_UNLOCK(sc_if);
1138                 break;
1139         case SIOCADDMULTI:
1140         case SIOCDELMULTI:
1141                 SK_IF_LOCK(sc_if);
1142                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1143                         sk_rxfilter(sc_if);
1144                 SK_IF_UNLOCK(sc_if);
1145                 break;
1146         case SIOCGIFMEDIA:
1147         case SIOCSIFMEDIA:
1148                 mii = device_get_softc(sc_if->sk_miibus);
1149                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1150                 break;
1151         case SIOCSIFCAP:
1152                 SK_IF_LOCK(sc_if);
1153                 if (sc_if->sk_softc->sk_type == SK_GENESIS) {
1154                         SK_IF_UNLOCK(sc_if);
1155                         break;
1156                 }
1157                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1158                 if ((mask & IFCAP_TXCSUM) != 0 &&
1159                     (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1160                         ifp->if_capenable ^= IFCAP_TXCSUM;
1161                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1162                                 ifp->if_hwassist |= SK_CSUM_FEATURES;
1163                         else
1164                                 ifp->if_hwassist &= ~SK_CSUM_FEATURES;
1165                 }
1166                 if ((mask & IFCAP_RXCSUM) != 0 &&
1167                     (IFCAP_RXCSUM & ifp->if_capabilities) != 0)
1168                         ifp->if_capenable ^= IFCAP_RXCSUM;
1169                 SK_IF_UNLOCK(sc_if);
1170                 break;
1171         default:
1172                 error = ether_ioctl(ifp, command, data);
1173                 break;
1174         }
1175
1176         return (error);
1177 }
1178
1179 /*
1180  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1181  * IDs against our list and return a device name if we find a match.
1182  */
1183 static int
1184 skc_probe(dev)
1185         device_t                dev;
1186 {
1187         const struct sk_type    *t = sk_devs;
1188
1189         while(t->sk_name != NULL) {
1190                 if ((pci_get_vendor(dev) == t->sk_vid) &&
1191                     (pci_get_device(dev) == t->sk_did)) {
1192                         /*
1193                          * Only attach to rev. 2 of the Linksys EG1032 adapter.
1194                          * Rev. 3 is supported by re(4).
1195                          */
1196                         if ((t->sk_vid == VENDORID_LINKSYS) &&
1197                                 (t->sk_did == DEVICEID_LINKSYS_EG1032) &&
1198                                 (pci_get_subdevice(dev) !=
1199                                  SUBDEVICEID_LINKSYS_EG1032_REV2)) {
1200                                 t++;
1201                                 continue;
1202                         }
1203                         device_set_desc(dev, t->sk_name);
1204                         return (BUS_PROBE_DEFAULT);
1205                 }
1206                 t++;
1207         }
1208
1209         return(ENXIO);
1210 }
1211
1212 /*
1213  * Force the GEnesis into reset, then bring it out of reset.
1214  */
1215 static void
1216 sk_reset(sc)
1217         struct sk_softc         *sc;
1218 {
1219
1220         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1221         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1222         if (SK_YUKON_FAMILY(sc->sk_type))
1223                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1224
1225         DELAY(1000);
1226         CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1227         DELAY(2);
1228         CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1229         if (SK_YUKON_FAMILY(sc->sk_type))
1230                 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1231
1232         if (sc->sk_type == SK_GENESIS) {
1233                 /* Configure packet arbiter */
1234                 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1235                 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1236                 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1237                 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1238                 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1239         }
1240
1241         /* Enable RAM interface */
1242         sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1243
1244         /*
1245          * Configure interrupt moderation. The moderation timer
1246          * defers interrupts specified in the interrupt moderation
1247          * timer mask based on the timeout specified in the interrupt
1248          * moderation timer init register. Each bit in the timer
1249          * register represents one tick, so to specify a timeout in
1250          * microseconds, we have to multiply by the correct number of
1251          * ticks-per-microsecond.
1252          */
1253         switch (sc->sk_type) {
1254         case SK_GENESIS:
1255                 sc->sk_int_ticks = SK_IMTIMER_TICKS_GENESIS;
1256                 break;
1257         default:
1258                 sc->sk_int_ticks = SK_IMTIMER_TICKS_YUKON;
1259                 break;
1260         }
1261         if (bootverbose)
1262                 device_printf(sc->sk_dev, "interrupt moderation is %d us\n",
1263                     sc->sk_int_mod);
1264         sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
1265             sc->sk_int_ticks));
1266         sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1267             SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1268         sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1269
1270         return;
1271 }
1272
1273 static int
1274 sk_probe(dev)
1275         device_t                dev;
1276 {
1277         struct sk_softc         *sc;
1278
1279         sc = device_get_softc(device_get_parent(dev));
1280
1281         /*
1282          * Not much to do here. We always know there will be
1283          * at least one XMAC present, and if there are two,
1284          * skc_attach() will create a second device instance
1285          * for us.
1286          */
1287         switch (sc->sk_type) {
1288         case SK_GENESIS:
1289                 device_set_desc(dev, "XaQti Corp. XMAC II");
1290                 break;
1291         case SK_YUKON:
1292         case SK_YUKON_LITE:
1293         case SK_YUKON_LP:
1294                 device_set_desc(dev, "Marvell Semiconductor, Inc. Yukon");
1295                 break;
1296         }
1297
1298         return (BUS_PROBE_DEFAULT);
1299 }
1300
1301 /*
1302  * Each XMAC chip is attached as a separate logical IP interface.
1303  * Single port cards will have only one logical interface of course.
1304  */
1305 static int
1306 sk_attach(dev)
1307         device_t                dev;
1308 {
1309         struct sk_softc         *sc;
1310         struct sk_if_softc      *sc_if;
1311         struct ifnet            *ifp;
1312         u_int32_t               r;
1313         int                     error, i, phy, port;
1314         u_char                  eaddr[6];
1315         u_char                  inv_mac[] = {0, 0, 0, 0, 0, 0};
1316
1317         if (dev == NULL)
1318                 return(EINVAL);
1319
1320         error = 0;
1321         sc_if = device_get_softc(dev);
1322         sc = device_get_softc(device_get_parent(dev));
1323         port = *(int *)device_get_ivars(dev);
1324
1325         sc_if->sk_if_dev = dev;
1326         sc_if->sk_port = port;
1327         sc_if->sk_softc = sc;
1328         sc->sk_if[port] = sc_if;
1329         if (port == SK_PORT_A)
1330                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1331         if (port == SK_PORT_B)
1332                 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1333
1334         callout_init_mtx(&sc_if->sk_tick_ch, &sc_if->sk_softc->sk_mtx, 0);
1335         callout_init_mtx(&sc_if->sk_watchdog_ch, &sc_if->sk_softc->sk_mtx, 0);
1336
1337         if (sk_dma_alloc(sc_if) != 0) {
1338                 error = ENOMEM;
1339                 goto fail;
1340         }
1341         sk_dma_jumbo_alloc(sc_if);
1342
1343         ifp = sc_if->sk_ifp = if_alloc(IFT_ETHER);
1344         if (ifp == NULL) {
1345                 device_printf(sc_if->sk_if_dev, "can not if_alloc()\n");
1346                 error = ENOSPC;
1347                 goto fail;
1348         }
1349         ifp->if_softc = sc_if;
1350         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1351         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1352         /*
1353          * SK_GENESIS has a bug in checksum offload - From linux.
1354          */
1355         if (sc_if->sk_softc->sk_type != SK_GENESIS) {
1356                 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM;
1357                 ifp->if_hwassist = 0;
1358         } else {
1359                 ifp->if_capabilities = 0;
1360                 ifp->if_hwassist = 0;
1361         }
1362         ifp->if_capenable = ifp->if_capabilities;
1363         /*
1364          * Some revision of Yukon controller generates corrupted
1365          * frame when TX checksum offloading is enabled.  The
1366          * frame has a valid checksum value so payload might be
1367          * modified during TX checksum calculation. Disable TX
1368          * checksum offloading but give users chance to enable it
1369          * when they know their controller works without problems
1370          * with TX checksum offloading.
1371          */
1372         ifp->if_capenable &= ~IFCAP_TXCSUM;
1373         ifp->if_ioctl = sk_ioctl;
1374         ifp->if_start = sk_start;
1375         ifp->if_init = sk_init;
1376         IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1377         ifp->if_snd.ifq_drv_maxlen = SK_TX_RING_CNT - 1;
1378         IFQ_SET_READY(&ifp->if_snd);
1379
1380         /*
1381          * Get station address for this interface. Note that
1382          * dual port cards actually come with three station
1383          * addresses: one for each port, plus an extra. The
1384          * extra one is used by the SysKonnect driver software
1385          * as a 'virtual' station address for when both ports
1386          * are operating in failover mode. Currently we don't
1387          * use this extra address.
1388          */
1389         SK_IF_LOCK(sc_if);
1390         for (i = 0; i < ETHER_ADDR_LEN; i++)
1391                 eaddr[i] =
1392                     sk_win_read_1(sc, SK_MAC0_0 + (port * 8) + i);
1393
1394         /* Verify whether the station address is invalid or not. */
1395         if (bcmp(eaddr, inv_mac, sizeof(inv_mac)) == 0) {
1396                 device_printf(sc_if->sk_if_dev,
1397                     "Generating random ethernet address\n");
1398                 r = arc4random();
1399                 /*
1400                  * Set OUI to convenient locally assigned address.  'b'
1401                  * is 0x62, which has the locally assigned bit set, and
1402                  * the broadcast/multicast bit clear.
1403                  */
1404                 eaddr[0] = 'b';
1405                 eaddr[1] = 's';
1406                 eaddr[2] = 'd';
1407                 eaddr[3] = (r >> 16) & 0xff;
1408                 eaddr[4] = (r >>  8) & 0xff;
1409                 eaddr[5] = (r >>  0) & 0xff;
1410         }
1411         /*
1412          * Set up RAM buffer addresses. The NIC will have a certain
1413          * amount of SRAM on it, somewhere between 512K and 2MB. We
1414          * need to divide this up a) between the transmitter and
1415          * receiver and b) between the two XMACs, if this is a
1416          * dual port NIC. Our algotithm is to divide up the memory
1417          * evenly so that everyone gets a fair share.
1418          *
1419          * Just to be contrary, Yukon2 appears to have separate memory
1420          * for each MAC.
1421          */
1422         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1423                 u_int32_t               chunk, val;
1424
1425                 chunk = sc->sk_ramsize / 2;
1426                 val = sc->sk_rboff / sizeof(u_int64_t);
1427                 sc_if->sk_rx_ramstart = val;
1428                 val += (chunk / sizeof(u_int64_t));
1429                 sc_if->sk_rx_ramend = val - 1;
1430                 sc_if->sk_tx_ramstart = val;
1431                 val += (chunk / sizeof(u_int64_t));
1432                 sc_if->sk_tx_ramend = val - 1;
1433         } else {
1434                 u_int32_t               chunk, val;
1435
1436                 chunk = sc->sk_ramsize / 4;
1437                 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1438                     sizeof(u_int64_t);
1439                 sc_if->sk_rx_ramstart = val;
1440                 val += (chunk / sizeof(u_int64_t));
1441                 sc_if->sk_rx_ramend = val - 1;
1442                 sc_if->sk_tx_ramstart = val;
1443                 val += (chunk / sizeof(u_int64_t));
1444                 sc_if->sk_tx_ramend = val - 1;
1445         }
1446
1447         /* Read and save PHY type and set PHY address */
1448         sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1449         if (!SK_YUKON_FAMILY(sc->sk_type)) {
1450                 switch(sc_if->sk_phytype) {
1451                 case SK_PHYTYPE_XMAC:
1452                         sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1453                         break;
1454                 case SK_PHYTYPE_BCOM:
1455                         sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1456                         break;
1457                 default:
1458                         device_printf(sc->sk_dev, "unsupported PHY type: %d\n",
1459                             sc_if->sk_phytype);
1460                         error = ENODEV;
1461                         SK_IF_UNLOCK(sc_if);
1462                         goto fail;
1463                 }
1464         } else {
1465                 if (sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1466                     sc->sk_pmd != 'S') {
1467                         /* not initialized, punt */
1468                         sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1469                         sc->sk_coppertype = 1;
1470                 }
1471
1472                 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1473
1474                 if (!(sc->sk_coppertype))
1475                         sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1476         }
1477
1478         /*
1479          * Call MI attach routine.  Can't hold locks when calling into ether_*.
1480          */
1481         SK_IF_UNLOCK(sc_if);
1482         ether_ifattach(ifp, eaddr);
1483         SK_IF_LOCK(sc_if);
1484
1485         /*
1486          * The hardware should be ready for VLAN_MTU by default:
1487          * XMAC II has 0x8100 in VLAN Tag Level 1 register initially;
1488          * YU_SMR_MFL_VLAN is set by this driver in Yukon.
1489          *
1490          */
1491         ifp->if_capabilities |= IFCAP_VLAN_MTU;
1492         ifp->if_capenable |= IFCAP_VLAN_MTU;
1493         /*
1494          * Tell the upper layer(s) we support long frames.
1495          * Must appear after the call to ether_ifattach() because
1496          * ether_ifattach() sets ifi_hdrlen to the default value.
1497          */
1498         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1499
1500         /*
1501          * Do miibus setup.
1502          */
1503         phy = MII_PHY_ANY;
1504         switch (sc->sk_type) {
1505         case SK_GENESIS:
1506                 sk_init_xmac(sc_if);
1507                 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
1508                         phy = 0;
1509                 break;
1510         case SK_YUKON:
1511         case SK_YUKON_LITE:
1512         case SK_YUKON_LP:
1513                 sk_init_yukon(sc_if);
1514                 phy = 0;
1515                 break;
1516         }
1517
1518         SK_IF_UNLOCK(sc_if);
1519         error = mii_attach(dev, &sc_if->sk_miibus, ifp, sk_ifmedia_upd,
1520             sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
1521         if (error != 0) {
1522                 device_printf(sc_if->sk_if_dev, "attaching PHYs failed\n");
1523                 ether_ifdetach(ifp);
1524                 goto fail;
1525         }
1526
1527 fail:
1528         if (error) {
1529                 /* Access should be ok even though lock has been dropped */
1530                 sc->sk_if[port] = NULL;
1531                 sk_detach(dev);
1532         }
1533
1534         return(error);
1535 }
1536
1537 /*
1538  * Attach the interface. Allocate softc structures, do ifmedia
1539  * setup and ethernet/BPF attach.
1540  */
1541 static int
1542 skc_attach(dev)
1543         device_t                dev;
1544 {
1545         struct sk_softc         *sc;
1546         int                     error = 0, *port;
1547         uint8_t                 skrs;
1548         const char              *pname = NULL;
1549         char                    *revstr;
1550
1551         sc = device_get_softc(dev);
1552         sc->sk_dev = dev;
1553
1554         mtx_init(&sc->sk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1555             MTX_DEF);
1556         mtx_init(&sc->sk_mii_mtx, "sk_mii_mutex", NULL, MTX_DEF);
1557         /*
1558          * Map control/status registers.
1559          */
1560         pci_enable_busmaster(dev);
1561
1562         /* Allocate resources */
1563 #ifdef SK_USEIOSPACE
1564         sc->sk_res_spec = sk_res_spec_io;
1565 #else
1566         sc->sk_res_spec = sk_res_spec_mem;
1567 #endif
1568         error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1569         if (error) {
1570                 if (sc->sk_res_spec == sk_res_spec_mem)
1571                         sc->sk_res_spec = sk_res_spec_io;
1572                 else
1573                         sc->sk_res_spec = sk_res_spec_mem;
1574                 error = bus_alloc_resources(dev, sc->sk_res_spec, sc->sk_res);
1575                 if (error) {
1576                         device_printf(dev, "couldn't allocate %s resources\n",
1577                             sc->sk_res_spec == sk_res_spec_mem ? "memory" :
1578                             "I/O");
1579                         goto fail;
1580                 }
1581         }
1582
1583         sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1584         sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4) & 0xf;
1585
1586         /* Bail out if chip is not recognized. */
1587         if (sc->sk_type != SK_GENESIS && !SK_YUKON_FAMILY(sc->sk_type)) {
1588                 device_printf(dev, "unknown device: chipver=%02x, rev=%x\n",
1589                     sc->sk_type, sc->sk_rev);
1590                 error = ENXIO;
1591                 goto fail;
1592         }
1593
1594         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1595                 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1596                 OID_AUTO, "int_mod", CTLTYPE_INT|CTLFLAG_RW,
1597                 &sc->sk_int_mod, 0, sysctl_hw_sk_int_mod, "I",
1598                 "SK interrupt moderation");
1599
1600         /* Pull in device tunables. */
1601         sc->sk_int_mod = SK_IM_DEFAULT;
1602         error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1603                 "int_mod", &sc->sk_int_mod);
1604         if (error == 0) {
1605                 if (sc->sk_int_mod < SK_IM_MIN ||
1606                     sc->sk_int_mod > SK_IM_MAX) {
1607                         device_printf(dev, "int_mod value out of range; "
1608                             "using default: %d\n", SK_IM_DEFAULT);
1609                         sc->sk_int_mod = SK_IM_DEFAULT;
1610                 }
1611         }
1612
1613         /* Reset the adapter. */
1614         sk_reset(sc);
1615
1616         skrs = sk_win_read_1(sc, SK_EPROM0);
1617         if (sc->sk_type == SK_GENESIS) {
1618                 /* Read and save RAM size and RAMbuffer offset */
1619                 switch(skrs) {
1620                 case SK_RAMSIZE_512K_64:
1621                         sc->sk_ramsize = 0x80000;
1622                         sc->sk_rboff = SK_RBOFF_0;
1623                         break;
1624                 case SK_RAMSIZE_1024K_64:
1625                         sc->sk_ramsize = 0x100000;
1626                         sc->sk_rboff = SK_RBOFF_80000;
1627                         break;
1628                 case SK_RAMSIZE_1024K_128:
1629                         sc->sk_ramsize = 0x100000;
1630                         sc->sk_rboff = SK_RBOFF_0;
1631                         break;
1632                 case SK_RAMSIZE_2048K_128:
1633                         sc->sk_ramsize = 0x200000;
1634                         sc->sk_rboff = SK_RBOFF_0;
1635                         break;
1636                 default:
1637                         device_printf(dev, "unknown ram size: %d\n", skrs);
1638                         error = ENXIO;
1639                         goto fail;
1640                 }
1641         } else { /* SK_YUKON_FAMILY */
1642                 if (skrs == 0x00)
1643                         sc->sk_ramsize = 0x20000;
1644                 else
1645                         sc->sk_ramsize = skrs * (1<<12);
1646                 sc->sk_rboff = SK_RBOFF_0;
1647         }
1648
1649         /* Read and save physical media type */
1650          sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1651
1652          if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1653                  sc->sk_coppertype = 1;
1654          else
1655                  sc->sk_coppertype = 0;
1656
1657         /* Determine whether to name it with VPD PN or just make it up.
1658          * Marvell Yukon VPD PN seems to freqently be bogus. */
1659         switch (pci_get_device(dev)) {
1660         case DEVICEID_SK_V1:
1661         case DEVICEID_BELKIN_5005:
1662         case DEVICEID_3COM_3C940:
1663         case DEVICEID_LINKSYS_EG1032:
1664         case DEVICEID_DLINK_DGE530T_A1:
1665         case DEVICEID_DLINK_DGE530T_B1:
1666                 /* Stay with VPD PN. */
1667                 (void) pci_get_vpd_ident(dev, &pname);
1668                 break;
1669         case DEVICEID_SK_V2:
1670                 /* YUKON VPD PN might bear no resemblance to reality. */
1671                 switch (sc->sk_type) {
1672                 case SK_GENESIS:
1673                         /* Stay with VPD PN. */
1674                         (void) pci_get_vpd_ident(dev, &pname);
1675                         break;
1676                 case SK_YUKON:
1677                         pname = "Marvell Yukon Gigabit Ethernet";
1678                         break;
1679                 case SK_YUKON_LITE:
1680                         pname = "Marvell Yukon Lite Gigabit Ethernet";
1681                         break;
1682                 case SK_YUKON_LP:
1683                         pname = "Marvell Yukon LP Gigabit Ethernet";
1684                         break;
1685                 default:
1686                         pname = "Marvell Yukon (Unknown) Gigabit Ethernet";
1687                         break;
1688                 }
1689
1690                 /* Yukon Lite Rev. A0 needs special test. */
1691                 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1692                         u_int32_t far;
1693                         u_int8_t testbyte;
1694
1695                         /* Save flash address register before testing. */
1696                         far = sk_win_read_4(sc, SK_EP_ADDR);
1697
1698                         sk_win_write_1(sc, SK_EP_ADDR+0x03, 0xff);
1699                         testbyte = sk_win_read_1(sc, SK_EP_ADDR+0x03);
1700
1701                         if (testbyte != 0x00) {
1702                                 /* Yukon Lite Rev. A0 detected. */
1703                                 sc->sk_type = SK_YUKON_LITE;
1704                                 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1705                                 /* Restore flash address register. */
1706                                 sk_win_write_4(sc, SK_EP_ADDR, far);
1707                         }
1708                 }
1709                 break;
1710         default:
1711                 device_printf(dev, "unknown device: vendor=%04x, device=%04x, "
1712                         "chipver=%02x, rev=%x\n",
1713                         pci_get_vendor(dev), pci_get_device(dev),
1714                         sc->sk_type, sc->sk_rev);
1715                 error = ENXIO;
1716                 goto fail;
1717         }
1718
1719         if (sc->sk_type == SK_YUKON_LITE) {
1720                 switch (sc->sk_rev) {
1721                 case SK_YUKON_LITE_REV_A0:
1722                         revstr = "A0";
1723                         break;
1724                 case SK_YUKON_LITE_REV_A1:
1725                         revstr = "A1";
1726                         break;
1727                 case SK_YUKON_LITE_REV_A3:
1728                         revstr = "A3";
1729                         break;
1730                 default:
1731                         revstr = "";
1732                         break;
1733                 }
1734         } else {
1735                 revstr = "";
1736         }
1737
1738         /* Announce the product name and more VPD data if there. */
1739         if (pname != NULL)
1740                 device_printf(dev, "%s rev. %s(0x%x)\n",
1741                         pname, revstr, sc->sk_rev);
1742
1743         if (bootverbose) {
1744                 device_printf(dev, "chip ver  = 0x%02x\n", sc->sk_type);
1745                 device_printf(dev, "chip rev  = 0x%02x\n", sc->sk_rev);
1746                 device_printf(dev, "SK_EPROM0 = 0x%02x\n", skrs);
1747                 device_printf(dev, "SRAM size = 0x%06x\n", sc->sk_ramsize);
1748         }
1749
1750         sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1751         if (sc->sk_devs[SK_PORT_A] == NULL) {
1752                 device_printf(dev, "failed to add child for PORT_A\n");
1753                 error = ENXIO;
1754                 goto fail;
1755         }
1756         port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1757         if (port == NULL) {
1758                 device_printf(dev, "failed to allocate memory for "
1759                     "ivars of PORT_A\n");
1760                 error = ENXIO;
1761                 goto fail;
1762         }
1763         *port = SK_PORT_A;
1764         device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1765
1766         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1767                 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1768                 if (sc->sk_devs[SK_PORT_B] == NULL) {
1769                         device_printf(dev, "failed to add child for PORT_B\n");
1770                         error = ENXIO;
1771                         goto fail;
1772                 }
1773                 port = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
1774                 if (port == NULL) {
1775                         device_printf(dev, "failed to allocate memory for "
1776                             "ivars of PORT_B\n");
1777                         error = ENXIO;
1778                         goto fail;
1779                 }
1780                 *port = SK_PORT_B;
1781                 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1782         }
1783
1784         /* Turn on the 'driver is loaded' LED. */
1785         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1786
1787         error = bus_generic_attach(dev);
1788         if (error) {
1789                 device_printf(dev, "failed to attach port(s)\n");
1790                 goto fail;
1791         }
1792
1793         /* Hook interrupt last to avoid having to lock softc */
1794         error = bus_setup_intr(dev, sc->sk_res[1], INTR_TYPE_NET|INTR_MPSAFE,
1795             NULL, sk_intr, sc, &sc->sk_intrhand);
1796
1797         if (error) {
1798                 device_printf(dev, "couldn't set up irq\n");
1799                 goto fail;
1800         }
1801
1802 fail:
1803         if (error)
1804                 skc_detach(dev);
1805
1806         return(error);
1807 }
1808
1809 /*
1810  * Shutdown hardware and free up resources. This can be called any
1811  * time after the mutex has been initialized. It is called in both
1812  * the error case in attach and the normal detach case so it needs
1813  * to be careful about only freeing resources that have actually been
1814  * allocated.
1815  */
1816 static int
1817 sk_detach(dev)
1818         device_t                dev;
1819 {
1820         struct sk_if_softc      *sc_if;
1821         struct ifnet            *ifp;
1822
1823         sc_if = device_get_softc(dev);
1824         KASSERT(mtx_initialized(&sc_if->sk_softc->sk_mtx),
1825             ("sk mutex not initialized in sk_detach"));
1826         SK_IF_LOCK(sc_if);
1827
1828         ifp = sc_if->sk_ifp;
1829         /* These should only be active if attach_xmac succeeded */
1830         if (device_is_attached(dev)) {
1831                 sk_stop(sc_if);
1832                 /* Can't hold locks while calling detach */
1833                 SK_IF_UNLOCK(sc_if);
1834                 callout_drain(&sc_if->sk_tick_ch);
1835                 callout_drain(&sc_if->sk_watchdog_ch);
1836                 ether_ifdetach(ifp);
1837                 SK_IF_LOCK(sc_if);
1838         }
1839         if (ifp)
1840                 if_free(ifp);
1841         /*
1842          * We're generally called from skc_detach() which is using
1843          * device_delete_child() to get to here. It's already trashed
1844          * miibus for us, so don't do it here or we'll panic.
1845          */
1846         /*
1847         if (sc_if->sk_miibus != NULL)
1848                 device_delete_child(dev, sc_if->sk_miibus);
1849         */
1850         bus_generic_detach(dev);
1851         sk_dma_jumbo_free(sc_if);
1852         sk_dma_free(sc_if);
1853         SK_IF_UNLOCK(sc_if);
1854
1855         return(0);
1856 }
1857
1858 static int
1859 skc_detach(dev)
1860         device_t                dev;
1861 {
1862         struct sk_softc         *sc;
1863
1864         sc = device_get_softc(dev);
1865         KASSERT(mtx_initialized(&sc->sk_mtx), ("sk mutex not initialized"));
1866
1867         if (device_is_alive(dev)) {
1868                 if (sc->sk_devs[SK_PORT_A] != NULL) {
1869                         free(device_get_ivars(sc->sk_devs[SK_PORT_A]), M_DEVBUF);
1870                         device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1871                 }
1872                 if (sc->sk_devs[SK_PORT_B] != NULL) {
1873                         free(device_get_ivars(sc->sk_devs[SK_PORT_B]), M_DEVBUF);
1874                         device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1875                 }
1876                 bus_generic_detach(dev);
1877         }
1878
1879         if (sc->sk_intrhand)
1880                 bus_teardown_intr(dev, sc->sk_res[1], sc->sk_intrhand);
1881         bus_release_resources(dev, sc->sk_res_spec, sc->sk_res);
1882
1883         mtx_destroy(&sc->sk_mii_mtx);
1884         mtx_destroy(&sc->sk_mtx);
1885
1886         return(0);
1887 }
1888
1889 static bus_dma_tag_t
1890 skc_get_dma_tag(device_t bus, device_t child __unused)
1891 {
1892
1893         return (bus_get_dma_tag(bus));
1894 }
1895
1896 struct sk_dmamap_arg {
1897         bus_addr_t      sk_busaddr;
1898 };
1899
1900 static void
1901 sk_dmamap_cb(arg, segs, nseg, error)
1902         void                    *arg;
1903         bus_dma_segment_t       *segs;
1904         int                     nseg;
1905         int                     error;
1906 {
1907         struct sk_dmamap_arg    *ctx;
1908
1909         if (error != 0)
1910                 return;
1911
1912         ctx = arg;
1913         ctx->sk_busaddr = segs[0].ds_addr;
1914 }
1915
1916 /*
1917  * Allocate jumbo buffer storage. The SysKonnect adapters support
1918  * "jumbograms" (9K frames), although SysKonnect doesn't currently
1919  * use them in their drivers. In order for us to use them, we need
1920  * large 9K receive buffers, however standard mbuf clusters are only
1921  * 2048 bytes in size. Consequently, we need to allocate and manage
1922  * our own jumbo buffer pool. Fortunately, this does not require an
1923  * excessive amount of additional code.
1924  */
1925 static int
1926 sk_dma_alloc(sc_if)
1927         struct sk_if_softc      *sc_if;
1928 {
1929         struct sk_dmamap_arg    ctx;
1930         struct sk_txdesc        *txd;
1931         struct sk_rxdesc        *rxd;
1932         int                     error, i;
1933
1934         /* create parent tag */
1935         /*
1936          * XXX
1937          * This driver should use BUS_SPACE_MAXADDR for lowaddr argument
1938          * in bus_dma_tag_create(9) as the NIC would support DAC mode.
1939          * However bz@ reported that it does not work on amd64 with > 4GB
1940          * RAM. Until we have more clues of the breakage, disable DAC mode
1941          * by limiting DMA address to be in 32bit address space.
1942          */
1943         error = bus_dma_tag_create(
1944                     bus_get_dma_tag(sc_if->sk_if_dev),/* parent */
1945                     1, 0,                       /* algnmnt, boundary */
1946                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1947                     BUS_SPACE_MAXADDR,          /* highaddr */
1948                     NULL, NULL,                 /* filter, filterarg */
1949                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1950                     0,                          /* nsegments */
1951                     BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1952                     0,                          /* flags */
1953                     NULL, NULL,                 /* lockfunc, lockarg */
1954                     &sc_if->sk_cdata.sk_parent_tag);
1955         if (error != 0) {
1956                 device_printf(sc_if->sk_if_dev,
1957                     "failed to create parent DMA tag\n");
1958                 goto fail;
1959         }
1960
1961         /* create tag for Tx ring */
1962         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1963                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1964                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1965                     BUS_SPACE_MAXADDR,          /* highaddr */
1966                     NULL, NULL,                 /* filter, filterarg */
1967                     SK_TX_RING_SZ,              /* maxsize */
1968                     1,                          /* nsegments */
1969                     SK_TX_RING_SZ,              /* maxsegsize */
1970                     0,                          /* flags */
1971                     NULL, NULL,                 /* lockfunc, lockarg */
1972                     &sc_if->sk_cdata.sk_tx_ring_tag);
1973         if (error != 0) {
1974                 device_printf(sc_if->sk_if_dev,
1975                     "failed to allocate Tx ring DMA tag\n");
1976                 goto fail;
1977         }
1978
1979         /* create tag for Rx ring */
1980         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1981                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
1982                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1983                     BUS_SPACE_MAXADDR,          /* highaddr */
1984                     NULL, NULL,                 /* filter, filterarg */
1985                     SK_RX_RING_SZ,              /* maxsize */
1986                     1,                          /* nsegments */
1987                     SK_RX_RING_SZ,              /* maxsegsize */
1988                     0,                          /* flags */
1989                     NULL, NULL,                 /* lockfunc, lockarg */
1990                     &sc_if->sk_cdata.sk_rx_ring_tag);
1991         if (error != 0) {
1992                 device_printf(sc_if->sk_if_dev,
1993                     "failed to allocate Rx ring DMA tag\n");
1994                 goto fail;
1995         }
1996
1997         /* create tag for Tx buffers */
1998         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
1999                     1, 0,                       /* algnmnt, boundary */
2000                     BUS_SPACE_MAXADDR,          /* lowaddr */
2001                     BUS_SPACE_MAXADDR,          /* highaddr */
2002                     NULL, NULL,                 /* filter, filterarg */
2003                     MCLBYTES * SK_MAXTXSEGS,    /* maxsize */
2004                     SK_MAXTXSEGS,               /* nsegments */
2005                     MCLBYTES,                   /* maxsegsize */
2006                     0,                          /* flags */
2007                     NULL, NULL,                 /* lockfunc, lockarg */
2008                     &sc_if->sk_cdata.sk_tx_tag);
2009         if (error != 0) {
2010                 device_printf(sc_if->sk_if_dev,
2011                     "failed to allocate Tx DMA tag\n");
2012                 goto fail;
2013         }
2014
2015         /* create tag for Rx buffers */
2016         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2017                     1, 0,                       /* algnmnt, boundary */
2018                     BUS_SPACE_MAXADDR,          /* lowaddr */
2019                     BUS_SPACE_MAXADDR,          /* highaddr */
2020                     NULL, NULL,                 /* filter, filterarg */
2021                     MCLBYTES,                   /* maxsize */
2022                     1,                          /* nsegments */
2023                     MCLBYTES,                   /* maxsegsize */
2024                     0,                          /* flags */
2025                     NULL, NULL,                 /* lockfunc, lockarg */
2026                     &sc_if->sk_cdata.sk_rx_tag);
2027         if (error != 0) {
2028                 device_printf(sc_if->sk_if_dev,
2029                     "failed to allocate Rx DMA tag\n");
2030                 goto fail;
2031         }
2032
2033         /* allocate DMA'able memory and load the DMA map for Tx ring */
2034         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_tx_ring_tag,
2035             (void **)&sc_if->sk_rdata.sk_tx_ring, BUS_DMA_NOWAIT |
2036             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_tx_ring_map);
2037         if (error != 0) {
2038                 device_printf(sc_if->sk_if_dev,
2039                     "failed to allocate DMA'able memory for Tx ring\n");
2040                 goto fail;
2041         }
2042
2043         ctx.sk_busaddr = 0;
2044         error = bus_dmamap_load(sc_if->sk_cdata.sk_tx_ring_tag,
2045             sc_if->sk_cdata.sk_tx_ring_map, sc_if->sk_rdata.sk_tx_ring,
2046             SK_TX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2047         if (error != 0) {
2048                 device_printf(sc_if->sk_if_dev,
2049                     "failed to load DMA'able memory for Tx ring\n");
2050                 goto fail;
2051         }
2052         sc_if->sk_rdata.sk_tx_ring_paddr = ctx.sk_busaddr;
2053
2054         /* allocate DMA'able memory and load the DMA map for Rx ring */
2055         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_rx_ring_tag,
2056             (void **)&sc_if->sk_rdata.sk_rx_ring, BUS_DMA_NOWAIT |
2057             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->sk_cdata.sk_rx_ring_map);
2058         if (error != 0) {
2059                 device_printf(sc_if->sk_if_dev,
2060                     "failed to allocate DMA'able memory for Rx ring\n");
2061                 goto fail;
2062         }
2063
2064         ctx.sk_busaddr = 0;
2065         error = bus_dmamap_load(sc_if->sk_cdata.sk_rx_ring_tag,
2066             sc_if->sk_cdata.sk_rx_ring_map, sc_if->sk_rdata.sk_rx_ring,
2067             SK_RX_RING_SZ, sk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2068         if (error != 0) {
2069                 device_printf(sc_if->sk_if_dev,
2070                     "failed to load DMA'able memory for Rx ring\n");
2071                 goto fail;
2072         }
2073         sc_if->sk_rdata.sk_rx_ring_paddr = ctx.sk_busaddr;
2074
2075         /* create DMA maps for Tx buffers */
2076         for (i = 0; i < SK_TX_RING_CNT; i++) {
2077                 txd = &sc_if->sk_cdata.sk_txdesc[i];
2078                 txd->tx_m = NULL;
2079                 txd->tx_dmamap = NULL;
2080                 error = bus_dmamap_create(sc_if->sk_cdata.sk_tx_tag, 0,
2081                     &txd->tx_dmamap);
2082                 if (error != 0) {
2083                         device_printf(sc_if->sk_if_dev,
2084                             "failed to create Tx dmamap\n");
2085                         goto fail;
2086                 }
2087         }
2088
2089         /* create DMA maps for Rx buffers */
2090         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2091             &sc_if->sk_cdata.sk_rx_sparemap)) != 0) {
2092                 device_printf(sc_if->sk_if_dev,
2093                     "failed to create spare Rx dmamap\n");
2094                 goto fail;
2095         }
2096         for (i = 0; i < SK_RX_RING_CNT; i++) {
2097                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2098                 rxd->rx_m = NULL;
2099                 rxd->rx_dmamap = NULL;
2100                 error = bus_dmamap_create(sc_if->sk_cdata.sk_rx_tag, 0,
2101                     &rxd->rx_dmamap);
2102                 if (error != 0) {
2103                         device_printf(sc_if->sk_if_dev,
2104                             "failed to create Rx dmamap\n");
2105                         goto fail;
2106                 }
2107         }
2108
2109 fail:
2110         return (error);
2111 }
2112
2113 static int
2114 sk_dma_jumbo_alloc(sc_if)
2115         struct sk_if_softc      *sc_if;
2116 {
2117         struct sk_dmamap_arg    ctx;
2118         struct sk_rxdesc        *jrxd;
2119         int                     error, i;
2120
2121         if (jumbo_disable != 0) {
2122                 device_printf(sc_if->sk_if_dev, "disabling jumbo frame support\n");
2123                 sc_if->sk_jumbo_disable = 1;
2124                 return (0);
2125         }
2126         /* create tag for jumbo Rx ring */
2127         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2128                     SK_RING_ALIGN, 0,           /* algnmnt, boundary */
2129                     BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
2130                     BUS_SPACE_MAXADDR,          /* highaddr */
2131                     NULL, NULL,                 /* filter, filterarg */
2132                     SK_JUMBO_RX_RING_SZ,        /* maxsize */
2133                     1,                          /* nsegments */
2134                     SK_JUMBO_RX_RING_SZ,        /* maxsegsize */
2135                     0,                          /* flags */
2136                     NULL, NULL,                 /* lockfunc, lockarg */
2137                     &sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2138         if (error != 0) {
2139                 device_printf(sc_if->sk_if_dev,
2140                     "failed to allocate jumbo Rx ring DMA tag\n");
2141                 goto jumbo_fail;
2142         }
2143
2144         /* create tag for jumbo Rx buffers */
2145         error = bus_dma_tag_create(sc_if->sk_cdata.sk_parent_tag,/* parent */
2146                     1, 0,                       /* algnmnt, boundary */
2147                     BUS_SPACE_MAXADDR,          /* lowaddr */
2148                     BUS_SPACE_MAXADDR,          /* highaddr */
2149                     NULL, NULL,                 /* filter, filterarg */
2150                     MJUM9BYTES,                 /* maxsize */
2151                     1,                          /* nsegments */
2152                     MJUM9BYTES,                 /* maxsegsize */
2153                     0,                          /* flags */
2154                     NULL, NULL,                 /* lockfunc, lockarg */
2155                     &sc_if->sk_cdata.sk_jumbo_rx_tag);
2156         if (error != 0) {
2157                 device_printf(sc_if->sk_if_dev,
2158                     "failed to allocate jumbo Rx DMA tag\n");
2159                 goto jumbo_fail;
2160         }
2161
2162         /* allocate DMA'able memory and load the DMA map for jumbo Rx ring */
2163         error = bus_dmamem_alloc(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2164             (void **)&sc_if->sk_rdata.sk_jumbo_rx_ring, BUS_DMA_NOWAIT |
2165             BUS_DMA_COHERENT | BUS_DMA_ZERO,
2166             &sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2167         if (error != 0) {
2168                 device_printf(sc_if->sk_if_dev,
2169                     "failed to allocate DMA'able memory for jumbo Rx ring\n");
2170                 goto jumbo_fail;
2171         }
2172
2173         ctx.sk_busaddr = 0;
2174         error = bus_dmamap_load(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2175             sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2176             sc_if->sk_rdata.sk_jumbo_rx_ring, SK_JUMBO_RX_RING_SZ, sk_dmamap_cb,
2177             &ctx, BUS_DMA_NOWAIT);
2178         if (error != 0) {
2179                 device_printf(sc_if->sk_if_dev,
2180                     "failed to load DMA'able memory for jumbo Rx ring\n");
2181                 goto jumbo_fail;
2182         }
2183         sc_if->sk_rdata.sk_jumbo_rx_ring_paddr = ctx.sk_busaddr;
2184
2185         /* create DMA maps for jumbo Rx buffers */
2186         if ((error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2187             &sc_if->sk_cdata.sk_jumbo_rx_sparemap)) != 0) {
2188                 device_printf(sc_if->sk_if_dev,
2189                     "failed to create spare jumbo Rx dmamap\n");
2190                 goto jumbo_fail;
2191         }
2192         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2193                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2194                 jrxd->rx_m = NULL;
2195                 jrxd->rx_dmamap = NULL;
2196                 error = bus_dmamap_create(sc_if->sk_cdata.sk_jumbo_rx_tag, 0,
2197                     &jrxd->rx_dmamap);
2198                 if (error != 0) {
2199                         device_printf(sc_if->sk_if_dev,
2200                             "failed to create jumbo Rx dmamap\n");
2201                         goto jumbo_fail;
2202                 }
2203         }
2204
2205         return (0);
2206
2207 jumbo_fail:
2208         sk_dma_jumbo_free(sc_if);
2209         device_printf(sc_if->sk_if_dev, "disabling jumbo frame support due to "
2210             "resource shortage\n");
2211         sc_if->sk_jumbo_disable = 1;
2212         return (0);
2213 }
2214
2215 static void
2216 sk_dma_free(sc_if)
2217         struct sk_if_softc      *sc_if;
2218 {
2219         struct sk_txdesc        *txd;
2220         struct sk_rxdesc        *rxd;
2221         int                     i;
2222
2223         /* Tx ring */
2224         if (sc_if->sk_cdata.sk_tx_ring_tag) {
2225                 if (sc_if->sk_cdata.sk_tx_ring_map)
2226                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_ring_tag,
2227                             sc_if->sk_cdata.sk_tx_ring_map);
2228                 if (sc_if->sk_cdata.sk_tx_ring_map &&
2229                     sc_if->sk_rdata.sk_tx_ring)
2230                         bus_dmamem_free(sc_if->sk_cdata.sk_tx_ring_tag,
2231                             sc_if->sk_rdata.sk_tx_ring,
2232                             sc_if->sk_cdata.sk_tx_ring_map);
2233                 sc_if->sk_rdata.sk_tx_ring = NULL;
2234                 sc_if->sk_cdata.sk_tx_ring_map = NULL;
2235                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_ring_tag);
2236                 sc_if->sk_cdata.sk_tx_ring_tag = NULL;
2237         }
2238         /* Rx ring */
2239         if (sc_if->sk_cdata.sk_rx_ring_tag) {
2240                 if (sc_if->sk_cdata.sk_rx_ring_map)
2241                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_ring_tag,
2242                             sc_if->sk_cdata.sk_rx_ring_map);
2243                 if (sc_if->sk_cdata.sk_rx_ring_map &&
2244                     sc_if->sk_rdata.sk_rx_ring)
2245                         bus_dmamem_free(sc_if->sk_cdata.sk_rx_ring_tag,
2246                             sc_if->sk_rdata.sk_rx_ring,
2247                             sc_if->sk_cdata.sk_rx_ring_map);
2248                 sc_if->sk_rdata.sk_rx_ring = NULL;
2249                 sc_if->sk_cdata.sk_rx_ring_map = NULL;
2250                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_ring_tag);
2251                 sc_if->sk_cdata.sk_rx_ring_tag = NULL;
2252         }
2253         /* Tx buffers */
2254         if (sc_if->sk_cdata.sk_tx_tag) {
2255                 for (i = 0; i < SK_TX_RING_CNT; i++) {
2256                         txd = &sc_if->sk_cdata.sk_txdesc[i];
2257                         if (txd->tx_dmamap) {
2258                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_tx_tag,
2259                                     txd->tx_dmamap);
2260                                 txd->tx_dmamap = NULL;
2261                         }
2262                 }
2263                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_tx_tag);
2264                 sc_if->sk_cdata.sk_tx_tag = NULL;
2265         }
2266         /* Rx buffers */
2267         if (sc_if->sk_cdata.sk_rx_tag) {
2268                 for (i = 0; i < SK_RX_RING_CNT; i++) {
2269                         rxd = &sc_if->sk_cdata.sk_rxdesc[i];
2270                         if (rxd->rx_dmamap) {
2271                                 bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2272                                     rxd->rx_dmamap);
2273                                 rxd->rx_dmamap = NULL;
2274                         }
2275                 }
2276                 if (sc_if->sk_cdata.sk_rx_sparemap) {
2277                         bus_dmamap_destroy(sc_if->sk_cdata.sk_rx_tag,
2278                             sc_if->sk_cdata.sk_rx_sparemap);
2279                         sc_if->sk_cdata.sk_rx_sparemap = NULL;
2280                 }
2281                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_rx_tag);
2282                 sc_if->sk_cdata.sk_rx_tag = NULL;
2283         }
2284
2285         if (sc_if->sk_cdata.sk_parent_tag) {
2286                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_parent_tag);
2287                 sc_if->sk_cdata.sk_parent_tag = NULL;
2288         }
2289 }
2290
2291 static void
2292 sk_dma_jumbo_free(sc_if)
2293         struct sk_if_softc      *sc_if;
2294 {
2295         struct sk_rxdesc        *jrxd;
2296         int                     i;
2297
2298         /* jumbo Rx ring */
2299         if (sc_if->sk_cdata.sk_jumbo_rx_ring_tag) {
2300                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map)
2301                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2302                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2303                 if (sc_if->sk_cdata.sk_jumbo_rx_ring_map &&
2304                     sc_if->sk_rdata.sk_jumbo_rx_ring)
2305                         bus_dmamem_free(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2306                             sc_if->sk_rdata.sk_jumbo_rx_ring,
2307                             sc_if->sk_cdata.sk_jumbo_rx_ring_map);
2308                 sc_if->sk_rdata.sk_jumbo_rx_ring = NULL;
2309                 sc_if->sk_cdata.sk_jumbo_rx_ring_map = NULL;
2310                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_ring_tag);
2311                 sc_if->sk_cdata.sk_jumbo_rx_ring_tag = NULL;
2312         }
2313
2314         /* jumbo Rx buffers */
2315         if (sc_if->sk_cdata.sk_jumbo_rx_tag) {
2316                 for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
2317                         jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
2318                         if (jrxd->rx_dmamap) {
2319                                 bus_dmamap_destroy(
2320                                     sc_if->sk_cdata.sk_jumbo_rx_tag,
2321                                     jrxd->rx_dmamap);
2322                                 jrxd->rx_dmamap = NULL;
2323                         }
2324                 }
2325                 if (sc_if->sk_cdata.sk_jumbo_rx_sparemap) {
2326                         bus_dmamap_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag,
2327                             sc_if->sk_cdata.sk_jumbo_rx_sparemap);
2328                         sc_if->sk_cdata.sk_jumbo_rx_sparemap = NULL;
2329                 }
2330                 bus_dma_tag_destroy(sc_if->sk_cdata.sk_jumbo_rx_tag);
2331                 sc_if->sk_cdata.sk_jumbo_rx_tag = NULL;
2332         }
2333 }
2334
2335 static void
2336 sk_txcksum(ifp, m, f)
2337         struct ifnet            *ifp;
2338         struct mbuf             *m;
2339         struct sk_tx_desc       *f;
2340 {
2341         struct ip               *ip;
2342         u_int16_t               offset;
2343         u_int8_t                *p;
2344
2345         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2346         for(; m && m->m_len == 0; m = m->m_next)
2347                 ;
2348         if (m == NULL || m->m_len < ETHER_HDR_LEN) {
2349                 if_printf(ifp, "%s: m_len < ETHER_HDR_LEN\n", __func__);
2350                 /* checksum may be corrupted */
2351                 goto sendit;
2352         }
2353         if (m->m_len < ETHER_HDR_LEN + sizeof(u_int32_t)) {
2354                 if (m->m_len != ETHER_HDR_LEN) {
2355                         if_printf(ifp, "%s: m_len != ETHER_HDR_LEN\n",
2356                             __func__);
2357                         /* checksum may be corrupted */
2358                         goto sendit;
2359                 }
2360                 for(m = m->m_next; m && m->m_len == 0; m = m->m_next)
2361                         ;
2362                 if (m == NULL) {
2363                         offset = sizeof(struct ip) + ETHER_HDR_LEN;
2364                         /* checksum may be corrupted */
2365                         goto sendit;
2366                 }
2367                 ip = mtod(m, struct ip *);
2368         } else {
2369                 p = mtod(m, u_int8_t *);
2370                 p += ETHER_HDR_LEN;
2371                 ip = (struct ip *)p;
2372         }
2373         offset = (ip->ip_hl << 2) + ETHER_HDR_LEN;
2374
2375 sendit:
2376         f->sk_csum_startval = 0;
2377         f->sk_csum_start = htole32(((offset + m->m_pkthdr.csum_data) & 0xffff) |
2378             (offset << 16));
2379 }
2380
2381 static int
2382 sk_encap(sc_if, m_head)
2383         struct sk_if_softc      *sc_if;
2384         struct mbuf             **m_head;
2385 {
2386         struct sk_txdesc        *txd;
2387         struct sk_tx_desc       *f = NULL;
2388         struct mbuf             *m;
2389         bus_dma_segment_t       txsegs[SK_MAXTXSEGS];
2390         u_int32_t               cflags, frag, si, sk_ctl;
2391         int                     error, i, nseg;
2392
2393         SK_IF_LOCK_ASSERT(sc_if);
2394
2395         if ((txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txfreeq)) == NULL)
2396                 return (ENOBUFS);
2397
2398         error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2399             txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2400         if (error == EFBIG) {
2401                 m = m_defrag(*m_head, M_NOWAIT);
2402                 if (m == NULL) {
2403                         m_freem(*m_head);
2404                         *m_head = NULL;
2405                         return (ENOMEM);
2406                 }
2407                 *m_head = m;
2408                 error = bus_dmamap_load_mbuf_sg(sc_if->sk_cdata.sk_tx_tag,
2409                     txd->tx_dmamap, *m_head, txsegs, &nseg, 0);
2410                 if (error != 0) {
2411                         m_freem(*m_head);
2412                         *m_head = NULL;
2413                         return (error);
2414                 }
2415         } else if (error != 0)
2416                 return (error);
2417         if (nseg == 0) {
2418                 m_freem(*m_head);
2419                 *m_head = NULL;
2420                 return (EIO);
2421         }
2422         if (sc_if->sk_cdata.sk_tx_cnt + nseg >= SK_TX_RING_CNT) {
2423                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2424                 return (ENOBUFS);
2425         }
2426
2427         m = *m_head;
2428         if ((m->m_pkthdr.csum_flags & sc_if->sk_ifp->if_hwassist) != 0)
2429                 cflags = SK_OPCODE_CSUM;
2430         else
2431                 cflags = SK_OPCODE_DEFAULT;
2432         si = frag = sc_if->sk_cdata.sk_tx_prod;
2433         for (i = 0; i < nseg; i++) {
2434                 f = &sc_if->sk_rdata.sk_tx_ring[frag];
2435                 f->sk_data_lo = htole32(SK_ADDR_LO(txsegs[i].ds_addr));
2436                 f->sk_data_hi = htole32(SK_ADDR_HI(txsegs[i].ds_addr));
2437                 sk_ctl = txsegs[i].ds_len | cflags;
2438                 if (i == 0) {
2439                         if (cflags == SK_OPCODE_CSUM)
2440                                 sk_txcksum(sc_if->sk_ifp, m, f);
2441                         sk_ctl |= SK_TXCTL_FIRSTFRAG;
2442                 } else
2443                         sk_ctl |= SK_TXCTL_OWN;
2444                 f->sk_ctl = htole32(sk_ctl);
2445                 sc_if->sk_cdata.sk_tx_cnt++;
2446                 SK_INC(frag, SK_TX_RING_CNT);
2447         }
2448         sc_if->sk_cdata.sk_tx_prod = frag;
2449
2450         /* set EOF on the last desciptor */
2451         frag = (frag + SK_TX_RING_CNT - 1) % SK_TX_RING_CNT;
2452         f = &sc_if->sk_rdata.sk_tx_ring[frag];
2453         f->sk_ctl |= htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
2454
2455         /* turn the first descriptor ownership to NIC */
2456         f = &sc_if->sk_rdata.sk_tx_ring[si];
2457         f->sk_ctl |= htole32(SK_TXCTL_OWN);
2458
2459         STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txfreeq, tx_q);
2460         STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txbusyq, txd, tx_q);
2461         txd->tx_m = m;
2462
2463         /* sync descriptors */
2464         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2465             BUS_DMASYNC_PREWRITE);
2466         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2467             sc_if->sk_cdata.sk_tx_ring_map,
2468             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2469
2470         return (0);
2471 }
2472
2473 static void
2474 sk_start(ifp)
2475         struct ifnet            *ifp;
2476 {
2477         struct sk_if_softc *sc_if;
2478
2479         sc_if = ifp->if_softc;
2480
2481         SK_IF_LOCK(sc_if);
2482         sk_start_locked(ifp);
2483         SK_IF_UNLOCK(sc_if);
2484
2485         return;
2486 }
2487
2488 static void
2489 sk_start_locked(ifp)
2490         struct ifnet            *ifp;
2491 {
2492         struct sk_softc         *sc;
2493         struct sk_if_softc      *sc_if;
2494         struct mbuf             *m_head;
2495         int                     enq;
2496
2497         sc_if = ifp->if_softc;
2498         sc = sc_if->sk_softc;
2499
2500         SK_IF_LOCK_ASSERT(sc_if);
2501
2502         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2503             sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 1; ) {
2504                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2505                 if (m_head == NULL)
2506                         break;
2507
2508                 /*
2509                  * Pack the data into the transmit ring. If we
2510                  * don't have room, set the OACTIVE flag and wait
2511                  * for the NIC to drain the ring.
2512                  */
2513                 if (sk_encap(sc_if, &m_head)) {
2514                         if (m_head == NULL)
2515                                 break;
2516                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2517                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2518                         break;
2519                 }
2520
2521                 enq++;
2522                 /*
2523                  * If there's a BPF listener, bounce a copy of this frame
2524                  * to him.
2525                  */
2526                 BPF_MTAP(ifp, m_head);
2527         }
2528
2529         if (enq > 0) {
2530                 /* Transmit */
2531                 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2532
2533                 /* Set a timeout in case the chip goes out to lunch. */
2534                 sc_if->sk_watchdog_timer = 5;
2535         }
2536 }
2537
2538
2539 static void
2540 sk_watchdog(arg)
2541         void                    *arg;
2542 {
2543         struct sk_if_softc      *sc_if;
2544         struct ifnet            *ifp;
2545
2546         ifp = arg;
2547         sc_if = ifp->if_softc;
2548
2549         SK_IF_LOCK_ASSERT(sc_if);
2550
2551         if (sc_if->sk_watchdog_timer == 0 || --sc_if->sk_watchdog_timer)
2552                 goto done;
2553
2554         /*
2555          * Reclaim first as there is a possibility of losing Tx completion
2556          * interrupts.
2557          */
2558         sk_txeof(sc_if);
2559         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2560                 if_printf(sc_if->sk_ifp, "watchdog timeout\n");
2561                 ifp->if_oerrors++;
2562                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2563                 sk_init_locked(sc_if);
2564         }
2565
2566 done:
2567         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
2568
2569         return;
2570 }
2571
2572 static int
2573 skc_shutdown(dev)
2574         device_t                dev;
2575 {
2576         struct sk_softc         *sc;
2577
2578         sc = device_get_softc(dev);
2579         SK_LOCK(sc);
2580
2581         /* Turn off the 'driver is loaded' LED. */
2582         CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2583
2584         /*
2585          * Reset the GEnesis controller. Doing this should also
2586          * assert the resets on the attached XMAC(s).
2587          */
2588         sk_reset(sc);
2589         SK_UNLOCK(sc);
2590
2591         return (0);
2592 }
2593
2594 static int
2595 skc_suspend(dev)
2596         device_t                dev;
2597 {
2598         struct sk_softc         *sc;
2599         struct sk_if_softc      *sc_if0, *sc_if1;
2600         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2601
2602         sc = device_get_softc(dev);
2603
2604         SK_LOCK(sc);
2605
2606         sc_if0 = sc->sk_if[SK_PORT_A];
2607         sc_if1 = sc->sk_if[SK_PORT_B];
2608         if (sc_if0 != NULL)
2609                 ifp0 = sc_if0->sk_ifp;
2610         if (sc_if1 != NULL)
2611                 ifp1 = sc_if1->sk_ifp;
2612         if (ifp0 != NULL)
2613                 sk_stop(sc_if0);
2614         if (ifp1 != NULL)
2615                 sk_stop(sc_if1);
2616         sc->sk_suspended = 1;
2617
2618         SK_UNLOCK(sc);
2619
2620         return (0);
2621 }
2622
2623 static int
2624 skc_resume(dev)
2625         device_t                dev;
2626 {
2627         struct sk_softc         *sc;
2628         struct sk_if_softc      *sc_if0, *sc_if1;
2629         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
2630
2631         sc = device_get_softc(dev);
2632
2633         SK_LOCK(sc);
2634
2635         sc_if0 = sc->sk_if[SK_PORT_A];
2636         sc_if1 = sc->sk_if[SK_PORT_B];
2637         if (sc_if0 != NULL)
2638                 ifp0 = sc_if0->sk_ifp;
2639         if (sc_if1 != NULL)
2640                 ifp1 = sc_if1->sk_ifp;
2641         if (ifp0 != NULL && ifp0->if_flags & IFF_UP)
2642                 sk_init_locked(sc_if0);
2643         if (ifp1 != NULL && ifp1->if_flags & IFF_UP)
2644                 sk_init_locked(sc_if1);
2645         sc->sk_suspended = 0;
2646
2647         SK_UNLOCK(sc);
2648
2649         return (0);
2650 }
2651
2652 /*
2653  * According to the data sheet from SK-NET GENESIS the hardware can compute
2654  * two Rx checksums at the same time(Each checksum start position is
2655  * programmed in Rx descriptors). However it seems that TCP/UDP checksum
2656  * does not work at least on my Yukon hardware. I tried every possible ways
2657  * to get correct checksum value but couldn't get correct one. So TCP/UDP
2658  * checksum offload was disabled at the moment and only IP checksum offload
2659  * was enabled.
2660  * As nomral IP header size is 20 bytes I can't expect it would give an
2661  * increase in throughput. However it seems it doesn't hurt performance in
2662  * my testing. If there is a more detailed information for checksum secret
2663  * of the hardware in question please contact yongari@FreeBSD.org to add
2664  * TCP/UDP checksum offload support.
2665  */
2666 static __inline void
2667 sk_rxcksum(ifp, m, csum)
2668         struct ifnet            *ifp;
2669         struct mbuf             *m;
2670         u_int32_t               csum;
2671 {
2672         struct ether_header     *eh;
2673         struct ip               *ip;
2674         int32_t                 hlen, len, pktlen;
2675         u_int16_t               csum1, csum2, ipcsum;
2676
2677         pktlen = m->m_pkthdr.len;
2678         if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
2679                 return;
2680         eh = mtod(m, struct ether_header *);
2681         if (eh->ether_type != htons(ETHERTYPE_IP))
2682                 return;
2683         ip = (struct ip *)(eh + 1);
2684         if (ip->ip_v != IPVERSION)
2685                 return;
2686         hlen = ip->ip_hl << 2;
2687         pktlen -= sizeof(struct ether_header);
2688         if (hlen < sizeof(struct ip))
2689                 return;
2690         if (ntohs(ip->ip_len) < hlen)
2691                 return;
2692         if (ntohs(ip->ip_len) != pktlen)
2693                 return;
2694
2695         csum1 = htons(csum & 0xffff);
2696         csum2 = htons((csum >> 16) & 0xffff);
2697         ipcsum = in_addword(csum1, ~csum2 & 0xffff);
2698         /* checksum fixup for IP options */
2699         len = hlen - sizeof(struct ip);
2700         if (len > 0) {
2701                 /*
2702                  * If the second checksum value is correct we can compute IP
2703                  * checksum with simple math. Unfortunately the second checksum
2704                  * value is wrong so we can't verify the checksum from the
2705                  * value(It seems there is some magic here to get correct
2706                  * value). If the second checksum value is correct it also
2707                  * means we can get TCP/UDP checksum) here. However, it still
2708                  * needs pseudo header checksum calculation due to hardware
2709                  * limitations.
2710                  */
2711                 return;
2712         }
2713         m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
2714         if (ipcsum == 0xffff)
2715                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2716 }
2717
2718 static __inline int
2719 sk_rxvalid(sc, stat, len)
2720         struct sk_softc         *sc;
2721         u_int32_t               stat, len;
2722 {
2723
2724         if (sc->sk_type == SK_GENESIS) {
2725                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
2726                     XM_RXSTAT_BYTES(stat) != len)
2727                         return (0);
2728         } else {
2729                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
2730                     YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
2731                     YU_RXSTAT_JABBER)) != 0 ||
2732                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
2733                     YU_RXSTAT_BYTES(stat) != len)
2734                         return (0);
2735         }
2736
2737         return (1);
2738 }
2739
2740 static void
2741 sk_rxeof(sc_if)
2742         struct sk_if_softc      *sc_if;
2743 {
2744         struct sk_softc         *sc;
2745         struct mbuf             *m;
2746         struct ifnet            *ifp;
2747         struct sk_rx_desc       *cur_rx;
2748         struct sk_rxdesc        *rxd;
2749         int                     cons, prog;
2750         u_int32_t               csum, rxstat, sk_ctl;
2751
2752         sc = sc_if->sk_softc;
2753         ifp = sc_if->sk_ifp;
2754
2755         SK_IF_LOCK_ASSERT(sc_if);
2756
2757         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2758             sc_if->sk_cdata.sk_rx_ring_map, BUS_DMASYNC_POSTREAD);
2759
2760         prog = 0;
2761         for (cons = sc_if->sk_cdata.sk_rx_cons; prog < SK_RX_RING_CNT;
2762             prog++, SK_INC(cons, SK_RX_RING_CNT)) {
2763                 cur_rx = &sc_if->sk_rdata.sk_rx_ring[cons];
2764                 sk_ctl = le32toh(cur_rx->sk_ctl);
2765                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2766                         break;
2767                 rxd = &sc_if->sk_cdata.sk_rxdesc[cons];
2768                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2769
2770                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2771                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2772                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2773                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2774                     SK_RXBYTES(sk_ctl) > SK_MAX_FRAMELEN ||
2775                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2776                         ifp->if_ierrors++;
2777                         sk_discard_rxbuf(sc_if, cons);
2778                         continue;
2779                 }
2780
2781                 m = rxd->rx_m;
2782                 csum = le32toh(cur_rx->sk_csum);
2783                 if (sk_newbuf(sc_if, cons) != 0) {
2784                         ifp->if_iqdrops++;
2785                         /* reuse old buffer */
2786                         sk_discard_rxbuf(sc_if, cons);
2787                         continue;
2788                 }
2789                 m->m_pkthdr.rcvif = ifp;
2790                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2791                 ifp->if_ipackets++;
2792                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2793                         sk_rxcksum(ifp, m, csum);
2794                 SK_IF_UNLOCK(sc_if);
2795                 (*ifp->if_input)(ifp, m);
2796                 SK_IF_LOCK(sc_if);
2797         }
2798
2799         if (prog > 0) {
2800                 sc_if->sk_cdata.sk_rx_cons = cons;
2801                 bus_dmamap_sync(sc_if->sk_cdata.sk_rx_ring_tag,
2802                     sc_if->sk_cdata.sk_rx_ring_map,
2803                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2804         }
2805 }
2806
2807 static void
2808 sk_jumbo_rxeof(sc_if)
2809         struct sk_if_softc      *sc_if;
2810 {
2811         struct sk_softc         *sc;
2812         struct mbuf             *m;
2813         struct ifnet            *ifp;
2814         struct sk_rx_desc       *cur_rx;
2815         struct sk_rxdesc        *jrxd;
2816         int                     cons, prog;
2817         u_int32_t               csum, rxstat, sk_ctl;
2818
2819         sc = sc_if->sk_softc;
2820         ifp = sc_if->sk_ifp;
2821
2822         SK_IF_LOCK_ASSERT(sc_if);
2823
2824         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2825             sc_if->sk_cdata.sk_jumbo_rx_ring_map, BUS_DMASYNC_POSTREAD);
2826
2827         prog = 0;
2828         for (cons = sc_if->sk_cdata.sk_jumbo_rx_cons;
2829             prog < SK_JUMBO_RX_RING_CNT;
2830             prog++, SK_INC(cons, SK_JUMBO_RX_RING_CNT)) {
2831                 cur_rx = &sc_if->sk_rdata.sk_jumbo_rx_ring[cons];
2832                 sk_ctl = le32toh(cur_rx->sk_ctl);
2833                 if ((sk_ctl & SK_RXCTL_OWN) != 0)
2834                         break;
2835                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[cons];
2836                 rxstat = le32toh(cur_rx->sk_xmac_rxstat);
2837
2838                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
2839                     SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
2840                     SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
2841                     SK_RXBYTES(sk_ctl) < SK_MIN_FRAMELEN ||
2842                     SK_RXBYTES(sk_ctl) > SK_JUMBO_FRAMELEN ||
2843                     sk_rxvalid(sc, rxstat, SK_RXBYTES(sk_ctl)) == 0) {
2844                         ifp->if_ierrors++;
2845                         sk_discard_jumbo_rxbuf(sc_if, cons);
2846                         continue;
2847                 }
2848
2849                 m = jrxd->rx_m;
2850                 csum = le32toh(cur_rx->sk_csum);
2851                 if (sk_jumbo_newbuf(sc_if, cons) != 0) {
2852                         ifp->if_iqdrops++;
2853                         /* reuse old buffer */
2854                         sk_discard_jumbo_rxbuf(sc_if, cons);
2855                         continue;
2856                 }
2857                 m->m_pkthdr.rcvif = ifp;
2858                 m->m_pkthdr.len = m->m_len = SK_RXBYTES(sk_ctl);
2859                 ifp->if_ipackets++;
2860                 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2861                         sk_rxcksum(ifp, m, csum);
2862                 SK_IF_UNLOCK(sc_if);
2863                 (*ifp->if_input)(ifp, m);
2864                 SK_IF_LOCK(sc_if);
2865         }
2866
2867         if (prog > 0) {
2868                 sc_if->sk_cdata.sk_jumbo_rx_cons = cons;
2869                 bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_ring_tag,
2870                     sc_if->sk_cdata.sk_jumbo_rx_ring_map,
2871                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2872         }
2873 }
2874
2875 static void
2876 sk_txeof(sc_if)
2877         struct sk_if_softc      *sc_if;
2878 {
2879         struct sk_txdesc        *txd;
2880         struct sk_tx_desc       *cur_tx;
2881         struct ifnet            *ifp;
2882         u_int32_t               idx, sk_ctl;
2883
2884         ifp = sc_if->sk_ifp;
2885
2886         txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2887         if (txd == NULL)
2888                 return;
2889         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2890             sc_if->sk_cdata.sk_tx_ring_map, BUS_DMASYNC_POSTREAD);
2891         /*
2892          * Go through our tx ring and free mbufs for those
2893          * frames that have been sent.
2894          */
2895         for (idx = sc_if->sk_cdata.sk_tx_cons;; SK_INC(idx, SK_TX_RING_CNT)) {
2896                 if (sc_if->sk_cdata.sk_tx_cnt <= 0)
2897                         break;
2898                 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2899                 sk_ctl = le32toh(cur_tx->sk_ctl);
2900                 if (sk_ctl & SK_TXCTL_OWN)
2901                         break;
2902                 sc_if->sk_cdata.sk_tx_cnt--;
2903                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2904                 if ((sk_ctl & SK_TXCTL_LASTFRAG) == 0)
2905                         continue;
2906                 bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap,
2907                     BUS_DMASYNC_POSTWRITE);
2908                 bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag, txd->tx_dmamap);
2909
2910                 ifp->if_opackets++;
2911                 m_freem(txd->tx_m);
2912                 txd->tx_m = NULL;
2913                 STAILQ_REMOVE_HEAD(&sc_if->sk_cdata.sk_txbusyq, tx_q);
2914                 STAILQ_INSERT_TAIL(&sc_if->sk_cdata.sk_txfreeq, txd, tx_q);
2915                 txd = STAILQ_FIRST(&sc_if->sk_cdata.sk_txbusyq);
2916         }
2917         sc_if->sk_cdata.sk_tx_cons = idx;
2918         sc_if->sk_watchdog_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
2919
2920         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_ring_tag,
2921             sc_if->sk_cdata.sk_tx_ring_map,
2922             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2923 }
2924
2925 static void
2926 sk_tick(xsc_if)
2927         void                    *xsc_if;
2928 {
2929         struct sk_if_softc      *sc_if;
2930         struct mii_data         *mii;
2931         struct ifnet            *ifp;
2932         int                     i;
2933
2934         sc_if = xsc_if;
2935         ifp = sc_if->sk_ifp;
2936         mii = device_get_softc(sc_if->sk_miibus);
2937
2938         if (!(ifp->if_flags & IFF_UP))
2939                 return;
2940
2941         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2942                 sk_intr_bcom(sc_if);
2943                 return;
2944         }
2945
2946         /*
2947          * According to SysKonnect, the correct way to verify that
2948          * the link has come back up is to poll bit 0 of the GPIO
2949          * register three times. This pin has the signal from the
2950          * link_sync pin connected to it; if we read the same link
2951          * state 3 times in a row, we know the link is up.
2952          */
2953         for (i = 0; i < 3; i++) {
2954                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2955                         break;
2956         }
2957
2958         if (i != 3) {
2959                 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2960                 return;
2961         }
2962
2963         /* Turn the GP0 interrupt back on. */
2964         SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2965         SK_XM_READ_2(sc_if, XM_ISR);
2966         mii_tick(mii);
2967         callout_stop(&sc_if->sk_tick_ch);
2968 }
2969
2970 static void
2971 sk_yukon_tick(xsc_if)
2972         void                    *xsc_if;
2973 {
2974         struct sk_if_softc      *sc_if;
2975         struct mii_data         *mii;
2976
2977         sc_if = xsc_if;
2978         mii = device_get_softc(sc_if->sk_miibus);
2979
2980         mii_tick(mii);
2981         callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
2982 }
2983
2984 static void
2985 sk_intr_bcom(sc_if)
2986         struct sk_if_softc      *sc_if;
2987 {
2988         struct mii_data         *mii;
2989         struct ifnet            *ifp;
2990         int                     status;
2991         mii = device_get_softc(sc_if->sk_miibus);
2992         ifp = sc_if->sk_ifp;
2993
2994         SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2995
2996         /*
2997          * Read the PHY interrupt register to make sure
2998          * we clear any pending interrupts.
2999          */
3000         status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
3001
3002         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3003                 sk_init_xmac(sc_if);
3004                 return;
3005         }
3006
3007         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
3008                 int                     lstat;
3009                 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
3010                     BRGPHY_MII_AUXSTS);
3011
3012                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
3013                         mii_mediachg(mii);
3014                         /* Turn off the link LED. */
3015                         SK_IF_WRITE_1(sc_if, 0,
3016                             SK_LINKLED1_CTL, SK_LINKLED_OFF);
3017                         sc_if->sk_link = 0;
3018                 } else if (status & BRGPHY_ISR_LNK_CHG) {
3019                         sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3020                             BRGPHY_MII_IMR, 0xFF00);
3021                         mii_tick(mii);
3022                         sc_if->sk_link = 1;
3023                         /* Turn on the link LED. */
3024                         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3025                             SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
3026                             SK_LINKLED_BLINK_OFF);
3027                 } else {
3028                         mii_tick(mii);
3029                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3030                 }
3031         }
3032
3033         SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3034
3035         return;
3036 }
3037
3038 static void
3039 sk_intr_xmac(sc_if)
3040         struct sk_if_softc      *sc_if;
3041 {
3042         struct sk_softc         *sc;
3043         u_int16_t               status;
3044
3045         sc = sc_if->sk_softc;
3046         status = SK_XM_READ_2(sc_if, XM_ISR);
3047
3048         /*
3049          * Link has gone down. Start MII tick timeout to
3050          * watch for link resync.
3051          */
3052         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
3053                 if (status & XM_ISR_GP0_SET) {
3054                         SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
3055                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3056                 }
3057
3058                 if (status & XM_ISR_AUTONEG_DONE) {
3059                         callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
3060                 }
3061         }
3062
3063         if (status & XM_IMR_TX_UNDERRUN)
3064                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
3065
3066         if (status & XM_IMR_RX_OVERRUN)
3067                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
3068
3069         status = SK_XM_READ_2(sc_if, XM_ISR);
3070
3071         return;
3072 }
3073
3074 static void
3075 sk_intr_yukon(sc_if)
3076         struct sk_if_softc      *sc_if;
3077 {
3078         u_int8_t status;
3079
3080         status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
3081         /* RX overrun */
3082         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
3083                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3084                     SK_RFCTL_RX_FIFO_OVER);
3085         }
3086         /* TX underrun */
3087         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
3088                 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
3089                     SK_TFCTL_TX_FIFO_UNDER);
3090         }
3091 }
3092
3093 static void
3094 sk_intr(xsc)
3095         void                    *xsc;
3096 {
3097         struct sk_softc         *sc = xsc;
3098         struct sk_if_softc      *sc_if0, *sc_if1;
3099         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
3100         u_int32_t               status;
3101
3102         SK_LOCK(sc);
3103
3104         status = CSR_READ_4(sc, SK_ISSR);
3105         if (status == 0 || status == 0xffffffff || sc->sk_suspended)
3106                 goto done_locked;
3107
3108         sc_if0 = sc->sk_if[SK_PORT_A];
3109         sc_if1 = sc->sk_if[SK_PORT_B];
3110
3111         if (sc_if0 != NULL)
3112                 ifp0 = sc_if0->sk_ifp;
3113         if (sc_if1 != NULL)
3114                 ifp1 = sc_if1->sk_ifp;
3115
3116         for (; (status &= sc->sk_intrmask) != 0;) {
3117                 /* Handle receive interrupts first. */
3118                 if (status & SK_ISR_RX1_EOF) {
3119                         if (ifp0->if_mtu > SK_MAX_FRAMELEN)
3120                                 sk_jumbo_rxeof(sc_if0);
3121                         else
3122                                 sk_rxeof(sc_if0);
3123                         CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
3124                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3125                 }
3126                 if (status & SK_ISR_RX2_EOF) {
3127                         if (ifp1->if_mtu > SK_MAX_FRAMELEN)
3128                                 sk_jumbo_rxeof(sc_if1);
3129                         else
3130                                 sk_rxeof(sc_if1);
3131                         CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
3132                             SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
3133                 }
3134
3135                 /* Then transmit interrupts. */
3136                 if (status & SK_ISR_TX1_S_EOF) {
3137                         sk_txeof(sc_if0);
3138                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR0, SK_TXBMU_CLR_IRQ_EOF);
3139                 }
3140                 if (status & SK_ISR_TX2_S_EOF) {
3141                         sk_txeof(sc_if1);
3142                         CSR_WRITE_4(sc, SK_BMU_TXS_CSR1, SK_TXBMU_CLR_IRQ_EOF);
3143                 }
3144
3145                 /* Then MAC interrupts. */
3146                 if (status & SK_ISR_MAC1 &&
3147                     ifp0->if_drv_flags & IFF_DRV_RUNNING) {
3148                         if (sc->sk_type == SK_GENESIS)
3149                                 sk_intr_xmac(sc_if0);
3150                         else
3151                                 sk_intr_yukon(sc_if0);
3152                 }
3153
3154                 if (status & SK_ISR_MAC2 &&
3155                     ifp1->if_drv_flags & IFF_DRV_RUNNING) {
3156                         if (sc->sk_type == SK_GENESIS)
3157                                 sk_intr_xmac(sc_if1);
3158                         else
3159                                 sk_intr_yukon(sc_if1);
3160                 }
3161
3162                 if (status & SK_ISR_EXTERNAL_REG) {
3163                         if (ifp0 != NULL &&
3164                             sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
3165                                 sk_intr_bcom(sc_if0);
3166                         if (ifp1 != NULL &&
3167                             sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
3168                                 sk_intr_bcom(sc_if1);
3169                 }
3170                 status = CSR_READ_4(sc, SK_ISSR);
3171         }
3172
3173         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3174
3175         if (ifp0 != NULL && !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3176                 sk_start_locked(ifp0);
3177         if (ifp1 != NULL && !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3178                 sk_start_locked(ifp1);
3179
3180 done_locked:
3181         SK_UNLOCK(sc);
3182 }
3183
3184 static void
3185 sk_init_xmac(sc_if)
3186         struct sk_if_softc      *sc_if;
3187 {
3188         struct sk_softc         *sc;
3189         struct ifnet            *ifp;
3190         u_int16_t               eaddr[(ETHER_ADDR_LEN+1)/2];
3191         static const struct sk_bcom_hack bhack[] = {
3192         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
3193         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
3194         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
3195         { 0, 0 } };
3196
3197         SK_IF_LOCK_ASSERT(sc_if);
3198
3199         sc = sc_if->sk_softc;
3200         ifp = sc_if->sk_ifp;
3201
3202         /* Unreset the XMAC. */
3203         SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
3204         DELAY(1000);
3205
3206         /* Reset the XMAC's internal state. */
3207         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3208
3209         /* Save the XMAC II revision */
3210         sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
3211
3212         /*
3213          * Perform additional initialization for external PHYs,
3214          * namely for the 1000baseTX cards that use the XMAC's
3215          * GMII mode.
3216          */
3217         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3218                 int                     i = 0;
3219                 u_int32_t               val;
3220
3221                 /* Take PHY out of reset. */
3222                 val = sk_win_read_4(sc, SK_GPIO);
3223                 if (sc_if->sk_port == SK_PORT_A)
3224                         val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
3225                 else
3226                         val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
3227                 sk_win_write_4(sc, SK_GPIO, val);
3228
3229                 /* Enable GMII mode on the XMAC. */
3230                 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
3231
3232                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3233                     BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
3234                 DELAY(10000);
3235                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3236                     BRGPHY_MII_IMR, 0xFFF0);
3237
3238                 /*
3239                  * Early versions of the BCM5400 apparently have
3240                  * a bug that requires them to have their reserved
3241                  * registers initialized to some magic values. I don't
3242                  * know what the numbers do, I'm just the messenger.
3243                  */
3244                 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
3245                     == 0x6041) {
3246                         while(bhack[i].reg) {
3247                                 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
3248                                     bhack[i].reg, bhack[i].val);
3249                                 i++;
3250                         }
3251                 }
3252         }
3253
3254         /* Set station address */
3255         bcopy(IF_LLADDR(sc_if->sk_ifp), eaddr, ETHER_ADDR_LEN);
3256         SK_XM_WRITE_2(sc_if, XM_PAR0, eaddr[0]);
3257         SK_XM_WRITE_2(sc_if, XM_PAR1, eaddr[1]);
3258         SK_XM_WRITE_2(sc_if, XM_PAR2, eaddr[2]);
3259         SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
3260
3261         if (ifp->if_flags & IFF_BROADCAST) {
3262                 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3263         } else {
3264                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
3265         }
3266
3267         /* We don't need the FCS appended to the packet. */
3268         SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
3269
3270         /* We want short frames padded to 60 bytes. */
3271         SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
3272
3273         /*
3274          * Enable the reception of all error frames. This is is
3275          * a necessary evil due to the design of the XMAC. The
3276          * XMAC's receive FIFO is only 8K in size, however jumbo
3277          * frames can be up to 9000 bytes in length. When bad
3278          * frame filtering is enabled, the XMAC's RX FIFO operates
3279          * in 'store and forward' mode. For this to work, the
3280          * entire frame has to fit into the FIFO, but that means
3281          * that jumbo frames larger than 8192 bytes will be
3282          * truncated. Disabling all bad frame filtering causes
3283          * the RX FIFO to operate in streaming mode, in which
3284          * case the XMAC will start transfering frames out of the
3285          * RX FIFO as soon as the FIFO threshold is reached.
3286          */
3287         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3288                 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
3289                     XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
3290                     XM_MODE_RX_INRANGELEN);
3291                 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3292         } else
3293                 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
3294
3295         /*
3296          * Bump up the transmit threshold. This helps hold off transmit
3297          * underruns when we're blasting traffic from both ports at once.
3298          */
3299         SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
3300
3301         /* Set Rx filter */
3302         sk_rxfilter_genesis(sc_if);
3303
3304         /* Clear and enable interrupts */
3305         SK_XM_READ_2(sc_if, XM_ISR);
3306         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
3307                 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
3308         else
3309                 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3310
3311         /* Configure MAC arbiter */
3312         switch(sc_if->sk_xmac_rev) {
3313         case XM_XMAC_REV_B2:
3314                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
3315                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
3316                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
3317                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
3318                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
3319                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
3320                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
3321                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
3322                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3323                 break;
3324         case XM_XMAC_REV_C1:
3325                 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
3326                 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
3327                 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
3328                 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
3329                 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
3330                 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
3331                 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
3332                 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
3333                 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
3334                 break;
3335         default:
3336                 break;
3337         }
3338         sk_win_write_2(sc, SK_MACARB_CTL,
3339             SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
3340
3341         sc_if->sk_link = 1;
3342
3343         return;
3344 }
3345
3346 static void
3347 sk_init_yukon(sc_if)
3348         struct sk_if_softc      *sc_if;
3349 {
3350         u_int32_t               phy, v;
3351         u_int16_t               reg;
3352         struct sk_softc         *sc;
3353         struct ifnet            *ifp;
3354         u_int8_t                *eaddr;
3355         int                     i;
3356
3357         SK_IF_LOCK_ASSERT(sc_if);
3358
3359         sc = sc_if->sk_softc;
3360         ifp = sc_if->sk_ifp;
3361
3362         if (sc->sk_type == SK_YUKON_LITE &&
3363             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3364                 /*
3365                  * Workaround code for COMA mode, set PHY reset.
3366                  * Otherwise it will not correctly take chip out of
3367                  * powerdown (coma)
3368                  */
3369                 v = sk_win_read_4(sc, SK_GPIO);
3370                 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
3371                 sk_win_write_4(sc, SK_GPIO, v);
3372         }
3373
3374         /* GMAC and GPHY Reset */
3375         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
3376         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
3377         DELAY(1000);
3378
3379         if (sc->sk_type == SK_YUKON_LITE &&
3380             sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
3381                 /*
3382                  * Workaround code for COMA mode, clear PHY reset
3383                  */
3384                 v = sk_win_read_4(sc, SK_GPIO);
3385                 v |= SK_GPIO_DIR9;
3386                 v &= ~SK_GPIO_DAT9;
3387                 sk_win_write_4(sc, SK_GPIO, v);
3388         }
3389
3390         phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
3391                 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
3392
3393         if (sc->sk_coppertype)
3394                 phy |= SK_GPHY_COPPER;
3395         else
3396                 phy |= SK_GPHY_FIBER;
3397
3398         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
3399         DELAY(1000);
3400         SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
3401         SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
3402                       SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
3403
3404         /* unused read of the interrupt source register */
3405         SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
3406
3407         reg = SK_YU_READ_2(sc_if, YUKON_PAR);
3408
3409         /* MIB Counter Clear Mode set */
3410         reg |= YU_PAR_MIB_CLR;
3411         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3412
3413         /* MIB Counter Clear Mode clear */
3414         reg &= ~YU_PAR_MIB_CLR;
3415         SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
3416
3417         /* receive control reg */
3418         SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
3419
3420         /* transmit parameter register */
3421         SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
3422                       YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
3423
3424         /* serial mode register */
3425         reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
3426         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3427                 reg |= YU_SMR_MFL_JUMBO;
3428         SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
3429
3430         /* Setup Yukon's station address */
3431         eaddr = IF_LLADDR(sc_if->sk_ifp);
3432         for (i = 0; i < 3; i++)
3433                 SK_YU_WRITE_2(sc_if, SK_MAC0_0 + i * 4,
3434                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3435         /* Set GMAC source address of flow control. */
3436         for (i = 0; i < 3; i++)
3437                 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
3438                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3439         /* Set GMAC virtual address. */
3440         for (i = 0; i < 3; i++)
3441                 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4,
3442                     eaddr[i * 2] | eaddr[i * 2 + 1] << 8);
3443
3444         /* Set Rx filter */
3445         sk_rxfilter_yukon(sc_if);
3446
3447         /* enable interrupt mask for counter overflows */
3448         SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
3449         SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
3450         SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
3451
3452         /* Configure RX MAC FIFO Flush Mask */
3453         v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
3454             YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
3455             YU_RXSTAT_JABBER;
3456         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
3457
3458         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
3459         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
3460                 v = SK_TFCTL_OPERATION_ON;
3461         else
3462                 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
3463         /* Configure RX MAC FIFO */
3464         SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
3465         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
3466
3467         /* Increase flush threshould to 64 bytes */
3468         SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
3469             SK_RFCTL_FIFO_THRESHOLD + 1);
3470
3471         /* Configure TX MAC FIFO */
3472         SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
3473         SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
3474 }
3475
3476 /*
3477  * Note that to properly initialize any part of the GEnesis chip,
3478  * you first have to take it out of reset mode.
3479  */
3480 static void
3481 sk_init(xsc)
3482         void                    *xsc;
3483 {
3484         struct sk_if_softc      *sc_if = xsc;
3485
3486         SK_IF_LOCK(sc_if);
3487         sk_init_locked(sc_if);
3488         SK_IF_UNLOCK(sc_if);
3489
3490         return;
3491 }
3492
3493 static void
3494 sk_init_locked(sc_if)
3495         struct sk_if_softc      *sc_if;
3496 {
3497         struct sk_softc         *sc;
3498         struct ifnet            *ifp;
3499         struct mii_data         *mii;
3500         u_int16_t               reg;
3501         u_int32_t               imr;
3502         int                     error;
3503
3504         SK_IF_LOCK_ASSERT(sc_if);
3505
3506         ifp = sc_if->sk_ifp;
3507         sc = sc_if->sk_softc;
3508         mii = device_get_softc(sc_if->sk_miibus);
3509
3510         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3511                 return;
3512
3513         /* Cancel pending I/O and free all RX/TX buffers. */
3514         sk_stop(sc_if);
3515
3516         if (sc->sk_type == SK_GENESIS) {
3517                 /* Configure LINK_SYNC LED */
3518                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
3519                 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
3520                         SK_LINKLED_LINKSYNC_ON);
3521
3522                 /* Configure RX LED */
3523                 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
3524                         SK_RXLEDCTL_COUNTER_START);
3525
3526                 /* Configure TX LED */
3527                 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
3528                         SK_TXLEDCTL_COUNTER_START);
3529         }
3530
3531         /*
3532          * Configure descriptor poll timer
3533          *
3534          * SK-NET GENESIS data sheet says that possibility of losing Start
3535          * transmit command due to CPU/cache related interim storage problems
3536          * under certain conditions. The document recommends a polling
3537          * mechanism to send a Start transmit command to initiate transfer
3538          * of ready descriptors regulary. To cope with this issue sk(4) now
3539          * enables descriptor poll timer to initiate descriptor processing
3540          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
3541          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
3542          * command instead of waiting for next descriptor polling time.
3543          * The same rule may apply to Rx side too but it seems that is not
3544          * needed at the moment.
3545          * Since sk(4) uses descriptor polling as a last resort there is no
3546          * need to set smaller polling time than maximum allowable one.
3547          */
3548         SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
3549
3550         /* Configure I2C registers */
3551
3552         /* Configure XMAC(s) */
3553         switch (sc->sk_type) {
3554         case SK_GENESIS:
3555                 sk_init_xmac(sc_if);
3556                 break;
3557         case SK_YUKON:
3558         case SK_YUKON_LITE:
3559         case SK_YUKON_LP:
3560                 sk_init_yukon(sc_if);
3561                 break;
3562         }
3563         mii_mediachg(mii);
3564
3565         if (sc->sk_type == SK_GENESIS) {
3566                 /* Configure MAC FIFOs */
3567                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
3568                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
3569                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
3570
3571                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
3572                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
3573                 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
3574         }
3575
3576         /* Configure transmit arbiter(s) */
3577         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
3578             SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
3579
3580         /* Configure RAMbuffers */
3581         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
3582         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
3583         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
3584         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
3585         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
3586         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
3587
3588         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
3589         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
3590         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
3591         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
3592         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
3593         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
3594         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
3595
3596         /* Configure BMUs */
3597         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
3598         if (ifp->if_mtu > SK_MAX_FRAMELEN) {
3599                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3600                     SK_ADDR_LO(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3601                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3602                     SK_ADDR_HI(SK_JUMBO_RX_RING_ADDR(sc_if, 0)));
3603         } else {
3604                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
3605                     SK_ADDR_LO(SK_RX_RING_ADDR(sc_if, 0)));
3606                 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
3607                     SK_ADDR_HI(SK_RX_RING_ADDR(sc_if, 0)));
3608         }
3609
3610         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
3611         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
3612             SK_ADDR_LO(SK_TX_RING_ADDR(sc_if, 0)));
3613         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
3614             SK_ADDR_HI(SK_TX_RING_ADDR(sc_if, 0)));
3615
3616         /* Init descriptors */
3617         if (ifp->if_mtu > SK_MAX_FRAMELEN)
3618                 error = sk_init_jumbo_rx_ring(sc_if);
3619         else
3620                 error = sk_init_rx_ring(sc_if);
3621         if (error != 0) {
3622                 device_printf(sc_if->sk_if_dev,
3623                     "initialization failed: no memory for rx buffers\n");
3624                 sk_stop(sc_if);
3625                 return;
3626         }
3627         sk_init_tx_ring(sc_if);
3628
3629         /* Set interrupt moderation if changed via sysctl. */
3630         imr = sk_win_read_4(sc, SK_IMTIMERINIT);
3631         if (imr != SK_IM_USECS(sc->sk_int_mod, sc->sk_int_ticks)) {
3632                 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod,
3633                     sc->sk_int_ticks));
3634                 if (bootverbose)
3635                         device_printf(sc_if->sk_if_dev,
3636                             "interrupt moderation is %d us.\n",
3637                             sc->sk_int_mod);
3638         }
3639
3640         /* Configure interrupt handling */
3641         CSR_READ_4(sc, SK_ISSR);
3642         if (sc_if->sk_port == SK_PORT_A)
3643                 sc->sk_intrmask |= SK_INTRS1;
3644         else
3645                 sc->sk_intrmask |= SK_INTRS2;
3646
3647         sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
3648
3649         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3650
3651         /* Start BMUs. */
3652         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
3653
3654         switch(sc->sk_type) {
3655         case SK_GENESIS:
3656                 /* Enable XMACs TX and RX state machines */
3657                 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
3658                 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
3659                 break;
3660         case SK_YUKON:
3661         case SK_YUKON_LITE:
3662         case SK_YUKON_LP:
3663                 reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
3664                 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
3665 #if 0
3666                 /* XXX disable 100Mbps and full duplex mode? */
3667                 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
3668 #endif
3669                 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
3670         }
3671
3672         /* Activate descriptor polling timer */
3673         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
3674         /* start transfer of Tx descriptors */
3675         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
3676
3677         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3678         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3679
3680         switch (sc->sk_type) {
3681         case SK_YUKON:
3682         case SK_YUKON_LITE:
3683         case SK_YUKON_LP:
3684                 callout_reset(&sc_if->sk_tick_ch, hz, sk_yukon_tick, sc_if);
3685                 break;
3686         }
3687
3688         callout_reset(&sc_if->sk_watchdog_ch, hz, sk_watchdog, ifp);
3689
3690         return;
3691 }
3692
3693 static void
3694 sk_stop(sc_if)
3695         struct sk_if_softc      *sc_if;
3696 {
3697         int                     i;
3698         struct sk_softc         *sc;
3699         struct sk_txdesc        *txd;
3700         struct sk_rxdesc        *rxd;
3701         struct sk_rxdesc        *jrxd;
3702         struct ifnet            *ifp;
3703         u_int32_t               val;
3704
3705         SK_IF_LOCK_ASSERT(sc_if);
3706         sc = sc_if->sk_softc;
3707         ifp = sc_if->sk_ifp;
3708
3709         callout_stop(&sc_if->sk_tick_ch);
3710         callout_stop(&sc_if->sk_watchdog_ch);
3711
3712         /* stop Tx descriptor polling timer */
3713         SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
3714         /* stop transfer of Tx descriptors */
3715         CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
3716         for (i = 0; i < SK_TIMEOUT; i++) {
3717                 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
3718                 if ((val & SK_TXBMU_TX_STOP) == 0)
3719                         break;
3720                 DELAY(1);
3721         }
3722         if (i == SK_TIMEOUT)
3723                 device_printf(sc_if->sk_if_dev,
3724                     "can not stop transfer of Tx descriptor\n");
3725         /* stop transfer of Rx descriptors */
3726         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
3727         for (i = 0; i < SK_TIMEOUT; i++) {
3728                 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
3729                 if ((val & SK_RXBMU_RX_STOP) == 0)
3730                         break;
3731                 DELAY(1);
3732         }
3733         if (i == SK_TIMEOUT)
3734                 device_printf(sc_if->sk_if_dev,
3735                     "can not stop transfer of Rx descriptor\n");
3736
3737         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
3738                 /* Put PHY back into reset. */
3739                 val = sk_win_read_4(sc, SK_GPIO);
3740                 if (sc_if->sk_port == SK_PORT_A) {
3741                         val |= SK_GPIO_DIR0;
3742                         val &= ~SK_GPIO_DAT0;
3743                 } else {
3744                         val |= SK_GPIO_DIR2;
3745                         val &= ~SK_GPIO_DAT2;
3746                 }
3747                 sk_win_write_4(sc, SK_GPIO, val);
3748         }
3749
3750         /* Turn off various components of this interface. */
3751         SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
3752         switch (sc->sk_type) {
3753         case SK_GENESIS:
3754                 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
3755                 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
3756                 break;
3757         case SK_YUKON:
3758         case SK_YUKON_LITE:
3759         case SK_YUKON_LP:
3760                 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
3761                 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
3762                 break;
3763         }
3764         SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
3765         SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3766         SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
3767         SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
3768         SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
3769         SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3770         SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
3771         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
3772         SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
3773
3774         /* Disable interrupts */
3775         if (sc_if->sk_port == SK_PORT_A)
3776                 sc->sk_intrmask &= ~SK_INTRS1;
3777         else
3778                 sc->sk_intrmask &= ~SK_INTRS2;
3779         CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
3780
3781         SK_XM_READ_2(sc_if, XM_ISR);
3782         SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
3783
3784         /* Free RX and TX mbufs still in the queues. */
3785         for (i = 0; i < SK_RX_RING_CNT; i++) {
3786                 rxd = &sc_if->sk_cdata.sk_rxdesc[i];
3787                 if (rxd->rx_m != NULL) {
3788                         bus_dmamap_sync(sc_if->sk_cdata.sk_rx_tag,
3789                             rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3790                         bus_dmamap_unload(sc_if->sk_cdata.sk_rx_tag,
3791                             rxd->rx_dmamap);
3792                         m_freem(rxd->rx_m);
3793                         rxd->rx_m = NULL;
3794                 }
3795         }
3796         for (i = 0; i < SK_JUMBO_RX_RING_CNT; i++) {
3797                 jrxd = &sc_if->sk_cdata.sk_jumbo_rxdesc[i];
3798                 if (jrxd->rx_m != NULL) {
3799                         bus_dmamap_sync(sc_if->sk_cdata.sk_jumbo_rx_tag,
3800                             jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3801                         bus_dmamap_unload(sc_if->sk_cdata.sk_jumbo_rx_tag,
3802                             jrxd->rx_dmamap);
3803                         m_freem(jrxd->rx_m);
3804                         jrxd->rx_m = NULL;
3805                 }
3806         }
3807         for (i = 0; i < SK_TX_RING_CNT; i++) {
3808                 txd = &sc_if->sk_cdata.sk_txdesc[i];
3809                 if (txd->tx_m != NULL) {
3810                         bus_dmamap_sync(sc_if->sk_cdata.sk_tx_tag,
3811                             txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3812                         bus_dmamap_unload(sc_if->sk_cdata.sk_tx_tag,
3813                             txd->tx_dmamap);
3814                         m_freem(txd->tx_m);
3815                         txd->tx_m = NULL;
3816                 }
3817         }
3818
3819         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE);
3820
3821         return;
3822 }
3823
3824 static int
3825 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3826 {
3827         int error, value;
3828
3829         if (!arg1)
3830                 return (EINVAL);
3831         value = *(int *)arg1;
3832         error = sysctl_handle_int(oidp, &value, 0, req);
3833         if (error || !req->newptr)
3834                 return (error);
3835         if (value < low || value > high)
3836                 return (EINVAL);
3837         *(int *)arg1 = value;
3838         return (0);
3839 }
3840
3841 static int
3842 sysctl_hw_sk_int_mod(SYSCTL_HANDLER_ARGS)
3843 {
3844         return (sysctl_int_range(oidp, arg1, arg2, req, SK_IM_MIN, SK_IM_MAX));
3845 }