2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
49 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52 #include <dev/uart/uart_dev_ns8250.h>
54 #include <dev/ic/ns16550.h>
58 #define DEFAULT_RCLK 1843200
60 static int broken_txfifo = 0;
61 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
62 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
63 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
66 * Clear pending interrupts. THRE is cleared by reading IIR. Data
67 * that may have been received gets lost here.
70 ns8250_clrint(struct uart_bas *bas)
74 iir = uart_getreg(bas, REG_IIR);
75 while ((iir & IIR_NOPEND) == 0) {
78 lsr = uart_getreg(bas, REG_LSR);
79 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
80 (void)uart_getreg(bas, REG_DATA);
81 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
82 (void)uart_getreg(bas, REG_DATA);
83 else if (iir == IIR_MLSC)
84 (void)uart_getreg(bas, REG_MSR);
86 iir = uart_getreg(bas, REG_IIR);
91 ns8250_delay(struct uart_bas *bas)
96 lcr = uart_getreg(bas, REG_LCR);
97 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
99 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
101 uart_setreg(bas, REG_LCR, lcr);
104 /* 1/10th the time to transmit 1 character (estimate). */
106 return (16000000 * divisor / bas->rclk);
107 return (16000 * divisor / (bas->rclk / 1000));
111 ns8250_divisor(int rclk, int baudrate)
113 int actual_baud, divisor;
119 divisor = (rclk / (baudrate << 3) + 1) >> 1;
120 if (divisor == 0 || divisor >= 65536)
122 actual_baud = rclk / (divisor << 4);
124 /* 10 times error in percent: */
125 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
127 /* 3.0% maximum error tolerance: */
128 if (error < -30 || error > 30)
135 ns8250_drain(struct uart_bas *bas, int what)
139 delay = ns8250_delay(bas);
141 if (what & UART_DRAIN_TRANSMITTER) {
143 * Pick an arbitrary high limit to avoid getting stuck in
144 * an infinite loop when the hardware is broken. Make the
145 * limit high enough to handle large FIFOs.
148 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
151 /* printf("ns8250: transmitter appears stuck... "); */
156 if (what & UART_DRAIN_RECEIVER) {
158 * Pick an arbitrary high limit to avoid getting stuck in
159 * an infinite loop when the hardware is broken. Make the
160 * limit high enough to handle large FIFOs and integrated
161 * UARTs. The HP rx2600 for example has 3 UARTs on the
162 * management board that tend to get a lot of data send
163 * to it when the UART is first activated.
166 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
167 (void)uart_getreg(bas, REG_DATA);
172 /* printf("ns8250: receiver appears broken... "); */
181 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
182 * drained. WARNING: this function clobbers the FIFO setting!
185 ns8250_flush(struct uart_bas *bas, int what)
190 if (what & UART_FLUSH_TRANSMITTER)
192 if (what & UART_FLUSH_RECEIVER)
194 uart_setreg(bas, REG_FCR, fcr);
199 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
208 else if (databits == 7)
210 else if (databits == 6)
220 divisor = ns8250_divisor(bas->rclk, baudrate);
223 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
225 uart_setreg(bas, REG_DLL, divisor & 0xff);
226 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
230 /* Set LCR and clear DLAB. */
231 uart_setreg(bas, REG_LCR, lcr);
237 * Low-level UART interface.
239 static int ns8250_probe(struct uart_bas *bas);
240 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
241 static void ns8250_term(struct uart_bas *bas);
242 static void ns8250_putc(struct uart_bas *bas, int);
243 static int ns8250_rxready(struct uart_bas *bas);
244 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
246 struct uart_ops uart_ns8250_ops = {
247 .probe = ns8250_probe,
251 .rxready = ns8250_rxready,
256 ns8250_probe(struct uart_bas *bas)
260 /* Check known 0 bits that don't depend on DLAB. */
261 val = uart_getreg(bas, REG_IIR);
265 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
266 * chip, but otherwise doesn't seem to have a function. In
267 * other words, uart(4) works regardless. Ignore that bit so
268 * the probe succeeds.
270 val = uart_getreg(bas, REG_MCR);
278 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
284 bas->rclk = DEFAULT_RCLK;
285 ns8250_param(bas, baudrate, databits, stopbits, parity);
287 /* Disable all interrupt sources. */
289 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
290 * UARTs split the receive time-out interrupt bit out separately as
291 * 0x10. This gets handled by ier_mask and ier_rxbits below.
293 ier = uart_getreg(bas, REG_IER) & 0xe0;
294 uart_setreg(bas, REG_IER, ier);
297 /* Disable the FIFO (if present). */
298 uart_setreg(bas, REG_FCR, 0);
302 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
309 ns8250_term(struct uart_bas *bas)
312 /* Clear RTS & DTR. */
313 uart_setreg(bas, REG_MCR, MCR_IE);
318 ns8250_putc(struct uart_bas *bas, int c)
323 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
325 uart_setreg(bas, REG_DATA, c);
328 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
333 ns8250_rxready(struct uart_bas *bas)
336 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
340 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
346 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
352 c = uart_getreg(bas, REG_DATA);
359 static kobj_method_t ns8250_methods[] = {
360 KOBJMETHOD(uart_attach, ns8250_bus_attach),
361 KOBJMETHOD(uart_detach, ns8250_bus_detach),
362 KOBJMETHOD(uart_flush, ns8250_bus_flush),
363 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
364 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
365 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
366 KOBJMETHOD(uart_param, ns8250_bus_param),
367 KOBJMETHOD(uart_probe, ns8250_bus_probe),
368 KOBJMETHOD(uart_receive, ns8250_bus_receive),
369 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
370 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
371 KOBJMETHOD(uart_grab, ns8250_bus_grab),
372 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
376 struct uart_class uart_ns8250_class = {
379 sizeof(struct ns8250_softc),
380 .uc_ops = &uart_ns8250_ops,
382 .uc_rclk = DEFAULT_RCLK
386 static struct ofw_compat_data compat_data[] = {
387 {"ns16550", (uintptr_t)&uart_ns8250_class},
388 {NULL, (uintptr_t)NULL},
390 UART_FDT_CLASS_AND_DEVICE(compat_data);
393 #define SIGCHG(c, i, s, d) \
395 i |= (i & s) ? s : s | d; \
397 i = (i & s) ? (i & ~s) | d : i; \
401 ns8250_bus_attach(struct uart_softc *sc)
403 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
404 struct uart_bas *bas;
411 ns8250->busy_detect = 0;
415 * Check whether uart requires to read USR reg when IIR_BUSY and
418 node = ofw_bus_get_node(sc->sc_dev);
419 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
420 ns8250->busy_detect = 1;
421 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
427 ns8250->mcr = uart_getreg(bas, REG_MCR);
428 ns8250->fcr = FCR_ENABLE;
429 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
431 if (UART_FLAGS_FCR_RX_LOW(ivar))
432 ns8250->fcr |= FCR_RX_LOW;
433 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
434 ns8250->fcr |= FCR_RX_MEDL;
435 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
436 ns8250->fcr |= FCR_RX_HIGH;
438 ns8250->fcr |= FCR_RX_MEDH;
440 ns8250->fcr |= FCR_RX_MEDH;
444 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
446 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
448 /* Get IER RX interrupt bits */
449 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
450 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
452 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
454 uart_setreg(bas, REG_FCR, ns8250->fcr);
456 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
458 if (ns8250->mcr & MCR_DTR)
459 sc->sc_hwsig |= SER_DTR;
460 if (ns8250->mcr & MCR_RTS)
461 sc->sc_hwsig |= SER_RTS;
462 ns8250_bus_getsig(sc);
465 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
466 ns8250->ier |= ns8250->ier_rxbits;
467 uart_setreg(bas, REG_IER, ns8250->ier);
471 * Timing of the H/W access was changed with r253161 of uart_core.c
472 * It has been observed that an ITE IT8513E would signal a break
473 * condition with pretty much every character it received, unless
474 * it had enough time to settle between ns8250_bus_attach() and
475 * ns8250_bus_ipend() -- which it accidentally had before r253161.
476 * It's not understood why the UART chip behaves this way and it
477 * could very well be that the DELAY make the H/W work in the same
478 * accidental manner as before. More analysis is warranted, but
479 * at least now we fixed a known regression.
486 ns8250_bus_detach(struct uart_softc *sc)
488 struct ns8250_softc *ns8250;
489 struct uart_bas *bas;
492 ns8250 = (struct ns8250_softc *)sc;
494 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
495 uart_setreg(bas, REG_IER, ier);
502 ns8250_bus_flush(struct uart_softc *sc, int what)
504 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
505 struct uart_bas *bas;
509 uart_lock(sc->sc_hwmtx);
510 if (sc->sc_rxfifosz > 1) {
511 ns8250_flush(bas, what);
512 uart_setreg(bas, REG_FCR, ns8250->fcr);
516 error = ns8250_drain(bas, what);
517 uart_unlock(sc->sc_hwmtx);
522 ns8250_bus_getsig(struct uart_softc *sc)
524 uint32_t new, old, sig;
530 uart_lock(sc->sc_hwmtx);
531 msr = uart_getreg(&sc->sc_bas, REG_MSR);
532 uart_unlock(sc->sc_hwmtx);
533 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
534 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
535 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
536 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
537 new = sig & ~SER_MASK_DELTA;
538 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
543 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
545 struct uart_bas *bas;
546 int baudrate, divisor, error;
551 uart_lock(sc->sc_hwmtx);
553 case UART_IOCTL_BREAK:
554 lcr = uart_getreg(bas, REG_LCR);
559 uart_setreg(bas, REG_LCR, lcr);
562 case UART_IOCTL_IFLOW:
563 lcr = uart_getreg(bas, REG_LCR);
565 uart_setreg(bas, REG_LCR, 0xbf);
567 efr = uart_getreg(bas, REG_EFR);
572 uart_setreg(bas, REG_EFR, efr);
574 uart_setreg(bas, REG_LCR, lcr);
577 case UART_IOCTL_OFLOW:
578 lcr = uart_getreg(bas, REG_LCR);
580 uart_setreg(bas, REG_LCR, 0xbf);
582 efr = uart_getreg(bas, REG_EFR);
587 uart_setreg(bas, REG_EFR, efr);
589 uart_setreg(bas, REG_LCR, lcr);
592 case UART_IOCTL_BAUD:
593 lcr = uart_getreg(bas, REG_LCR);
594 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
596 divisor = uart_getreg(bas, REG_DLL) |
597 (uart_getreg(bas, REG_DLH) << 8);
599 uart_setreg(bas, REG_LCR, lcr);
601 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
603 *(int*)data = baudrate;
611 uart_unlock(sc->sc_hwmtx);
616 ns8250_bus_ipend(struct uart_softc *sc)
618 struct uart_bas *bas;
619 struct ns8250_softc *ns8250;
623 ns8250 = (struct ns8250_softc *)sc;
625 uart_lock(sc->sc_hwmtx);
626 iir = uart_getreg(bas, REG_IIR);
628 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
629 (void)uart_getreg(bas, DW_REG_USR);
630 uart_unlock(sc->sc_hwmtx);
633 if (iir & IIR_NOPEND) {
634 uart_unlock(sc->sc_hwmtx);
638 if (iir & IIR_RXRDY) {
639 lsr = uart_getreg(bas, REG_LSR);
641 ipend |= SER_INT_OVERRUN;
643 ipend |= SER_INT_BREAK;
645 ipend |= SER_INT_RXREADY;
647 if (iir & IIR_TXRDY) {
648 ipend |= SER_INT_TXIDLE;
649 uart_setreg(bas, REG_IER, ns8250->ier);
651 ipend |= SER_INT_SIGCHG;
655 uart_unlock(sc->sc_hwmtx);
660 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
661 int stopbits, int parity)
663 struct ns8250_softc *ns8250;
664 struct uart_bas *bas;
667 ns8250 = (struct ns8250_softc*)sc;
669 uart_lock(sc->sc_hwmtx);
671 * When using DW UART with BUSY detection it is necessary to wait
672 * until all serial transfers are finished before manipulating the
673 * line control. LCR will not be affected when UART is busy.
675 if (ns8250->busy_detect != 0) {
677 * Pick an arbitrary high limit to avoid getting stuck in
678 * an infinite loop in case when the hardware is broken.
681 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
686 /* UART appears to be stuck */
687 uart_unlock(sc->sc_hwmtx);
692 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
693 uart_unlock(sc->sc_hwmtx);
698 ns8250_bus_probe(struct uart_softc *sc)
700 struct ns8250_softc *ns8250;
701 struct uart_bas *bas;
702 int count, delay, error, limit;
703 uint8_t lsr, mcr, ier;
705 ns8250 = (struct ns8250_softc *)sc;
708 error = ns8250_probe(bas);
713 if (sc->sc_sysdev == NULL) {
714 /* By using ns8250_init() we also set DTR and RTS. */
715 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
717 mcr |= MCR_DTR | MCR_RTS;
719 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
724 * Set loopback mode. This avoids having garbage on the wire and
725 * also allows us send and receive data. We set DTR and RTS to
726 * avoid the possibility that automatic flow-control prevents
727 * any data from being sent.
729 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
733 * Enable FIFOs. And check that the UART has them. If not, we're
734 * done. Since this is the first time we enable the FIFOs, we reset
737 uart_setreg(bas, REG_FCR, FCR_ENABLE);
739 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
741 * NS16450 or INS8250. We don't bother to differentiate
742 * between them. They're too old to be interesting.
744 uart_setreg(bas, REG_MCR, mcr);
746 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
747 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
751 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
755 delay = ns8250_delay(bas);
757 /* We have FIFOs. Drain the transmitter and receiver. */
758 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
760 uart_setreg(bas, REG_MCR, mcr);
761 uart_setreg(bas, REG_FCR, 0);
767 * We should have a sufficiently clean "pipe" to determine the
768 * size of the FIFOs. We send as much characters as is reasonable
769 * and wait for the overflow bit in the LSR register to be
770 * asserted, counting the characters as we send them. Based on
771 * that count we know the FIFO size.
774 uart_setreg(bas, REG_DATA, 0);
781 * LSR bits are cleared upon read, so we must accumulate
782 * them to be able to test LSR_OE below.
784 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
788 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
789 uart_setreg(bas, REG_IER, ier);
790 uart_setreg(bas, REG_MCR, mcr);
791 uart_setreg(bas, REG_FCR, 0);
796 } while ((lsr & LSR_OE) == 0 && count < 130);
799 uart_setreg(bas, REG_MCR, mcr);
802 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
805 if (count >= 14 && count <= 16) {
806 sc->sc_rxfifosz = 16;
807 device_set_desc(sc->sc_dev, "16550 or compatible");
808 } else if (count >= 28 && count <= 32) {
809 sc->sc_rxfifosz = 32;
810 device_set_desc(sc->sc_dev, "16650 or compatible");
811 } else if (count >= 56 && count <= 64) {
812 sc->sc_rxfifosz = 64;
813 device_set_desc(sc->sc_dev, "16750 or compatible");
814 } else if (count >= 112 && count <= 128) {
815 sc->sc_rxfifosz = 128;
816 device_set_desc(sc->sc_dev, "16950 or compatible");
818 sc->sc_rxfifosz = 16;
819 device_set_desc(sc->sc_dev,
820 "Non-standard ns8250 class UART with FIFOs");
824 * Force the Tx FIFO size to 16 bytes for now. We don't program the
825 * Tx trigger. Also, we assume that all data has been sent when the
828 sc->sc_txfifosz = 16;
832 * XXX there are some issues related to hardware flow control and
833 * it's likely that uart(4) is the cause. This basicly needs more
834 * investigation, but we avoid using for hardware flow control
837 /* 16650s or higher have automatic flow control. */
838 if (sc->sc_rxfifosz > 16) {
848 ns8250_bus_receive(struct uart_softc *sc)
850 struct uart_bas *bas;
855 uart_lock(sc->sc_hwmtx);
856 lsr = uart_getreg(bas, REG_LSR);
857 while (lsr & LSR_RXRDY) {
858 if (uart_rx_full(sc)) {
859 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
862 xc = uart_getreg(bas, REG_DATA);
864 xc |= UART_STAT_FRAMERR;
866 xc |= UART_STAT_PARERR;
868 lsr = uart_getreg(bas, REG_LSR);
870 /* Discard everything left in the Rx FIFO. */
871 while (lsr & LSR_RXRDY) {
872 (void)uart_getreg(bas, REG_DATA);
874 lsr = uart_getreg(bas, REG_LSR);
876 uart_unlock(sc->sc_hwmtx);
881 ns8250_bus_setsig(struct uart_softc *sc, int sig)
883 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
884 struct uart_bas *bas;
891 if (sig & SER_DDTR) {
892 SIGCHG(sig & SER_DTR, new, SER_DTR,
895 if (sig & SER_DRTS) {
896 SIGCHG(sig & SER_RTS, new, SER_RTS,
899 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
900 uart_lock(sc->sc_hwmtx);
901 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
903 ns8250->mcr |= MCR_DTR;
905 ns8250->mcr |= MCR_RTS;
906 uart_setreg(bas, REG_MCR, ns8250->mcr);
908 uart_unlock(sc->sc_hwmtx);
913 ns8250_bus_transmit(struct uart_softc *sc)
915 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
916 struct uart_bas *bas;
920 uart_lock(sc->sc_hwmtx);
921 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
923 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
925 for (i = 0; i < sc->sc_txdatasz; i++) {
926 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
930 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
933 uart_unlock(sc->sc_hwmtx);
935 uart_sched_softih(sc, SER_INT_TXIDLE);
940 ns8250_bus_grab(struct uart_softc *sc)
942 struct uart_bas *bas = &sc->sc_bas;
945 * turn off all interrupts to enter polling mode. Leave the
946 * saved mask alone. We'll restore whatever it was in ungrab.
947 * All pending interupt signals are reset when IER is set to 0.
949 uart_lock(sc->sc_hwmtx);
950 uart_setreg(bas, REG_IER, 0);
952 uart_unlock(sc->sc_hwmtx);
956 ns8250_bus_ungrab(struct uart_softc *sc)
958 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
959 struct uart_bas *bas = &sc->sc_bas;
962 * Restore previous interrupt mask
964 uart_lock(sc->sc_hwmtx);
965 uart_setreg(bas, REG_IER, ns8250->ier);
967 uart_unlock(sc->sc_hwmtx);