sys/dev/usb/controller/at91dci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * This file contains the driver for the AT91 series USB Device
  29  * Controller
  30  */
  31
  32 /*
  33  * Thanks to "David Brownell" for helping out regarding the hardware
  34  * endpoint profiles.
  35  */
  36
  37 /*
  38  * NOTE: The "fifo_bank" is not reset in hardware when the endpoint is
  39  * reset.
  40  *
  41  * NOTE: When the chip detects BUS-reset it will also reset the
  42  * endpoints, Function-address and more.
  43  */
  44
  45 #ifdef USB_GLOBAL_INCLUDE_FILE
  46 #include USB_GLOBAL_INCLUDE_FILE
  47 #else
  48 #include <sys/stdint.h>
  49 #include <sys/stddef.h>
  50 #include <sys/param.h>
  51 #include <sys/queue.h>
  52 #include <sys/types.h>
  53 #include <sys/systm.h>
  54 #include <sys/kernel.h>
  55 #include <sys/bus.h>
  56 #include <sys/module.h>
  57 #include <sys/lock.h>
  58 #include <sys/mutex.h>
  59 #include <sys/condvar.h>
  60 #include <sys/sysctl.h>
  61 #include <sys/sx.h>
  62 #include <sys/unistd.h>
  63 #include <sys/callout.h>
  64 #include <sys/malloc.h>
  65 #include <sys/priv.h>
  66
  67 #include <dev/usb/usb.h>
  68 #include <dev/usb/usbdi.h>
  69
  70 #define USB_DEBUG_VAR at91dcidebug
  71
  72 #include <dev/usb/usb_core.h>
  73 #include <dev/usb/usb_debug.h>
  74 #include <dev/usb/usb_busdma.h>
  75 #include <dev/usb/usb_process.h>
  76 #include <dev/usb/usb_transfer.h>
  77 #include <dev/usb/usb_device.h>
  78 #include <dev/usb/usb_hub.h>
  79 #include <dev/usb/usb_util.h>
  80
  81 #include <dev/usb/usb_controller.h>
  82 #include <dev/usb/usb_bus.h>
  83 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  84
  85 #include <dev/usb/controller/at91dci.h>
  86
  87 #define AT9100_DCI_BUS2SC(bus) \
  88    ((struct at91dci_softc *)(((uint8_t *)(bus)) - \
  89     ((uint8_t *)&(((struct at91dci_softc *)0)->sc_bus))))
  90
  91 #define AT9100_DCI_PC2SC(pc) \
  92    AT9100_DCI_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus)
  93
  94 #define AT9100_DCI_THREAD_IRQ \
  95   (AT91_UDP_INT_BUS | AT91_UDP_INT_END_BR | AT91_UDP_INT_RXRSM | AT91_UDP_INT_RXSUSP)
  96
  97 #ifdef USB_DEBUG
  98 static int at91dcidebug = 0;
  99
 100 static SYSCTL_NODE(_hw_usb, OID_AUTO, at91dci, CTLFLAG_RW, 0, "USB at91dci");
 101 SYSCTL_INT(_hw_usb_at91dci, OID_AUTO, debug, CTLFLAG_RW,
 102     &at91dcidebug, 0, "at91dci debug level");
 103 #endif
 104
 105 #define AT9100_DCI_INTR_ENDPT 1
 106
 107 /* prototypes */
 108
 109 struct usb_bus_methods at91dci_bus_methods;
 110 struct usb_pipe_methods at91dci_device_bulk_methods;
 111 struct usb_pipe_methods at91dci_device_ctrl_methods;
 112 struct usb_pipe_methods at91dci_device_intr_methods;
 113 struct usb_pipe_methods at91dci_device_isoc_fs_methods;
 114
 115 static at91dci_cmd_t at91dci_setup_rx;
 116 static at91dci_cmd_t at91dci_data_rx;
 117 static at91dci_cmd_t at91dci_data_tx;
 118 static at91dci_cmd_t at91dci_data_tx_sync;
 119 static void     at91dci_device_done(struct usb_xfer *, usb_error_t);
 120 static void     at91dci_do_poll(struct usb_bus *);
 121 static void     at91dci_standard_done(struct usb_xfer *);
 122 static void     at91dci_root_intr(struct at91dci_softc *sc);
 123
 124 /*
 125  * NOTE: Some of the bits in the CSR register have inverse meaning so
 126  * we need a helper macro when acknowledging events:
 127  */
 128 #define AT91_CSR_ACK(csr, what) do {            \
 129   (csr) &= ~((AT91_UDP_CSR_FORCESTALL|          \
 130               AT91_UDP_CSR_TXPKTRDY|            \
 131               AT91_UDP_CSR_RXBYTECNT) ^ (what));\
 132   (csr) |= ((AT91_UDP_CSR_RX_DATA_BK0|          \
 133              AT91_UDP_CSR_RX_DATA_BK1|          \
 134              AT91_UDP_CSR_TXCOMP|               \
 135              AT91_UDP_CSR_RXSETUP|              \
 136              AT91_UDP_CSR_STALLSENT) ^ (what)); \
 137 } while (0)
 138
 139 /*
 140  * Here is a list of what the chip supports.
 141  * Probably it supports more than listed here!
 142  */
 143 static const struct usb_hw_ep_profile
 144         at91dci_ep_profile[AT91_UDP_EP_MAX] = {
 145
 146         [0] = {
 147                 .max_in_frame_size = 8,
 148                 .max_out_frame_size = 8,
 149                 .is_simplex = 1,
 150                 .support_control = 1,
 151         },
 152         [1] = {
 153                 .max_in_frame_size = 64,
 154                 .max_out_frame_size = 64,
 155                 .is_simplex = 1,
 156                 .support_multi_buffer = 1,
 157                 .support_bulk = 1,
 158                 .support_interrupt = 1,
 159                 .support_isochronous = 1,
 160                 .support_in = 1,
 161                 .support_out = 1,
 162         },
 163         [2] = {
 164                 .max_in_frame_size = 64,
 165                 .max_out_frame_size = 64,
 166                 .is_simplex = 1,
 167                 .support_multi_buffer = 1,
 168                 .support_bulk = 1,
 169                 .support_interrupt = 1,
 170                 .support_isochronous = 1,
 171                 .support_in = 1,
 172                 .support_out = 1,
 173         },
 174         [3] = {
 175                 /* can also do BULK */
 176                 .max_in_frame_size = 8,
 177                 .max_out_frame_size = 8,
 178                 .is_simplex = 1,
 179                 .support_interrupt = 1,
 180                 .support_in = 1,
 181                 .support_out = 1,
 182         },
 183         [4] = {
 184                 .max_in_frame_size = 256,
 185                 .max_out_frame_size = 256,
 186                 .is_simplex = 1,
 187                 .support_multi_buffer = 1,
 188                 .support_bulk = 1,
 189                 .support_interrupt = 1,
 190                 .support_isochronous = 1,
 191                 .support_in = 1,
 192                 .support_out = 1,
 193         },
 194         [5] = {
 195                 .max_in_frame_size = 256,
 196                 .max_out_frame_size = 256,
 197                 .is_simplex = 1,
 198                 .support_multi_buffer = 1,
 199                 .support_bulk = 1,
 200                 .support_interrupt = 1,
 201                 .support_isochronous = 1,
 202                 .support_in = 1,
 203                 .support_out = 1,
 204         },
 205 };
 206
 207 static void
 208 at91dci_get_hw_ep_profile(struct usb_device *udev,
 209     const struct usb_hw_ep_profile **ppf, uint8_t ep_addr)
 210 {
 211         if (ep_addr < AT91_UDP_EP_MAX) {
 212                 *ppf = (at91dci_ep_profile + ep_addr);
 213         } else {
 214                 *ppf = NULL;
 215         }
 216 }
 217
 218 static void
 219 at91dci_clocks_on(struct at91dci_softc *sc)
 220 {
 221         if (sc->sc_flags.clocks_off &&
 222             sc->sc_flags.port_powered) {
 223
 224                 DPRINTFN(5, "\n");
 225
 226                 if (sc->sc_clocks_on) {
 227                         (sc->sc_clocks_on) (sc->sc_clocks_arg);
 228                 }
 229                 sc->sc_flags.clocks_off = 0;
 230
 231                 /* enable Transceiver */
 232                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, 0);
 233         }
 234 }
 235
 236 static void
 237 at91dci_clocks_off(struct at91dci_softc *sc)
 238 {
 239         if (!sc->sc_flags.clocks_off) {
 240
 241                 DPRINTFN(5, "\n");
 242
 243                 /* disable Transceiver */
 244                 AT91_UDP_WRITE_4(sc, AT91_UDP_TXVC, AT91_UDP_TXVC_DIS);
 245
 246                 if (sc->sc_clocks_off) {
 247                         (sc->sc_clocks_off) (sc->sc_clocks_arg);
 248                 }
 249                 sc->sc_flags.clocks_off = 1;
 250         }
 251 }
 252
 253 static void
 254 at91dci_pull_up(struct at91dci_softc *sc)
 255 {
 256         /* pullup D+, if possible */
 257
 258         if (!sc->sc_flags.d_pulled_up &&
 259             sc->sc_flags.port_powered) {
 260                 sc->sc_flags.d_pulled_up = 1;
 261                 (sc->sc_pull_up) (sc->sc_pull_arg);
 262         }
 263 }
 264
 265 static void
 266 at91dci_pull_down(struct at91dci_softc *sc)
 267 {
 268         /* pulldown D+, if possible */
 269
 270         if (sc->sc_flags.d_pulled_up) {
 271                 sc->sc_flags.d_pulled_up = 0;
 272                 (sc->sc_pull_down) (sc->sc_pull_arg);
 273         }
 274 }
 275
 276 static void
 277 at91dci_wakeup_peer(struct at91dci_softc *sc)
 278 {
 279         if (!(sc->sc_flags.status_suspend)) {
 280                 return;
 281         }
 282
 283         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, AT91_UDP_GSTATE_ESR);
 284
 285         /* wait 8 milliseconds */
 286         /* Wait for reset to complete. */
 287         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125);
 288
 289         AT91_UDP_WRITE_4(sc, AT91_UDP_GSTATE, 0);
 290 }
 291
 292 static void
 293 at91dci_set_address(struct at91dci_softc *sc, uint8_t addr)
 294 {
 295         DPRINTFN(5, "addr=%d\n", addr);
 296
 297         AT91_UDP_WRITE_4(sc, AT91_UDP_FADDR, addr |
 298             AT91_UDP_FADDR_EN);
 299 }
 300
 301 static uint8_t
 302 at91dci_setup_rx(struct at91dci_softc *sc, struct at91dci_td *td)
 303 {
 304         struct usb_device_request req;
 305         uint32_t csr;
 306         uint32_t temp;
 307         uint16_t count;
 308
 309         /* read out FIFO status */
 310         csr = AT91_UDP_READ_4(sc, td->status_reg);
 311
 312         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 313
 314         temp = csr;
 315         temp &= (AT91_UDP_CSR_RX_DATA_BK0 |
 316             AT91_UDP_CSR_RX_DATA_BK1 |
 317             AT91_UDP_CSR_STALLSENT |
 318             AT91_UDP_CSR_RXSETUP |
 319             AT91_UDP_CSR_TXCOMP);
 320
 321         if (!(csr & AT91_UDP_CSR_RXSETUP)) {
 322                 goto not_complete;
 323         }
 324         /* clear did stall */
 325         td->did_stall = 0;
 326
 327         /* get the packet byte count */
 328         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 329
 330         /* verify data length */
 331         if (count != td->remainder) {
 332                 DPRINTFN(0, "Invalid SETUP packet "
 333                     "length, %d bytes\n", count);
 334                 goto not_complete;
 335         }
 336         if (count != sizeof(req)) {
 337                 DPRINTFN(0, "Unsupported SETUP packet "
 338                     "length, %d bytes\n", count);
 339                 goto not_complete;
 340         }
 341         /* receive data */
 342         bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 343             td->fifo_reg, (void *)&req, sizeof(req));
 344
 345         /* copy data into real buffer */
 346         usbd_copy_in(td->pc, 0, &req, sizeof(req));
 347
 348         td->offset = sizeof(req);
 349         td->remainder = 0;
 350
 351         /* sneak peek the set address */
 352         if ((req.bmRequestType == UT_WRITE_DEVICE) &&
 353             (req.bRequest == UR_SET_ADDRESS)) {
 354                 sc->sc_dv_addr = req.wValue[0] & 0x7F;
 355         } else {
 356                 sc->sc_dv_addr = 0xFF;
 357         }
 358
 359         /* sneak peek the endpoint direction */
 360         if (req.bmRequestType & UE_DIR_IN) {
 361                 csr |= AT91_UDP_CSR_DIR;
 362         } else {
 363                 csr &= ~AT91_UDP_CSR_DIR;
 364         }
 365
 366         /* write the direction of the control transfer */
 367         AT91_CSR_ACK(csr, temp);
 368         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 369         return (0);                     /* complete */
 370
 371 not_complete:
 372         /* abort any ongoing transfer */
 373         if (!td->did_stall) {
 374                 DPRINTFN(5, "stalling\n");
 375                 temp |= AT91_UDP_CSR_FORCESTALL;
 376                 td->did_stall = 1;
 377         }
 378
 379         /* clear interrupts, if any */
 380         if (temp) {
 381                 DPRINTFN(5, "clearing 0x%08x\n", temp);
 382                 AT91_CSR_ACK(csr, temp);
 383                 AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 384         }
 385         return (1);                     /* not complete */
 386 }
 387
 388 static uint8_t
 389 at91dci_data_rx(struct at91dci_softc *sc, struct at91dci_td *td)
 390 {
 391         struct usb_page_search buf_res;
 392         uint32_t csr;
 393         uint32_t temp;
 394         uint16_t count;
 395         uint8_t to;
 396         uint8_t got_short;
 397
 398         to = 2;                         /* don't loop forever! */
 399         got_short = 0;
 400
 401         /* check if any of the FIFO banks have data */
 402 repeat:
 403         /* read out FIFO status */
 404         csr = AT91_UDP_READ_4(sc, td->status_reg);
 405
 406         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 407
 408         if (csr & AT91_UDP_CSR_RXSETUP) {
 409                 if (td->remainder == 0) {
 410                         /*
 411                          * We are actually complete and have
 412                          * received the next SETUP
 413                          */
 414                         DPRINTFN(5, "faking complete\n");
 415                         return (0);     /* complete */
 416                 }
 417                 /*
 418                  * USB Host Aborted the transfer.
 419                  */
 420                 td->error = 1;
 421                 return (0);             /* complete */
 422         }
 423         /* Make sure that "STALLSENT" gets cleared */
 424         temp = csr;
 425         temp &= AT91_UDP_CSR_STALLSENT;
 426
 427         /* check status */
 428         if (!(csr & (AT91_UDP_CSR_RX_DATA_BK0 |
 429             AT91_UDP_CSR_RX_DATA_BK1))) {
 430                 if (temp) {
 431                         /* write command */
 432                         AT91_CSR_ACK(csr, temp);
 433                         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 434                 }
 435                 return (1);             /* not complete */
 436         }
 437         /* get the packet byte count */
 438         count = (csr & AT91_UDP_CSR_RXBYTECNT) >> 16;
 439
 440         /* verify the packet byte count */
 441         if (count != td->max_packet_size) {
 442                 if (count < td->max_packet_size) {
 443                         /* we have a short packet */
 444                         td->short_pkt = 1;
 445                         got_short = 1;
 446                 } else {
 447                         /* invalid USB packet */
 448                         td->error = 1;
 449                         return (0);     /* we are complete */
 450                 }
 451         }
 452         /* verify the packet byte count */
 453         if (count > td->remainder) {
 454                 /* invalid USB packet */
 455                 td->error = 1;
 456                 return (0);             /* we are complete */
 457         }
 458         while (count > 0) {
 459                 usbd_get_page(td->pc, td->offset, &buf_res);
 460
 461                 /* get correct length */
 462                 if (buf_res.length > count) {
 463                         buf_res.length = count;
 464                 }
 465                 /* receive data */
 466                 bus_space_read_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 467                     td->fifo_reg, buf_res.buffer, buf_res.length);
 468
 469                 /* update counters */
 470                 count -= buf_res.length;
 471                 td->offset += buf_res.length;
 472                 td->remainder -= buf_res.length;
 473         }
 474
 475         /* clear status bits */
 476         if (td->support_multi_buffer) {
 477                 if (td->fifo_bank) {
 478                         td->fifo_bank = 0;
 479                         temp |= AT91_UDP_CSR_RX_DATA_BK1;
 480                 } else {
 481                         td->fifo_bank = 1;
 482                         temp |= AT91_UDP_CSR_RX_DATA_BK0;
 483                 }
 484         } else {
 485                 temp |= (AT91_UDP_CSR_RX_DATA_BK0 |
 486                     AT91_UDP_CSR_RX_DATA_BK1);
 487         }
 488
 489         /* write command */
 490         AT91_CSR_ACK(csr, temp);
 491         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 492
 493         /*
 494          * NOTE: We may have to delay a little bit before
 495          * proceeding after clearing the DATA_BK bits.
 496          */
 497
 498         /* check if we are complete */
 499         if ((td->remainder == 0) || got_short) {
 500                 if (td->short_pkt) {
 501                         /* we are complete */
 502                         return (0);
 503                 }
 504                 /* else need to receive a zero length packet */
 505         }
 506         if (--to) {
 507                 goto repeat;
 508         }
 509         return (1);                     /* not complete */
 510 }
 511
 512 static uint8_t
 513 at91dci_data_tx(struct at91dci_softc *sc, struct at91dci_td *td)
 514 {
 515         struct usb_page_search buf_res;
 516         uint32_t csr;
 517         uint32_t temp;
 518         uint16_t count;
 519         uint8_t to;
 520
 521         to = 2;                         /* don't loop forever! */
 522
 523 repeat:
 524
 525         /* read out FIFO status */
 526         csr = AT91_UDP_READ_4(sc, td->status_reg);
 527
 528         DPRINTFN(5, "csr=0x%08x rem=%u\n", csr, td->remainder);
 529
 530         if (csr & AT91_UDP_CSR_RXSETUP) {
 531                 /*
 532                  * The current transfer was aborted
 533                  * by the USB Host
 534                  */
 535                 td->error = 1;
 536                 return (0);             /* complete */
 537         }
 538         /* Make sure that "STALLSENT" gets cleared */
 539         temp = csr;
 540         temp &= AT91_UDP_CSR_STALLSENT;
 541
 542         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 543                 if (temp) {
 544                         /* write command */
 545                         AT91_CSR_ACK(csr, temp);
 546                         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 547                 }
 548                 return (1);             /* not complete */
 549         } else {
 550                 /* clear TXCOMP and set TXPKTRDY */
 551                 temp |= (AT91_UDP_CSR_TXCOMP |
 552                     AT91_UDP_CSR_TXPKTRDY);
 553         }
 554
 555         count = td->max_packet_size;
 556         if (td->remainder < count) {
 557                 /* we have a short packet */
 558                 td->short_pkt = 1;
 559                 count = td->remainder;
 560         }
 561         while (count > 0) {
 562                 usbd_get_page(td->pc, td->offset, &buf_res);
 563
 564                 /* get correct length */
 565                 if (buf_res.length > count) {
 566                         buf_res.length = count;
 567                 }
 568                 /* transmit data */
 569                 bus_space_write_multi_1(sc->sc_io_tag, sc->sc_io_hdl,
 570                     td->fifo_reg, buf_res.buffer, buf_res.length);
 571
 572                 /* update counters */
 573                 count -= buf_res.length;
 574                 td->offset += buf_res.length;
 575                 td->remainder -= buf_res.length;
 576         }
 577
 578         /* write command */
 579         AT91_CSR_ACK(csr, temp);
 580         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 581
 582         /* check remainder */
 583         if (td->remainder == 0) {
 584                 if (td->short_pkt) {
 585                         return (0);     /* complete */
 586                 }
 587                 /* else we need to transmit a short packet */
 588         }
 589         if (--to) {
 590                 goto repeat;
 591         }
 592         return (1);                     /* not complete */
 593 }
 594
 595 static uint8_t
 596 at91dci_data_tx_sync(struct at91dci_softc *sc, struct at91dci_td *td)
 597 {
 598         uint32_t csr;
 599         uint32_t temp;
 600
 601         /* read out FIFO status */
 602         csr = AT91_UDP_READ_4(sc, td->status_reg);
 603
 604         DPRINTFN(5, "csr=0x%08x\n", csr);
 605
 606         if (csr & AT91_UDP_CSR_RXSETUP) {
 607                 DPRINTFN(5, "faking complete\n");
 608                 /* Race condition */
 609                 return (0);             /* complete */
 610         }
 611         temp = csr;
 612         temp &= (AT91_UDP_CSR_STALLSENT |
 613             AT91_UDP_CSR_TXCOMP);
 614
 615         /* check status */
 616         if (csr & AT91_UDP_CSR_TXPKTRDY) {
 617                 goto not_complete;
 618         }
 619         if (!(csr & AT91_UDP_CSR_TXCOMP)) {
 620                 goto not_complete;
 621         }
 622         if (td->status_reg == AT91_UDP_CSR(0) && sc->sc_dv_addr != 0xFF) {
 623                 /*
 624                  * The AT91 has a special requirement with regard to
 625                  * setting the address and that is to write the new
 626                  * address before clearing TXCOMP:
 627                  */
 628                 at91dci_set_address(sc, sc->sc_dv_addr);
 629         }
 630         /* write command */
 631         AT91_CSR_ACK(csr, temp);
 632         AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 633
 634         return (0);                     /* complete */
 635
 636 not_complete:
 637         if (temp) {
 638                 /* write command */
 639                 AT91_CSR_ACK(csr, temp);
 640                 AT91_UDP_WRITE_4(sc, td->status_reg, csr);
 641         }
 642         return (1);                     /* not complete */
 643 }
 644
 645 static void
 646 at91dci_xfer_do_fifo(struct usb_xfer *xfer)
 647 {
 648         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 649         struct at91dci_td *td;
 650         uint8_t temp;
 651
 652         DPRINTFN(9, "\n");
 653
 654         td = xfer->td_transfer_cache;
 655         if (td == NULL)
 656                 return;
 657
 658         while (1) {
 659                 if ((td->func) (sc, td)) {
 660                         /* operation in progress */
 661                         break;
 662                 }
 663                 if (((void *)td) == xfer->td_transfer_last) {
 664                         goto done;
 665                 }
 666                 if (td->error) {
 667                         goto done;
 668                 } else if (td->remainder > 0) {
 669                         /*
 670                          * We had a short transfer. If there is no alternate
 671                          * next, stop processing !
 672                          */
 673                         if (!td->alt_next) {
 674                                 goto done;
 675                         }
 676                 }
 677                 /*
 678                  * Fetch the next transfer descriptor and transfer
 679                  * some flags to the next transfer descriptor
 680                  */
 681                 temp = 0;
 682                 if (td->fifo_bank)
 683                         temp |= 1;
 684                 td = td->obj_next;
 685                 xfer->td_transfer_cache = td;
 686                 if (temp & 1)
 687                         td->fifo_bank = 1;
 688         }
 689         return;
 690
 691 done:
 692         temp = (xfer->endpointno & UE_ADDR);
 693
 694         /* update FIFO bank flag and multi buffer */
 695         if (td->fifo_bank) {
 696                 sc->sc_ep_flags[temp].fifo_bank = 1;
 697         } else {
 698                 sc->sc_ep_flags[temp].fifo_bank = 0;
 699         }
 700
 701         /* compute all actual lengths */
 702         xfer->td_transfer_cache = NULL;
 703         sc->sc_xfer_complete = 1;
 704 }
 705
 706 static uint8_t
 707 at91dci_xfer_do_complete(struct usb_xfer *xfer)
 708 {
 709         struct at91dci_td *td;
 710
 711         DPRINTFN(9, "\n");
 712         td = xfer->td_transfer_cache;
 713         if (td == NULL) {
 714                 /* compute all actual lengths */
 715                 at91dci_standard_done(xfer);
 716                 return(1);
 717         }
 718         return (0);
 719 }
 720
 721 static void
 722 at91dci_interrupt_poll_locked(struct at91dci_softc *sc)
 723 {
 724         struct usb_xfer *xfer;
 725
 726         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry)
 727                 at91dci_xfer_do_fifo(xfer);
 728 }
 729
 730 static void
 731 at91dci_interrupt_complete_locked(struct at91dci_softc *sc)
 732 {
 733         struct usb_xfer *xfer;
 734 repeat:
 735         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
 736                 if (at91dci_xfer_do_complete(xfer))
 737                         goto repeat;
 738         }
 739 }
 740
 741 void
 742 at91dci_vbus_interrupt(struct at91dci_softc *sc, uint8_t is_on)
 743 {
 744         DPRINTFN(5, "vbus = %u\n", is_on);
 745
 746         if (is_on) {
 747                 if (!sc->sc_flags.status_vbus) {
 748                         sc->sc_flags.status_vbus = 1;
 749
 750                         /* complete root HUB interrupt endpoint */
 751                         at91dci_root_intr(sc);
 752                 }
 753         } else {
 754                 if (sc->sc_flags.status_vbus) {
 755                         sc->sc_flags.status_vbus = 0;
 756                         sc->sc_flags.status_bus_reset = 0;
 757                         sc->sc_flags.status_suspend = 0;
 758                         sc->sc_flags.change_suspend = 0;
 759                         sc->sc_flags.change_connect = 1;
 760
 761                         /* complete root HUB interrupt endpoint */
 762                         at91dci_root_intr(sc);
 763                 }
 764         }
 765 }
 766
 767 int
 768 at91dci_filter_interrupt(void *arg)
 769 {
 770         struct at91dci_softc *sc = arg;
 771         int retval = FILTER_HANDLED;
 772         uint32_t status;
 773
 774         USB_BUS_SPIN_LOCK(&sc->sc_bus);
 775
 776         status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
 777         status &= AT91_UDP_INT_DEFAULT;
 778
 779         if (status & AT9100_DCI_THREAD_IRQ)
 780                 retval = FILTER_SCHEDULE_THREAD;
 781
 782         /* acknowledge interrupts */
 783         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status & ~AT9100_DCI_THREAD_IRQ);
 784
 785         /* poll FIFOs, if any */
 786         at91dci_interrupt_poll_locked(sc);
 787
 788         if (sc->sc_xfer_complete != 0)
 789                 retval = FILTER_SCHEDULE_THREAD;
 790
 791         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
 792
 793         return (retval);
 794 }
 795
 796 void
 797 at91dci_interrupt(void *arg)
 798 {
 799         struct at91dci_softc *sc = arg;
 800         uint32_t status;
 801
 802         USB_BUS_LOCK(&sc->sc_bus);
 803         USB_BUS_SPIN_LOCK(&sc->sc_bus);
 804
 805         status = AT91_UDP_READ_4(sc, AT91_UDP_ISR);
 806         status &= AT9100_DCI_THREAD_IRQ;
 807
 808         /* acknowledge interrupts */
 809
 810         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, status);
 811
 812         /* check for any bus state change interrupts */
 813
 814         if (status & AT91_UDP_INT_BUS) {
 815
 816                 DPRINTFN(5, "real bus interrupt 0x%08x\n", status);
 817
 818                 if (status & AT91_UDP_INT_END_BR) {
 819
 820                         /* set correct state */
 821                         sc->sc_flags.status_bus_reset = 1;
 822                         sc->sc_flags.status_suspend = 0;
 823                         sc->sc_flags.change_suspend = 0;
 824                         sc->sc_flags.change_connect = 1;
 825
 826                         /* disable resume interrupt */
 827                         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 828                             AT91_UDP_INT_RXRSM);
 829                         /* enable suspend interrupt */
 830                         AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 831                             AT91_UDP_INT_RXSUSP);
 832                 }
 833                 /*
 834                  * If RXRSM and RXSUSP is set at the same time we interpret
 835                  * that like RESUME. Resume is set when there is at least 3
 836                  * milliseconds of inactivity on the USB BUS.
 837                  */
 838                 if (status & AT91_UDP_INT_RXRSM) {
 839                         if (sc->sc_flags.status_suspend) {
 840                                 sc->sc_flags.status_suspend = 0;
 841                                 sc->sc_flags.change_suspend = 1;
 842
 843                                 /* disable resume interrupt */
 844                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 845                                     AT91_UDP_INT_RXRSM);
 846                                 /* enable suspend interrupt */
 847                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 848                                     AT91_UDP_INT_RXSUSP);
 849                         }
 850                 } else if (status & AT91_UDP_INT_RXSUSP) {
 851                         if (!sc->sc_flags.status_suspend) {
 852                                 sc->sc_flags.status_suspend = 1;
 853                                 sc->sc_flags.change_suspend = 1;
 854
 855                                 /* disable suspend interrupt */
 856                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR,
 857                                     AT91_UDP_INT_RXSUSP);
 858
 859                                 /* enable resume interrupt */
 860                                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER,
 861                                     AT91_UDP_INT_RXRSM);
 862                         }
 863                 }
 864                 /* complete root HUB interrupt endpoint */
 865                 at91dci_root_intr(sc);
 866         }
 867
 868         if (sc->sc_xfer_complete != 0) {
 869                 sc->sc_xfer_complete = 0;
 870                 at91dci_interrupt_complete_locked(sc);
 871         }
 872         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
 873         USB_BUS_UNLOCK(&sc->sc_bus);
 874 }
 875
 876 static void
 877 at91dci_setup_standard_chain_sub(struct at91dci_std_temp *temp)
 878 {
 879         struct at91dci_td *td;
 880
 881         /* get current Transfer Descriptor */
 882         td = temp->td_next;
 883         temp->td = td;
 884
 885         /* prepare for next TD */
 886         temp->td_next = td->obj_next;
 887
 888         /* fill out the Transfer Descriptor */
 889         td->func = temp->func;
 890         td->pc = temp->pc;
 891         td->offset = temp->offset;
 892         td->remainder = temp->len;
 893         td->fifo_bank = 0;
 894         td->error = 0;
 895         td->did_stall = temp->did_stall;
 896         td->short_pkt = temp->short_pkt;
 897         td->alt_next = temp->setup_alt_next;
 898 }
 899
 900 static void
 901 at91dci_setup_standard_chain(struct usb_xfer *xfer)
 902 {
 903         struct at91dci_std_temp temp;
 904         struct at91dci_softc *sc;
 905         struct at91dci_td *td;
 906         uint32_t x;
 907         uint8_t ep_no;
 908         uint8_t need_sync;
 909
 910         DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
 911             xfer->address, UE_GET_ADDR(xfer->endpointno),
 912             xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
 913
 914         temp.max_frame_size = xfer->max_frame_size;
 915
 916         td = xfer->td_start[0];
 917         xfer->td_transfer_first = td;
 918         xfer->td_transfer_cache = td;
 919
 920         /* setup temp */
 921
 922         temp.pc = NULL;
 923         temp.td = NULL;
 924         temp.td_next = xfer->td_start[0];
 925         temp.offset = 0;
 926         temp.setup_alt_next = xfer->flags_int.short_frames_ok;
 927         temp.did_stall = !xfer->flags_int.control_stall;
 928
 929         sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
 930         ep_no = (xfer->endpointno & UE_ADDR);
 931
 932         /* check if we should prepend a setup message */
 933
 934         if (xfer->flags_int.control_xfr) {
 935                 if (xfer->flags_int.control_hdr) {
 936
 937                         temp.func = &at91dci_setup_rx;
 938                         temp.len = xfer->frlengths[0];
 939                         temp.pc = xfer->frbuffers + 0;
 940                         temp.short_pkt = temp.len ? 1 : 0;
 941                         /* check for last frame */
 942                         if (xfer->nframes == 1) {
 943                                 /* no STATUS stage yet, SETUP is last */
 944                                 if (xfer->flags_int.control_act)
 945                                         temp.setup_alt_next = 0;
 946                         }
 947
 948                         at91dci_setup_standard_chain_sub(&temp);
 949                 }
 950                 x = 1;
 951         } else {
 952                 x = 0;
 953         }
 954
 955         if (x != xfer->nframes) {
 956                 if (xfer->endpointno & UE_DIR_IN) {
 957                         temp.func = &at91dci_data_tx;
 958                         need_sync = 1;
 959                 } else {
 960                         temp.func = &at91dci_data_rx;
 961                         need_sync = 0;
 962                 }
 963
 964                 /* setup "pc" pointer */
 965                 temp.pc = xfer->frbuffers + x;
 966         } else {
 967                 need_sync = 0;
 968         }
 969         while (x != xfer->nframes) {
 970
 971                 /* DATA0 / DATA1 message */
 972
 973                 temp.len = xfer->frlengths[x];
 974
 975                 x++;
 976
 977                 if (x == xfer->nframes) {
 978                         if (xfer->flags_int.control_xfr) {
 979                                 if (xfer->flags_int.control_act) {
 980                                         temp.setup_alt_next = 0;
 981                                 }
 982                         } else {
 983                                 temp.setup_alt_next = 0;
 984                         }
 985                 }
 986                 if (temp.len == 0) {
 987
 988                         /* make sure that we send an USB packet */
 989
 990                         temp.short_pkt = 0;
 991
 992                 } else {
 993
 994                         /* regular data transfer */
 995
 996                         temp.short_pkt = (xfer->flags.force_short_xfer) ? 0 : 1;
 997                 }
 998
 999                 at91dci_setup_standard_chain_sub(&temp);
1000
1001                 if (xfer->flags_int.isochronous_xfr) {
1002                         temp.offset += temp.len;
1003                 } else {
1004                         /* get next Page Cache pointer */
1005                         temp.pc = xfer->frbuffers + x;
1006                 }
1007         }
1008
1009         /* check for control transfer */
1010         if (xfer->flags_int.control_xfr) {
1011
1012                 /* always setup a valid "pc" pointer for status and sync */
1013                 temp.pc = xfer->frbuffers + 0;
1014                 temp.len = 0;
1015                 temp.short_pkt = 0;
1016                 temp.setup_alt_next = 0;
1017
1018                 /* check if we need to sync */
1019                 if (need_sync) {
1020                         /* we need a SYNC point after TX */
1021                         temp.func = &at91dci_data_tx_sync;
1022                         at91dci_setup_standard_chain_sub(&temp);
1023                 }
1024
1025                 /* check if we should append a status stage */
1026                 if (!xfer->flags_int.control_act) {
1027
1028                         /*
1029                          * Send a DATA1 message and invert the current
1030                          * endpoint direction.
1031                          */
1032                         if (xfer->endpointno & UE_DIR_IN) {
1033                                 temp.func = &at91dci_data_rx;
1034                                 need_sync = 0;
1035                         } else {
1036                                 temp.func = &at91dci_data_tx;
1037                                 need_sync = 1;
1038                         }
1039
1040                         at91dci_setup_standard_chain_sub(&temp);
1041                         if (need_sync) {
1042                                 /* we need a SYNC point after TX */
1043                                 temp.func = &at91dci_data_tx_sync;
1044                                 at91dci_setup_standard_chain_sub(&temp);
1045                         }
1046                 }
1047         }
1048
1049         /* must have at least one frame! */
1050         td = temp.td;
1051         xfer->td_transfer_last = td;
1052
1053         /* setup the correct fifo bank */
1054         if (sc->sc_ep_flags[ep_no].fifo_bank) {
1055                 td = xfer->td_transfer_first;
1056                 td->fifo_bank = 1;
1057         }
1058 }
1059
1060 static void
1061 at91dci_timeout(void *arg)
1062 {
1063         struct usb_xfer *xfer = arg;
1064
1065         DPRINTF("xfer=%p\n", xfer);
1066
1067         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1068
1069         /* transfer is transferred */
1070         at91dci_device_done(xfer, USB_ERR_TIMEOUT);
1071 }
1072
1073 static void
1074 at91dci_start_standard_chain(struct usb_xfer *xfer)
1075 {
1076         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1077
1078         DPRINTFN(9, "\n");
1079
1080         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1081
1082         /* poll one time */
1083         at91dci_xfer_do_fifo(xfer);
1084
1085         if (at91dci_xfer_do_complete(xfer) == 0) {
1086
1087                 uint8_t ep_no = xfer->endpointno & UE_ADDR;
1088
1089                 /*
1090                  * Only enable the endpoint interrupt when we are actually
1091                  * waiting for data, hence we are dealing with level
1092                  * triggered interrupts !
1093                  */
1094                 AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_EP(ep_no));
1095
1096                 DPRINTFN(15, "enable interrupts on endpoint %d\n", ep_no);
1097
1098                 /* put transfer on interrupt queue */
1099                 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
1100
1101                 /* start timeout, if any */
1102                 if (xfer->timeout != 0) {
1103                         usbd_transfer_timeout_ms(xfer,
1104                             &at91dci_timeout, xfer->timeout);
1105                 }
1106         }
1107         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1108 }
1109
1110 static void
1111 at91dci_root_intr(struct at91dci_softc *sc)
1112 {
1113         DPRINTFN(9, "\n");
1114
1115         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1116
1117         /* set port bit */
1118         sc->sc_hub_idata[0] = 0x02;     /* we only have one port */
1119
1120         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
1121             sizeof(sc->sc_hub_idata));
1122 }
1123
1124 static usb_error_t
1125 at91dci_standard_done_sub(struct usb_xfer *xfer)
1126 {
1127         struct at91dci_td *td;
1128         uint32_t len;
1129         uint8_t error;
1130
1131         DPRINTFN(9, "\n");
1132
1133         td = xfer->td_transfer_cache;
1134
1135         do {
1136                 len = td->remainder;
1137
1138                 if (xfer->aframes != xfer->nframes) {
1139                         /*
1140                          * Verify the length and subtract
1141                          * the remainder from "frlengths[]":
1142                          */
1143                         if (len > xfer->frlengths[xfer->aframes]) {
1144                                 td->error = 1;
1145                         } else {
1146                                 xfer->frlengths[xfer->aframes] -= len;
1147                         }
1148                 }
1149                 /* Check for transfer error */
1150                 if (td->error) {
1151                         /* the transfer is finished */
1152                         error = 1;
1153                         td = NULL;
1154                         break;
1155                 }
1156                 /* Check for short transfer */
1157                 if (len > 0) {
1158                         if (xfer->flags_int.short_frames_ok) {
1159                                 /* follow alt next */
1160                                 if (td->alt_next) {
1161                                         td = td->obj_next;
1162                                 } else {
1163                                         td = NULL;
1164                                 }
1165                         } else {
1166                                 /* the transfer is finished */
1167                                 td = NULL;
1168                         }
1169                         error = 0;
1170                         break;
1171                 }
1172                 td = td->obj_next;
1173
1174                 /* this USB frame is complete */
1175                 error = 0;
1176                 break;
1177
1178         } while (0);
1179
1180         /* update transfer cache */
1181
1182         xfer->td_transfer_cache = td;
1183
1184         return (error ?
1185             USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1186 }
1187
1188 static void
1189 at91dci_standard_done(struct usb_xfer *xfer)
1190 {
1191         usb_error_t err = 0;
1192
1193         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1194             xfer, xfer->endpoint);
1195
1196         /* reset scanner */
1197
1198         xfer->td_transfer_cache = xfer->td_transfer_first;
1199
1200         if (xfer->flags_int.control_xfr) {
1201
1202                 if (xfer->flags_int.control_hdr) {
1203
1204                         err = at91dci_standard_done_sub(xfer);
1205                 }
1206                 xfer->aframes = 1;
1207
1208                 if (xfer->td_transfer_cache == NULL) {
1209                         goto done;
1210                 }
1211         }
1212         while (xfer->aframes != xfer->nframes) {
1213
1214                 err = at91dci_standard_done_sub(xfer);
1215                 xfer->aframes++;
1216
1217                 if (xfer->td_transfer_cache == NULL) {
1218                         goto done;
1219                 }
1220         }
1221
1222         if (xfer->flags_int.control_xfr &&
1223             !xfer->flags_int.control_act) {
1224
1225                 err = at91dci_standard_done_sub(xfer);
1226         }
1227 done:
1228         at91dci_device_done(xfer, err);
1229 }
1230
1231 /*------------------------------------------------------------------------*
1232  *      at91dci_device_done
1233  *
1234  * NOTE: this function can be called more than one time on the
1235  * same USB transfer!
1236  *------------------------------------------------------------------------*/
1237 static void
1238 at91dci_device_done(struct usb_xfer *xfer, usb_error_t error)
1239 {
1240         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1241         uint8_t ep_no;
1242
1243         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1244
1245         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1246             xfer, xfer->endpoint, error);
1247
1248         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1249
1250         if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) {
1251                 ep_no = (xfer->endpointno & UE_ADDR);
1252
1253                 /* disable endpoint interrupt */
1254                 AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, AT91_UDP_INT_EP(ep_no));
1255
1256                 DPRINTFN(15, "disable interrupts on endpoint %d\n", ep_no);
1257         }
1258
1259         /* dequeue transfer and start next transfer */
1260         usbd_transfer_done(xfer, error);
1261
1262         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1263 }
1264
1265 static void
1266 at91dci_xfer_stall(struct usb_xfer *xfer)
1267 {
1268         at91dci_device_done(xfer, USB_ERR_STALLED);
1269 }
1270
1271 static void
1272 at91dci_set_stall(struct usb_device *udev,
1273     struct usb_endpoint *ep, uint8_t *did_stall)
1274 {
1275         struct at91dci_softc *sc;
1276         uint32_t csr_val;
1277         uint8_t csr_reg;
1278
1279         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1280
1281         DPRINTFN(5, "endpoint=%p\n", ep);
1282
1283         /* set FORCESTALL */
1284         sc = AT9100_DCI_BUS2SC(udev->bus);
1285
1286         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1287         csr_reg = (ep->edesc->bEndpointAddress & UE_ADDR);
1288         csr_reg = AT91_UDP_CSR(csr_reg);
1289         csr_val = AT91_UDP_READ_4(sc, csr_reg);
1290         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_FORCESTALL);
1291         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1292         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1293 }
1294
1295 static void
1296 at91dci_clear_stall_sub(struct at91dci_softc *sc, uint8_t ep_no,
1297     uint8_t ep_type, uint8_t ep_dir)
1298 {
1299         const struct usb_hw_ep_profile *pf;
1300         uint32_t csr_val;
1301         uint32_t temp;
1302         uint8_t csr_reg;
1303         uint8_t to;
1304
1305         if (ep_type == UE_CONTROL) {
1306                 /* clearing stall is not needed */
1307                 return;
1308         }
1309
1310         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1311
1312         /* compute CSR register offset */
1313         csr_reg = AT91_UDP_CSR(ep_no);
1314
1315         /* compute default CSR value */
1316         csr_val = 0;
1317         AT91_CSR_ACK(csr_val, 0);
1318
1319         /* disable endpoint */
1320         AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1321
1322         /* get endpoint profile */
1323         at91dci_get_hw_ep_profile(NULL, &pf, ep_no);
1324
1325         /* reset FIFO */
1326         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, AT91_UDP_RST_EP(ep_no));
1327         AT91_UDP_WRITE_4(sc, AT91_UDP_RST, 0);
1328
1329         /*
1330          * NOTE: One would assume that a FIFO reset would release the
1331          * FIFO banks aswell, but it doesn't! We have to do this
1332          * manually!
1333          */
1334
1335         /* release FIFO banks, if any */
1336         for (to = 0; to != 2; to++) {
1337
1338                 /* get csr value */
1339                 csr_val = AT91_UDP_READ_4(sc, csr_reg);
1340
1341                 if (csr_val & (AT91_UDP_CSR_RX_DATA_BK0 |
1342                     AT91_UDP_CSR_RX_DATA_BK1)) {
1343                         /* clear status bits */
1344                         if (pf->support_multi_buffer) {
1345                                 if (sc->sc_ep_flags[ep_no].fifo_bank) {
1346                                         sc->sc_ep_flags[ep_no].fifo_bank = 0;
1347                                         temp = AT91_UDP_CSR_RX_DATA_BK1;
1348                                 } else {
1349                                         sc->sc_ep_flags[ep_no].fifo_bank = 1;
1350                                         temp = AT91_UDP_CSR_RX_DATA_BK0;
1351                                 }
1352                         } else {
1353                                 temp = (AT91_UDP_CSR_RX_DATA_BK0 |
1354                                     AT91_UDP_CSR_RX_DATA_BK1);
1355                         }
1356                 } else {
1357                         temp = 0;
1358                 }
1359
1360                 /* clear FORCESTALL */
1361                 temp |= AT91_UDP_CSR_STALLSENT;
1362
1363                 AT91_CSR_ACK(csr_val, temp);
1364                 AT91_UDP_WRITE_4(sc, csr_reg, csr_val);
1365         }
1366
1367         /* compute default CSR value */
1368         csr_val = 0;
1369         AT91_CSR_ACK(csr_val, 0);
1370
1371         /* enable endpoint */
1372         csr_val &= ~AT91_UDP_CSR_ET_MASK;
1373         csr_val |= AT91_UDP_CSR_EPEDS;
1374
1375         if (ep_type == UE_CONTROL) {
1376                 csr_val |= AT91_UDP_CSR_ET_CTRL;
1377         } else {
1378                 if (ep_type == UE_BULK) {
1379                         csr_val |= AT91_UDP_CSR_ET_BULK;
1380                 } else if (ep_type == UE_INTERRUPT) {
1381                         csr_val |= AT91_UDP_CSR_ET_INT;
1382                 } else {
1383                         csr_val |= AT91_UDP_CSR_ET_ISO;
1384                 }
1385                 if (ep_dir & UE_DIR_IN) {
1386                         csr_val |= AT91_UDP_CSR_ET_DIR_IN;
1387                 }
1388         }
1389
1390         /* enable endpoint */
1391         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(ep_no), csr_val);
1392
1393         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1394 }
1395
1396 static void
1397 at91dci_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
1398 {
1399         struct at91dci_softc *sc;
1400         struct usb_endpoint_descriptor *ed;
1401
1402         DPRINTFN(5, "endpoint=%p\n", ep);
1403
1404         USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED);
1405
1406         /* check mode */
1407         if (udev->flags.usb_mode != USB_MODE_DEVICE) {
1408                 /* not supported */
1409                 return;
1410         }
1411         /* get softc */
1412         sc = AT9100_DCI_BUS2SC(udev->bus);
1413
1414         /* get endpoint descriptor */
1415         ed = ep->edesc;
1416
1417         /* reset endpoint */
1418         at91dci_clear_stall_sub(sc,
1419             (ed->bEndpointAddress & UE_ADDR),
1420             (ed->bmAttributes & UE_XFERTYPE),
1421             (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT)));
1422 }
1423
1424 usb_error_t
1425 at91dci_init(struct at91dci_softc *sc)
1426 {
1427         uint32_t csr_val;
1428         uint8_t n;
1429
1430         DPRINTF("start\n");
1431
1432         /* set up the bus structure */
1433         sc->sc_bus.usbrev = USB_REV_1_1;
1434         sc->sc_bus.methods = &at91dci_bus_methods;
1435
1436         USB_BUS_LOCK(&sc->sc_bus);
1437
1438         /* turn on clocks */
1439
1440         if (sc->sc_clocks_on) {
1441                 (sc->sc_clocks_on) (sc->sc_clocks_arg);
1442         }
1443         /* wait a little for things to stabilise */
1444         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
1445
1446         /* disable and clear all interrupts */
1447
1448         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1449         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1450
1451         /* compute default CSR value */
1452
1453         csr_val = 0;
1454         AT91_CSR_ACK(csr_val, 0);
1455
1456         /* disable all endpoints */
1457
1458         for (n = 0; n != AT91_UDP_EP_MAX; n++) {
1459
1460                 /* disable endpoint */
1461                 AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(n), csr_val);
1462         }
1463
1464         /* enable the control endpoint */
1465
1466         AT91_CSR_ACK(csr_val, AT91_UDP_CSR_ET_CTRL |
1467             AT91_UDP_CSR_EPEDS);
1468
1469         /* write to FIFO control register */
1470
1471         AT91_UDP_WRITE_4(sc, AT91_UDP_CSR(0), csr_val);
1472
1473         /* enable the interrupts we want */
1474
1475         AT91_UDP_WRITE_4(sc, AT91_UDP_IER, AT91_UDP_INT_BUS);
1476
1477         /* turn off clocks */
1478
1479         at91dci_clocks_off(sc);
1480
1481         USB_BUS_UNLOCK(&sc->sc_bus);
1482
1483         /* catch any lost interrupts */
1484
1485         at91dci_do_poll(&sc->sc_bus);
1486
1487         return (0);                     /* success */
1488 }
1489
1490 void
1491 at91dci_uninit(struct at91dci_softc *sc)
1492 {
1493         USB_BUS_LOCK(&sc->sc_bus);
1494
1495         /* disable and clear all interrupts */
1496         AT91_UDP_WRITE_4(sc, AT91_UDP_IDR, 0xFFFFFFFF);
1497         AT91_UDP_WRITE_4(sc, AT91_UDP_ICR, 0xFFFFFFFF);
1498
1499         sc->sc_flags.port_powered = 0;
1500         sc->sc_flags.status_vbus = 0;
1501         sc->sc_flags.status_bus_reset = 0;
1502         sc->sc_flags.status_suspend = 0;
1503         sc->sc_flags.change_suspend = 0;
1504         sc->sc_flags.change_connect = 1;
1505
1506         at91dci_pull_down(sc);
1507         at91dci_clocks_off(sc);
1508         USB_BUS_UNLOCK(&sc->sc_bus);
1509 }
1510
1511 static void
1512 at91dci_suspend(struct at91dci_softc *sc)
1513 {
1514         /* TODO */
1515 }
1516
1517 static void
1518 at91dci_resume(struct at91dci_softc *sc)
1519 {
1520         /* TODO */
1521 }
1522
1523 static void
1524 at91dci_do_poll(struct usb_bus *bus)
1525 {
1526         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
1527
1528         USB_BUS_LOCK(&sc->sc_bus);
1529         USB_BUS_SPIN_LOCK(&sc->sc_bus);
1530         at91dci_interrupt_poll_locked(sc);
1531         at91dci_interrupt_complete_locked(sc);
1532         USB_BUS_SPIN_UNLOCK(&sc->sc_bus);
1533         USB_BUS_UNLOCK(&sc->sc_bus);
1534 }
1535
1536 /*------------------------------------------------------------------------*
1537  * at91dci bulk support
1538  *------------------------------------------------------------------------*/
1539 static void
1540 at91dci_device_bulk_open(struct usb_xfer *xfer)
1541 {
1542         return;
1543 }
1544
1545 static void
1546 at91dci_device_bulk_close(struct usb_xfer *xfer)
1547 {
1548         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1549 }
1550
1551 static void
1552 at91dci_device_bulk_enter(struct usb_xfer *xfer)
1553 {
1554         return;
1555 }
1556
1557 static void
1558 at91dci_device_bulk_start(struct usb_xfer *xfer)
1559 {
1560         /* setup TDs */
1561         at91dci_setup_standard_chain(xfer);
1562         at91dci_start_standard_chain(xfer);
1563 }
1564
1565 struct usb_pipe_methods at91dci_device_bulk_methods =
1566 {
1567         .open = at91dci_device_bulk_open,
1568         .close = at91dci_device_bulk_close,
1569         .enter = at91dci_device_bulk_enter,
1570         .start = at91dci_device_bulk_start,
1571 };
1572
1573 /*------------------------------------------------------------------------*
1574  * at91dci control support
1575  *------------------------------------------------------------------------*/
1576 static void
1577 at91dci_device_ctrl_open(struct usb_xfer *xfer)
1578 {
1579         return;
1580 }
1581
1582 static void
1583 at91dci_device_ctrl_close(struct usb_xfer *xfer)
1584 {
1585         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1586 }
1587
1588 static void
1589 at91dci_device_ctrl_enter(struct usb_xfer *xfer)
1590 {
1591         return;
1592 }
1593
1594 static void
1595 at91dci_device_ctrl_start(struct usb_xfer *xfer)
1596 {
1597         /* setup TDs */
1598         at91dci_setup_standard_chain(xfer);
1599         at91dci_start_standard_chain(xfer);
1600 }
1601
1602 struct usb_pipe_methods at91dci_device_ctrl_methods =
1603 {
1604         .open = at91dci_device_ctrl_open,
1605         .close = at91dci_device_ctrl_close,
1606         .enter = at91dci_device_ctrl_enter,
1607         .start = at91dci_device_ctrl_start,
1608 };
1609
1610 /*------------------------------------------------------------------------*
1611  * at91dci interrupt support
1612  *------------------------------------------------------------------------*/
1613 static void
1614 at91dci_device_intr_open(struct usb_xfer *xfer)
1615 {
1616         return;
1617 }
1618
1619 static void
1620 at91dci_device_intr_close(struct usb_xfer *xfer)
1621 {
1622         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1623 }
1624
1625 static void
1626 at91dci_device_intr_enter(struct usb_xfer *xfer)
1627 {
1628         return;
1629 }
1630
1631 static void
1632 at91dci_device_intr_start(struct usb_xfer *xfer)
1633 {
1634         /* setup TDs */
1635         at91dci_setup_standard_chain(xfer);
1636         at91dci_start_standard_chain(xfer);
1637 }
1638
1639 struct usb_pipe_methods at91dci_device_intr_methods =
1640 {
1641         .open = at91dci_device_intr_open,
1642         .close = at91dci_device_intr_close,
1643         .enter = at91dci_device_intr_enter,
1644         .start = at91dci_device_intr_start,
1645 };
1646
1647 /*------------------------------------------------------------------------*
1648  * at91dci full speed isochronous support
1649  *------------------------------------------------------------------------*/
1650 static void
1651 at91dci_device_isoc_fs_open(struct usb_xfer *xfer)
1652 {
1653         return;
1654 }
1655
1656 static void
1657 at91dci_device_isoc_fs_close(struct usb_xfer *xfer)
1658 {
1659         at91dci_device_done(xfer, USB_ERR_CANCELLED);
1660 }
1661
1662 static void
1663 at91dci_device_isoc_fs_enter(struct usb_xfer *xfer)
1664 {
1665         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(xfer->xroot->bus);
1666         uint32_t temp;
1667         uint32_t nframes;
1668
1669         DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
1670             xfer, xfer->endpoint->isoc_next, xfer->nframes);
1671
1672         /* get the current frame index */
1673
1674         nframes = AT91_UDP_READ_4(sc, AT91_UDP_FRM);
1675
1676         /*
1677          * check if the frame index is within the window where the frames
1678          * will be inserted
1679          */
1680         temp = (nframes - xfer->endpoint->isoc_next) & AT91_UDP_FRM_MASK;
1681
1682         if ((xfer->endpoint->is_synced == 0) ||
1683             (temp < xfer->nframes)) {
1684                 /*
1685                  * If there is data underflow or the endpoint queue is
1686                  * empty we schedule the transfer a few frames ahead
1687                  * of the current frame position. Else two isochronous
1688                  * transfers might overlap.
1689                  */
1690                 xfer->endpoint->isoc_next = (nframes + 3) & AT91_UDP_FRM_MASK;
1691                 xfer->endpoint->is_synced = 1;
1692                 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
1693         }
1694         /*
1695          * compute how many milliseconds the insertion is ahead of the
1696          * current frame position:
1697          */
1698         temp = (xfer->endpoint->isoc_next - nframes) & AT91_UDP_FRM_MASK;
1699
1700         /*
1701          * pre-compute when the isochronous transfer will be finished:
1702          */
1703         xfer->isoc_time_complete =
1704             usb_isoc_time_expand(&sc->sc_bus, nframes) + temp +
1705             xfer->nframes;
1706
1707         /* compute frame number for next insertion */
1708         xfer->endpoint->isoc_next += xfer->nframes;
1709
1710         /* setup TDs */
1711         at91dci_setup_standard_chain(xfer);
1712 }
1713
1714 static void
1715 at91dci_device_isoc_fs_start(struct usb_xfer *xfer)
1716 {
1717         /* start TD chain */
1718         at91dci_start_standard_chain(xfer);
1719 }
1720
1721 struct usb_pipe_methods at91dci_device_isoc_fs_methods =
1722 {
1723         .open = at91dci_device_isoc_fs_open,
1724         .close = at91dci_device_isoc_fs_close,
1725         .enter = at91dci_device_isoc_fs_enter,
1726         .start = at91dci_device_isoc_fs_start,
1727 };
1728
1729 /*------------------------------------------------------------------------*
1730  * at91dci root control support
1731  *------------------------------------------------------------------------*
1732  * Simulate a hardware HUB by handling all the necessary requests.
1733  *------------------------------------------------------------------------*/
1734
1735 static const struct usb_device_descriptor at91dci_devd = {
1736         .bLength = sizeof(struct usb_device_descriptor),
1737         .bDescriptorType = UDESC_DEVICE,
1738         .bcdUSB = {0x00, 0x02},
1739         .bDeviceClass = UDCLASS_HUB,
1740         .bDeviceSubClass = UDSUBCLASS_HUB,
1741         .bDeviceProtocol = UDPROTO_FSHUB,
1742         .bMaxPacketSize = 64,
1743         .bcdDevice = {0x00, 0x01},
1744         .iManufacturer = 1,
1745         .iProduct = 2,
1746         .bNumConfigurations = 1,
1747 };
1748
1749 static const struct at91dci_config_desc at91dci_confd = {
1750         .confd = {
1751                 .bLength = sizeof(struct usb_config_descriptor),
1752                 .bDescriptorType = UDESC_CONFIG,
1753                 .wTotalLength[0] = sizeof(at91dci_confd),
1754                 .bNumInterface = 1,
1755                 .bConfigurationValue = 1,
1756                 .iConfiguration = 0,
1757                 .bmAttributes = UC_SELF_POWERED,
1758                 .bMaxPower = 0,
1759         },
1760         .ifcd = {
1761                 .bLength = sizeof(struct usb_interface_descriptor),
1762                 .bDescriptorType = UDESC_INTERFACE,
1763                 .bNumEndpoints = 1,
1764                 .bInterfaceClass = UICLASS_HUB,
1765                 .bInterfaceSubClass = UISUBCLASS_HUB,
1766                 .bInterfaceProtocol = 0,
1767         },
1768         .endpd = {
1769                 .bLength = sizeof(struct usb_endpoint_descriptor),
1770                 .bDescriptorType = UDESC_ENDPOINT,
1771                 .bEndpointAddress = (UE_DIR_IN | AT9100_DCI_INTR_ENDPT),
1772                 .bmAttributes = UE_INTERRUPT,
1773                 .wMaxPacketSize[0] = 8,
1774                 .bInterval = 255,
1775         },
1776 };
1777
1778 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
1779
1780 static const struct usb_hub_descriptor_min at91dci_hubd = {
1781         .bDescLength = sizeof(at91dci_hubd),
1782         .bDescriptorType = UDESC_HUB,
1783         .bNbrPorts = 1,
1784         HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)),
1785         .bPwrOn2PwrGood = 50,
1786         .bHubContrCurrent = 0,
1787         .DeviceRemovable = {0},         /* port is removable */
1788 };
1789
1790 #define STRING_VENDOR \
1791   "A\0T\0M\0E\0L"
1792
1793 #define STRING_PRODUCT \
1794   "D\0C\0I\0 \0R\0o\0o\0t\0 \0H\0U\0B"
1795
1796 USB_MAKE_STRING_DESC(STRING_VENDOR, at91dci_vendor);
1797 USB_MAKE_STRING_DESC(STRING_PRODUCT, at91dci_product);
1798
1799 static usb_error_t
1800 at91dci_roothub_exec(struct usb_device *udev,
1801     struct usb_device_request *req, const void **pptr, uint16_t *plength)
1802 {
1803         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
1804         const void *ptr;
1805         uint16_t len;
1806         uint16_t value;
1807         uint16_t index;
1808         usb_error_t err;
1809
1810         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1811
1812         /* buffer reset */
1813         ptr = (const void *)&sc->sc_hub_temp;
1814         len = 0;
1815         err = 0;
1816
1817         value = UGETW(req->wValue);
1818         index = UGETW(req->wIndex);
1819
1820         /* demultiplex the control request */
1821
1822         switch (req->bmRequestType) {
1823         case UT_READ_DEVICE:
1824                 switch (req->bRequest) {
1825                 case UR_GET_DESCRIPTOR:
1826                         goto tr_handle_get_descriptor;
1827                 case UR_GET_CONFIG:
1828                         goto tr_handle_get_config;
1829                 case UR_GET_STATUS:
1830                         goto tr_handle_get_status;
1831                 default:
1832                         goto tr_stalled;
1833                 }
1834                 break;
1835
1836         case UT_WRITE_DEVICE:
1837                 switch (req->bRequest) {
1838                 case UR_SET_ADDRESS:
1839                         goto tr_handle_set_address;
1840                 case UR_SET_CONFIG:
1841                         goto tr_handle_set_config;
1842                 case UR_CLEAR_FEATURE:
1843                         goto tr_valid;  /* nop */
1844                 case UR_SET_DESCRIPTOR:
1845                         goto tr_valid;  /* nop */
1846                 case UR_SET_FEATURE:
1847                 default:
1848                         goto tr_stalled;
1849                 }
1850                 break;
1851
1852         case UT_WRITE_ENDPOINT:
1853                 switch (req->bRequest) {
1854                 case UR_CLEAR_FEATURE:
1855                         switch (UGETW(req->wValue)) {
1856                         case UF_ENDPOINT_HALT:
1857                                 goto tr_handle_clear_halt;
1858                         case UF_DEVICE_REMOTE_WAKEUP:
1859                                 goto tr_handle_clear_wakeup;
1860                         default:
1861                                 goto tr_stalled;
1862                         }
1863                         break;
1864                 case UR_SET_FEATURE:
1865                         switch (UGETW(req->wValue)) {
1866                         case UF_ENDPOINT_HALT:
1867                                 goto tr_handle_set_halt;
1868                         case UF_DEVICE_REMOTE_WAKEUP:
1869                                 goto tr_handle_set_wakeup;
1870                         default:
1871                                 goto tr_stalled;
1872                         }
1873                         break;
1874                 case UR_SYNCH_FRAME:
1875                         goto tr_valid;  /* nop */
1876                 default:
1877                         goto tr_stalled;
1878                 }
1879                 break;
1880
1881         case UT_READ_ENDPOINT:
1882                 switch (req->bRequest) {
1883                 case UR_GET_STATUS:
1884                         goto tr_handle_get_ep_status;
1885                 default:
1886                         goto tr_stalled;
1887                 }
1888                 break;
1889
1890         case UT_WRITE_INTERFACE:
1891                 switch (req->bRequest) {
1892                 case UR_SET_INTERFACE:
1893                         goto tr_handle_set_interface;
1894                 case UR_CLEAR_FEATURE:
1895                         goto tr_valid;  /* nop */
1896                 case UR_SET_FEATURE:
1897                 default:
1898                         goto tr_stalled;
1899                 }
1900                 break;
1901
1902         case UT_READ_INTERFACE:
1903                 switch (req->bRequest) {
1904                 case UR_GET_INTERFACE:
1905                         goto tr_handle_get_interface;
1906                 case UR_GET_STATUS:
1907                         goto tr_handle_get_iface_status;
1908                 default:
1909                         goto tr_stalled;
1910                 }
1911                 break;
1912
1913         case UT_WRITE_CLASS_INTERFACE:
1914         case UT_WRITE_VENDOR_INTERFACE:
1915                 /* XXX forward */
1916                 break;
1917
1918         case UT_READ_CLASS_INTERFACE:
1919         case UT_READ_VENDOR_INTERFACE:
1920                 /* XXX forward */
1921                 break;
1922
1923         case UT_WRITE_CLASS_DEVICE:
1924                 switch (req->bRequest) {
1925                 case UR_CLEAR_FEATURE:
1926                         goto tr_valid;
1927                 case UR_SET_DESCRIPTOR:
1928                 case UR_SET_FEATURE:
1929                         break;
1930                 default:
1931                         goto tr_stalled;
1932                 }
1933                 break;
1934
1935         case UT_WRITE_CLASS_OTHER:
1936                 switch (req->bRequest) {
1937                 case UR_CLEAR_FEATURE:
1938                         goto tr_handle_clear_port_feature;
1939                 case UR_SET_FEATURE:
1940                         goto tr_handle_set_port_feature;
1941                 case UR_CLEAR_TT_BUFFER:
1942                 case UR_RESET_TT:
1943                 case UR_STOP_TT:
1944                         goto tr_valid;
1945
1946                 default:
1947                         goto tr_stalled;
1948                 }
1949                 break;
1950
1951         case UT_READ_CLASS_OTHER:
1952                 switch (req->bRequest) {
1953                 case UR_GET_TT_STATE:
1954                         goto tr_handle_get_tt_state;
1955                 case UR_GET_STATUS:
1956                         goto tr_handle_get_port_status;
1957                 default:
1958                         goto tr_stalled;
1959                 }
1960                 break;
1961
1962         case UT_READ_CLASS_DEVICE:
1963                 switch (req->bRequest) {
1964                 case UR_GET_DESCRIPTOR:
1965                         goto tr_handle_get_class_descriptor;
1966                 case UR_GET_STATUS:
1967                         goto tr_handle_get_class_status;
1968
1969                 default:
1970                         goto tr_stalled;
1971                 }
1972                 break;
1973         default:
1974                 goto tr_stalled;
1975         }
1976         goto tr_valid;
1977
1978 tr_handle_get_descriptor:
1979         switch (value >> 8) {
1980         case UDESC_DEVICE:
1981                 if (value & 0xff) {
1982                         goto tr_stalled;
1983                 }
1984                 len = sizeof(at91dci_devd);
1985                 ptr = (const void *)&at91dci_devd;
1986                 goto tr_valid;
1987         case UDESC_CONFIG:
1988                 if (value & 0xff) {
1989                         goto tr_stalled;
1990                 }
1991                 len = sizeof(at91dci_confd);
1992                 ptr = (const void *)&at91dci_confd;
1993                 goto tr_valid;
1994         case UDESC_STRING:
1995                 switch (value & 0xff) {
1996                 case 0:         /* Language table */
1997                         len = sizeof(usb_string_lang_en);
1998                         ptr = (const void *)&usb_string_lang_en;
1999                         goto tr_valid;
2000
2001                 case 1:         /* Vendor */
2002                         len = sizeof(at91dci_vendor);
2003                         ptr = (const void *)&at91dci_vendor;
2004                         goto tr_valid;
2005
2006                 case 2:         /* Product */
2007                         len = sizeof(at91dci_product);
2008                         ptr = (const void *)&at91dci_product;
2009                         goto tr_valid;
2010                 default:
2011                         break;
2012                 }
2013                 break;
2014         default:
2015                 goto tr_stalled;
2016         }
2017         goto tr_stalled;
2018
2019 tr_handle_get_config:
2020         len = 1;
2021         sc->sc_hub_temp.wValue[0] = sc->sc_conf;
2022         goto tr_valid;
2023
2024 tr_handle_get_status:
2025         len = 2;
2026         USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED);
2027         goto tr_valid;
2028
2029 tr_handle_set_address:
2030         if (value & 0xFF00) {
2031                 goto tr_stalled;
2032         }
2033         sc->sc_rt_addr = value;
2034         goto tr_valid;
2035
2036 tr_handle_set_config:
2037         if (value >= 2) {
2038                 goto tr_stalled;
2039         }
2040         sc->sc_conf = value;
2041         goto tr_valid;
2042
2043 tr_handle_get_interface:
2044         len = 1;
2045         sc->sc_hub_temp.wValue[0] = 0;
2046         goto tr_valid;
2047
2048 tr_handle_get_tt_state:
2049 tr_handle_get_class_status:
2050 tr_handle_get_iface_status:
2051 tr_handle_get_ep_status:
2052         len = 2;
2053         USETW(sc->sc_hub_temp.wValue, 0);
2054         goto tr_valid;
2055
2056 tr_handle_set_halt:
2057 tr_handle_set_interface:
2058 tr_handle_set_wakeup:
2059 tr_handle_clear_wakeup:
2060 tr_handle_clear_halt:
2061         goto tr_valid;
2062
2063 tr_handle_clear_port_feature:
2064         if (index != 1) {
2065                 goto tr_stalled;
2066         }
2067         DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index);
2068
2069         switch (value) {
2070         case UHF_PORT_SUSPEND:
2071                 at91dci_wakeup_peer(sc);
2072                 break;
2073
2074         case UHF_PORT_ENABLE:
2075                 sc->sc_flags.port_enabled = 0;
2076                 break;
2077
2078         case UHF_PORT_TEST:
2079         case UHF_PORT_INDICATOR:
2080         case UHF_C_PORT_ENABLE:
2081         case UHF_C_PORT_OVER_CURRENT:
2082         case UHF_C_PORT_RESET:
2083                 /* nops */
2084                 break;
2085         case UHF_PORT_POWER:
2086                 sc->sc_flags.port_powered = 0;
2087                 at91dci_pull_down(sc);
2088                 at91dci_clocks_off(sc);
2089                 break;
2090         case UHF_C_PORT_CONNECTION:
2091                 sc->sc_flags.change_connect = 0;
2092                 break;
2093         case UHF_C_PORT_SUSPEND:
2094                 sc->sc_flags.change_suspend = 0;
2095                 break;
2096         default:
2097                 err = USB_ERR_IOERROR;
2098                 goto done;
2099         }
2100         goto tr_valid;
2101
2102 tr_handle_set_port_feature:
2103         if (index != 1) {
2104                 goto tr_stalled;
2105         }
2106         DPRINTFN(9, "UR_SET_PORT_FEATURE\n");
2107
2108         switch (value) {
2109         case UHF_PORT_ENABLE:
2110                 sc->sc_flags.port_enabled = 1;
2111                 break;
2112         case UHF_PORT_SUSPEND:
2113         case UHF_PORT_RESET:
2114         case UHF_PORT_TEST:
2115         case UHF_PORT_INDICATOR:
2116                 /* nops */
2117                 break;
2118         case UHF_PORT_POWER:
2119                 sc->sc_flags.port_powered = 1;
2120                 break;
2121         default:
2122                 err = USB_ERR_IOERROR;
2123                 goto done;
2124         }
2125         goto tr_valid;
2126
2127 tr_handle_get_port_status:
2128
2129         DPRINTFN(9, "UR_GET_PORT_STATUS\n");
2130
2131         if (index != 1) {
2132                 goto tr_stalled;
2133         }
2134         if (sc->sc_flags.status_vbus) {
2135                 at91dci_clocks_on(sc);
2136                 at91dci_pull_up(sc);
2137         } else {
2138                 at91dci_pull_down(sc);
2139                 at91dci_clocks_off(sc);
2140         }
2141
2142         /* Select FULL-speed and Device Side Mode */
2143
2144         value = UPS_PORT_MODE_DEVICE;
2145
2146         if (sc->sc_flags.port_powered) {
2147                 value |= UPS_PORT_POWER;
2148         }
2149         if (sc->sc_flags.port_enabled) {
2150                 value |= UPS_PORT_ENABLED;
2151         }
2152         if (sc->sc_flags.status_vbus &&
2153             sc->sc_flags.status_bus_reset) {
2154                 value |= UPS_CURRENT_CONNECT_STATUS;
2155         }
2156         if (sc->sc_flags.status_suspend) {
2157                 value |= UPS_SUSPEND;
2158         }
2159         USETW(sc->sc_hub_temp.ps.wPortStatus, value);
2160
2161         value = 0;
2162
2163         if (sc->sc_flags.change_connect) {
2164                 value |= UPS_C_CONNECT_STATUS;
2165
2166                 if (sc->sc_flags.status_vbus &&
2167                     sc->sc_flags.status_bus_reset) {
2168                         /* reset endpoint flags */
2169                         memset(sc->sc_ep_flags, 0, sizeof(sc->sc_ep_flags));
2170                 }
2171         }
2172         if (sc->sc_flags.change_suspend) {
2173                 value |= UPS_C_SUSPEND;
2174         }
2175         USETW(sc->sc_hub_temp.ps.wPortChange, value);
2176         len = sizeof(sc->sc_hub_temp.ps);
2177         goto tr_valid;
2178
2179 tr_handle_get_class_descriptor:
2180         if (value & 0xFF) {
2181                 goto tr_stalled;
2182         }
2183         ptr = (const void *)&at91dci_hubd;
2184         len = sizeof(at91dci_hubd);
2185         goto tr_valid;
2186
2187 tr_stalled:
2188         err = USB_ERR_STALLED;
2189 tr_valid:
2190 done:
2191         *plength = len;
2192         *pptr = ptr;
2193         return (err);
2194 }
2195
2196 static void
2197 at91dci_xfer_setup(struct usb_setup_params *parm)
2198 {
2199         const struct usb_hw_ep_profile *pf;
2200         struct at91dci_softc *sc;
2201         struct usb_xfer *xfer;
2202         void *last_obj;
2203         uint32_t ntd;
2204         uint32_t n;
2205         uint8_t ep_no;
2206
2207         sc = AT9100_DCI_BUS2SC(parm->udev->bus);
2208         xfer = parm->curr_xfer;
2209
2210         /*
2211          * NOTE: This driver does not use any of the parameters that
2212          * are computed from the following values. Just set some
2213          * reasonable dummies:
2214          */
2215         parm->hc_max_packet_size = 0x500;
2216         parm->hc_max_packet_count = 1;
2217         parm->hc_max_frame_size = 0x500;
2218
2219         usbd_transfer_setup_sub(parm);
2220
2221         /*
2222          * compute maximum number of TDs
2223          */
2224         if (parm->methods == &at91dci_device_ctrl_methods) {
2225
2226                 ntd = xfer->nframes + 1 /* STATUS */ + 1        /* SYNC 1 */
2227                     + 1 /* SYNC 2 */ ;
2228
2229         } else if (parm->methods == &at91dci_device_bulk_methods) {
2230
2231                 ntd = xfer->nframes + 1 /* SYNC */ ;
2232
2233         } else if (parm->methods == &at91dci_device_intr_methods) {
2234
2235                 ntd = xfer->nframes + 1 /* SYNC */ ;
2236
2237         } else if (parm->methods == &at91dci_device_isoc_fs_methods) {
2238
2239                 ntd = xfer->nframes + 1 /* SYNC */ ;
2240
2241         } else {
2242
2243                 ntd = 0;
2244         }
2245
2246         /*
2247          * check if "usbd_transfer_setup_sub" set an error
2248          */
2249         if (parm->err) {
2250                 return;
2251         }
2252         /*
2253          * allocate transfer descriptors
2254          */
2255         last_obj = NULL;
2256
2257         /*
2258          * get profile stuff
2259          */
2260         if (ntd) {
2261
2262                 ep_no = xfer->endpointno & UE_ADDR;
2263                 at91dci_get_hw_ep_profile(parm->udev, &pf, ep_no);
2264
2265                 if (pf == NULL) {
2266                         /* should not happen */
2267                         parm->err = USB_ERR_INVAL;
2268                         return;
2269                 }
2270         } else {
2271                 ep_no = 0;
2272                 pf = NULL;
2273         }
2274
2275         /* align data */
2276         parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1));
2277
2278         for (n = 0; n != ntd; n++) {
2279
2280                 struct at91dci_td *td;
2281
2282                 if (parm->buf) {
2283
2284                         td = USB_ADD_BYTES(parm->buf, parm->size[0]);
2285
2286                         /* init TD */
2287                         td->max_packet_size = xfer->max_packet_size;
2288                         td->status_reg = AT91_UDP_CSR(ep_no);
2289                         td->fifo_reg = AT91_UDP_FDR(ep_no);
2290                         if (pf->support_multi_buffer) {
2291                                 td->support_multi_buffer = 1;
2292                         }
2293                         td->obj_next = last_obj;
2294
2295                         last_obj = td;
2296                 }
2297                 parm->size[0] += sizeof(*td);
2298         }
2299
2300         xfer->td_start[0] = last_obj;
2301 }
2302
2303 static void
2304 at91dci_xfer_unsetup(struct usb_xfer *xfer)
2305 {
2306         return;
2307 }
2308
2309 static void
2310 at91dci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2311     struct usb_endpoint *ep)
2312 {
2313         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(udev->bus);
2314
2315         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2316             ep, udev->address,
2317             edesc->bEndpointAddress, udev->flags.usb_mode,
2318             sc->sc_rt_addr);
2319
2320         if (udev->device_index != sc->sc_rt_addr) {
2321
2322                 if (udev->speed != USB_SPEED_FULL) {
2323                         /* not supported */
2324                         return;
2325                 }
2326                 switch (edesc->bmAttributes & UE_XFERTYPE) {
2327                 case UE_CONTROL:
2328                         ep->methods = &at91dci_device_ctrl_methods;
2329                         break;
2330                 case UE_INTERRUPT:
2331                         ep->methods = &at91dci_device_intr_methods;
2332                         break;
2333                 case UE_ISOCHRONOUS:
2334                         ep->methods = &at91dci_device_isoc_fs_methods;
2335                         break;
2336                 case UE_BULK:
2337                         ep->methods = &at91dci_device_bulk_methods;
2338                         break;
2339                 default:
2340                         /* do nothing */
2341                         break;
2342                 }
2343         }
2344 }
2345
2346 static void
2347 at91dci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
2348 {
2349         struct at91dci_softc *sc = AT9100_DCI_BUS2SC(bus);
2350
2351         switch (state) {
2352         case USB_HW_POWER_SUSPEND:
2353                 at91dci_suspend(sc);
2354                 break;
2355         case USB_HW_POWER_SHUTDOWN:
2356                 at91dci_uninit(sc);
2357                 break;
2358         case USB_HW_POWER_RESUME:
2359                 at91dci_resume(sc);
2360                 break;
2361         default:
2362                 break;
2363         }
2364 }
2365
2366 struct usb_bus_methods at91dci_bus_methods =
2367 {
2368         .endpoint_init = &at91dci_ep_init,
2369         .xfer_setup = &at91dci_xfer_setup,
2370         .xfer_unsetup = &at91dci_xfer_unsetup,
2371         .get_hw_ep_profile = &at91dci_get_hw_ep_profile,
2372         .set_stall = &at91dci_set_stall,
2373         .xfer_stall = &at91dci_xfer_stall,
2374         .clear_stall = &at91dci_clear_stall,
2375         .roothub_exec = &at91dci_roothub_exec,
2376         .xfer_poll = &at91dci_do_poll,
2377         .set_hw_power_sleep = &at91dci_set_hw_power_sleep,
2378 };