1 /* $OpenBSD: rt2860reg.h,v 1.19 2009/05/18 19:25:07 damien Exp $ */
5 * Damien Bergamini <damien.bergamini@free.fr>
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
25 #define RT2860_CONFIG_NO 1
26 #define RT2860_IFACE_INDEX 0
28 #define RT3070_OPT_14 0x0114
30 /* SCH/DMA registers */
31 #define RT2860_INT_STATUS 0x0200
32 #define RT2860_INT_MASK 0x0204
33 #define RT2860_WPDMA_GLO_CFG 0x0208
34 #define RT2860_WPDMA_RST_IDX 0x020c
35 #define RT2860_DELAY_INT_CFG 0x0210
36 #define RT2860_WMM_AIFSN_CFG 0x0214
37 #define RT2860_WMM_CWMIN_CFG 0x0218
38 #define RT2860_WMM_CWMAX_CFG 0x021c
39 #define RT2860_WMM_TXOP0_CFG 0x0220
40 #define RT2860_WMM_TXOP1_CFG 0x0224
41 #define RT2860_GPIO_CTRL 0x0228
42 #define RT2860_MCU_CMD_REG 0x022c
43 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16)
44 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16)
45 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16)
46 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16)
47 #define RT2860_RX_BASE_PTR 0x0290
48 #define RT2860_RX_MAX_CNT 0x0294
49 #define RT2860_RX_CALC_IDX 0x0298
50 #define RT2860_FS_DRX_IDX 0x029c
51 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */
52 #define RT2860_US_CYC_CNT 0x02a4
55 #define RT2860_SYS_CTRL 0x0400
56 #define RT2860_HOST_CMD 0x0404
57 #define RT2860_PBF_CFG 0x0408
58 #define RT2860_MAX_PCNT 0x040c
59 #define RT2860_BUF_CTRL 0x0410
60 #define RT2860_MCU_INT_STA 0x0414
61 #define RT2860_MCU_INT_ENA 0x0418
62 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4)
63 #define RT2860_RX0Q_IO 0x0424
64 #define RT2860_BCN_OFFSET0 0x042c
65 #define RT2860_BCN_OFFSET1 0x0430
66 #define RT2860_TXRXQ_STA 0x0434
67 #define RT2860_TXRXQ_PCNT 0x0438
68 #define RT2860_PBF_DBG 0x043c
69 #define RT2860_CAP_CTRL 0x0440
71 /* RT3070 registers */
72 #define RT3070_RF_CSR_CFG 0x0500
73 #define RT3070_EFUSE_CTRL 0x0580
74 #define RT3070_EFUSE_DATA0 0x0590
75 #define RT3070_EFUSE_DATA1 0x0594
76 #define RT3070_EFUSE_DATA2 0x0598
77 #define RT3070_EFUSE_DATA3 0x059c
78 #define RT3070_LDO_CFG0 0x05d4
79 #define RT3070_GPIO_SWITCH 0x05dc
81 /* RT5592 registers */
82 #define RT5592_DEBUG_INDEX 0x05e8
85 #define RT2860_ASIC_VER_ID 0x1000
86 #define RT2860_MAC_SYS_CTRL 0x1004
87 #define RT2860_MAC_ADDR_DW0 0x1008
88 #define RT2860_MAC_ADDR_DW1 0x100c
89 #define RT2860_MAC_BSSID_DW0 0x1010
90 #define RT2860_MAC_BSSID_DW1 0x1014
91 #define RT2860_MAX_LEN_CFG 0x1018
92 #define RT2860_BBP_CSR_CFG 0x101c
93 #define RT2860_RF_CSR_CFG0 0x1020
94 #define RT2860_RF_CSR_CFG1 0x1024
95 #define RT2860_RF_CSR_CFG2 0x1028
96 #define RT2860_LED_CFG 0x102c
98 /* undocumented registers */
99 #define RT2860_DEBUG 0x10f4
101 /* MAC Timing control registers */
102 #define RT2860_XIFS_TIME_CFG 0x1100
103 #define RT2860_BKOFF_SLOT_CFG 0x1104
104 #define RT2860_NAV_TIME_CFG 0x1108
105 #define RT2860_CH_TIME_CFG 0x110c
106 #define RT2860_PBF_LIFE_TIMER 0x1110
107 #define RT2860_BCN_TIME_CFG 0x1114
108 #define RT2860_TBTT_SYNC_CFG 0x1118
109 #define RT2860_TSF_TIMER_DW0 0x111c
110 #define RT2860_TSF_TIMER_DW1 0x1120
111 #define RT2860_TBTT_TIMER 0x1124
112 #define RT2860_INT_TIMER_CFG 0x1128
113 #define RT2860_INT_TIMER_EN 0x112c
114 #define RT2860_CH_IDLE_TIME 0x1130
116 /* MAC Power Save configuration registers */
117 #define RT2860_MAC_STATUS_REG 0x1200
118 #define RT2860_PWR_PIN_CFG 0x1204
119 #define RT2860_AUTO_WAKEUP_CFG 0x1208
121 /* MAC TX configuration registers */
122 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4)
123 #define RT2860_EDCA_TID_AC_MAP 0x1310
124 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4)
125 #define RT2860_TX_PIN_CFG 0x1328
126 #define RT2860_TX_BAND_CFG 0x132c
127 #define RT2860_TX_SW_CFG0 0x1330
128 #define RT2860_TX_SW_CFG1 0x1334
129 #define RT2860_TX_SW_CFG2 0x1338
130 #define RT2860_TXOP_THRES_CFG 0x133c
131 #define RT2860_TXOP_CTRL_CFG 0x1340
132 #define RT2860_TX_RTS_CFG 0x1344
133 #define RT2860_TX_TIMEOUT_CFG 0x1348
134 #define RT2860_TX_RTY_CFG 0x134c
135 #define RT2860_TX_LINK_CFG 0x1350
136 #define RT2860_HT_FBK_CFG0 0x1354
137 #define RT2860_HT_FBK_CFG1 0x1358
138 #define RT2860_LG_FBK_CFG0 0x135c
139 #define RT2860_LG_FBK_CFG1 0x1360
140 #define RT2860_CCK_PROT_CFG 0x1364
141 #define RT2860_OFDM_PROT_CFG 0x1368
142 #define RT2860_MM20_PROT_CFG 0x136c
143 #define RT2860_MM40_PROT_CFG 0x1370
144 #define RT2860_GF20_PROT_CFG 0x1374
145 #define RT2860_GF40_PROT_CFG 0x1378
146 #define RT2860_EXP_CTS_TIME 0x137c
147 #define RT2860_EXP_ACK_TIME 0x1380
149 /* MAC RX configuration registers */
150 #define RT2860_RX_FILTR_CFG 0x1400
151 #define RT2860_AUTO_RSP_CFG 0x1404
152 #define RT2860_LEGACY_BASIC_RATE 0x1408
153 #define RT2860_HT_BASIC_RATE 0x140c
154 #define RT2860_HT_CTRL_CFG 0x1410
155 #define RT2860_SIFS_COST_CFG 0x1414
156 #define RT2860_RX_PARSER_CFG 0x1418
158 /* MAC Security configuration registers */
159 #define RT2860_TX_SEC_CNT0 0x1500
160 #define RT2860_RX_SEC_CNT0 0x1504
161 #define RT2860_CCMP_FC_MUTE 0x1508
163 /* MAC HCCA/PSMP configuration registers */
164 #define RT2860_TXOP_HLDR_ADDR0 0x1600
165 #define RT2860_TXOP_HLDR_ADDR1 0x1604
166 #define RT2860_TXOP_HLDR_ET 0x1608
167 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c
168 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610
169 #define RT2860_QOS_CFPOLL_QC 0x1614
171 /* MAC Statistics Counters */
172 #define RT2860_RX_STA_CNT0 0x1700
173 #define RT2860_RX_STA_CNT1 0x1704
174 #define RT2860_RX_STA_CNT2 0x1708
175 #define RT2860_TX_STA_CNT0 0x170c
176 #define RT2860_TX_STA_CNT1 0x1710
177 #define RT2860_TX_STA_CNT2 0x1714
178 #define RT2860_TX_STAT_FIFO 0x1718
180 /* RX WCID search table */
181 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8)
183 #define RT2860_FW_BASE 0x2000
184 #define RT2870_FW_BASE 0x3000
186 /* Pair-wise key table */
187 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32)
190 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8)
192 /* WCID attribute table */
193 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4)
195 /* Shared Key Table */
196 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32)
198 /* Shared Key Mode */
199 #define RT2860_SKEY_MODE_0_7 0x7000
200 #define RT2860_SKEY_MODE_8_15 0x7004
201 #define RT2860_SKEY_MODE_16_23 0x7008
202 #define RT2860_SKEY_MODE_24_31 0x700c
204 /* Shared Memory between MCU and host */
205 #define RT2860_H2M_MAILBOX 0x7010
206 #define RT2860_H2M_MAILBOX_CID 0x7014
207 #define RT2860_H2M_MAILBOX_STATUS 0x701c
208 #define RT2860_H2M_INTSRC 0x7024
209 #define RT2860_H2M_BBPAGENT 0x7028
210 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512)
213 /* possible flags for register RT2860_PCI_EECTRL */
214 #define RT2860_C (1 << 0)
215 #define RT2860_S (1 << 1)
216 #define RT2860_D (1 << 2)
217 #define RT2860_SHIFT_D 2
218 #define RT2860_Q (1 << 3)
219 #define RT2860_SHIFT_Q 3
221 /* possible flags for registers INT_STATUS/INT_MASK */
222 #define RT2860_TX_COHERENT (1 << 17)
223 #define RT2860_RX_COHERENT (1 << 16)
224 #define RT2860_MAC_INT_4 (1 << 15)
225 #define RT2860_MAC_INT_3 (1 << 14)
226 #define RT2860_MAC_INT_2 (1 << 13)
227 #define RT2860_MAC_INT_1 (1 << 12)
228 #define RT2860_MAC_INT_0 (1 << 11)
229 #define RT2860_TX_RX_COHERENT (1 << 10)
230 #define RT2860_MCU_CMD_INT (1 << 9)
231 #define RT2860_TX_DONE_INT5 (1 << 8)
232 #define RT2860_TX_DONE_INT4 (1 << 7)
233 #define RT2860_TX_DONE_INT3 (1 << 6)
234 #define RT2860_TX_DONE_INT2 (1 << 5)
235 #define RT2860_TX_DONE_INT1 (1 << 4)
236 #define RT2860_TX_DONE_INT0 (1 << 3)
237 #define RT2860_RX_DONE_INT (1 << 2)
238 #define RT2860_TX_DLY_INT (1 << 1)
239 #define RT2860_RX_DLY_INT (1 << 0)
241 /* possible flags for register WPDMA_GLO_CFG */
242 #define RT2860_HDR_SEG_LEN_SHIFT 8
243 #define RT2860_BIG_ENDIAN (1 << 7)
244 #define RT2860_TX_WB_DDONE (1 << 6)
245 #define RT2860_WPDMA_BT_SIZE_SHIFT 4
246 #define RT2860_WPDMA_BT_SIZE16 0
247 #define RT2860_WPDMA_BT_SIZE32 1
248 #define RT2860_WPDMA_BT_SIZE64 2
249 #define RT2860_WPDMA_BT_SIZE128 3
250 #define RT2860_RX_DMA_BUSY (1 << 3)
251 #define RT2860_RX_DMA_EN (1 << 2)
252 #define RT2860_TX_DMA_BUSY (1 << 1)
253 #define RT2860_TX_DMA_EN (1 << 0)
255 /* possible flags for register DELAY_INT_CFG */
256 #define RT2860_TXDLY_INT_EN (1U << 31)
257 #define RT2860_TXMAX_PINT_SHIFT 24
258 #define RT2860_TXMAX_PTIME_SHIFT 16
259 #define RT2860_RXDLY_INT_EN (1 << 15)
260 #define RT2860_RXMAX_PINT_SHIFT 8
261 #define RT2860_RXMAX_PTIME_SHIFT 0
263 /* possible flags for register GPIO_CTRL */
264 #define RT2860_GPIO_D_SHIFT 8
265 #define RT2860_GPIO_O_SHIFT 0
267 /* possible flags for register USB_DMA_CFG */
268 #define RT2860_USB_TX_BUSY (1U << 31)
269 #define RT2860_USB_RX_BUSY (1 << 30)
270 #define RT2860_USB_EPOUT_VLD_SHIFT 24
271 #define RT2860_USB_TX_EN (1 << 23)
272 #define RT2860_USB_RX_EN (1 << 22)
273 #define RT2860_USB_RX_AGG_EN (1 << 21)
274 #define RT2860_USB_TXOP_HALT (1 << 20)
275 #define RT2860_USB_TX_CLEAR (1 << 19)
276 #define RT2860_USB_PHY_WD_EN (1 << 16)
277 #define RT2860_USB_PHY_MAN_RST (1 << 15)
278 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */
279 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */
281 /* possible flags for register US_CYC_CNT */
282 #define RT2860_TEST_EN (1 << 24)
283 #define RT2860_TEST_SEL_SHIFT 16
284 #define RT2860_BT_MODE_EN (1 << 8)
285 #define RT2860_US_CYC_CNT_SHIFT 0
287 /* possible flags for register SYS_CTRL */
288 #define RT2860_HST_PM_SEL (1 << 16)
289 #define RT2860_CAP_MODE (1 << 14)
290 #define RT2860_PME_OEN (1 << 13)
291 #define RT2860_CLKSELECT (1 << 12)
292 #define RT2860_PBF_CLK_EN (1 << 11)
293 #define RT2860_MAC_CLK_EN (1 << 10)
294 #define RT2860_DMA_CLK_EN (1 << 9)
295 #define RT2860_MCU_READY (1 << 7)
296 #define RT2860_ASY_RESET (1 << 4)
297 #define RT2860_PBF_RESET (1 << 3)
298 #define RT2860_MAC_RESET (1 << 2)
299 #define RT2860_DMA_RESET (1 << 1)
300 #define RT2860_MCU_RESET (1 << 0)
302 /* possible values for register HOST_CMD */
303 #define RT2860_MCU_CMD_SLEEP 0x30
304 #define RT2860_MCU_CMD_WAKEUP 0x31
305 #define RT2860_MCU_CMD_LEDS 0x50
306 #define RT2860_MCU_CMD_LED_RSSI 0x51
307 #define RT2860_MCU_CMD_LED1 0x52
308 #define RT2860_MCU_CMD_LED2 0x53
309 #define RT2860_MCU_CMD_LED3 0x54
310 #define RT2860_MCU_CMD_RFRESET 0x72
311 #define RT2860_MCU_CMD_ANTSEL 0x73
312 #define RT2860_MCU_CMD_BBP 0x80
313 #define RT2860_MCU_CMD_PSLEVEL 0x83
315 /* possible flags for register PBF_CFG */
316 #define RT2860_TX1Q_NUM_SHIFT 21
317 #define RT2860_TX2Q_NUM_SHIFT 16
318 #define RT2860_NULL0_MODE (1 << 15)
319 #define RT2860_NULL1_MODE (1 << 14)
320 #define RT2860_RX_DROP_MODE (1 << 13)
321 #define RT2860_TX0Q_MANUAL (1 << 12)
322 #define RT2860_TX1Q_MANUAL (1 << 11)
323 #define RT2860_TX2Q_MANUAL (1 << 10)
324 #define RT2860_RX0Q_MANUAL (1 << 9)
325 #define RT2860_HCCA_EN (1 << 8)
326 #define RT2860_TX0Q_EN (1 << 4)
327 #define RT2860_TX1Q_EN (1 << 3)
328 #define RT2860_TX2Q_EN (1 << 2)
329 #define RT2860_RX0Q_EN (1 << 1)
331 /* possible flags for register BUF_CTRL */
332 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid)))
333 #define RT2860_NULL0_KICK (1 << 7)
334 #define RT2860_NULL1_KICK (1 << 6)
335 #define RT2860_BUF_RESET (1 << 5)
336 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid))
337 #define RT2860_READ_RX0Q (1 << 0)
339 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */
340 #define RT2860_MCU_MAC_INT_8 (1 << 24)
341 #define RT2860_MCU_MAC_INT_7 (1 << 23)
342 #define RT2860_MCU_MAC_INT_6 (1 << 22)
343 #define RT2860_MCU_MAC_INT_4 (1 << 20)
344 #define RT2860_MCU_MAC_INT_3 (1 << 19)
345 #define RT2860_MCU_MAC_INT_2 (1 << 18)
346 #define RT2860_MCU_MAC_INT_1 (1 << 17)
347 #define RT2860_MCU_MAC_INT_0 (1 << 16)
348 #define RT2860_DTX0_INT (1 << 11)
349 #define RT2860_DTX1_INT (1 << 10)
350 #define RT2860_DTX2_INT (1 << 9)
351 #define RT2860_DRX0_INT (1 << 8)
352 #define RT2860_HCMD_INT (1 << 7)
353 #define RT2860_N0TX_INT (1 << 6)
354 #define RT2860_N1TX_INT (1 << 5)
355 #define RT2860_BCNTX_INT (1 << 4)
356 #define RT2860_MTX0_INT (1 << 3)
357 #define RT2860_MTX1_INT (1 << 2)
358 #define RT2860_MTX2_INT (1 << 1)
359 #define RT2860_MRX0_INT (1 << 0)
361 /* possible flags for register TXRXQ_PCNT */
362 #define RT2860_RX0Q_PCNT_MASK 0xff000000
363 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000
364 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00
365 #define RT2860_TX0Q_PCNT_MASK 0x000000ff
367 /* possible flags for register CAP_CTRL */
368 #define RT2860_CAP_ADC_FEQ (1U << 31)
369 #define RT2860_CAP_START (1 << 30)
370 #define RT2860_MAN_TRIG (1 << 29)
371 #define RT2860_TRIG_OFFSET_SHIFT 16
372 #define RT2860_START_ADDR_SHIFT 0
374 /* possible flags for register RF_CSR_CFG */
375 #define RT3070_RF_KICK (1 << 17)
376 #define RT3070_RF_WRITE (1 << 16)
378 /* possible flags for register EFUSE_CTRL */
379 #define RT3070_SEL_EFUSE (1U << 31)
380 #define RT3070_EFSROM_KICK (1 << 30)
381 #define RT3070_EFSROM_AIN_MASK 0x03ff0000
382 #define RT3070_EFSROM_AIN_SHIFT 16
383 #define RT3070_EFSROM_MODE_MASK 0x000000c0
384 #define RT3070_EFUSE_AOUT_MASK 0x0000003f
386 /* possible flag for register DEBUG_INDEX */
387 #define RT5592_SEL_XTAL (1U << 31)
389 /* possible flags for register MAC_SYS_CTRL */
390 #define RT2860_RX_TS_EN (1 << 7)
391 #define RT2860_WLAN_HALT_EN (1 << 6)
392 #define RT2860_PBF_LOOP_EN (1 << 5)
393 #define RT2860_CONT_TX_TEST (1 << 4)
394 #define RT2860_MAC_RX_EN (1 << 3)
395 #define RT2860_MAC_TX_EN (1 << 2)
396 #define RT2860_BBP_HRST (1 << 1)
397 #define RT2860_MAC_SRST (1 << 0)
399 /* possible flags for register MAC_BSSID_DW1 */
400 #define RT2860_MULTI_BCN_NUM_SHIFT 18
401 #define RT2860_MULTI_BSSID_MODE_SHIFT 16
403 /* possible flags for register MAX_LEN_CFG */
404 #define RT2860_MIN_MPDU_LEN_SHIFT 16
405 #define RT2860_MAX_PSDU_LEN_SHIFT 12
406 #define RT2860_MAX_PSDU_LEN8K 0
407 #define RT2860_MAX_PSDU_LEN16K 1
408 #define RT2860_MAX_PSDU_LEN32K 2
409 #define RT2860_MAX_PSDU_LEN64K 3
410 #define RT2860_MAX_MPDU_LEN_SHIFT 0
412 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */
413 #define RT2860_BBP_RW_PARALLEL (1 << 19)
414 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18)
415 #define RT2860_BBP_CSR_KICK (1 << 17)
416 #define RT2860_BBP_CSR_READ (1 << 16)
417 #define RT2860_BBP_ADDR_SHIFT 8
418 #define RT2860_BBP_DATA_SHIFT 0
420 /* possible flags for register RF_CSR_CFG0 */
421 #define RT2860_RF_REG_CTRL (1U << 31)
422 #define RT2860_RF_LE_SEL1 (1 << 30)
423 #define RT2860_RF_LE_STBY (1 << 29)
424 #define RT2860_RF_REG_WIDTH_SHIFT 24
425 #define RT2860_RF_REG_0_SHIFT 0
427 /* possible flags for register RF_CSR_CFG1 */
428 #define RT2860_RF_DUR_5 (1 << 24)
429 #define RT2860_RF_REG_1_SHIFT 0
431 /* possible flags for register LED_CFG */
432 #define RT2860_LED_POL (1 << 30)
433 #define RT2860_Y_LED_MODE_SHIFT 28
434 #define RT2860_G_LED_MODE_SHIFT 26
435 #define RT2860_R_LED_MODE_SHIFT 24
436 #define RT2860_LED_MODE_OFF 0
437 #define RT2860_LED_MODE_BLINK_TX 1
438 #define RT2860_LED_MODE_SLOW_BLINK 2
439 #define RT2860_LED_MODE_ON 3
440 #define RT2860_SLOW_BLK_TIME_SHIFT 16
441 #define RT2860_LED_OFF_TIME_SHIFT 8
442 #define RT2860_LED_ON_TIME_SHIFT 0
444 /* possible flags for register XIFS_TIME_CFG */
445 #define RT2860_BB_RXEND_EN (1 << 29)
446 #define RT2860_EIFS_TIME_SHIFT 20
447 #define RT2860_OFDM_XIFS_TIME_SHIFT 16
448 #define RT2860_OFDM_SIFS_TIME_SHIFT 8
449 #define RT2860_CCK_SIFS_TIME_SHIFT 0
451 /* possible flags for register BKOFF_SLOT_CFG */
452 #define RT2860_CC_DELAY_TIME_SHIFT 8
453 #define RT2860_SLOT_TIME 0
455 /* possible flags for register NAV_TIME_CFG */
456 #define RT2860_NAV_UPD (1U << 31)
457 #define RT2860_NAV_UPD_VAL_SHIFT 16
458 #define RT2860_NAV_CLR_EN (1 << 15)
459 #define RT2860_NAV_TIMER_SHIFT 0
461 /* possible flags for register CH_TIME_CFG */
462 #define RT2860_EIFS_AS_CH_BUSY (1 << 4)
463 #define RT2860_NAV_AS_CH_BUSY (1 << 3)
464 #define RT2860_RX_AS_CH_BUSY (1 << 2)
465 #define RT2860_TX_AS_CH_BUSY (1 << 1)
466 #define RT2860_CH_STA_TIMER_EN (1 << 0)
468 /* possible values for register BCN_TIME_CFG */
469 #define RT2860_TSF_INS_COMP_SHIFT 24
470 #define RT2860_BCN_TX_EN (1 << 20)
471 #define RT2860_TBTT_TIMER_EN (1 << 19)
472 #define RT2860_TSF_SYNC_MODE_SHIFT 17
473 #define RT2860_TSF_SYNC_MODE_DIS 0
474 #define RT2860_TSF_SYNC_MODE_STA 1
475 #define RT2860_TSF_SYNC_MODE_IBSS 2
476 #define RT2860_TSF_SYNC_MODE_HOSTAP 3
477 #define RT2860_TSF_TIMER_EN (1 << 16)
478 #define RT2860_BCN_INTVAL_SHIFT 0
480 /* possible flags for register TBTT_SYNC_CFG */
481 #define RT2860_BCN_CWMIN_SHIFT 20
482 #define RT2860_BCN_AIFSN_SHIFT 16
483 #define RT2860_BCN_EXP_WIN_SHIFT 8
484 #define RT2860_TBTT_ADJUST_SHIFT 0
486 /* possible flags for register INT_TIMER_CFG */
487 #define RT2860_GP_TIMER_SHIFT 16
488 #define RT2860_PRE_TBTT_TIMER_SHIFT 0
490 /* possible flags for register INT_TIMER_EN */
491 #define RT2860_GP_TIMER_EN (1 << 1)
492 #define RT2860_PRE_TBTT_INT_EN (1 << 0)
494 /* possible flags for register MAC_STATUS_REG */
495 #define RT2860_RX_STATUS_BUSY (1 << 1)
496 #define RT2860_TX_STATUS_BUSY (1 << 0)
498 /* possible flags for register PWR_PIN_CFG */
499 #define RT2860_IO_ADDA_PD (1 << 3)
500 #define RT2860_IO_PLL_PD (1 << 2)
501 #define RT2860_IO_RA_PE (1 << 1)
502 #define RT2860_IO_RF_PE (1 << 0)
504 /* possible flags for register AUTO_WAKEUP_CFG */
505 #define RT2860_AUTO_WAKEUP_EN (1 << 15)
506 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8
507 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0
509 /* possible flags for register TX_PIN_CFG */
510 #define RT2860_TRSW_POL (1 << 19)
511 #define RT2860_TRSW_EN (1 << 18)
512 #define RT2860_RFTR_POL (1 << 17)
513 #define RT2860_RFTR_EN (1 << 16)
514 #define RT2860_LNA_PE_G1_POL (1 << 15)
515 #define RT2860_LNA_PE_A1_POL (1 << 14)
516 #define RT2860_LNA_PE_G0_POL (1 << 13)
517 #define RT2860_LNA_PE_A0_POL (1 << 12)
518 #define RT2860_LNA_PE_G1_EN (1 << 11)
519 #define RT2860_LNA_PE_A1_EN (1 << 10)
520 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN)
521 #define RT2860_LNA_PE_G0_EN (1 << 9)
522 #define RT2860_LNA_PE_A0_EN (1 << 8)
523 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN)
524 #define RT2860_PA_PE_G1_POL (1 << 7)
525 #define RT2860_PA_PE_A1_POL (1 << 6)
526 #define RT2860_PA_PE_G0_POL (1 << 5)
527 #define RT2860_PA_PE_A0_POL (1 << 4)
528 #define RT2860_PA_PE_G1_EN (1 << 3)
529 #define RT2860_PA_PE_A1_EN (1 << 2)
530 #define RT2860_PA_PE_G0_EN (1 << 1)
531 #define RT2860_PA_PE_A0_EN (1 << 0)
533 /* possible flags for register TX_BAND_CFG */
534 #define RT2860_5G_BAND_SEL_N (1 << 2)
535 #define RT2860_5G_BAND_SEL_P (1 << 1)
536 #define RT2860_TX_BAND_SEL (1 << 0)
538 /* possible flags for register TX_SW_CFG0 */
539 #define RT2860_DLY_RFTR_EN_SHIFT 24
540 #define RT2860_DLY_TRSW_EN_SHIFT 16
541 #define RT2860_DLY_PAPE_EN_SHIFT 8
542 #define RT2860_DLY_TXPE_EN_SHIFT 0
544 /* possible flags for register TX_SW_CFG1 */
545 #define RT2860_DLY_RFTR_DIS_SHIFT 16
546 #define RT2860_DLY_TRSW_DIS_SHIFT 8
547 #define RT2860_DLY_PAPE_DIS SHIFT 0
549 /* possible flags for register TX_SW_CFG2 */
550 #define RT2860_DLY_LNA_EN_SHIFT 24
551 #define RT2860_DLY_LNA_DIS_SHIFT 16
552 #define RT2860_DLY_DAC_EN_SHIFT 8
553 #define RT2860_DLY_DAC_DIS_SHIFT 0
555 /* possible flags for register TXOP_THRES_CFG */
556 #define RT2860_TXOP_REM_THRES_SHIFT 24
557 #define RT2860_CF_END_THRES_SHIFT 16
558 #define RT2860_RDG_IN_THRES 8
559 #define RT2860_RDG_OUT_THRES 0
561 /* possible flags for register TXOP_CTRL_CFG */
562 #define RT2860_EXT_CW_MIN_SHIFT 16
563 #define RT2860_EXT_CCA_DLY_SHIFT 8
564 #define RT2860_EXT_CCA_EN (1 << 7)
565 #define RT2860_LSIG_TXOP_EN (1 << 6)
566 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4)
567 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3)
568 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2)
569 #define RT2860_TXOP_TRUN_EN_AC (1 << 1)
570 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0)
572 /* possible flags for register TX_RTS_CFG */
573 #define RT2860_RTS_FBK_EN (1 << 24)
574 #define RT2860_RTS_THRES_SHIFT 8
575 #define RT2860_RTS_RTY_LIMIT_SHIFT 0
577 /* possible flags for register TX_TIMEOUT_CFG */
578 #define RT2860_TXOP_TIMEOUT_SHIFT 16
579 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8
580 #define RT2860_MPDU_LIFE_TIME_SHIFT 4
582 /* possible flags for register TX_RTY_CFG */
583 #define RT2860_TX_AUTOFB_EN (1 << 30)
584 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29)
585 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28)
586 #define RT2860_LONG_RTY_THRES_SHIFT 16
587 #define RT2860_LONG_RTY_LIMIT_SHIFT 8
588 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0
590 /* possible flags for register TX_LINK_CFG */
591 #define RT2860_REMOTE_MFS_SHIFT 24
592 #define RT2860_REMOTE_MFB_SHIFT 16
593 #define RT2860_TX_CFACK_EN (1 << 12)
594 #define RT2860_TX_RDG_EN (1 << 11)
595 #define RT2860_TX_MRQ_EN (1 << 10)
596 #define RT2860_REMOTE_UMFS_EN (1 << 9)
597 #define RT2860_TX_MFB_EN (1 << 8)
598 #define RT2860_REMOTE_MFB_LT_SHIFT 0
600 /* possible flags for registers *_PROT_CFG */
601 #define RT2860_RTSTH_EN (1 << 26)
602 #define RT2860_TXOP_ALLOW_GF40 (1 << 25)
603 #define RT2860_TXOP_ALLOW_GF20 (1 << 24)
604 #define RT2860_TXOP_ALLOW_MM40 (1 << 23)
605 #define RT2860_TXOP_ALLOW_MM20 (1 << 22)
606 #define RT2860_TXOP_ALLOW_OFDM (1 << 21)
607 #define RT2860_TXOP_ALLOW_CCK (1 << 20)
608 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20)
609 #define RT2860_PROT_NAV_SHORT (1 << 18)
610 #define RT2860_PROT_NAV_LONG (2 << 18)
611 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16)
612 #define RT2860_PROT_CTRL_CTS (2 << 16)
614 /* possible flags for registers EXP_{CTS,ACK}_TIME */
615 #define RT2860_EXP_OFDM_TIME_SHIFT 16
616 #define RT2860_EXP_CCK_TIME_SHIFT 0
618 /* possible flags for register RX_FILTR_CFG */
619 #define RT2860_DROP_CTRL_RSV (1 << 16)
620 #define RT2860_DROP_BAR (1 << 15)
621 #define RT2860_DROP_BA (1 << 14)
622 #define RT2860_DROP_PSPOLL (1 << 13)
623 #define RT2860_DROP_RTS (1 << 12)
624 #define RT2860_DROP_CTS (1 << 11)
625 #define RT2860_DROP_ACK (1 << 10)
626 #define RT2860_DROP_CFEND (1 << 9)
627 #define RT2860_DROP_CFACK (1 << 8)
628 #define RT2860_DROP_DUPL (1 << 7)
629 #define RT2860_DROP_BC (1 << 6)
630 #define RT2860_DROP_MC (1 << 5)
631 #define RT2860_DROP_VER_ERR (1 << 4)
632 #define RT2860_DROP_NOT_MYBSS (1 << 3)
633 #define RT2860_DROP_UC_NOME (1 << 2)
634 #define RT2860_DROP_PHY_ERR (1 << 1)
635 #define RT2860_DROP_CRC_ERR (1 << 0)
637 /* possible flags for register AUTO_RSP_CFG */
638 #define RT2860_CTRL_PWR_BIT (1 << 7)
639 #define RT2860_BAC_ACK_POLICY (1 << 6)
640 #define RT2860_CCK_SHORT_EN (1 << 4)
641 #define RT2860_CTS_40M_REF_EN (1 << 3)
642 #define RT2860_CTS_40M_MODE_EN (1 << 2)
643 #define RT2860_BAC_ACKPOLICY_EN (1 << 1)
644 #define RT2860_AUTO_RSP_EN (1 << 0)
646 /* possible flags for register SIFS_COST_CFG */
647 #define RT2860_OFDM_SIFS_COST_SHIFT 8
648 #define RT2860_CCK_SIFS_COST_SHIFT 0
650 /* possible flags for register TXOP_HLDR_ET */
651 #define RT2860_TXOP_ETM1_EN (1 << 25)
652 #define RT2860_TXOP_ETM0_EN (1 << 24)
653 #define RT2860_TXOP_ETM_THRES_SHIFT 16
654 #define RT2860_TXOP_ETO_EN (1 << 8)
655 #define RT2860_TXOP_ETO_THRES_SHIFT 1
656 #define RT2860_PER_RX_RST_EN (1 << 0)
658 /* possible flags for register TX_STAT_FIFO */
659 #define RT2860_TXQ_MCS_SHIFT 16
660 #define RT2860_TXQ_WCID_SHIFT 8
661 #define RT2860_TXQ_ACKREQ (1 << 7)
662 #define RT2860_TXQ_AGG (1 << 6)
663 #define RT2860_TXQ_OK (1 << 5)
664 #define RT2860_TXQ_PID_SHIFT 1
665 #define RT2860_TXQ_VLD (1 << 0)
667 /* possible flags for register WCID_ATTR */
668 #define RT2860_MODE_NOSEC 0
669 #define RT2860_MODE_WEP40 1
670 #define RT2860_MODE_WEP104 2
671 #define RT2860_MODE_TKIP 3
672 #define RT2860_MODE_AES_CCMP 4
673 #define RT2860_MODE_CKIP40 5
674 #define RT2860_MODE_CKIP104 6
675 #define RT2860_MODE_CKIP128 7
676 #define RT2860_RX_PKEY_EN (1 << 0)
678 /* possible flags for register H2M_MAILBOX */
679 #define RT2860_H2M_BUSY (1 << 24)
680 #define RT2860_TOKEN_NO_INTR 0xff
682 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */
683 #define RT2860_LED_RADIO (1 << 13)
684 #define RT2860_LED_LINK_2GHZ (1 << 14)
685 #define RT2860_LED_LINK_5GHZ (1 << 15)
687 /* possible flags for RT3020 RF register 1 */
688 #define RT3070_RF_BLOCK (1 << 0)
689 #define RT3070_PLL_PD (1 << 1)
690 #define RT3070_RX0_PD (1 << 2)
691 #define RT3070_TX0_PD (1 << 3)
692 #define RT3070_RX1_PD (1 << 4)
693 #define RT3070_TX1_PD (1 << 5)
694 #define RT3070_RX2_PD (1 << 6)
695 #define RT3070_TX2_PD (1 << 7)
697 /* possible flags for RT3020 RF register 15 */
698 #define RT3070_TX_LO2 (1 << 3)
700 /* possible flags for RT3020 RF register 17 */
701 #define RT3070_TX_LO1 (1 << 3)
703 /* possible flags for RT3020 RF register 20 */
704 #define RT3070_RX_LO1 (1 << 3)
706 /* possible flags for RT3020 RF register 21 */
707 #define RT3070_RX_LO2 (1 << 3)
709 /* possible flags for RT3053 RF register 18 */
710 #define RT3593_AUTOTUNE_BYPASS (1 << 6)
712 /* possible flags for RT3053 RF register 50 */
713 #define RT3593_TX_LO2 (1 << 4)
715 /* possible flags for RT3053 RF register 51 */
716 #define RT3593_TX_LO1 (1 << 4)
718 /* Possible flags for RT5390 RF register 2. */
719 #define RT5390_RESCAL (1 << 7)
721 /* Possible flags for RT5390 RF register 3. */
722 #define RT5390_VCOCAL (1 << 7)
724 /* Possible flags for RT5390 RF register 38. */
725 #define RT5390_RX_LO1 (1 << 5)
727 /* Possible flags for RT5390 RF register 39. */
728 #define RT5390_RX_LO2 (1 << 7)
730 /* Possible flags for RT5390 BBP register 4. */
731 #define RT5390_MAC_IF_CTRL (1 << 6)
733 /* Possible flags for RT5390 BBP register 105. */
734 #define RT5390_MLD (1 << 2)
735 #define RT5390_EN_SIG_MODULATION (1 << 3)
737 /* RT2860 TX descriptor */
739 uint32_t sdp0; /* Segment Data Pointer 0 */
740 uint16_t sdl1; /* Segment Data Length 1 */
741 #define RT2860_TX_BURST (1 << 15)
742 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */
744 uint16_t sdl0; /* Segment Data Length 0 */
745 #define RT2860_TX_DDONE (1 << 15)
746 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */
748 uint32_t sdp1; /* Segment Data Pointer 1 */
751 #define RT2860_TX_QSEL_SHIFT 1
752 #define RT2860_TX_QSEL_MGMT (0 << 1)
753 #define RT2860_TX_QSEL_HCCA (1 << 1)
754 #define RT2860_TX_QSEL_EDCA (2 << 1)
755 #define RT2860_TX_WIV (1 << 0)
758 /* RT2870 TX descriptor */
765 /* TX Wireless Information */
768 #define RT2860_TX_MPDU_DSITY_SHIFT 5
769 #define RT2860_TX_AMPDU (1 << 4)
770 #define RT2860_TX_TS (1 << 3)
771 #define RT2860_TX_CFACK (1 << 2)
772 #define RT2860_TX_MMPS (1 << 1)
773 #define RT2860_TX_FRAG (1 << 0)
776 #define RT2860_TX_TXOP_HT 0
777 #define RT2860_TX_TXOP_PIFS 1
778 #define RT2860_TX_TXOP_SIFS 2
779 #define RT2860_TX_TXOP_BACKOFF 3
782 #define RT2860_PHY_MODE 0xc000
783 #define RT2860_PHY_CCK (0 << 14)
784 #define RT2860_PHY_OFDM (1 << 14)
785 #define RT2860_PHY_HT (2 << 14)
786 #define RT2860_PHY_HT_GF (3 << 14)
787 #define RT2860_PHY_SGI (1 << 8)
788 #define RT2860_PHY_BW40 (1 << 7)
789 #define RT2860_PHY_MCS 0x7f
790 #define RT2860_PHY_SHPRE (1 << 3)
793 #define RT2860_TX_BAWINSIZE_SHIFT 2
794 #define RT2860_TX_NSEQ (1 << 1)
795 #define RT2860_TX_ACK (1 << 0)
797 uint8_t wcid; /* Wireless Client ID */
799 #define RT2860_TX_PID_SHIFT 12
805 /* RT2860 RX descriptor */
808 uint16_t sdl1; /* unused */
810 #define RT2860_RX_DDONE (1 << 15)
811 #define RT2860_RX_LS0 (1 << 14)
813 uint32_t sdp1; /* unused */
815 #define RT2860_RX_DEC (1 << 16)
816 #define RT2860_RX_AMPDU (1 << 15)
817 #define RT2860_RX_L2PAD (1 << 14)
818 #define RT2860_RX_RSSI (1 << 13)
819 #define RT2860_RX_HTC (1 << 12)
820 #define RT2860_RX_AMSDU (1 << 11)
821 #define RT2860_RX_MICERR (1 << 10)
822 #define RT2860_RX_ICVERR (1 << 9)
823 #define RT2860_RX_CRCERR (1 << 8)
824 #define RT2860_RX_MYBSS (1 << 7)
825 #define RT2860_RX_BC (1 << 6)
826 #define RT2860_RX_MC (1 << 5)
827 #define RT2860_RX_UC2ME (1 << 4)
828 #define RT2860_RX_FRAG (1 << 3)
829 #define RT2860_RX_NULL (1 << 2)
830 #define RT2860_RX_DATA (1 << 1)
831 #define RT2860_RX_BA (1 << 0)
834 /* RT2870 RX descriptor */
836 /* single 32-bit field */
840 /* RX Wireless Information */
844 #define RT2860_RX_UDF_SHIFT 5
845 #define RT2860_RX_BSS_IDX_SHIFT 2
848 #define RT2860_RX_TID_SHIFT 12
858 #define RT2860_RF_2820 0x0001 /* 2T3R */
859 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */
860 #define RT2860_RF_2720 0x0003 /* 1T2R */
861 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */
862 #define RT3070_RF_3020 0x0005 /* 1T1R */
863 #define RT3070_RF_2020 0x0006 /* b/g */
864 #define RT3070_RF_3021 0x0007 /* 1T2R */
865 #define RT3070_RF_3022 0x0008 /* 2T2R */
866 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */
867 #define RT3593_RF_3053 0x000d /* dual-band 3T3R */
868 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */
869 #define RT5390_RF_5370 0x5370 /* 1T1R */
870 #define RT5390_RF_5372 0x5372 /* 2T2R */
872 /* USB commands for RT2870 only */
873 #define RT2870_RESET 1
874 #define RT2870_WRITE_2 2
875 #define RT2870_WRITE_REGION_1 6
876 #define RT2870_READ_REGION_1 7
877 #define RT2870_EEPROM_READ 9
879 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
881 #define RT2860_EEPROM_VERSION 0x01
882 #define RT2860_EEPROM_MAC01 0x02
883 #define RT2860_EEPROM_MAC23 0x03
884 #define RT2860_EEPROM_MAC45 0x04
885 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11
886 #define RT2860_EEPROM_REV 0x12
887 #define RT2860_EEPROM_ANTENNA 0x1a
888 #define RT2860_EEPROM_CONFIG 0x1b
889 #define RT2860_EEPROM_COUNTRY 0x1c
890 #define RT2860_EEPROM_FREQ_LEDS 0x1d
891 #define RT2860_EEPROM_LED1 0x1e
892 #define RT2860_EEPROM_LED2 0x1f
893 #define RT2860_EEPROM_LED3 0x20
894 #define RT2860_EEPROM_LNA 0x22
895 #define RT2860_EEPROM_RSSI1_2GHZ 0x23
896 #define RT2860_EEPROM_RSSI2_2GHZ 0x24
897 #define RT2860_EEPROM_RSSI1_5GHZ 0x25
898 #define RT2860_EEPROM_RSSI2_5GHZ 0x26
899 #define RT2860_EEPROM_DELTAPWR 0x28
900 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29
901 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30
902 #define RT2860_EEPROM_TSSI1_2GHZ 0x37
903 #define RT2860_EEPROM_TSSI2_2GHZ 0x38
904 #define RT2860_EEPROM_TSSI3_2GHZ 0x39
905 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a
906 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b
907 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c
908 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53
909 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a
910 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b
911 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c
912 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d
913 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e
914 #define RT2860_EEPROM_RPWR 0x6f
915 #define RT2860_EEPROM_BBP_BASE 0x78
916 #define RT3071_EEPROM_RF_BASE 0x82
918 /* EEPROM registers for RT3593. */
919 #define RT3593_EEPROM_FREQ_LEDS 0x21
920 #define RT3593_EEPROM_FREQ 0x22
921 #define RT3593_EEPROM_LED1 0x22
922 #define RT3593_EEPROM_LED2 0x23
923 #define RT3593_EEPROM_LED3 0x24
924 #define RT3593_EEPROM_LNA 0x26
925 #define RT3593_EEPROM_LNA_5GHZ 0x27
926 #define RT3593_EEPROM_RSSI1_2GHZ 0x28
927 #define RT3593_EEPROM_RSSI2_2GHZ 0x29
928 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a
929 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b
930 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30
931 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37
932 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e
933 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b
934 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65
935 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f
938 * EEPROM IQ calibration.
940 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130
941 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131
942 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133
943 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134
944 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c
945 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d
946 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144
947 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145
948 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146
949 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147
950 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148
951 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149
952 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a
953 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b
954 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c
955 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d
956 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e
957 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f
959 #define RT2860_RIDX_CCK1 0
960 #define RT2860_RIDX_CCK11 3
961 #define RT2860_RIDX_OFDM6 4
962 #define RT2860_RIDX_MAX 12
965 * Control and status registers access macros.
967 #define RAL_READ(sc, reg) \
968 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
970 #define RAL_WRITE(sc, reg, val) \
971 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
973 #define RAL_BARRIER_WRITE(sc) \
974 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \
975 BUS_SPACE_BARRIER_WRITE)
977 #define RAL_BARRIER_READ_WRITE(sc) \
978 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \
979 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
981 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \
982 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \
985 #define RAL_SET_REGION_4(sc, offset, val, count) \
986 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
990 * EEPROM access macro.
992 #define RT2860_EEPROM_CTL(sc, val) do { \
993 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \
994 RAL_BARRIER_READ_WRITE((sc)); \
995 DELAY(RT2860_EEPROM_DELAY); \
996 } while (/* CONSTCOND */0)
999 * Default values for MAC registers; values taken from the reference driver.
1001 #define RT2870_DEF_MAC \
1002 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
1003 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \
1004 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
1005 { RT2860_HT_BASIC_RATE, 0x00008003 }, \
1006 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
1007 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
1008 { RT2860_TX_SW_CFG0, 0x00000000 }, \
1009 { RT2860_TX_SW_CFG1, 0x00080606 }, \
1010 { RT2860_TX_LINK_CFG, 0x00001020 }, \
1011 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
1012 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \
1013 { RT2860_LED_CFG, 0x7f031e46 }, \
1014 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
1015 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
1016 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
1017 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
1018 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
1019 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
1020 { RT2860_CCK_PROT_CFG, 0x05740003 }, \
1021 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
1022 { RT2860_PBF_CFG, 0x00f40006 }, \
1023 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \
1024 { RT2860_GF20_PROT_CFG, 0x01744004 }, \
1025 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
1026 { RT2860_MM20_PROT_CFG, 0x01744004 }, \
1027 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \
1028 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
1029 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
1030 { RT2860_TX_RTS_CFG, 0x00092b20 }, \
1031 { RT2860_EXP_ACK_TIME, 0x002400ca }, \
1032 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
1033 { RT2860_PWR_PIN_CFG, 0x00000003 }
1036 * Default values for BBP registers; values taken from the reference driver.
1038 #define RT2860_DEF_BBP \
1056 #define RT5390_DEF_BBP \
1080 #define RT5592_DEF_BBP \
1113 * Default settings for RF registers; values derived from the reference driver.
1115 #define RT2860_RF2850 \
1116 { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \
1117 { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \
1118 { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \
1119 { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, \
1120 { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, \
1121 { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, \
1122 { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, \
1123 { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, \
1124 { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, \
1125 { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, \
1126 { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, \
1127 { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, \
1128 { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, \
1129 { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, \
1130 { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, \
1131 { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, \
1132 { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, \
1133 { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, \
1134 { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, \
1135 { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, \
1136 { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, \
1137 { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, \
1138 { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, \
1139 { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, \
1140 { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, \
1141 { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, \
1142 { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, \
1143 { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, \
1144 { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, \
1145 { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, \
1146 { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, \
1147 { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, \
1148 { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, \
1149 { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, \
1150 { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, \
1151 { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, \
1152 { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, \
1153 { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, \
1154 { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, \
1155 { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, \
1156 { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, \
1157 { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, \
1158 { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, \
1159 { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, \
1160 { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, \
1161 { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, \
1162 { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, \
1163 { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, \
1164 { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, \
1165 { 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f }, \
1166 { 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 }, \
1167 { 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 }, \
1168 { 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f }, \
1169 { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, \
1170 { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, \
1171 { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, \
1172 { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, \
1173 { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, \
1174 { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \
1175 { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 }
1177 #define RT3070_RF3052 \
1232 #define RT5592_RF5592_20MHZ \
1233 { 0x1e2, 4, 10, 3 }, \
1234 { 0x1e3, 4, 10, 3 }, \
1235 { 0x1e4, 4, 10, 3 }, \
1236 { 0x1e5, 4, 10, 3 }, \
1237 { 0x1e6, 4, 10, 3 }, \
1238 { 0x1e7, 4, 10, 3 }, \
1239 { 0x1e8, 4, 10, 3 }, \
1240 { 0x1e9, 4, 10, 3 }, \
1241 { 0x1ea, 4, 10, 3 }, \
1242 { 0x1eb, 4, 10, 3 }, \
1243 { 0x1ec, 4, 10, 3 }, \
1244 { 0x1ed, 4, 10, 3 }, \
1245 { 0x1ee, 4, 10, 3 }, \
1246 { 0x1f0, 8, 10, 3 }, \
1247 { 0xac, 8, 12, 1 }, \
1248 { 0xad, 0, 12, 1 }, \
1249 { 0xad, 4, 12, 1 }, \
1250 { 0xae, 0, 12, 1 }, \
1251 { 0xae, 4, 12, 1 }, \
1252 { 0xae, 8, 12, 1 }, \
1253 { 0xaf, 4, 12, 1 }, \
1254 { 0xaf, 8, 12, 1 }, \
1255 { 0xb0, 0, 12, 1 }, \
1256 { 0xb0, 8, 12, 1 }, \
1257 { 0xb1, 0, 12, 1 }, \
1258 { 0xb1, 4, 12, 1 }, \
1259 { 0xb7, 4, 12, 1 }, \
1260 { 0xb7, 8, 12, 1 }, \
1261 { 0xb8, 0, 12, 1 }, \
1262 { 0xb8, 8, 12, 1 }, \
1263 { 0xb9, 0, 12, 1 }, \
1264 { 0xb9, 4, 12, 1 }, \
1265 { 0xba, 0, 12, 1 }, \
1266 { 0xba, 4, 12, 1 }, \
1267 { 0xba, 8, 12, 1 }, \
1268 { 0xbb, 4, 12, 1 }, \
1269 { 0xbb, 8, 12, 1 }, \
1270 { 0xbc, 0, 12, 1 }, \
1271 { 0xbc, 8, 12, 1 }, \
1272 { 0xbd, 0, 12, 1 }, \
1273 { 0xbd, 4, 12, 1 }, \
1274 { 0xbe, 0, 12, 1 }, \
1275 { 0xbf, 6, 12, 1 }, \
1276 { 0xbf, 10, 12, 1 }, \
1277 { 0xc0, 2, 12, 1 }, \
1278 { 0xc0, 10, 12, 1 }, \
1279 { 0xc1, 2, 12, 1 }, \
1280 { 0xc1, 6, 12, 1 }, \
1281 { 0xc2, 2, 12, 1 }, \
1282 { 0xa4, 0, 12, 1 }, \
1283 { 0xa4, 4, 12, 1 }, \
1284 { 0xa5, 8, 12, 1 }, \
1287 #define RT5592_RF5592_40MHZ \
1288 { 0xf1, 2, 10, 3 }, \
1289 { 0xf1, 7, 10, 3 }, \
1290 { 0xf2, 2, 10, 3 }, \
1291 { 0xf2, 7, 10, 3 }, \
1292 { 0xf3, 2, 10, 3 }, \
1293 { 0xf3, 7, 10, 3 }, \
1294 { 0xf4, 2, 10, 3 }, \
1295 { 0xf4, 7, 10, 3 }, \
1296 { 0xf5, 2, 10, 3 }, \
1297 { 0xf5, 7, 10, 3 }, \
1298 { 0xf6, 2, 10, 3 }, \
1299 { 0xf6, 7, 10, 3 }, \
1300 { 0xf7, 2, 10, 3 }, \
1301 { 0xf8, 4, 10, 3 }, \
1302 { 0x56, 4, 12, 1 }, \
1303 { 0x56, 6, 12, 1 }, \
1304 { 0x56, 8, 12, 1 }, \
1305 { 0x57, 0, 12, 1 }, \
1306 { 0x57, 2, 12, 1 }, \
1307 { 0x57, 4, 12, 1 }, \
1308 { 0x57, 8, 12, 1 }, \
1309 { 0x57, 10, 12, 1 }, \
1310 { 0x58, 0, 12, 1 }, \
1311 { 0x58, 4, 12, 1 }, \
1312 { 0x58, 6, 12, 1 }, \
1313 { 0x58, 8, 12, 1 }, \
1314 { 0x5b, 8, 12, 1 }, \
1315 { 0x5b, 10, 12, 1 }, \
1316 { 0x5c, 0, 12, 1 }, \
1317 { 0x5c, 4, 12, 1 }, \
1318 { 0x5c, 6, 12, 1 }, \
1319 { 0x5c, 8, 12, 1 }, \
1320 { 0x5d, 0, 12, 1 }, \
1321 { 0x5d, 2, 12, 1 }, \
1322 { 0x5d, 4, 12, 1 }, \
1323 { 0x5d, 8, 12, 1 }, \
1324 { 0x5d, 10, 12, 1 }, \
1325 { 0x5e, 0, 12, 1 }, \
1326 { 0x5e, 4, 12, 1 }, \
1327 { 0x5e, 6, 12, 1 }, \
1328 { 0x5e, 8, 12, 1 }, \
1329 { 0x5f, 0, 12, 1 }, \
1330 { 0x5f, 9, 12, 1 }, \
1331 { 0x5f, 11, 12, 1 }, \
1332 { 0x60, 1, 12, 1 }, \
1333 { 0x60, 5, 12, 1 }, \
1334 { 0x60, 7, 12, 1 }, \
1335 { 0x60, 9, 12, 1 }, \
1336 { 0x61, 1, 12, 1 }, \
1337 { 0x52, 0, 12, 1 }, \
1338 { 0x52, 4, 12, 1 }, \
1339 { 0x52, 8, 12, 1 }, \
1342 #define RT3070_DEF_RF \
1363 #define RT3572_DEF_RF \
1396 #define RT3593_DEF_RF \
1430 #define RT5390_DEF_RF \
1489 #define RT5392_DEF_RF \
1549 #define RT5592_DEF_RF \
1572 #define RT5592_2GHZ_DEF_RF \
1603 #define RT5592_5GHZ_DEF_RF \
1620 #define RT5592_CHAN_5GHZ \
1621 { 36, 64, 12, 0x2e }, \
1622 { 100, 165, 12, 0x0e }, \
1623 { 36, 64, 13, 0x22 }, \
1624 { 100, 165, 13, 0x42 }, \
1625 { 36, 64, 22, 0x60 }, \
1626 { 100, 165, 22, 0x40 }, \
1627 { 36, 64, 23, 0x7f }, \
1628 { 100, 153, 23, 0x3c }, \
1629 { 155, 165, 23, 0x38 }, \
1630 { 36, 50, 24, 0x09 }, \
1631 { 52, 64, 24, 0x07 }, \
1632 { 100, 153, 24, 0x06 }, \
1633 { 155, 165, 24, 0x05 }, \
1634 { 36, 64, 39, 0x1c }, \
1635 { 100, 138, 39, 0x1a }, \
1636 { 140, 165, 39, 0x18 }, \
1637 { 36, 64, 43, 0x5b }, \
1638 { 100, 138, 43, 0x3b }, \
1639 { 140, 165, 43, 0x1b }, \
1640 { 36, 64, 44, 0x40 }, \
1641 { 100, 138, 44, 0x20 }, \
1642 { 140, 165, 44, 0x10 }, \
1643 { 36, 64, 46, 0x00 }, \
1644 { 100, 138, 46, 0x18 }, \
1645 { 140, 165, 46, 0x08 }, \
1646 { 36, 64, 51, 0xfe }, \
1647 { 100, 124, 51, 0xfc }, \
1648 { 126, 165, 51, 0xec }, \
1649 { 36, 64, 52, 0x0c }, \
1650 { 100, 138, 52, 0x06 }, \
1651 { 140, 165, 52, 0x06 }, \
1652 { 36, 64, 54, 0xf8 }, \
1653 { 100, 165, 54, 0xeb }, \
1654 { 36, 50, 55, 0x06 }, \
1655 { 52, 64, 55, 0x04 }, \
1656 { 100, 138, 55, 0x01 }, \
1657 { 140, 165, 55, 0x00 }, \
1658 { 36, 50, 56, 0xd3 }, \
1659 { 52, 128, 56, 0xbb }, \
1660 { 130, 165, 56, 0xab }, \
1661 { 36, 64, 58, 0x15 }, \
1662 { 100, 116, 58, 0x1d }, \
1663 { 118, 165, 58, 0x15 }, \
1664 { 36, 64, 59, 0x7f }, \
1665 { 100, 138, 59, 0x3f }, \
1666 { 140, 165, 59, 0x7c }, \
1667 { 36, 64, 62, 0x15 }, \
1668 { 100, 116, 62, 0x1d }, \
1669 { 118, 165, 62, 0x15 }
1683 #endif /* _IF_RUNREG_H_ */