sys/gnu/dts/arm/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42                 serial0 = &serial_0;
  43                 serial1 = &serial_1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0>;
  54                         clock-frequency = <1000000000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <1>;
  61                         clock-frequency = <1000000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 fixed-rate-clocks {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         xusbxti: clock@0 {
  76                                 compatible = "fixed-clock";
  77                                 #address-cells = <1>;
  78                                 #size-cells = <0>;
  79                                 reg = <0>;
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                                 clock-output-names = "xusbxti";
  83                         };
  84
  85                         xxti: clock@1 {
  86                                 compatible = "fixed-clock";
  87                                 reg = <1>;
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                                 clock-output-names = "xxti";
  91                         };
  92
  93                         xtcxo: clock@2 {
  94                                 compatible = "fixed-clock";
  95                                 reg = <2>;
  96                                 clock-frequency = <0>;
  97                                 #clock-cells = <0>;
  98                                 clock-output-names = "xtcxo";
  99                         };
 100                 };
 101
 102                 sysram@02020000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x02020000 0x40000>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0x02020000 0x40000>;
 108
 109                         smp-sysram@0 {
 110                                 compatible = "samsung,exynos4210-sysram";
 111                                 reg = <0x0 0x1000>;
 112                         };
 113
 114                         smp-sysram@3f000 {
 115                                 compatible = "samsung,exynos4210-sysram-ns";
 116                                 reg = <0x3f000 0x1000>;
 117                         };
 118                 };
 119
 120                 chipid@10000000 {
 121                         compatible = "samsung,exynos4210-chipid";
 122                         reg = <0x10000000 0x100>;
 123                 };
 124
 125                 sys_reg: syscon@10010000 {
 126                         compatible = "samsung,exynos3-sysreg", "syscon";
 127                         reg = <0x10010000 0x400>;
 128                 };
 129
 130                 pmu_system_controller: system-controller@10020000 {
 131                         compatible = "samsung,exynos3250-pmu", "syscon";
 132                         reg = <0x10020000 0x4000>;
 133                 };
 134
 135                 mipi_phy: video-phy@10020710 {
 136                         compatible = "samsung,s5pv210-mipi-video-phy";
 137                         reg = <0x10020710 8>;
 138                         #phy-cells = <1>;
 139                 };
 140
 141                 pd_cam: cam-power-domain@10023C00 {
 142                         compatible = "samsung,exynos4210-pd";
 143                         reg = <0x10023C00 0x20>;
 144                         #power-domain-cells = <0>;
 145                 };
 146
 147                 pd_mfc: mfc-power-domain@10023C40 {
 148                         compatible = "samsung,exynos4210-pd";
 149                         reg = <0x10023C40 0x20>;
 150                         #power-domain-cells = <0>;
 151                 };
 152
 153                 pd_g3d: g3d-power-domain@10023C60 {
 154                         compatible = "samsung,exynos4210-pd";
 155                         reg = <0x10023C60 0x20>;
 156                         #power-domain-cells = <0>;
 157                 };
 158
 159                 pd_lcd0: lcd0-power-domain@10023C80 {
 160                         compatible = "samsung,exynos4210-pd";
 161                         reg = <0x10023C80 0x20>;
 162                         #power-domain-cells = <0>;
 163                 };
 164
 165                 pd_isp: isp-power-domain@10023CA0 {
 166                         compatible = "samsung,exynos4210-pd";
 167                         reg = <0x10023CA0 0x20>;
 168                         #power-domain-cells = <0>;
 169                 };
 170
 171                 cmu: clock-controller@10030000 {
 172                         compatible = "samsung,exynos3250-cmu";
 173                         reg = <0x10030000 0x20000>;
 174                         #clock-cells = <1>;
 175                 };
 176
 177                 cmu_dmc: clock-controller@105C0000 {
 178                         compatible = "samsung,exynos3250-cmu-dmc";
 179                         reg = <0x105C0000 0x2000>;
 180                         #clock-cells = <1>;
 181                 };
 182
 183                 rtc: rtc@10070000 {
 184                         compatible = "samsung,exynos3250-rtc";
 185                         reg = <0x10070000 0x100>;
 186                         interrupts = <0 73 0>, <0 74 0>;
 187                         status = "disabled";
 188                 };
 189
 190                 tmu: tmu@100C0000 {
 191                         compatible = "samsung,exynos3250-tmu";
 192                         reg = <0x100C0000 0x100>;
 193                         interrupts = <0 216 0>;
 194                         clocks = <&cmu CLK_TMU_APBIF>;
 195                         clock-names = "tmu_apbif";
 196                         status = "disabled";
 197                 };
 198
 199                 gic: interrupt-controller@10481000 {
 200                         compatible = "arm,cortex-a15-gic";
 201                         #interrupt-cells = <3>;
 202                         interrupt-controller;
 203                         reg = <0x10481000 0x1000>,
 204                               <0x10482000 0x1000>,
 205                               <0x10484000 0x2000>,
 206                               <0x10486000 0x2000>;
 207                         interrupts = <1 9 0xf04>;
 208                 };
 209
 210                 mct@10050000 {
 211                         compatible = "samsung,exynos4210-mct";
 212                         reg = <0x10050000 0x800>;
 213                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 214                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 215                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 216                         clock-names = "fin_pll", "mct";
 217                 };
 218
 219                 pinctrl_1: pinctrl@11000000 {
 220                         compatible = "samsung,exynos3250-pinctrl";
 221                         reg = <0x11000000 0x1000>;
 222                         interrupts = <0 225 0>;
 223
 224                         wakeup-interrupt-controller {
 225                                 compatible = "samsung,exynos4210-wakeup-eint";
 226                                 interrupts = <0 48 0>;
 227                         };
 228                 };
 229
 230                 pinctrl_0: pinctrl@11400000 {
 231                         compatible = "samsung,exynos3250-pinctrl";
 232                         reg = <0x11400000 0x1000>;
 233                         interrupts = <0 240 0>;
 234                 };
 235
 236                 fimd: fimd@11c00000 {
 237                         compatible = "samsung,exynos3250-fimd";
 238                         reg = <0x11c00000 0x30000>;
 239                         interrupt-names = "fifo", "vsync", "lcd_sys";
 240                         interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
 241                         clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
 242                         clock-names = "sclk_fimd", "fimd";
 243                         power-domains = <&pd_lcd0>;
 244                         samsung,sysreg = <&sys_reg>;
 245                         status = "disabled";
 246                 };
 247
 248                 dsi_0: dsi@11C80000 {
 249                         compatible = "samsung,exynos3250-mipi-dsi";
 250                         reg = <0x11C80000 0x10000>;
 251                         interrupts = <0 83 0>;
 252                         samsung,phy-type = <0>;
 253                         power-domains = <&pd_lcd0>;
 254                         phys = <&mipi_phy 1>;
 255                         phy-names = "dsim";
 256                         clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
 257                         clock-names = "bus_clk", "pll_clk";
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260                         status = "disabled";
 261                 };
 262
 263                 hsotg: hsotg@12480000 {
 264                         compatible = "snps,dwc2";
 265                         reg = <0x12480000 0x20000>;
 266                         interrupts = <0 141 0>;
 267                         clocks = <&cmu CLK_USBOTG>;
 268                         clock-names = "otg";
 269                         phys = <&exynos_usbphy 0>;
 270                         phy-names = "usb2-phy";
 271                         status = "disabled";
 272                 };
 273
 274                 mshc_0: mshc@12510000 {
 275                         compatible = "samsung,exynos5250-dw-mshc";
 276                         reg = <0x12510000 0x1000>;
 277                         interrupts = <0 142 0>;
 278                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 279                         clock-names = "biu", "ciu";
 280                         fifo-depth = <0x80>;
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         status = "disabled";
 284                 };
 285
 286                 mshc_1: mshc@12520000 {
 287                         compatible = "samsung,exynos5250-dw-mshc";
 288                         reg = <0x12520000 0x1000>;
 289                         interrupts = <0 143 0>;
 290                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 291                         clock-names = "biu", "ciu";
 292                         fifo-depth = <0x80>;
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         status = "disabled";
 296                 };
 297
 298                 exynos_usbphy: exynos-usbphy@125B0000 {
 299                         compatible = "samsung,exynos3250-usb2-phy";
 300                         reg = <0x125B0000 0x100>;
 301                         samsung,pmureg-phandle = <&pmu_system_controller>;
 302                         clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
 303                         clock-names = "phy", "ref";
 304                         #phy-cells = <1>;
 305                         status = "disabled";
 306                 };
 307
 308                 amba {
 309                         compatible = "arm,amba-bus";
 310                         #address-cells = <1>;
 311                         #size-cells = <1>;
 312                         ranges;
 313
 314                         pdma0: pdma@12680000 {
 315                                 compatible = "arm,pl330", "arm,primecell";
 316                                 reg = <0x12680000 0x1000>;
 317                                 interrupts = <0 138 0>;
 318                                 clocks = <&cmu CLK_PDMA0>;
 319                                 clock-names = "apb_pclk";
 320                                 #dma-cells = <1>;
 321                                 #dma-channels = <8>;
 322                                 #dma-requests = <32>;
 323                         };
 324
 325                         pdma1: pdma@12690000 {
 326                                 compatible = "arm,pl330", "arm,primecell";
 327                                 reg = <0x12690000 0x1000>;
 328                                 interrupts = <0 139 0>;
 329                                 clocks = <&cmu CLK_PDMA1>;
 330                                 clock-names = "apb_pclk";
 331                                 #dma-cells = <1>;
 332                                 #dma-channels = <8>;
 333                                 #dma-requests = <32>;
 334                         };
 335                 };
 336
 337                 adc: adc@126C0000 {
 338                         compatible = "samsung,exynos3250-adc",
 339                                      "samsung,exynos-adc-v2";
 340                         reg = <0x126C0000 0x100>;
 341                         interrupts = <0 137 0>;
 342                         clock-names = "adc", "sclk";
 343                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 344                         #io-channel-cells = <1>;
 345                         io-channel-ranges;
 346                         samsung,syscon-phandle = <&pmu_system_controller>;
 347                         status = "disabled";
 348                 };
 349
 350                 mfc: codec@13400000 {
 351                         compatible = "samsung,mfc-v7";
 352                         reg = <0x13400000 0x10000>;
 353                         interrupts = <0 102 0>;
 354                         clock-names = "mfc", "sclk_mfc";
 355                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
 356                         power-domains = <&pd_mfc>;
 357                         status = "disabled";
 358                 };
 359
 360                 serial_0: serial@13800000 {
 361                         compatible = "samsung,exynos4210-uart";
 362                         reg = <0x13800000 0x100>;
 363                         interrupts = <0 109 0>;
 364                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 365                         clock-names = "uart", "clk_uart_baud0";
 366                         pinctrl-names = "default";
 367                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 368                         status = "disabled";
 369                 };
 370
 371                 serial_1: serial@13810000 {
 372                         compatible = "samsung,exynos4210-uart";
 373                         reg = <0x13810000 0x100>;
 374                         interrupts = <0 110 0>;
 375                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 376                         clock-names = "uart", "clk_uart_baud0";
 377                         pinctrl-names = "default";
 378                         pinctrl-0 = <&uart1_data>;
 379                         status = "disabled";
 380                 };
 381
 382                 i2c_0: i2c@13860000 {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         compatible = "samsung,s3c2440-i2c";
 386                         reg = <0x13860000 0x100>;
 387                         interrupts = <0 113 0>;
 388                         clocks = <&cmu CLK_I2C0>;
 389                         clock-names = "i2c";
 390                         pinctrl-names = "default";
 391                         pinctrl-0 = <&i2c0_bus>;
 392                         status = "disabled";
 393                 };
 394
 395                 i2c_1: i2c@13870000 {
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         compatible = "samsung,s3c2440-i2c";
 399                         reg = <0x13870000 0x100>;
 400                         interrupts = <0 114 0>;
 401                         clocks = <&cmu CLK_I2C1>;
 402                         clock-names = "i2c";
 403                         pinctrl-names = "default";
 404                         pinctrl-0 = <&i2c1_bus>;
 405                         status = "disabled";
 406                 };
 407
 408                 i2c_2: i2c@13880000 {
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         compatible = "samsung,s3c2440-i2c";
 412                         reg = <0x13880000 0x100>;
 413                         interrupts = <0 115 0>;
 414                         clocks = <&cmu CLK_I2C2>;
 415                         clock-names = "i2c";
 416                         pinctrl-names = "default";
 417                         pinctrl-0 = <&i2c2_bus>;
 418                         status = "disabled";
 419                 };
 420
 421                 i2c_3: i2c@13890000 {
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                         compatible = "samsung,s3c2440-i2c";
 425                         reg = <0x13890000 0x100>;
 426                         interrupts = <0 116 0>;
 427                         clocks = <&cmu CLK_I2C3>;
 428                         clock-names = "i2c";
 429                         pinctrl-names = "default";
 430                         pinctrl-0 = <&i2c3_bus>;
 431                         status = "disabled";
 432                 };
 433
 434                 i2c_4: i2c@138A0000 {
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         compatible = "samsung,s3c2440-i2c";
 438                         reg = <0x138A0000 0x100>;
 439                         interrupts = <0 117 0>;
 440                         clocks = <&cmu CLK_I2C4>;
 441                         clock-names = "i2c";
 442                         pinctrl-names = "default";
 443                         pinctrl-0 = <&i2c4_bus>;
 444                         status = "disabled";
 445                 };
 446
 447                 i2c_5: i2c@138B0000 {
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         compatible = "samsung,s3c2440-i2c";
 451                         reg = <0x138B0000 0x100>;
 452                         interrupts = <0 118 0>;
 453                         clocks = <&cmu CLK_I2C5>;
 454                         clock-names = "i2c";
 455                         pinctrl-names = "default";
 456                         pinctrl-0 = <&i2c5_bus>;
 457                         status = "disabled";
 458                 };
 459
 460                 i2c_6: i2c@138C0000 {
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         compatible = "samsung,s3c2440-i2c";
 464                         reg = <0x138C0000 0x100>;
 465                         interrupts = <0 119 0>;
 466                         clocks = <&cmu CLK_I2C6>;
 467                         clock-names = "i2c";
 468                         pinctrl-names = "default";
 469                         pinctrl-0 = <&i2c6_bus>;
 470                         status = "disabled";
 471                 };
 472
 473                 i2c_7: i2c@138D0000 {
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         compatible = "samsung,s3c2440-i2c";
 477                         reg = <0x138D0000 0x100>;
 478                         interrupts = <0 120 0>;
 479                         clocks = <&cmu CLK_I2C7>;
 480                         clock-names = "i2c";
 481                         pinctrl-names = "default";
 482                         pinctrl-0 = <&i2c7_bus>;
 483                         status = "disabled";
 484                 };
 485
 486                 spi_0: spi@13920000 {
 487                         compatible = "samsung,exynos4210-spi";
 488                         reg = <0x13920000 0x100>;
 489                         interrupts = <0 121 0>;
 490                         dmas = <&pdma0 7>, <&pdma0 6>;
 491                         dma-names = "tx", "rx";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 495                         clock-names = "spi", "spi_busclk0";
 496                         samsung,spi-src-clk = <0>;
 497                         pinctrl-names = "default";
 498                         pinctrl-0 = <&spi0_bus>;
 499                         status = "disabled";
 500                 };
 501
 502                 spi_1: spi@13930000 {
 503                         compatible = "samsung,exynos4210-spi";
 504                         reg = <0x13930000 0x100>;
 505                         interrupts = <0 122 0>;
 506                         dmas = <&pdma1 7>, <&pdma1 6>;
 507                         dma-names = "tx", "rx";
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 511                         clock-names = "spi", "spi_busclk0";
 512                         samsung,spi-src-clk = <0>;
 513                         pinctrl-names = "default";
 514                         pinctrl-0 = <&spi1_bus>;
 515                         status = "disabled";
 516                 };
 517
 518                 i2s2: i2s@13970000 {
 519                         compatible = "samsung,s3c6410-i2s";
 520                         reg = <0x13970000 0x100>;
 521                         interrupts = <0 126 0>;
 522                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 523                         clock-names = "iis", "i2s_opclk0";
 524                         dmas = <&pdma0 14>, <&pdma0 13>;
 525                         dma-names = "tx", "rx";
 526                         pinctrl-0 = <&i2s2_bus>;
 527                         pinctrl-names = "default";
 528                         status = "disabled";
 529                 };
 530
 531                 pwm: pwm@139D0000 {
 532                         compatible = "samsung,exynos4210-pwm";
 533                         reg = <0x139D0000 0x1000>;
 534                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 535                                      <0 107 0>, <0 108 0>;
 536                         #pwm-cells = <3>;
 537                         status = "disabled";
 538                 };
 539
 540                 pmu {
 541                         compatible = "arm,cortex-a7-pmu";
 542                         interrupts = <0 18 0>, <0 19 0>;
 543                 };
 544
 545                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 546                         compatible = "samsung,exynos-ppmu";
 547                         reg = <0x106a0000 0x2000>;
 548                         status = "disabled";
 549                 };
 550
 551                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 552                         compatible = "samsung,exynos-ppmu";
 553                         reg = <0x106b0000 0x2000>;
 554                         status = "disabled";
 555                 };
 556
 557                 ppmu_cpu: ppmu_cpu@106c0000 {
 558                         compatible = "samsung,exynos-ppmu";
 559                         reg = <0x106c0000 0x2000>;
 560                         status = "disabled";
 561                 };
 562
 563                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 564                         compatible = "samsung,exynos-ppmu";
 565                         reg = <0x112a0000 0x2000>;
 566                         clocks = <&cmu CLK_PPMURIGHT>;
 567                         clock-names = "ppmu";
 568                         status = "disabled";
 569                 };
 570
 571                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 572                         compatible = "samsung,exynos-ppmu";
 573                         reg = <0x116a0000 0x2000>;
 574                         clocks = <&cmu CLK_PPMULEFT>;
 575                         clock-names = "ppmu";
 576                         status = "disabled";
 577                 };
 578
 579                 ppmu_camif: ppmu_camif@11ac0000 {
 580                         compatible = "samsung,exynos-ppmu";
 581                         reg = <0x11ac0000 0x2000>;
 582                         clocks = <&cmu CLK_PPMUCAMIF>;
 583                         clock-names = "ppmu";
 584                         status = "disabled";
 585                 };
 586
 587                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 588                         compatible = "samsung,exynos-ppmu";
 589                         reg = <0x11e40000 0x2000>;
 590                         clocks = <&cmu CLK_PPMULCD0>;
 591                         clock-names = "ppmu";
 592                         status = "disabled";
 593                 };
 594
 595                 ppmu_fsys: ppmu_fsys@12630000 {
 596                         compatible = "samsung,exynos-ppmu";
 597                         reg = <0x12630000 0x2000>;
 598                         clocks = <&cmu CLK_PPMUFILE>;
 599                         clock-names = "ppmu";
 600                         status = "disabled";
 601                 };
 602
 603                 ppmu_g3d: ppmu_g3d@13220000 {
 604                         compatible = "samsung,exynos-ppmu";
 605                         reg = <0x13220000 0x2000>;
 606                         clocks = <&cmu CLK_PPMUG3D>;
 607                         clock-names = "ppmu";
 608                         status = "disabled";
 609                 };
 610
 611                 ppmu_mfc: ppmu_mfc@13660000 {
 612                         compatible = "samsung,exynos-ppmu";
 613                         reg = <0x13660000 0x2000>;
 614                         clocks = <&cmu CLK_PPMUMFC_L>;
 615                         clock-names = "ppmu";
 616                         status = "disabled";
 617                 };
 618         };
 619 };
 620
 621 #include "exynos3250-pinctrl.dtsi"