sys/gnu/dts/arm/hip04.dtsi

   1 /*
   2  * Hisilicon Ltd. HiP04 SoC
   3  *
   4  * Copyright (C) 2013-2014 Hisilicon Ltd.
   5  * Copyright (C) 2013-2014 Linaro Ltd.
   6  *
   7  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 / {
  15         /* memory bus is 64-bit */
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         bootwrapper {
  24                 compatible = "hisilicon,hip04-bootwrapper";
  25                 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu-map {
  33                         cluster0 {
  34                                 core0 {
  35                                         cpu = <&CPU0>;
  36                                 };
  37                                 core1 {
  38                                         cpu = <&CPU1>;
  39                                 };
  40                                 core2 {
  41                                         cpu = <&CPU2>;
  42                                 };
  43                                 core3 {
  44                                         cpu = <&CPU3>;
  45                                 };
  46                         };
  47                         cluster1 {
  48                                 core0 {
  49                                         cpu = <&CPU4>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&CPU5>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&CPU6>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&CPU7>;
  59                                 };
  60                         };
  61                         cluster2 {
  62                                 core0 {
  63                                         cpu = <&CPU8>;
  64                                 };
  65                                 core1 {
  66                                         cpu = <&CPU9>;
  67                                 };
  68                                 core2 {
  69                                         cpu = <&CPU10>;
  70                                 };
  71                                 core3 {
  72                                         cpu = <&CPU11>;
  73                                 };
  74                         };
  75                         cluster3 {
  76                                 core0 {
  77                                         cpu = <&CPU12>;
  78                                 };
  79                                 core1 {
  80                                         cpu = <&CPU13>;
  81                                 };
  82                                 core2 {
  83                                         cpu = <&CPU14>;
  84                                 };
  85                                 core3 {
  86                                         cpu = <&CPU15>;
  87                                 };
  88                         };
  89                 };
  90                 CPU0: cpu@0 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a15";
  93                         reg = <0>;
  94                 };
  95                 CPU1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a15";
  98                         reg = <1>;
  99                 };
 100                 CPU2: cpu@2 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a15";
 103                         reg = <2>;
 104                 };
 105                 CPU3: cpu@3 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a15";
 108                         reg = <3>;
 109                 };
 110                 CPU4: cpu@100 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a15";
 113                         reg = <0x100>;
 114                 };
 115                 CPU5: cpu@101 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a15";
 118                         reg = <0x101>;
 119                 };
 120                 CPU6: cpu@102 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a15";
 123                         reg = <0x102>;
 124                 };
 125                 CPU7: cpu@103 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a15";
 128                         reg = <0x103>;
 129                 };
 130                 CPU8: cpu@200 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a15";
 133                         reg = <0x200>;
 134                 };
 135                 CPU9: cpu@201 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a15";
 138                         reg = <0x201>;
 139                 };
 140                 CPU10: cpu@202 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a15";
 143                         reg = <0x202>;
 144                 };
 145                 CPU11: cpu@203 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a15";
 148                         reg = <0x203>;
 149                 };
 150                 CPU12: cpu@300 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a15";
 153                         reg = <0x300>;
 154                 };
 155                 CPU13: cpu@301 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a15";
 158                         reg = <0x301>;
 159                 };
 160                 CPU14: cpu@302 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a15";
 163                         reg = <0x302>;
 164                 };
 165                 CPU15: cpu@303 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a15";
 168                         reg = <0x303>;
 169                 };
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv7-timer";
 174                 interrupt-parent = <&gic>;
 175                 interrupts = <1 13 0xf08>,
 176                              <1 14 0xf08>,
 177                              <1 11 0xf08>,
 178                              <1 10 0xf08>;
 179         };
 180
 181         clk_50m: clk_50m {
 182                 #clock-cells = <0>;
 183                 compatible = "fixed-clock";
 184                 clock-frequency = <50000000>;
 185         };
 186
 187         clk_168m: clk_168m {
 188                 #clock-cells = <0>;
 189                 compatible = "fixed-clock";
 190                 clock-frequency = <168000000>;
 191         };
 192
 193         clk_375m: clk_375m {
 194                 #clock-cells = <0>;
 195                 compatible = "fixed-clock";
 196                 clock-frequency = <375000000>;
 197         };
 198
 199         soc {
 200                 /* It's a 32-bit SoC. */
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203                 compatible = "simple-bus";
 204                 interrupt-parent = <&gic>;
 205                 ranges = <0 0 0xe0000000 0x10000000>;
 206
 207                 gic: interrupt-controller@c01000 {
 208                         compatible = "hisilicon,hip04-intc";
 209                         #interrupt-cells = <3>;
 210                         #address-cells = <0>;
 211                         interrupt-controller;
 212                         interrupts = <1 9 0xf04>;
 213
 214                         reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
 215                               <0xc04000 0x2000>, <0xc06000 0x2000>;
 216                 };
 217
 218                 sysctrl: sysctrl {
 219                         compatible = "hisilicon,sysctrl";
 220                         reg = <0x3e00000 0x00100000>;
 221                 };
 222
 223                 fabric: fabric {
 224                         compatible = "hisilicon,hip04-fabric";
 225                         reg = <0x302a000 0x1000>;
 226                 };
 227
 228                 dual_timer0: dual_timer@3000000 {
 229                         compatible = "arm,sp804", "arm,primecell";
 230                         reg = <0x3000000 0x1000>;
 231                         interrupts = <0 224 4>;
 232                         clocks = <&clk_50m>, <&clk_50m>;
 233                         clock-names = "apb_pclk";
 234                 };
 235
 236                 arm-pmu {
 237                         compatible = "arm,cortex-a15-pmu";
 238                         interrupts = <0 64 4>,
 239                                      <0 65 4>,
 240                                      <0 66 4>,
 241                                      <0 67 4>,
 242                                      <0 68 4>,
 243                                      <0 69 4>,
 244                                      <0 70 4>,
 245                                      <0 71 4>,
 246                                      <0 72 4>,
 247                                      <0 73 4>,
 248                                      <0 74 4>,
 249                                      <0 75 4>,
 250                                      <0 76 4>,
 251                                      <0 77 4>,
 252                                      <0 78 4>,
 253                                      <0 79 4>;
 254                 };
 255
 256                 uart0: uart@4007000 {
 257                         compatible = "snps,dw-apb-uart";
 258                         reg = <0x4007000 0x1000>;
 259                         interrupts = <0 381 4>;
 260                         clocks = <&clk_168m>;
 261                         clock-names = "uartclk";
 262                         reg-shift = <2>;
 263                         status = "disabled";
 264                 };
 265
 266                 sata0: sata@a000000 {
 267                         compatible = "hisilicon,hisi-ahci";
 268                         reg = <0xa000000 0x1000000>;
 269                         interrupts = <0 372 4>;
 270                 };
 271
 272         };
 273
 274         etb@0,e3c42000 {
 275                 compatible = "arm,coresight-etb10", "arm,primecell";
 276                 reg = <0 0xe3c42000 0 0x1000>;
 277
 278                 coresight-default-sink;
 279                 clocks = <&clk_375m>;
 280                 clock-names = "apb_pclk";
 281                 port {
 282                         etb0_in_port: endpoint@0 {
 283                                 slave-mode;
 284                                 remote-endpoint = <&replicator0_out_port0>;
 285                         };
 286                 };
 287         };
 288
 289         etb@0,e3c82000 {
 290                 compatible = "arm,coresight-etb10", "arm,primecell";
 291                 reg = <0 0xe3c82000 0 0x1000>;
 292
 293                 clocks = <&clk_375m>;
 294                 clock-names = "apb_pclk";
 295                 port {
 296                         etb1_in_port: endpoint@0 {
 297                                 slave-mode;
 298                                 remote-endpoint = <&replicator1_out_port0>;
 299                         };
 300                 };
 301         };
 302
 303         etb@0,e3cc2000 {
 304                 compatible = "arm,coresight-etb10", "arm,primecell";
 305                 reg = <0 0xe3cc2000 0 0x1000>;
 306
 307                 clocks = <&clk_375m>;
 308                 clock-names = "apb_pclk";
 309                 port {
 310                         etb2_in_port: endpoint@0 {
 311                                 slave-mode;
 312                                 remote-endpoint = <&replicator2_out_port0>;
 313                         };
 314                 };
 315         };
 316
 317         etb@0,e3d02000 {
 318                 compatible = "arm,coresight-etb10", "arm,primecell";
 319                 reg = <0 0xe3d02000 0 0x1000>;
 320
 321                 clocks = <&clk_375m>;
 322                 clock-names = "apb_pclk";
 323                 port {
 324                         etb3_in_port: endpoint@0 {
 325                                 slave-mode;
 326                                 remote-endpoint = <&replicator3_out_port0>;
 327                         };
 328                 };
 329         };
 330
 331         tpiu@0,e3c05000 {
 332                 compatible = "arm,coresight-tpiu", "arm,primecell";
 333                 reg = <0 0xe3c05000 0 0x1000>;
 334
 335                 clocks = <&clk_375m>;
 336                 clock-names = "apb_pclk";
 337                 port {
 338                         tpiu_in_port: endpoint@0 {
 339                                 slave-mode;
 340                                 remote-endpoint = <&funnel4_out_port0>;
 341                         };
 342                 };
 343         };
 344
 345         replicator0 {
 346                 /* non-configurable replicators don't show up on the
 347                  * AMBA bus.  As such no need to add "arm,primecell".
 348                  */
 349                 compatible = "arm,coresight-replicator";
 350
 351                 ports {
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354
 355                         /* replicator output ports */
 356                         port@0 {
 357                                 reg = <0>;
 358                                 replicator0_out_port0: endpoint {
 359                                         remote-endpoint = <&etb0_in_port>;
 360                                 };
 361                         };
 362
 363                         port@1 {
 364                                 reg = <1>;
 365                                 replicator0_out_port1: endpoint {
 366                                         remote-endpoint = <&funnel4_in_port0>;
 367                                 };
 368                         };
 369
 370                         /* replicator input port */
 371                         port@2 {
 372                                 reg = <0>;
 373                                 replicator0_in_port0: endpoint {
 374                                         slave-mode;
 375                                         remote-endpoint = <&funnel0_out_port0>;
 376                                 };
 377                         };
 378                 };
 379         };
 380
 381         replicator1 {
 382                 /* non-configurable replicators don't show up on the
 383                  * AMBA bus.  As such no need to add "arm,primecell".
 384                  */
 385                 compatible = "arm,coresight-replicator";
 386
 387                 ports {
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390
 391                         /* replicator output ports */
 392                         port@0 {
 393                                 reg = <0>;
 394                                 replicator1_out_port0: endpoint {
 395                                         remote-endpoint = <&etb1_in_port>;
 396                                 };
 397                         };
 398
 399                         port@1 {
 400                                 reg = <1>;
 401                                 replicator1_out_port1: endpoint {
 402                                         remote-endpoint = <&funnel4_in_port1>;
 403                                 };
 404                         };
 405
 406                         /* replicator input port */
 407                         port@2 {
 408                                 reg = <0>;
 409                                 replicator1_in_port0: endpoint {
 410                                         slave-mode;
 411                                         remote-endpoint = <&funnel1_out_port0>;
 412                                 };
 413                         };
 414                 };
 415         };
 416
 417         replicator2 {
 418                 /* non-configurable replicators don't show up on the
 419                  * AMBA bus.  As such no need to add "arm,primecell".
 420                  */
 421                 compatible = "arm,coresight-replicator";
 422
 423                 ports {
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426
 427                         /* replicator output ports */
 428                         port@0 {
 429                                 reg = <0>;
 430                                 replicator2_out_port0: endpoint {
 431                                         remote-endpoint = <&etb2_in_port>;
 432                                 };
 433                         };
 434
 435                         port@1 {
 436                                 reg = <1>;
 437                                         replicator2_out_port1: endpoint {
 438                                         remote-endpoint = <&funnel4_in_port2>;
 439                                 };
 440                         };
 441
 442                         /* replicator input port */
 443                         port@2 {
 444                                 reg = <0>;
 445                                 replicator2_in_port0: endpoint {
 446                                         slave-mode;
 447                                         remote-endpoint = <&funnel2_out_port0>;
 448                                 };
 449                         };
 450                 };
 451         };
 452
 453         replicator3 {
 454                 /* non-configurable replicators don't show up on the
 455                  * AMBA bus.  As such no need to add "arm,primecell".
 456                  */
 457                 compatible = "arm,coresight-replicator";
 458
 459                 ports {
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462
 463                         /* replicator output ports */
 464                         port@0 {
 465                                 reg = <0>;
 466                                 replicator3_out_port0: endpoint {
 467                                         remote-endpoint = <&etb3_in_port>;
 468                                 };
 469                         };
 470
 471                         port@1 {
 472                                 reg = <1>;
 473                                 replicator3_out_port1: endpoint {
 474                                         remote-endpoint = <&funnel4_in_port3>;
 475                                 };
 476                         };
 477
 478                         /* replicator input port */
 479                         port@2 {
 480                                 reg = <0>;
 481                                 replicator3_in_port0: endpoint {
 482                                         slave-mode;
 483                                         remote-endpoint = <&funnel3_out_port0>;
 484                                 };
 485                         };
 486                 };
 487         };
 488
 489         funnel@0,e3c41000 {
 490                 compatible = "arm,coresight-funnel", "arm,primecell";
 491                 reg = <0 0xe3c41000 0 0x1000>;
 492
 493                 clocks = <&clk_375m>;
 494                 clock-names = "apb_pclk";
 495                 ports {
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498
 499                         /* funnel output port */
 500                         port@0 {
 501                                 reg = <0>;
 502                                 funnel0_out_port0: endpoint {
 503                                         remote-endpoint =
 504                                                 <&replicator0_in_port0>;
 505                                 };
 506                         };
 507
 508                         /* funnel input ports */
 509                         port@1 {
 510                                 reg = <0>;
 511                                 funnel0_in_port0: endpoint {
 512                                         slave-mode;
 513                                         remote-endpoint = <&ptm0_out_port>;
 514                                 };
 515                         };
 516
 517                         port@2 {
 518                                 reg = <1>;
 519                                 funnel0_in_port1: endpoint {
 520                                         slave-mode;
 521                                         remote-endpoint = <&ptm1_out_port>;
 522                                 };
 523                         };
 524
 525                         port@3 {
 526                                 reg = <2>;
 527                                 funnel0_in_port2: endpoint {
 528                                         slave-mode;
 529                                         remote-endpoint = <&ptm2_out_port>;
 530                                 };
 531                         };
 532
 533                         port@4 {
 534                                 reg = <3>;
 535                                 funnel0_in_port3: endpoint {
 536                                         slave-mode;
 537                                         remote-endpoint = <&ptm3_out_port>;
 538                                 };
 539                         };
 540                 };
 541         };
 542
 543         funnel@0,e3c81000 {
 544                 compatible = "arm,coresight-funnel", "arm,primecell";
 545                 reg = <0 0xe3c81000 0 0x1000>;
 546
 547                 clocks = <&clk_375m>;
 548                 clock-names = "apb_pclk";
 549                 ports {
 550                         #address-cells = <1>;
 551                         #size-cells = <0>;
 552
 553                         /* funnel output port */
 554                         port@0 {
 555                                 reg = <0>;
 556                                 funnel1_out_port0: endpoint {
 557                                         remote-endpoint =
 558                                                 <&replicator1_in_port0>;
 559                                 };
 560                         };
 561
 562                         /* funnel input ports */
 563                         port@1 {
 564                                 reg = <0>;
 565                                 funnel1_in_port0: endpoint {
 566                                         slave-mode;
 567                                         remote-endpoint = <&ptm4_out_port>;
 568                                 };
 569                         };
 570
 571                         port@2 {
 572                                 reg = <1>;
 573                                 funnel1_in_port1: endpoint {
 574                                         slave-mode;
 575                                         remote-endpoint = <&ptm5_out_port>;
 576                                 };
 577                         };
 578
 579                         port@3 {
 580                                 reg = <2>;
 581                                 funnel1_in_port2: endpoint {
 582                                         slave-mode;
 583                                         remote-endpoint = <&ptm6_out_port>;
 584                                 };
 585                         };
 586
 587                         port@4 {
 588                                 reg = <3>;
 589                                 funnel1_in_port3: endpoint {
 590                                         slave-mode;
 591                                         remote-endpoint = <&ptm7_out_port>;
 592                                 };
 593                         };
 594                 };
 595         };
 596
 597         funnel@0,e3cc1000 {
 598                 compatible = "arm,coresight-funnel", "arm,primecell";
 599                 reg = <0 0xe3cc1000 0 0x1000>;
 600
 601                 clocks = <&clk_375m>;
 602                 clock-names = "apb_pclk";
 603                 ports {
 604                         #address-cells = <1>;
 605                         #size-cells = <0>;
 606
 607                         /* funnel output port */
 608                         port@0 {
 609                                 reg = <0>;
 610                                 funnel2_out_port0: endpoint {
 611                                         remote-endpoint =
 612                                                 <&replicator2_in_port0>;
 613                                 };
 614                         };
 615
 616                         /* funnel input ports */
 617                         port@1 {
 618                                 reg = <0>;
 619                                 funnel2_in_port0: endpoint {
 620                                         slave-mode;
 621                                         remote-endpoint = <&ptm8_out_port>;
 622                                 };
 623                         };
 624
 625                         port@2 {
 626                                 reg = <1>;
 627                                 funnel2_in_port1: endpoint {
 628                                         slave-mode;
 629                                         remote-endpoint = <&ptm9_out_port>;
 630                                 };
 631                         };
 632
 633                         port@3 {
 634                                 reg = <2>;
 635                                 funnel2_in_port2: endpoint {
 636                                         slave-mode;
 637                                         remote-endpoint = <&ptm10_out_port>;
 638                                 };
 639                         };
 640
 641                         port@4 {
 642                                 reg = <3>;
 643                                 funnel2_in_port3: endpoint {
 644                                         slave-mode;
 645                                         remote-endpoint = <&ptm11_out_port>;
 646                                 };
 647                         };
 648                 };
 649         };
 650
 651         funnel@0,e3d01000 {
 652                 compatible = "arm,coresight-funnel", "arm,primecell";
 653                 reg = <0 0xe3d01000 0 0x1000>;
 654
 655                 clocks = <&clk_375m>;
 656                 clock-names = "apb_pclk";
 657                 ports {
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660
 661                         /* funnel output port */
 662                         port@0 {
 663                                 reg = <0>;
 664                                 funnel3_out_port0: endpoint {
 665                                         remote-endpoint =
 666                                                 <&replicator3_in_port0>;
 667                                 };
 668                         };
 669
 670                         /* funnel input ports */
 671                         port@1 {
 672                                 reg = <0>;
 673                                 funnel3_in_port0: endpoint {
 674                                         slave-mode;
 675                                         remote-endpoint = <&ptm12_out_port>;
 676                                 };
 677                         };
 678
 679                         port@2 {
 680                                 reg = <1>;
 681                                 funnel3_in_port1: endpoint {
 682                                         slave-mode;
 683                                         remote-endpoint = <&ptm13_out_port>;
 684                                 };
 685                         };
 686
 687                         port@3 {
 688                                 reg = <2>;
 689                                 funnel3_in_port2: endpoint {
 690                                         slave-mode;
 691                                         remote-endpoint = <&ptm14_out_port>;
 692                                 };
 693                         };
 694
 695                         port@4 {
 696                                 reg = <3>;
 697                                 funnel3_in_port3: endpoint {
 698                                         slave-mode;
 699                                         remote-endpoint = <&ptm15_out_port>;
 700                                 };
 701                         };
 702                 };
 703         };
 704
 705         funnel@0,e3c04000 {
 706                 compatible = "arm,coresight-funnel", "arm,primecell";
 707                 reg = <0 0xe3c04000 0 0x1000>;
 708
 709                 clocks = <&clk_375m>;
 710                 clock-names = "apb_pclk";
 711                 ports {
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714
 715                         /* funnel output port */
 716                         port@0 {
 717                                 reg = <0>;
 718                                 funnel4_out_port0: endpoint {
 719                                         remote-endpoint = <&tpiu_in_port>;
 720                                 };
 721                         };
 722
 723                         /* funnel input ports */
 724                         port@1 {
 725                                 reg = <0>;
 726                                 funnel4_in_port0: endpoint {
 727                                         slave-mode;
 728                                         remote-endpoint =
 729                                                 <&replicator0_out_port1>;
 730                                 };
 731                         };
 732
 733                         port@2 {
 734                                 reg = <1>;
 735                                 funnel4_in_port1: endpoint {
 736                                         slave-mode;
 737                                         remote-endpoint =
 738                                                 <&replicator1_out_port1>;
 739                                 };
 740                         };
 741
 742                         port@3 {
 743                                 reg = <2>;
 744                                 funnel4_in_port2: endpoint {
 745                                         slave-mode;
 746                                         remote-endpoint =
 747                                                 <&replicator2_out_port1>;
 748                                 };
 749                         };
 750
 751                         port@4 {
 752                                 reg = <3>;
 753                                 funnel4_in_port3: endpoint {
 754                                         slave-mode;
 755                                         remote-endpoint =
 756                                                 <&replicator3_out_port1>;
 757                                 };
 758                         };
 759                 };
 760         };
 761
 762         ptm@0,e3c7c000 {
 763                 compatible = "arm,coresight-etm3x", "arm,primecell";
 764                 reg = <0 0xe3c7c000 0 0x1000>;
 765
 766                 clocks = <&clk_375m>;
 767                 clock-names = "apb_pclk";
 768                 cpu = <&CPU0>;
 769                 port {
 770                         ptm0_out_port: endpoint {
 771                                 remote-endpoint = <&funnel0_in_port0>;
 772                         };
 773                 };
 774         };
 775
 776         ptm@0,e3c7d000 {
 777                 compatible = "arm,coresight-etm3x", "arm,primecell";
 778                 reg = <0 0xe3c7d000 0 0x1000>;
 779
 780                 clocks = <&clk_375m>;
 781                 clock-names = "apb_pclk";
 782                 cpu = <&CPU1>;
 783                 port {
 784                         ptm1_out_port: endpoint {
 785                                 remote-endpoint = <&funnel0_in_port1>;
 786                         };
 787                 };
 788         };
 789
 790         ptm@0,e3c7e000 {
 791                 compatible = "arm,coresight-etm3x", "arm,primecell";
 792                 reg = <0 0xe3c7e000 0 0x1000>;
 793
 794                 clocks = <&clk_375m>;
 795                 clock-names = "apb_pclk";
 796                 cpu = <&CPU2>;
 797                 port {
 798                         ptm2_out_port: endpoint {
 799                                 remote-endpoint = <&funnel0_in_port2>;
 800                         };
 801                 };
 802         };
 803
 804         ptm@0,e3c7f000 {
 805                 compatible = "arm,coresight-etm3x", "arm,primecell";
 806                 reg = <0 0xe3c7f000 0 0x1000>;
 807
 808                 clocks = <&clk_375m>;
 809                 clock-names = "apb_pclk";
 810                 cpu = <&CPU3>;
 811                 port {
 812                         ptm3_out_port: endpoint {
 813                                 remote-endpoint = <&funnel0_in_port3>;
 814                         };
 815                 };
 816         };
 817
 818         ptm@0,e3cbc000 {
 819                 compatible = "arm,coresight-etm3x", "arm,primecell";
 820                 reg = <0 0xe3cbc000 0 0x1000>;
 821
 822                 clocks = <&clk_375m>;
 823                 clock-names = "apb_pclk";
 824                 cpu = <&CPU4>;
 825                 port {
 826                         ptm4_out_port: endpoint {
 827                                 remote-endpoint = <&funnel1_in_port0>;
 828                         };
 829                 };
 830         };
 831
 832         ptm@0,e3cbd000 {
 833                 compatible = "arm,coresight-etm3x", "arm,primecell";
 834                 reg = <0 0xe3cbd000 0 0x1000>;
 835
 836                 clocks = <&clk_375m>;
 837                 clock-names = "apb_pclk";
 838                 cpu = <&CPU5>;
 839                 port {
 840                         ptm5_out_port: endpoint {
 841                                 remote-endpoint = <&funnel1_in_port1>;
 842                         };
 843                 };
 844         };
 845
 846         ptm@0,e3cbe000 {
 847                 compatible = "arm,coresight-etm3x", "arm,primecell";
 848                 reg = <0 0xe3cbe000 0 0x1000>;
 849
 850                 clocks = <&clk_375m>;
 851                 clock-names = "apb_pclk";
 852                 cpu = <&CPU6>;
 853                 port {
 854                         ptm6_out_port: endpoint {
 855                                 remote-endpoint = <&funnel1_in_port2>;
 856                         };
 857                 };
 858         };
 859
 860         ptm@0,e3cbf000 {
 861                 compatible = "arm,coresight-etm3x", "arm,primecell";
 862                 reg = <0 0xe3cbf000 0 0x1000>;
 863
 864                 clocks = <&clk_375m>;
 865                 clock-names = "apb_pclk";
 866                 cpu = <&CPU7>;
 867                 port {
 868                         ptm7_out_port: endpoint {
 869                                 remote-endpoint = <&funnel1_in_port3>;
 870                         };
 871                 };
 872         };
 873
 874         ptm@0,e3cfc000 {
 875                 compatible = "arm,coresight-etm3x", "arm,primecell";
 876                 reg = <0 0xe3cfc000 0 0x1000>;
 877
 878                 clocks = <&clk_375m>;
 879                 clock-names = "apb_pclk";
 880                 cpu = <&CPU8>;
 881                 port {
 882                         ptm8_out_port: endpoint {
 883                                 remote-endpoint = <&funnel2_in_port0>;
 884                         };
 885                 };
 886         };
 887
 888         ptm@0,e3cfd000 {
 889                 compatible = "arm,coresight-etm3x", "arm,primecell";
 890                 reg = <0 0xe3cfd000 0 0x1000>;
 891                 clocks = <&clk_375m>;
 892                 clock-names = "apb_pclk";
 893                 cpu = <&CPU9>;
 894                 port {
 895                         ptm9_out_port: endpoint {
 896                                 remote-endpoint = <&funnel2_in_port1>;
 897                         };
 898                 };
 899         };
 900
 901         ptm@0,e3cfe000 {
 902                 compatible = "arm,coresight-etm3x", "arm,primecell";
 903                 reg = <0 0xe3cfe000 0 0x1000>;
 904
 905                 clocks = <&clk_375m>;
 906                 clock-names = "apb_pclk";
 907                 cpu = <&CPU10>;
 908                 port {
 909                         ptm10_out_port: endpoint {
 910                                 remote-endpoint = <&funnel2_in_port2>;
 911                         };
 912                 };
 913         };
 914
 915         ptm@0,e3cff000 {
 916                 compatible = "arm,coresight-etm3x", "arm,primecell";
 917                 reg = <0 0xe3cff000 0 0x1000>;
 918
 919                 clocks = <&clk_375m>;
 920                 clock-names = "apb_pclk";
 921                 cpu = <&CPU11>;
 922                 port {
 923                         ptm11_out_port: endpoint {
 924                                 remote-endpoint = <&funnel2_in_port3>;
 925                         };
 926                 };
 927         };
 928
 929         ptm@0,e3d3c000 {
 930                 compatible = "arm,coresight-etm3x", "arm,primecell";
 931                 reg = <0 0xe3d3c000 0 0x1000>;
 932
 933                 clocks = <&clk_375m>;
 934                 clock-names = "apb_pclk";
 935                 cpu = <&CPU12>;
 936                 port {
 937                         ptm12_out_port: endpoint {
 938                                 remote-endpoint = <&funnel3_in_port0>;
 939                         };
 940                 };
 941         };
 942
 943         ptm@0,e3d3d000 {
 944                 compatible = "arm,coresight-etm3x", "arm,primecell";
 945                 reg = <0 0xe3d3d000 0 0x1000>;
 946
 947                 clocks = <&clk_375m>;
 948                 clock-names = "apb_pclk";
 949                 cpu = <&CPU13>;
 950                 port {
 951                         ptm13_out_port: endpoint {
 952                                 remote-endpoint = <&funnel3_in_port1>;
 953                         };
 954                 };
 955         };
 956
 957         ptm@0,e3d3e000 {
 958                 compatible = "arm,coresight-etm3x", "arm,primecell";
 959                 reg = <0 0xe3d3e000 0 0x1000>;
 960
 961                 clocks = <&clk_375m>;
 962                 clock-names = "apb_pclk";
 963                 cpu = <&CPU14>;
 964                 port {
 965                         ptm14_out_port: endpoint {
 966                                 remote-endpoint = <&funnel3_in_port2>;
 967                         };
 968                 };
 969         };
 970
 971         ptm@0,e3d3f000 {
 972                 compatible = "arm,coresight-etm3x", "arm,primecell";
 973                 reg = <0 0xe3d3f000 0 0x1000>;
 974
 975                 clocks = <&clk_375m>;
 976                 clock-names = "apb_pclk";
 977                 cpu = <&CPU15>;
 978                 port {
 979                         ptm15_out_port: endpoint {
 980                                 remote-endpoint = <&funnel3_in_port3>;
 981                         };
 982                 };
 983         };
 984 };