sys/gnu/dts/arm/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/pinctrl/rockchip.h>
  18 #include <dt-bindings/clock/rk3066a-cru.h>
  19 #include "rk3xxx.dtsi"
  20
  21 / {
  22         compatible = "rockchip,rk3066a";
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 enable-method = "rockchip,rk3066-smp";
  28
  29                 cpu0: cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a9";
  32                         next-level-cache = <&L2>;
  33                         reg = <0x0>;
  34                         operating-points = <
  35                                 /* kHz    uV */
  36                                 1008000 1075000
  37                                  816000 1025000
  38                                  600000 1025000
  39                                  504000 1000000
  40                                  312000  975000
  41                         >;
  42                         clock-latency = <40000>;
  43                         clocks = <&cru ARMCLK>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a9";
  48                         next-level-cache = <&L2>;
  49                         reg = <0x1>;
  50                 };
  51         };
  52
  53         sram: sram@10080000 {
  54                 compatible = "mmio-sram";
  55                 reg = <0x10080000 0x10000>;
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges = <0 0x10080000 0x10000>;
  59
  60                 smp-sram@0 {
  61                         compatible = "rockchip,rk3066-smp-sram";
  62                         reg = <0x0 0x50>;
  63                 };
  64         };
  65
  66         i2s0: i2s@10118000 {
  67                 compatible = "rockchip,rk3066-i2s";
  68                 reg = <0x10118000 0x2000>;
  69                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&i2s0_bus>;
  74                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
  75                 dma-names = "tx", "rx";
  76                 clock-names = "i2s_hclk", "i2s_clk";
  77                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
  78                 status = "disabled";
  79         };
  80
  81         i2s1: i2s@1011a000 {
  82                 compatible = "rockchip,rk3066-i2s";
  83                 reg = <0x1011a000 0x2000>;
  84                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  85                 #address-cells = <1>;
  86                 #size-cells = <0>;
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&i2s1_bus>;
  89                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
  90                 dma-names = "tx", "rx";
  91                 clock-names = "i2s_hclk", "i2s_clk";
  92                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
  93                 status = "disabled";
  94         };
  95
  96         i2s2: i2s@1011c000 {
  97                 compatible = "rockchip,rk3066-i2s";
  98                 reg = <0x1011c000 0x2000>;
  99                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&i2s2_bus>;
 104                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 105                 dma-names = "tx", "rx";
 106                 clock-names = "i2s_hclk", "i2s_clk";
 107                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 108                 status = "disabled";
 109         };
 110
 111         cru: clock-controller@20000000 {
 112                 compatible = "rockchip,rk3066a-cru";
 113                 reg = <0x20000000 0x1000>;
 114                 rockchip,grf = <&grf>;
 115
 116                 #clock-cells = <1>;
 117                 #reset-cells = <1>;
 118         };
 119
 120         timer@2000e000 {
 121                 compatible = "snps,dw-apb-timer-osc";
 122                 reg = <0x2000e000 0x100>;
 123                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 124                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 125                 clock-names = "timer", "pclk";
 126         };
 127
 128         timer@20038000 {
 129                 compatible = "snps,dw-apb-timer-osc";
 130                 reg = <0x20038000 0x100>;
 131                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 133                 clock-names = "timer", "pclk";
 134         };
 135
 136         timer@2003a000 {
 137                 compatible = "snps,dw-apb-timer-osc";
 138                 reg = <0x2003a000 0x100>;
 139                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 140                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 141                 clock-names = "timer", "pclk";
 142         };
 143
 144         pinctrl: pinctrl {
 145                 compatible = "rockchip,rk3066a-pinctrl";
 146                 rockchip,grf = <&grf>;
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 ranges;
 150
 151                 gpio0: gpio0@20034000 {
 152                         compatible = "rockchip,gpio-bank";
 153                         reg = <0x20034000 0x100>;
 154                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 155                         clocks = <&cru PCLK_GPIO0>;
 156
 157                         gpio-controller;
 158                         #gpio-cells = <2>;
 159
 160                         interrupt-controller;
 161                         #interrupt-cells = <2>;
 162                 };
 163
 164                 gpio1: gpio1@2003c000 {
 165                         compatible = "rockchip,gpio-bank";
 166                         reg = <0x2003c000 0x100>;
 167                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&cru PCLK_GPIO1>;
 169
 170                         gpio-controller;
 171                         #gpio-cells = <2>;
 172
 173                         interrupt-controller;
 174                         #interrupt-cells = <2>;
 175                 };
 176
 177                 gpio2: gpio2@2003e000 {
 178                         compatible = "rockchip,gpio-bank";
 179                         reg = <0x2003e000 0x100>;
 180                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 181                         clocks = <&cru PCLK_GPIO2>;
 182
 183                         gpio-controller;
 184                         #gpio-cells = <2>;
 185
 186                         interrupt-controller;
 187                         #interrupt-cells = <2>;
 188                 };
 189
 190                 gpio3: gpio3@20080000 {
 191                         compatible = "rockchip,gpio-bank";
 192                         reg = <0x20080000 0x100>;
 193                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&cru PCLK_GPIO3>;
 195
 196                         gpio-controller;
 197                         #gpio-cells = <2>;
 198
 199                         interrupt-controller;
 200                         #interrupt-cells = <2>;
 201                 };
 202
 203                 gpio4: gpio4@20084000 {
 204                         compatible = "rockchip,gpio-bank";
 205                         reg = <0x20084000 0x100>;
 206                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&cru PCLK_GPIO4>;
 208
 209                         gpio-controller;
 210                         #gpio-cells = <2>;
 211
 212                         interrupt-controller;
 213                         #interrupt-cells = <2>;
 214                 };
 215
 216                 gpio6: gpio6@2000a000 {
 217                         compatible = "rockchip,gpio-bank";
 218                         reg = <0x2000a000 0x100>;
 219                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&cru PCLK_GPIO6>;
 221
 222                         gpio-controller;
 223                         #gpio-cells = <2>;
 224
 225                         interrupt-controller;
 226                         #interrupt-cells = <2>;
 227                 };
 228
 229                 pcfg_pull_default: pcfg_pull_default {
 230                         bias-pull-pin-default;
 231                 };
 232
 233                 pcfg_pull_none: pcfg_pull_none {
 234                         bias-disable;
 235                 };
 236
 237                 emac {
 238                         emac_xfer: emac-xfer {
 239                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 240                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 241                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 242                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 243                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 244                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 245                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 246                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 247                         };
 248
 249                         emac_mdio: emac-mdio {
 250                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 251                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 252                         };
 253                 };
 254
 255                 emmc {
 256                         emmc_clk: emmc-clk {
 257                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 258                         };
 259
 260                         emmc_cmd: emmc-cmd {
 261                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 262                         };
 263
 264                         emmc_rst: emmc-rst {
 265                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 266                         };
 267
 268                         /*
 269                          * The data pins are shared between nandc and emmc and
 270                          * not accessible through pinctrl. Also they should've
 271                          * been already set correctly by firmware, as
 272                          * flash/emmc is the boot-device.
 273                          */
 274                 };
 275
 276                 i2c0 {
 277                         i2c0_xfer: i2c0-xfer {
 278                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 279                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 280                         };
 281                 };
 282
 283                 i2c1 {
 284                         i2c1_xfer: i2c1-xfer {
 285                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 286                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 287                         };
 288                 };
 289
 290                 i2c2 {
 291                         i2c2_xfer: i2c2-xfer {
 292                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 293                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 294                         };
 295                 };
 296
 297                 i2c3 {
 298                         i2c3_xfer: i2c3-xfer {
 299                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 300                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 301                         };
 302                 };
 303
 304                 i2c4 {
 305                         i2c4_xfer: i2c4-xfer {
 306                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 307                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 308                         };
 309                 };
 310
 311                 pwm0 {
 312                         pwm0_out: pwm0-out {
 313                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 314                         };
 315                 };
 316
 317                 pwm1 {
 318                         pwm1_out: pwm1-out {
 319                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 320                         };
 321                 };
 322
 323                 pwm2 {
 324                         pwm2_out: pwm2-out {
 325                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 326                         };
 327                 };
 328
 329                 pwm3 {
 330                         pwm3_out: pwm3-out {
 331                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 332                         };
 333                 };
 334
 335                 spi0 {
 336                         spi0_clk: spi0-clk {
 337                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 338                         };
 339                         spi0_cs0: spi0-cs0 {
 340                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 341                         };
 342                         spi0_tx: spi0-tx {
 343                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 344                         };
 345                         spi0_rx: spi0-rx {
 346                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 347                         };
 348                         spi0_cs1: spi0-cs1 {
 349                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 350                         };
 351                 };
 352
 353                 spi1 {
 354                         spi1_clk: spi1-clk {
 355                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 356                         };
 357                         spi1_cs0: spi1-cs0 {
 358                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 359                         };
 360                         spi1_rx: spi1-rx {
 361                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 362                         };
 363                         spi1_tx: spi1-tx {
 364                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 365                         };
 366                         spi1_cs1: spi1-cs1 {
 367                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 368                         };
 369                 };
 370
 371                 uart0 {
 372                         uart0_xfer: uart0-xfer {
 373                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 374                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 375                         };
 376
 377                         uart0_cts: uart0-cts {
 378                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 379                         };
 380
 381                         uart0_rts: uart0-rts {
 382                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 383                         };
 384                 };
 385
 386                 uart1 {
 387                         uart1_xfer: uart1-xfer {
 388                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 389                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 390                         };
 391
 392                         uart1_cts: uart1-cts {
 393                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 394                         };
 395
 396                         uart1_rts: uart1-rts {
 397                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 398                         };
 399                 };
 400
 401                 uart2 {
 402                         uart2_xfer: uart2-xfer {
 403                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 404                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 405                         };
 406                         /* no rts / cts for uart2 */
 407                 };
 408
 409                 uart3 {
 410                         uart3_xfer: uart3-xfer {
 411                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 412                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 413                         };
 414
 415                         uart3_cts: uart3-cts {
 416                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 417                         };
 418
 419                         uart3_rts: uart3-rts {
 420                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 421                         };
 422                 };
 423
 424                 sd0 {
 425                         sd0_clk: sd0-clk {
 426                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 427                         };
 428
 429                         sd0_cmd: sd0-cmd {
 430                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 431                         };
 432
 433                         sd0_cd: sd0-cd {
 434                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 435                         };
 436
 437                         sd0_wp: sd0-wp {
 438                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 439                         };
 440
 441                         sd0_bus1: sd0-bus-width1 {
 442                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 443                         };
 444
 445                         sd0_bus4: sd0-bus-width4 {
 446                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 447                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 448                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 449                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 450                         };
 451                 };
 452
 453                 sd1 {
 454                         sd1_clk: sd1-clk {
 455                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 456                         };
 457
 458                         sd1_cmd: sd1-cmd {
 459                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 460                         };
 461
 462                         sd1_cd: sd1-cd {
 463                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 464                         };
 465
 466                         sd1_wp: sd1-wp {
 467                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 468                         };
 469
 470                         sd1_bus1: sd1-bus-width1 {
 471                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 472                         };
 473
 474                         sd1_bus4: sd1-bus-width4 {
 475                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 476                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 477                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 478                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 479                         };
 480                 };
 481
 482                 i2s0 {
 483                         i2s0_bus: i2s0-bus {
 484                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 485                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 486                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 487                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 488                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 489                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 490                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 491                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 492                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 493                         };
 494                 };
 495
 496                 i2s1 {
 497                         i2s1_bus: i2s1-bus {
 498                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 499                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 500                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 501                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 502                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 503                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 504                         };
 505                 };
 506
 507                 i2s2 {
 508                         i2s2_bus: i2s2-bus {
 509                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 510                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 511                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 512                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 513                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 514                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 515                         };
 516                 };
 517         };
 518 };
 519
 520 &i2c0 {
 521         pinctrl-names = "default";
 522         pinctrl-0 = <&i2c0_xfer>;
 523 };
 524
 525 &i2c1 {
 526         pinctrl-names = "default";
 527         pinctrl-0 = <&i2c1_xfer>;
 528 };
 529
 530 &i2c2 {
 531         pinctrl-names = "default";
 532         pinctrl-0 = <&i2c2_xfer>;
 533 };
 534
 535 &i2c3 {
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&i2c3_xfer>;
 538 };
 539
 540 &i2c4 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&i2c4_xfer>;
 543 };
 544
 545 &mmc0 {
 546         pinctrl-names = "default";
 547         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 548 };
 549
 550 &mmc1 {
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 553 };
 554
 555 &pwm0 {
 556         pinctrl-names = "default";
 557         pinctrl-0 = <&pwm0_out>;
 558 };
 559
 560 &pwm1 {
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&pwm1_out>;
 563 };
 564
 565 &pwm2 {
 566         pinctrl-names = "default";
 567         pinctrl-0 = <&pwm2_out>;
 568 };
 569
 570 &pwm3 {
 571         pinctrl-names = "default";
 572         pinctrl-0 = <&pwm3_out>;
 573 };
 574
 575 &spi0 {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 578 };
 579
 580 &spi1 {
 581         pinctrl-names = "default";
 582         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 583 };
 584
 585 &uart0 {
 586         pinctrl-names = "default";
 587         pinctrl-0 = <&uart0_xfer>;
 588 };
 589
 590 &uart1 {
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&uart1_xfer>;
 593 };
 594
 595 &uart2 {
 596         pinctrl-names = "default";
 597         pinctrl-0 = <&uart2_xfer>;
 598 };
 599
 600 &uart3 {
 601         pinctrl-names = "default";
 602         pinctrl-0 = <&uart3_xfer>;
 603 };
 604
 605 &wdt {
 606         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 607 };
 608
 609 &emac {
 610         compatible = "rockchip,rk3066-emac";
 611 };