sys/gnu/dts/arm/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 #include <dt-bindings/dma/sun4i-a10.h>
  18 #include <dt-bindings/pinctrl/sun4i-a10.h>
  19
  20 / {
  21         interrupt-parent = <&intc>;
  22
  23         aliases {
  24                 ethernet0 = &emac;
  25         };
  26
  27         chosen {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 ranges;
  31
  32                 framebuffer@0 {
  33                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  34                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  35                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  36                                  <&ahb_gates 44>;
  37                         status = "disabled";
  38                 };
  39
  40                 framebuffer@1 {
  41                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  42                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  43                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  44                                  <&ahb_gates 44>, <&ahb_gates 46>;
  45                         status = "disabled";
  46                 };
  47
  48                 framebuffer@2 {
  49                         compatible = "allwinner,simple-framebuffer",
  50                                      "simple-framebuffer";
  51                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  52                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  53                                  <&ahb_gates 46>;
  54                         status = "disabled";
  55                 };
  56
  57                 framebuffer@3 {
  58                         compatible = "allwinner,simple-framebuffer",
  59                                      "simple-framebuffer";
  60                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  61                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  62                                  <&ahb_gates 44>, <&ahb_gates 46>;
  63                         status = "disabled";
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70                 cpu0: cpu@0 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a8";
  73                         reg = <0x0>;
  74                         clocks = <&cpu>;
  75                         clock-latency = <244144>; /* 8 32k periods */
  76                         operating-points = <
  77                                 /* kHz    uV */
  78                                 1056000 1500000
  79                                 1008000 1400000
  80                                 912000  1350000
  81                                 864000  1300000
  82                                 624000  1250000
  83                                 >;
  84                         #cooling-cells = <2>;
  85                         cooling-min-level = <0>;
  86                         cooling-max-level = <4>;
  87                 };
  88         };
  89
  90         thermal-zones {
  91                 cpu_thermal {
  92                         /* milliseconds */
  93                         polling-delay-passive = <250>;
  94                         polling-delay = <1000>;
  95                         thermal-sensors = <&rtp>;
  96
  97                         cooling-maps {
  98                                 map0 {
  99                                         trip = <&cpu_alert0>;
 100                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 101                                 };
 102                         };
 103
 104                         trips {
 105                                 cpu_alert0: cpu_alert0 {
 106                                         /* milliCelsius */
 107                                         temperature = <850000>;
 108                                         hysteresis = <2000>;
 109                                         type = "passive";
 110                                 };
 111
 112                                 cpu_crit: cpu_crit {
 113                                         /* milliCelsius */
 114                                         temperature = <100000>;
 115                                         hysteresis = <2000>;
 116                                         type = "critical";
 117                                 };
 118                         };
 119                 };
 120         };
 121
 122         memory {
 123                 reg = <0x40000000 0x80000000>;
 124         };
 125
 126         clocks {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 ranges;
 130
 131                 /*
 132                  * This is a dummy clock, to be used as placeholder on
 133                  * other mux clocks when a specific parent clock is not
 134                  * yet implemented. It should be dropped when the driver
 135                  * is complete.
 136                  */
 137                 dummy: dummy {
 138                         #clock-cells = <0>;
 139                         compatible = "fixed-clock";
 140                         clock-frequency = <0>;
 141                 };
 142
 143                 osc24M: clk@01c20050 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-a10-osc-clk";
 146                         reg = <0x01c20050 0x4>;
 147                         clock-frequency = <24000000>;
 148                         clock-output-names = "osc24M";
 149                 };
 150
 151                 osc32k: clk@0 {
 152                         #clock-cells = <0>;
 153                         compatible = "fixed-clock";
 154                         clock-frequency = <32768>;
 155                         clock-output-names = "osc32k";
 156                 };
 157
 158                 pll1: clk@01c20000 {
 159                         #clock-cells = <0>;
 160                         compatible = "allwinner,sun4i-a10-pll1-clk";
 161                         reg = <0x01c20000 0x4>;
 162                         clocks = <&osc24M>;
 163                         clock-output-names = "pll1";
 164                 };
 165
 166                 pll4: clk@01c20018 {
 167                         #clock-cells = <0>;
 168                         compatible = "allwinner,sun4i-a10-pll1-clk";
 169                         reg = <0x01c20018 0x4>;
 170                         clocks = <&osc24M>;
 171                         clock-output-names = "pll4";
 172                 };
 173
 174                 pll5: clk@01c20020 {
 175                         #clock-cells = <1>;
 176                         compatible = "allwinner,sun4i-a10-pll5-clk";
 177                         reg = <0x01c20020 0x4>;
 178                         clocks = <&osc24M>;
 179                         clock-output-names = "pll5_ddr", "pll5_other";
 180                 };
 181
 182                 pll6: clk@01c20028 {
 183                         #clock-cells = <1>;
 184                         compatible = "allwinner,sun4i-a10-pll6-clk";
 185                         reg = <0x01c20028 0x4>;
 186                         clocks = <&osc24M>;
 187                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 188                 };
 189
 190                 /* dummy is 200M */
 191                 cpu: cpu@01c20054 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-cpu-clk";
 194                         reg = <0x01c20054 0x4>;
 195                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 196                         clock-output-names = "cpu";
 197                 };
 198
 199                 axi: axi@01c20054 {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun4i-a10-axi-clk";
 202                         reg = <0x01c20054 0x4>;
 203                         clocks = <&cpu>;
 204                         clock-output-names = "axi";
 205                 };
 206
 207                 axi_gates: clk@01c2005c {
 208                         #clock-cells = <1>;
 209                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 210                         reg = <0x01c2005c 0x4>;
 211                         clocks = <&axi>;
 212                         clock-output-names = "axi_dram";
 213                 };
 214
 215                 ahb: ahb@01c20054 {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun4i-a10-ahb-clk";
 218                         reg = <0x01c20054 0x4>;
 219                         clocks = <&axi>;
 220                         clock-output-names = "ahb";
 221                 };
 222
 223                 ahb_gates: clk@01c20060 {
 224                         #clock-cells = <1>;
 225                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 226                         reg = <0x01c20060 0x8>;
 227                         clocks = <&ahb>;
 228                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 229                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 230                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 231                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 232                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 233                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 234                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 235                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 236                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 237                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 238                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 239                 };
 240
 241                 apb0: apb0@01c20054 {
 242                         #clock-cells = <0>;
 243                         compatible = "allwinner,sun4i-a10-apb0-clk";
 244                         reg = <0x01c20054 0x4>;
 245                         clocks = <&ahb>;
 246                         clock-output-names = "apb0";
 247                 };
 248
 249                 apb0_gates: clk@01c20068 {
 250                         #clock-cells = <1>;
 251                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 252                         reg = <0x01c20068 0x4>;
 253                         clocks = <&apb0>;
 254                         clock-output-names = "apb0_codec", "apb0_spdif",
 255                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 256                                 "apb0_ir1", "apb0_keypad";
 257                 };
 258
 259                 apb1: clk@01c20058 {
 260                         #clock-cells = <0>;
 261                         compatible = "allwinner,sun4i-a10-apb1-clk";
 262                         reg = <0x01c20058 0x4>;
 263                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 264                         clock-output-names = "apb1";
 265                 };
 266
 267                 apb1_gates: clk@01c2006c {
 268                         #clock-cells = <1>;
 269                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 270                         reg = <0x01c2006c 0x4>;
 271                         clocks = <&apb1>;
 272                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 273                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 274                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 275                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 276                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 277                                 "apb1_uart7";
 278                 };
 279
 280                 nand_clk: clk@01c20080 {
 281                         #clock-cells = <0>;
 282                         compatible = "allwinner,sun4i-a10-mod0-clk";
 283                         reg = <0x01c20080 0x4>;
 284                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 285                         clock-output-names = "nand";
 286                 };
 287
 288                 ms_clk: clk@01c20084 {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun4i-a10-mod0-clk";
 291                         reg = <0x01c20084 0x4>;
 292                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 293                         clock-output-names = "ms";
 294                 };
 295
 296                 mmc0_clk: clk@01c20088 {
 297                         #clock-cells = <1>;
 298                         compatible = "allwinner,sun4i-a10-mmc-clk";
 299                         reg = <0x01c20088 0x4>;
 300                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 301                         clock-output-names = "mmc0",
 302                                              "mmc0_output",
 303                                              "mmc0_sample";
 304                 };
 305
 306                 mmc1_clk: clk@01c2008c {
 307                         #clock-cells = <1>;
 308                         compatible = "allwinner,sun4i-a10-mmc-clk";
 309                         reg = <0x01c2008c 0x4>;
 310                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 311                         clock-output-names = "mmc1",
 312                                              "mmc1_output",
 313                                              "mmc1_sample";
 314                 };
 315
 316                 mmc2_clk: clk@01c20090 {
 317                         #clock-cells = <1>;
 318                         compatible = "allwinner,sun4i-a10-mmc-clk";
 319                         reg = <0x01c20090 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "mmc2",
 322                                              "mmc2_output",
 323                                              "mmc2_sample";
 324                 };
 325
 326                 mmc3_clk: clk@01c20094 {
 327                         #clock-cells = <1>;
 328                         compatible = "allwinner,sun4i-a10-mmc-clk";
 329                         reg = <0x01c20094 0x4>;
 330                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 331                         clock-output-names = "mmc3",
 332                                              "mmc3_output",
 333                                              "mmc3_sample";
 334                 };
 335
 336                 ts_clk: clk@01c20098 {
 337                         #clock-cells = <0>;
 338                         compatible = "allwinner,sun4i-a10-mod0-clk";
 339                         reg = <0x01c20098 0x4>;
 340                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 341                         clock-output-names = "ts";
 342                 };
 343
 344                 ss_clk: clk@01c2009c {
 345                         #clock-cells = <0>;
 346                         compatible = "allwinner,sun4i-a10-mod0-clk";
 347                         reg = <0x01c2009c 0x4>;
 348                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 349                         clock-output-names = "ss";
 350                 };
 351
 352                 spi0_clk: clk@01c200a0 {
 353                         #clock-cells = <0>;
 354                         compatible = "allwinner,sun4i-a10-mod0-clk";
 355                         reg = <0x01c200a0 0x4>;
 356                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 357                         clock-output-names = "spi0";
 358                 };
 359
 360                 spi1_clk: clk@01c200a4 {
 361                         #clock-cells = <0>;
 362                         compatible = "allwinner,sun4i-a10-mod0-clk";
 363                         reg = <0x01c200a4 0x4>;
 364                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 365                         clock-output-names = "spi1";
 366                 };
 367
 368                 spi2_clk: clk@01c200a8 {
 369                         #clock-cells = <0>;
 370                         compatible = "allwinner,sun4i-a10-mod0-clk";
 371                         reg = <0x01c200a8 0x4>;
 372                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 373                         clock-output-names = "spi2";
 374                 };
 375
 376                 pata_clk: clk@01c200ac {
 377                         #clock-cells = <0>;
 378                         compatible = "allwinner,sun4i-a10-mod0-clk";
 379                         reg = <0x01c200ac 0x4>;
 380                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 381                         clock-output-names = "pata";
 382                 };
 383
 384                 ir0_clk: clk@01c200b0 {
 385                         #clock-cells = <0>;
 386                         compatible = "allwinner,sun4i-a10-mod0-clk";
 387                         reg = <0x01c200b0 0x4>;
 388                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 389                         clock-output-names = "ir0";
 390                 };
 391
 392                 ir1_clk: clk@01c200b4 {
 393                         #clock-cells = <0>;
 394                         compatible = "allwinner,sun4i-a10-mod0-clk";
 395                         reg = <0x01c200b4 0x4>;
 396                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 397                         clock-output-names = "ir1";
 398                 };
 399
 400                 usb_clk: clk@01c200cc {
 401                         #clock-cells = <1>;
 402                         #reset-cells = <1>;
 403                         compatible = "allwinner,sun4i-a10-usb-clk";
 404                         reg = <0x01c200cc 0x4>;
 405                         clocks = <&pll6 1>;
 406                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 407                 };
 408
 409                 spi3_clk: clk@01c200d4 {
 410                         #clock-cells = <0>;
 411                         compatible = "allwinner,sun4i-a10-mod0-clk";
 412                         reg = <0x01c200d4 0x4>;
 413                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 414                         clock-output-names = "spi3";
 415                 };
 416         };
 417
 418         soc@01c00000 {
 419                 compatible = "simple-bus";
 420                 #address-cells = <1>;
 421                 #size-cells = <1>;
 422                 ranges;
 423
 424                 dma: dma-controller@01c02000 {
 425                         compatible = "allwinner,sun4i-a10-dma";
 426                         reg = <0x01c02000 0x1000>;
 427                         interrupts = <27>;
 428                         clocks = <&ahb_gates 6>;
 429                         #dma-cells = <2>;
 430                 };
 431
 432                 spi0: spi@01c05000 {
 433                         compatible = "allwinner,sun4i-a10-spi";
 434                         reg = <0x01c05000 0x1000>;
 435                         interrupts = <10>;
 436                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 437                         clock-names = "ahb", "mod";
 438                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 439                                <&dma SUN4I_DMA_DEDICATED 26>;
 440                         dma-names = "rx", "tx";
 441                         status = "disabled";
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                 };
 445
 446                 spi1: spi@01c06000 {
 447                         compatible = "allwinner,sun4i-a10-spi";
 448                         reg = <0x01c06000 0x1000>;
 449                         interrupts = <11>;
 450                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 451                         clock-names = "ahb", "mod";
 452                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 453                                <&dma SUN4I_DMA_DEDICATED 8>;
 454                         dma-names = "rx", "tx";
 455                         status = "disabled";
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                 };
 459
 460                 emac: ethernet@01c0b000 {
 461                         compatible = "allwinner,sun4i-a10-emac";
 462                         reg = <0x01c0b000 0x1000>;
 463                         interrupts = <55>;
 464                         clocks = <&ahb_gates 17>;
 465                         status = "disabled";
 466                 };
 467
 468                 mdio: mdio@01c0b080 {
 469                         compatible = "allwinner,sun4i-a10-mdio";
 470                         reg = <0x01c0b080 0x14>;
 471                         status = "disabled";
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 mmc0: mmc@01c0f000 {
 477                         compatible = "allwinner,sun4i-a10-mmc";
 478                         reg = <0x01c0f000 0x1000>;
 479                         clocks = <&ahb_gates 8>,
 480                                  <&mmc0_clk 0>,
 481                                  <&mmc0_clk 1>,
 482                                  <&mmc0_clk 2>;
 483                         clock-names = "ahb",
 484                                       "mmc",
 485                                       "output",
 486                                       "sample";
 487                         interrupts = <32>;
 488                         status = "disabled";
 489                 };
 490
 491                 mmc1: mmc@01c10000 {
 492                         compatible = "allwinner,sun4i-a10-mmc";
 493                         reg = <0x01c10000 0x1000>;
 494                         clocks = <&ahb_gates 9>,
 495                                  <&mmc1_clk 0>,
 496                                  <&mmc1_clk 1>,
 497                                  <&mmc1_clk 2>;
 498                         clock-names = "ahb",
 499                                       "mmc",
 500                                       "output",
 501                                       "sample";
 502                         interrupts = <33>;
 503                         status = "disabled";
 504                 };
 505
 506                 mmc2: mmc@01c11000 {
 507                         compatible = "allwinner,sun4i-a10-mmc";
 508                         reg = <0x01c11000 0x1000>;
 509                         clocks = <&ahb_gates 10>,
 510                                  <&mmc2_clk 0>,
 511                                  <&mmc2_clk 1>,
 512                                  <&mmc2_clk 2>;
 513                         clock-names = "ahb",
 514                                       "mmc",
 515                                       "output",
 516                                       "sample";
 517                         interrupts = <34>;
 518                         status = "disabled";
 519                 };
 520
 521                 mmc3: mmc@01c12000 {
 522                         compatible = "allwinner,sun4i-a10-mmc";
 523                         reg = <0x01c12000 0x1000>;
 524                         clocks = <&ahb_gates 11>,
 525                                  <&mmc3_clk 0>,
 526                                  <&mmc3_clk 1>,
 527                                  <&mmc3_clk 2>;
 528                         clock-names = "ahb",
 529                                       "mmc",
 530                                       "output",
 531                                       "sample";
 532                         interrupts = <35>;
 533                         status = "disabled";
 534                 };
 535
 536                 usbphy: phy@01c13400 {
 537                         #phy-cells = <1>;
 538                         compatible = "allwinner,sun4i-a10-usb-phy";
 539                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 540                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 541                         clocks = <&usb_clk 8>;
 542                         clock-names = "usb_phy";
 543                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 544                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 545                         status = "disabled";
 546                 };
 547
 548                 ehci0: usb@01c14000 {
 549                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 550                         reg = <0x01c14000 0x100>;
 551                         interrupts = <39>;
 552                         clocks = <&ahb_gates 1>;
 553                         phys = <&usbphy 1>;
 554                         phy-names = "usb";
 555                         status = "disabled";
 556                 };
 557
 558                 ohci0: usb@01c14400 {
 559                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 560                         reg = <0x01c14400 0x100>;
 561                         interrupts = <64>;
 562                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 563                         phys = <&usbphy 1>;
 564                         phy-names = "usb";
 565                         status = "disabled";
 566                 };
 567
 568                 spi2: spi@01c17000 {
 569                         compatible = "allwinner,sun4i-a10-spi";
 570                         reg = <0x01c17000 0x1000>;
 571                         interrupts = <12>;
 572                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 573                         clock-names = "ahb", "mod";
 574                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 575                                <&dma SUN4I_DMA_DEDICATED 28>;
 576                         dma-names = "rx", "tx";
 577                         status = "disabled";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                 };
 581
 582                 ahci: sata@01c18000 {
 583                         compatible = "allwinner,sun4i-a10-ahci";
 584                         reg = <0x01c18000 0x1000>;
 585                         interrupts = <56>;
 586                         clocks = <&pll6 0>, <&ahb_gates 25>;
 587                         status = "disabled";
 588                 };
 589
 590                 ehci1: usb@01c1c000 {
 591                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 592                         reg = <0x01c1c000 0x100>;
 593                         interrupts = <40>;
 594                         clocks = <&ahb_gates 3>;
 595                         phys = <&usbphy 2>;
 596                         phy-names = "usb";
 597                         status = "disabled";
 598                 };
 599
 600                 ohci1: usb@01c1c400 {
 601                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 602                         reg = <0x01c1c400 0x100>;
 603                         interrupts = <65>;
 604                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 605                         phys = <&usbphy 2>;
 606                         phy-names = "usb";
 607                         status = "disabled";
 608                 };
 609
 610                 spi3: spi@01c1f000 {
 611                         compatible = "allwinner,sun4i-a10-spi";
 612                         reg = <0x01c1f000 0x1000>;
 613                         interrupts = <50>;
 614                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 615                         clock-names = "ahb", "mod";
 616                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 617                                <&dma SUN4I_DMA_DEDICATED 30>;
 618                         dma-names = "rx", "tx";
 619                         status = "disabled";
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                 };
 623
 624                 intc: interrupt-controller@01c20400 {
 625                         compatible = "allwinner,sun4i-a10-ic";
 626                         reg = <0x01c20400 0x400>;
 627                         interrupt-controller;
 628                         #interrupt-cells = <1>;
 629                 };
 630
 631                 pio: pinctrl@01c20800 {
 632                         compatible = "allwinner,sun4i-a10-pinctrl";
 633                         reg = <0x01c20800 0x400>;
 634                         interrupts = <28>;
 635                         clocks = <&apb0_gates 5>;
 636                         gpio-controller;
 637                         interrupt-controller;
 638                         #interrupt-cells = <2>;
 639                         #size-cells = <0>;
 640                         #gpio-cells = <3>;
 641
 642                         pwm0_pins_a: pwm0@0 {
 643                                 allwinner,pins = "PB2";
 644                                 allwinner,function = "pwm";
 645                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 646                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 647                         };
 648
 649                         pwm1_pins_a: pwm1@0 {
 650                                 allwinner,pins = "PI3";
 651                                 allwinner,function = "pwm";
 652                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 653                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 654                         };
 655
 656                         uart0_pins_a: uart0@0 {
 657                                 allwinner,pins = "PB22", "PB23";
 658                                 allwinner,function = "uart0";
 659                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 660                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 661                         };
 662
 663                         uart0_pins_b: uart0@1 {
 664                                 allwinner,pins = "PF2", "PF4";
 665                                 allwinner,function = "uart0";
 666                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 667                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 668                         };
 669
 670                         uart1_pins_a: uart1@0 {
 671                                 allwinner,pins = "PA10", "PA11";
 672                                 allwinner,function = "uart1";
 673                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 674                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 675                         };
 676
 677                         i2c0_pins_a: i2c0@0 {
 678                                 allwinner,pins = "PB0", "PB1";
 679                                 allwinner,function = "i2c0";
 680                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 681                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 682                         };
 683
 684                         i2c1_pins_a: i2c1@0 {
 685                                 allwinner,pins = "PB18", "PB19";
 686                                 allwinner,function = "i2c1";
 687                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 688                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 689                         };
 690
 691                         i2c2_pins_a: i2c2@0 {
 692                                 allwinner,pins = "PB20", "PB21";
 693                                 allwinner,function = "i2c2";
 694                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 695                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 696                         };
 697
 698                         emac_pins_a: emac0@0 {
 699                                 allwinner,pins = "PA0", "PA1", "PA2",
 700                                                 "PA3", "PA4", "PA5", "PA6",
 701                                                 "PA7", "PA8", "PA9", "PA10",
 702                                                 "PA11", "PA12", "PA13", "PA14",
 703                                                 "PA15", "PA16";
 704                                 allwinner,function = "emac";
 705                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 706                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 707                         };
 708
 709                         mmc0_pins_a: mmc0@0 {
 710                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 711                                 allwinner,function = "mmc0";
 712                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 713                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 714                         };
 715
 716                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 717                                 allwinner,pins = "PH1";
 718                                 allwinner,function = "gpio_in";
 719                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 720                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 721                         };
 722
 723                         ir0_pins_a: ir0@0 {
 724                                 allwinner,pins = "PB3","PB4";
 725                                 allwinner,function = "ir0";
 726                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 727                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 728                         };
 729
 730                         ir1_pins_a: ir1@0 {
 731                                 allwinner,pins = "PB22","PB23";
 732                                 allwinner,function = "ir1";
 733                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 734                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 735                         };
 736
 737                         spi0_pins_a: spi0@0 {
 738                                 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
 739                                 allwinner,function = "spi0";
 740                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 741                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 742                         };
 743
 744                         spi1_pins_a: spi1@0 {
 745                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 746                                 allwinner,function = "spi1";
 747                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 748                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 749                         };
 750
 751                         spi2_pins_a: spi2@0 {
 752                                 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
 753                                 allwinner,function = "spi2";
 754                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 755                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 756                         };
 757
 758                         spi2_pins_b: spi2@1 {
 759                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 760                                 allwinner,function = "spi2";
 761                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 762                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 763                         };
 764
 765                         ps20_pins_a: ps20@0 {
 766                                 allwinner,pins = "PI20", "PI21";
 767                                 allwinner,function = "ps2";
 768                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 769                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 770                         };
 771
 772                         ps21_pins_a: ps21@0 {
 773                                 allwinner,pins = "PH12", "PH13";
 774                                 allwinner,function = "ps2";
 775                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 776                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 777                         };
 778                 };
 779
 780                 timer@01c20c00 {
 781                         compatible = "allwinner,sun4i-a10-timer";
 782                         reg = <0x01c20c00 0x90>;
 783                         interrupts = <22>;
 784                         clocks = <&osc24M>;
 785                 };
 786
 787                 wdt: watchdog@01c20c90 {
 788                         compatible = "allwinner,sun4i-a10-wdt";
 789                         reg = <0x01c20c90 0x10>;
 790                 };
 791
 792                 rtc: rtc@01c20d00 {
 793                         compatible = "allwinner,sun4i-a10-rtc";
 794                         reg = <0x01c20d00 0x20>;
 795                         interrupts = <24>;
 796                 };
 797
 798                 pwm: pwm@01c20e00 {
 799                         compatible = "allwinner,sun4i-a10-pwm";
 800                         reg = <0x01c20e00 0xc>;
 801                         clocks = <&osc24M>;
 802                         #pwm-cells = <3>;
 803                         status = "disabled";
 804                 };
 805
 806                 ir0: ir@01c21800 {
 807                         compatible = "allwinner,sun4i-a10-ir";
 808                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 809                         clock-names = "apb", "ir";
 810                         interrupts = <5>;
 811                         reg = <0x01c21800 0x40>;
 812                         status = "disabled";
 813                 };
 814
 815                 ir1: ir@01c21c00 {
 816                         compatible = "allwinner,sun4i-a10-ir";
 817                         clocks = <&apb0_gates 7>, <&ir1_clk>;
 818                         clock-names = "apb", "ir";
 819                         interrupts = <6>;
 820                         reg = <0x01c21c00 0x40>;
 821                         status = "disabled";
 822                 };
 823
 824                 lradc: lradc@01c22800 {
 825                         compatible = "allwinner,sun4i-a10-lradc-keys";
 826                         reg = <0x01c22800 0x100>;
 827                         interrupts = <31>;
 828                         status = "disabled";
 829                 };
 830
 831                 sid: eeprom@01c23800 {
 832                         compatible = "allwinner,sun4i-a10-sid";
 833                         reg = <0x01c23800 0x10>;
 834                 };
 835
 836                 rtp: rtp@01c25000 {
 837                         compatible = "allwinner,sun4i-a10-ts";
 838                         reg = <0x01c25000 0x100>;
 839                         interrupts = <29>;
 840                         #thermal-sensor-cells = <0>;
 841                 };
 842
 843                 uart0: serial@01c28000 {
 844                         compatible = "snps,dw-apb-uart";
 845                         reg = <0x01c28000 0x400>;
 846                         interrupts = <1>;
 847                         reg-shift = <2>;
 848                         reg-io-width = <4>;
 849                         clocks = <&apb1_gates 16>;
 850                         status = "disabled";
 851                 };
 852
 853                 uart1: serial@01c28400 {
 854                         compatible = "snps,dw-apb-uart";
 855                         reg = <0x01c28400 0x400>;
 856                         interrupts = <2>;
 857                         reg-shift = <2>;
 858                         reg-io-width = <4>;
 859                         clocks = <&apb1_gates 17>;
 860                         status = "disabled";
 861                 };
 862
 863                 uart2: serial@01c28800 {
 864                         compatible = "snps,dw-apb-uart";
 865                         reg = <0x01c28800 0x400>;
 866                         interrupts = <3>;
 867                         reg-shift = <2>;
 868                         reg-io-width = <4>;
 869                         clocks = <&apb1_gates 18>;
 870                         status = "disabled";
 871                 };
 872
 873                 uart3: serial@01c28c00 {
 874                         compatible = "snps,dw-apb-uart";
 875                         reg = <0x01c28c00 0x400>;
 876                         interrupts = <4>;
 877                         reg-shift = <2>;
 878                         reg-io-width = <4>;
 879                         clocks = <&apb1_gates 19>;
 880                         status = "disabled";
 881                 };
 882
 883                 uart4: serial@01c29000 {
 884                         compatible = "snps,dw-apb-uart";
 885                         reg = <0x01c29000 0x400>;
 886                         interrupts = <17>;
 887                         reg-shift = <2>;
 888                         reg-io-width = <4>;
 889                         clocks = <&apb1_gates 20>;
 890                         status = "disabled";
 891                 };
 892
 893                 uart5: serial@01c29400 {
 894                         compatible = "snps,dw-apb-uart";
 895                         reg = <0x01c29400 0x400>;
 896                         interrupts = <18>;
 897                         reg-shift = <2>;
 898                         reg-io-width = <4>;
 899                         clocks = <&apb1_gates 21>;
 900                         status = "disabled";
 901                 };
 902
 903                 uart6: serial@01c29800 {
 904                         compatible = "snps,dw-apb-uart";
 905                         reg = <0x01c29800 0x400>;
 906                         interrupts = <19>;
 907                         reg-shift = <2>;
 908                         reg-io-width = <4>;
 909                         clocks = <&apb1_gates 22>;
 910                         status = "disabled";
 911                 };
 912
 913                 uart7: serial@01c29c00 {
 914                         compatible = "snps,dw-apb-uart";
 915                         reg = <0x01c29c00 0x400>;
 916                         interrupts = <20>;
 917                         reg-shift = <2>;
 918                         reg-io-width = <4>;
 919                         clocks = <&apb1_gates 23>;
 920                         status = "disabled";
 921                 };
 922
 923                 i2c0: i2c@01c2ac00 {
 924                         compatible = "allwinner,sun4i-a10-i2c";
 925                         reg = <0x01c2ac00 0x400>;
 926                         interrupts = <7>;
 927                         clocks = <&apb1_gates 0>;
 928                         status = "disabled";
 929                         #address-cells = <1>;
 930                         #size-cells = <0>;
 931                 };
 932
 933                 i2c1: i2c@01c2b000 {
 934                         compatible = "allwinner,sun4i-a10-i2c";
 935                         reg = <0x01c2b000 0x400>;
 936                         interrupts = <8>;
 937                         clocks = <&apb1_gates 1>;
 938                         status = "disabled";
 939                         #address-cells = <1>;
 940                         #size-cells = <0>;
 941                 };
 942
 943                 i2c2: i2c@01c2b400 {
 944                         compatible = "allwinner,sun4i-a10-i2c";
 945                         reg = <0x01c2b400 0x400>;
 946                         interrupts = <9>;
 947                         clocks = <&apb1_gates 2>;
 948                         status = "disabled";
 949                         #address-cells = <1>;
 950                         #size-cells = <0>;
 951                 };
 952
 953                 ps20: ps2@01c2a000 {
 954                         compatible = "allwinner,sun4i-a10-ps2";
 955                         reg = <0x01c2a000 0x400>;
 956                         interrupts = <62>;
 957                         clocks = <&apb1_gates 6>;
 958                         status = "disabled";
 959                 };
 960
 961                 ps21: ps2@01c2a400 {
 962                         compatible = "allwinner,sun4i-a10-ps2";
 963                         reg = <0x01c2a400 0x400>;
 964                         interrupts = <63>;
 965                         clocks = <&apb1_gates 7>;
 966                         status = "disabled";
 967                 };
 968         };
 969 };