2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 * Manages physical address maps.
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
101 #include "opt_pmap.h"
103 #include "opt_xbox.h"
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
124 #include <sys/cpuset.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_object.h>
133 #include <vm/vm_extern.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_pager.h>
136 #include <vm/vm_phys.h>
137 #include <vm/vm_radix.h>
138 #include <vm/vm_reserv.h>
143 #include <machine/intr_machdep.h>
144 #include <machine/apicvar.h>
146 #include <machine/cpu.h>
147 #include <machine/cputypes.h>
148 #include <machine/md_var.h>
149 #include <machine/pcb.h>
150 #include <machine/specialreg.h>
152 #include <machine/smp.h>
156 #include <machine/xbox.h>
159 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
160 #define CPU_ENABLE_SSE
163 #ifndef PMAP_SHPGPERPROC
164 #define PMAP_SHPGPERPROC 200
167 #if !defined(DIAGNOSTIC)
168 #ifdef __GNUC_GNU_INLINE__
169 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
171 #define PMAP_INLINE extern inline
178 #define PV_STAT(x) do { x ; } while (0)
180 #define PV_STAT(x) do { } while (0)
183 #define pa_index(pa) ((pa) >> PDRSHIFT)
184 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
187 * Get PDEs and PTEs for user/kernel address space
189 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
190 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
192 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
193 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
194 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
195 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
196 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
198 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
199 atomic_clear_int((u_int *)(pte), PG_W))
200 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
202 struct pmap kernel_pmap_store;
203 LIST_HEAD(pmaplist, pmap);
204 static struct pmaplist allpmaps;
205 static struct mtx allpmaps_lock;
207 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
208 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
209 int pgeflag = 0; /* PG_G or-in */
210 int pseflag = 0; /* PG_PS or-in */
212 static int nkpt = NKPT;
213 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
214 extern u_int32_t KERNend;
215 extern u_int32_t KPTphys;
217 #if defined(PAE) || defined(PAE_TABLES)
219 static uma_zone_t pdptzone;
222 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
224 static int pat_works = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
226 "Is page attribute table fully functional?");
228 static int pg_ps_enabled = 1;
229 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
230 "Are large page mappings enabled?");
232 #define PAT_INDEX_SIZE 8
233 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
235 static struct rwlock_padalign pvh_global_lock;
238 * Data for the pv entry allocation mechanism
240 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
241 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
242 static struct md_page *pv_table;
243 static int shpgperproc = PMAP_SHPGPERPROC;
245 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
246 int pv_maxchunks; /* How many chunks we have KVA for */
247 vm_offset_t pv_vafree; /* freelist stored in the PTE */
250 * All those kernel PT submaps that BSD is so fond of
259 static struct sysmaps sysmaps_pcpu[MAXCPU];
261 static pd_entry_t *KPTD;
264 struct msgbuf *msgbufp = 0;
269 static caddr_t crashdumpmap;
271 static pt_entry_t *PMAP1 = 0, *PMAP2;
272 static pt_entry_t *PADDR1 = 0, *PADDR2;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
314 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
315 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #if defined(PAE) || defined(PAE_TABLES)
343 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
345 static void pmap_set_pg(void);
347 static __inline void pagezero(void *page);
349 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
350 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
353 * If you get an error here, then you set KVA_PAGES wrong! See the
354 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
355 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
357 CTASSERT(KERNBASE % (1 << 24) == 0);
360 * Bootstrap the system enough to run with virtual memory.
362 * On the i386 this is called after mapping has already been enabled
363 * and just syncs the pmap module with what has already been done.
364 * [We can't call it easily with mapping off since the kernel is not
365 * mapped with PA == VA, hence we would have to relocate every address
366 * from the linked base (virtual) address "KERNBASE" to the actual
367 * (physical) address starting relative to 0]
370 pmap_bootstrap(vm_paddr_t firstaddr)
373 pt_entry_t *pte, *unused;
374 struct sysmaps *sysmaps;
378 * Add a physical memory segment (vm_phys_seg) corresponding to the
379 * preallocated kernel page table pages so that vm_page structures
380 * representing these pages will be created. The vm_page structures
381 * are required for promotion of the corresponding kernel virtual
382 * addresses to superpage mappings.
384 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
387 * Initialize the first available kernel virtual address. However,
388 * using "firstaddr" may waste a few pages of the kernel virtual
389 * address space, because locore may not have mapped every physical
390 * page that it allocated. Preferably, locore would provide a first
391 * unused virtual address in addition to "firstaddr".
393 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
395 virtual_end = VM_MAX_KERNEL_ADDRESS;
398 * Initialize the kernel pmap (which is statically allocated).
400 PMAP_LOCK_INIT(kernel_pmap);
401 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
402 #if defined(PAE) || defined(PAE_TABLES)
403 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
405 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
406 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
409 * Initialize the global pv list lock.
411 rw_init(&pvh_global_lock, "pmap pv global");
413 LIST_INIT(&allpmaps);
416 * Request a spin mutex so that changes to allpmaps cannot be
417 * preempted by smp_rendezvous_cpus(). Otherwise,
418 * pmap_update_pde_kernel() could access allpmaps while it is
421 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
422 mtx_lock_spin(&allpmaps_lock);
423 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
424 mtx_unlock_spin(&allpmaps_lock);
427 * Reserve some special page table entries/VA space for temporary
430 #define SYSMAP(c, p, v, n) \
431 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
437 * CMAP1/CMAP2 are used for zeroing and copying pages.
438 * CMAP3 is used for the idle process page zeroing.
440 for (i = 0; i < MAXCPU; i++) {
441 sysmaps = &sysmaps_pcpu[i];
442 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
443 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
444 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
446 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
451 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
454 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
456 SYSMAP(caddr_t, unused, ptvmmap, 1)
459 * msgbufp is used to map the system message buffer.
461 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
464 * KPTmap is used by pmap_kextract().
466 * KPTmap is first initialized by locore. However, that initial
467 * KPTmap can only support NKPT page table pages. Here, a larger
468 * KPTmap is created that can support KVA_PAGES page table pages.
470 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
472 for (i = 0; i < NKPT; i++)
473 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
476 * Adjust the start of the KPTD and KPTmap so that the implementation
477 * of pmap_kextract() and pmap_growkernel() can be made simpler.
480 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
483 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
486 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
487 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
489 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
494 * Leave in place an identity mapping (virt == phys) for the low 1 MB
495 * physical memory region that is used by the ACPI wakeup code. This
496 * mapping must not have PG_G set.
499 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
500 * an early stadium, we cannot yet neatly map video memory ... :-(
501 * Better fixes are very welcome! */
502 if (!arch_i386_is_xbox)
504 for (i = 1; i < NKPT; i++)
507 /* Initialize the PAT MSR if present. */
510 /* Turn on PG_G on kernel page(s) */
520 int pat_table[PAT_INDEX_SIZE];
525 /* Set default PAT index table. */
526 for (i = 0; i < PAT_INDEX_SIZE; i++)
528 pat_table[PAT_WRITE_BACK] = 0;
529 pat_table[PAT_WRITE_THROUGH] = 1;
530 pat_table[PAT_UNCACHEABLE] = 3;
531 pat_table[PAT_WRITE_COMBINING] = 3;
532 pat_table[PAT_WRITE_PROTECTED] = 3;
533 pat_table[PAT_UNCACHED] = 3;
535 /* Bail if this CPU doesn't implement PAT. */
536 if ((cpu_feature & CPUID_PAT) == 0) {
537 for (i = 0; i < PAT_INDEX_SIZE; i++)
538 pat_index[i] = pat_table[i];
544 * Due to some Intel errata, we can only safely use the lower 4
547 * Intel Pentium III Processor Specification Update
548 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
551 * Intel Pentium IV Processor Specification Update
552 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
554 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
555 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
558 /* Initialize default PAT entries. */
559 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
560 PAT_VALUE(1, PAT_WRITE_THROUGH) |
561 PAT_VALUE(2, PAT_UNCACHED) |
562 PAT_VALUE(3, PAT_UNCACHEABLE) |
563 PAT_VALUE(4, PAT_WRITE_BACK) |
564 PAT_VALUE(5, PAT_WRITE_THROUGH) |
565 PAT_VALUE(6, PAT_UNCACHED) |
566 PAT_VALUE(7, PAT_UNCACHEABLE);
570 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
571 * Program 5 and 6 as WP and WC.
572 * Leave 4 and 7 as WB and UC.
574 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
575 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
576 PAT_VALUE(6, PAT_WRITE_COMBINING);
577 pat_table[PAT_UNCACHED] = 2;
578 pat_table[PAT_WRITE_PROTECTED] = 5;
579 pat_table[PAT_WRITE_COMBINING] = 6;
582 * Just replace PAT Index 2 with WC instead of UC-.
584 pat_msr &= ~PAT_MASK(2);
585 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
586 pat_table[PAT_WRITE_COMBINING] = 2;
591 load_cr4(cr4 & ~CR4_PGE);
593 /* Disable caches (CD = 1, NW = 0). */
595 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
597 /* Flushes caches and TLBs. */
601 /* Update PAT and index table. */
602 wrmsr(MSR_PAT, pat_msr);
603 for (i = 0; i < PAT_INDEX_SIZE; i++)
604 pat_index[i] = pat_table[i];
606 /* Flush caches and TLBs again. */
610 /* Restore caches and PGE. */
616 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
622 vm_offset_t va, endva;
627 endva = KERNBASE + KERNend;
630 va = KERNBASE + KERNLOAD;
632 pdir_pde(PTD, va) |= pgeflag;
633 invltlb(); /* Play it safe, invltlb() every time */
637 va = (vm_offset_t)btext;
642 invltlb(); /* Play it safe, invltlb() every time */
649 * Initialize a vm_page's machine-dependent fields.
652 pmap_page_init(vm_page_t m)
655 TAILQ_INIT(&m->md.pv_list);
656 m->md.pat_mode = PAT_WRITE_BACK;
659 #if defined(PAE) || defined(PAE_TABLES)
661 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
664 /* Inform UMA that this allocator uses kernel_map/object. */
665 *flags = UMA_SLAB_KERNEL;
666 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
667 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
672 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
674 * - Must deal with pages in order to ensure that none of the PG_* bits
675 * are ever set, PG_V in particular.
676 * - Assumes we can write to ptes without pte_store() atomic ops, even
677 * on PAE systems. This should be ok.
678 * - Assumes nothing will ever test these addresses for 0 to indicate
679 * no mapping instead of correctly checking PG_V.
680 * - Assumes a vm_offset_t will fit in a pte (true for i386).
681 * Because PG_V is never set, there can be no mappings to invalidate.
684 pmap_ptelist_alloc(vm_offset_t *head)
691 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
695 panic("pmap_ptelist_alloc: va with PG_V set!");
701 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
706 panic("pmap_ptelist_free: freeing va with PG_V set!");
708 *pte = *head; /* virtual! PG_V is 0 though */
713 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
719 for (i = npages - 1; i >= 0; i--) {
720 va = (vm_offset_t)base + i * PAGE_SIZE;
721 pmap_ptelist_free(head, va);
727 * Initialize the pmap module.
728 * Called by vm_init, to initialize any structures that the pmap
729 * system needs to map virtual memory.
739 * Initialize the vm page array entries for the kernel pmap's
742 for (i = 0; i < NKPT; i++) {
743 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
744 KASSERT(mpte >= vm_page_array &&
745 mpte < &vm_page_array[vm_page_array_size],
746 ("pmap_init: page table page is out of range"));
747 mpte->pindex = i + KPTDI;
748 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
752 * Initialize the address space (zone) for the pv entries. Set a
753 * high water mark so that the system can recover from excessive
754 * numbers of pv entries.
756 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
757 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
758 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
759 pv_entry_max = roundup(pv_entry_max, _NPCPV);
760 pv_entry_high_water = 9 * (pv_entry_max / 10);
763 * If the kernel is running on a virtual machine, then it must assume
764 * that MCA is enabled by the hypervisor. Moreover, the kernel must
765 * be prepared for the hypervisor changing the vendor and family that
766 * are reported by CPUID. Consequently, the workaround for AMD Family
767 * 10h Erratum 383 is enabled if the processor's feature set does not
768 * include at least one feature that is only supported by older Intel
769 * or newer AMD processors.
771 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
772 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
773 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
775 workaround_erratum383 = 1;
778 * Are large page mappings supported and enabled?
780 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
783 else if (pg_ps_enabled) {
784 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
785 ("pmap_init: can't assign to pagesizes[1]"));
786 pagesizes[1] = NBPDR;
790 * Calculate the size of the pv head table for superpages.
791 * Handle the possibility that "vm_phys_segs[...].end" is zero.
793 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
794 PAGE_SIZE) / NBPDR + 1;
797 * Allocate memory for the pv head table for superpages.
799 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
801 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
803 for (i = 0; i < pv_npg; i++)
804 TAILQ_INIT(&pv_table[i].pv_list);
806 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
807 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
808 if (pv_chunkbase == NULL)
809 panic("pmap_init: not enough kvm for pv chunks");
810 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
811 #if defined(PAE) || defined(PAE_TABLES)
812 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
813 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
814 UMA_ZONE_VM | UMA_ZONE_NOFREE);
815 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
820 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
821 "Max number of PV entries");
822 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
823 "Page share factor per proc");
825 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
826 "2/4MB page mapping counters");
828 static u_long pmap_pde_demotions;
829 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
830 &pmap_pde_demotions, 0, "2/4MB page demotions");
832 static u_long pmap_pde_mappings;
833 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
834 &pmap_pde_mappings, 0, "2/4MB page mappings");
836 static u_long pmap_pde_p_failures;
837 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
838 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
840 static u_long pmap_pde_promotions;
841 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
842 &pmap_pde_promotions, 0, "2/4MB page promotions");
844 /***************************************************
845 * Low level helper routines.....
846 ***************************************************/
849 * Determine the appropriate bits to set in a PTE or PDE for a specified
853 pmap_cache_bits(int mode, boolean_t is_pde)
855 int cache_bits, pat_flag, pat_idx;
857 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
858 panic("Unknown caching mode %d\n", mode);
860 /* The PAT bit is different for PTE's and PDE's. */
861 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
863 /* Map the caching mode to a PAT index. */
864 pat_idx = pat_index[mode];
866 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
869 cache_bits |= pat_flag;
871 cache_bits |= PG_NC_PCD;
873 cache_bits |= PG_NC_PWT;
878 * The caller is responsible for maintaining TLB consistency.
881 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
885 boolean_t PTD_updated;
888 mtx_lock_spin(&allpmaps_lock);
889 LIST_FOREACH(pmap, &allpmaps, pm_list) {
890 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
893 pde = pmap_pde(pmap, va);
894 pde_store(pde, newpde);
896 mtx_unlock_spin(&allpmaps_lock);
898 ("pmap_kenter_pde: current page table is not in allpmaps"));
902 * After changing the page size for the specified virtual address in the page
903 * table, flush the corresponding entries from the processor's TLB. Only the
904 * calling processor's TLB is affected.
906 * The calling thread must be pinned to a processor.
909 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
913 if ((newpde & PG_PS) == 0)
914 /* Demotion: flush a specific 2MB page mapping. */
916 else if ((newpde & PG_G) == 0)
918 * Promotion: flush every 4KB page mapping from the TLB
919 * because there are too many to flush individually.
924 * Promotion: flush every 4KB page mapping from the TLB,
925 * including any global (PG_G) mappings.
928 load_cr4(cr4 & ~CR4_PGE);
930 * Although preemption at this point could be detrimental to
931 * performance, it would not lead to an error. PG_G is simply
932 * ignored if CR4.PGE is clear. Moreover, in case this block
933 * is re-entered, the load_cr4() either above or below will
934 * modify CR4.PGE flushing the TLB.
936 load_cr4(cr4 | CR4_PGE);
941 * For SMP, these functions have to use the IPI mechanism for coherence.
943 * N.B.: Before calling any of the following TLB invalidation functions,
944 * the calling processor must ensure that all stores updating a non-
945 * kernel page table are globally performed. Otherwise, another
946 * processor could cache an old, pre-update entry without being
947 * invalidated. This can happen one of two ways: (1) The pmap becomes
948 * active on another processor after its pm_active field is checked by
949 * one of the following functions but before a store updating the page
950 * table is globally performed. (2) The pmap becomes active on another
951 * processor before its pm_active field is checked but due to
952 * speculative loads one of the following functions stills reads the
953 * pmap as inactive on the other processor.
955 * The kernel page table is exempt because its pm_active field is
956 * immutable. The kernel page table is always active on every
960 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
966 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
970 cpuid = PCPU_GET(cpuid);
971 other_cpus = all_cpus;
972 CPU_CLR(cpuid, &other_cpus);
973 if (CPU_ISSET(cpuid, &pmap->pm_active))
975 CPU_AND(&other_cpus, &pmap->pm_active);
976 if (!CPU_EMPTY(&other_cpus))
977 smp_masked_invlpg(other_cpus, va);
983 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
990 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
991 for (addr = sva; addr < eva; addr += PAGE_SIZE)
993 smp_invlpg_range(sva, eva);
995 cpuid = PCPU_GET(cpuid);
996 other_cpus = all_cpus;
997 CPU_CLR(cpuid, &other_cpus);
998 if (CPU_ISSET(cpuid, &pmap->pm_active))
999 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1001 CPU_AND(&other_cpus, &pmap->pm_active);
1002 if (!CPU_EMPTY(&other_cpus))
1003 smp_masked_invlpg_range(other_cpus, sva, eva);
1009 pmap_invalidate_all(pmap_t pmap)
1011 cpuset_t other_cpus;
1015 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1019 cpuid = PCPU_GET(cpuid);
1020 other_cpus = all_cpus;
1021 CPU_CLR(cpuid, &other_cpus);
1022 if (CPU_ISSET(cpuid, &pmap->pm_active))
1024 CPU_AND(&other_cpus, &pmap->pm_active);
1025 if (!CPU_EMPTY(&other_cpus))
1026 smp_masked_invltlb(other_cpus);
1032 pmap_invalidate_cache(void)
1042 cpuset_t invalidate; /* processors that invalidate their TLB */
1046 u_int store; /* processor that updates the PDE */
1050 pmap_update_pde_kernel(void *arg)
1052 struct pde_action *act = arg;
1056 if (act->store == PCPU_GET(cpuid)) {
1059 * Elsewhere, this operation requires allpmaps_lock for
1060 * synchronization. Here, it does not because it is being
1061 * performed in the context of an all_cpus rendezvous.
1063 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1064 pde = pmap_pde(pmap, act->va);
1065 pde_store(pde, act->newpde);
1071 pmap_update_pde_user(void *arg)
1073 struct pde_action *act = arg;
1075 if (act->store == PCPU_GET(cpuid))
1076 pde_store(act->pde, act->newpde);
1080 pmap_update_pde_teardown(void *arg)
1082 struct pde_action *act = arg;
1084 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1085 pmap_update_pde_invalidate(act->va, act->newpde);
1089 * Change the page size for the specified virtual address in a way that
1090 * prevents any possibility of the TLB ever having two entries that map the
1091 * same virtual address using different page sizes. This is the recommended
1092 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1093 * machine check exception for a TLB state that is improperly diagnosed as a
1097 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1099 struct pde_action act;
1100 cpuset_t active, other_cpus;
1104 cpuid = PCPU_GET(cpuid);
1105 other_cpus = all_cpus;
1106 CPU_CLR(cpuid, &other_cpus);
1107 if (pmap == kernel_pmap)
1110 active = pmap->pm_active;
1111 if (CPU_OVERLAP(&active, &other_cpus)) {
1113 act.invalidate = active;
1116 act.newpde = newpde;
1117 CPU_SET(cpuid, &active);
1118 smp_rendezvous_cpus(active,
1119 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1120 pmap_update_pde_kernel : pmap_update_pde_user,
1121 pmap_update_pde_teardown, &act);
1123 if (pmap == kernel_pmap)
1124 pmap_kenter_pde(va, newpde);
1126 pde_store(pde, newpde);
1127 if (CPU_ISSET(cpuid, &active))
1128 pmap_update_pde_invalidate(va, newpde);
1134 * Normal, non-SMP, 486+ invalidation functions.
1135 * We inline these within pmap.c for speed.
1138 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1141 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1146 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1150 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1151 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1156 pmap_invalidate_all(pmap_t pmap)
1159 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1164 pmap_invalidate_cache(void)
1171 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1174 if (pmap == kernel_pmap)
1175 pmap_kenter_pde(va, newpde);
1177 pde_store(pde, newpde);
1178 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1179 pmap_update_pde_invalidate(va, newpde);
1183 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1186 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1190 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1192 KASSERT((sva & PAGE_MASK) == 0,
1193 ("pmap_invalidate_cache_range: sva not page-aligned"));
1194 KASSERT((eva & PAGE_MASK) == 0,
1195 ("pmap_invalidate_cache_range: eva not page-aligned"));
1198 if ((cpu_feature & CPUID_SS) != 0 && !force)
1199 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1200 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1201 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1205 * XXX: Some CPUs fault, hang, or trash the local APIC
1206 * registers if we use CLFLUSH on the local APIC
1207 * range. The local APIC is always uncached, so we
1208 * don't need to flush for that range anyway.
1210 if (pmap_kextract(sva) == lapic_paddr)
1214 * Otherwise, do per-cache line flush. Use the mfence
1215 * instruction to insure that previous stores are
1216 * included in the write-back. The processor
1217 * propagates flush to other processors in the cache
1221 for (; sva < eva; sva += cpu_clflush_line_size)
1227 * No targeted cache flush methods are supported by CPU,
1228 * or the supplied range is bigger than 2MB.
1229 * Globally invalidate cache.
1231 pmap_invalidate_cache();
1236 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1240 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1241 (cpu_feature & CPUID_CLFSH) == 0) {
1242 pmap_invalidate_cache();
1244 for (i = 0; i < count; i++)
1245 pmap_flush_page(pages[i]);
1250 * Are we current address space or kernel? N.B. We return FALSE when
1251 * a pmap's page table is in use because a kernel thread is borrowing
1252 * it. The borrowed page table can change spontaneously, making any
1253 * dependence on its continued use subject to a race condition.
1256 pmap_is_current(pmap_t pmap)
1259 return (pmap == kernel_pmap ||
1260 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1261 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1265 * If the given pmap is not the current or kernel pmap, the returned pte must
1266 * be released by passing it to pmap_pte_release().
1269 pmap_pte(pmap_t pmap, vm_offset_t va)
1274 pde = pmap_pde(pmap, va);
1278 /* are we current address space or kernel? */
1279 if (pmap_is_current(pmap))
1280 return (vtopte(va));
1281 mtx_lock(&PMAP2mutex);
1282 newpf = *pde & PG_FRAME;
1283 if ((*PMAP2 & PG_FRAME) != newpf) {
1284 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1285 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1287 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1293 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1296 static __inline void
1297 pmap_pte_release(pt_entry_t *pte)
1300 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1301 mtx_unlock(&PMAP2mutex);
1305 * NB: The sequence of updating a page table followed by accesses to the
1306 * corresponding pages is subject to the situation described in the "AMD64
1307 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1308 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1309 * right after modifying the PTE bits is crucial.
1311 static __inline void
1312 invlcaddr(void *caddr)
1315 invlpg((u_int)caddr);
1319 * Super fast pmap_pte routine best used when scanning
1320 * the pv lists. This eliminates many coarse-grained
1321 * invltlb calls. Note that many of the pv list
1322 * scans are across different pmaps. It is very wasteful
1323 * to do an entire invltlb for checking a single mapping.
1325 * If the given pmap is not the current pmap, pvh_global_lock
1326 * must be held and curthread pinned to a CPU.
1329 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1334 pde = pmap_pde(pmap, va);
1338 /* are we current address space or kernel? */
1339 if (pmap_is_current(pmap))
1340 return (vtopte(va));
1341 rw_assert(&pvh_global_lock, RA_WLOCKED);
1342 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1343 newpf = *pde & PG_FRAME;
1344 if ((*PMAP1 & PG_FRAME) != newpf) {
1345 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1347 PMAP1cpu = PCPU_GET(cpuid);
1353 if (PMAP1cpu != PCPU_GET(cpuid)) {
1354 PMAP1cpu = PCPU_GET(cpuid);
1360 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1366 * Routine: pmap_extract
1368 * Extract the physical page address associated
1369 * with the given map/virtual_address pair.
1372 pmap_extract(pmap_t pmap, vm_offset_t va)
1380 pde = pmap->pm_pdir[va >> PDRSHIFT];
1382 if ((pde & PG_PS) != 0)
1383 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1385 pte = pmap_pte(pmap, va);
1386 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1387 pmap_pte_release(pte);
1395 * Routine: pmap_extract_and_hold
1397 * Atomically extract and hold the physical page
1398 * with the given pmap and virtual address pair
1399 * if that mapping permits the given protection.
1402 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1405 pt_entry_t pte, *ptep;
1413 pde = *pmap_pde(pmap, va);
1416 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1417 if (vm_page_pa_tryrelock(pmap, (pde &
1418 PG_PS_FRAME) | (va & PDRMASK), &pa))
1420 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1425 ptep = pmap_pte(pmap, va);
1427 pmap_pte_release(ptep);
1429 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1430 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1433 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1443 /***************************************************
1444 * Low level mapping routines.....
1445 ***************************************************/
1448 * Add a wired page to the kva.
1449 * Note: not SMP coherent.
1451 * This function may be used before pmap_bootstrap() is called.
1454 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1459 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1462 static __inline void
1463 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1468 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1472 * Remove a page from the kernel pagetables.
1473 * Note: not SMP coherent.
1475 * This function may be used before pmap_bootstrap() is called.
1478 pmap_kremove(vm_offset_t va)
1487 * Used to map a range of physical addresses into kernel
1488 * virtual address space.
1490 * The value passed in '*virt' is a suggested virtual address for
1491 * the mapping. Architectures which can support a direct-mapped
1492 * physical to virtual region can return the appropriate address
1493 * within that region, leaving '*virt' unchanged. Other
1494 * architectures should map the pages starting at '*virt' and
1495 * update '*virt' with the first usable address after the mapped
1499 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1501 vm_offset_t va, sva;
1502 vm_paddr_t superpage_offset;
1507 * Does the physical address range's size and alignment permit at
1508 * least one superpage mapping to be created?
1510 superpage_offset = start & PDRMASK;
1511 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1513 * Increase the starting virtual address so that its alignment
1514 * does not preclude the use of superpage mappings.
1516 if ((va & PDRMASK) < superpage_offset)
1517 va = (va & ~PDRMASK) + superpage_offset;
1518 else if ((va & PDRMASK) > superpage_offset)
1519 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1522 while (start < end) {
1523 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1525 KASSERT((va & PDRMASK) == 0,
1526 ("pmap_map: misaligned va %#x", va));
1527 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1528 pmap_kenter_pde(va, newpde);
1532 pmap_kenter(va, start);
1537 pmap_invalidate_range(kernel_pmap, sva, va);
1544 * Add a list of wired pages to the kva
1545 * this routine is only used for temporary
1546 * kernel mappings that do not need to have
1547 * page modification or references recorded.
1548 * Note that old mappings are simply written
1549 * over. The page *must* be wired.
1550 * Note: SMP coherent. Uses a ranged shootdown IPI.
1553 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1555 pt_entry_t *endpte, oldpte, pa, *pte;
1560 endpte = pte + count;
1561 while (pte < endpte) {
1563 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1564 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1566 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1570 if (__predict_false((oldpte & PG_V) != 0))
1571 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1576 * This routine tears out page mappings from the
1577 * kernel -- it is meant only for temporary mappings.
1578 * Note: SMP coherent. Uses a ranged shootdown IPI.
1581 pmap_qremove(vm_offset_t sva, int count)
1586 while (count-- > 0) {
1590 pmap_invalidate_range(kernel_pmap, sva, va);
1593 /***************************************************
1594 * Page table page management routines.....
1595 ***************************************************/
1596 static __inline void
1597 pmap_free_zero_pages(struct spglist *free)
1601 while ((m = SLIST_FIRST(free)) != NULL) {
1602 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1603 /* Preserve the page's PG_ZERO setting. */
1604 vm_page_free_toq(m);
1609 * Schedule the specified unused page table page to be freed. Specifically,
1610 * add the page to the specified list of pages that will be released to the
1611 * physical memory manager after the TLB has been updated.
1613 static __inline void
1614 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1615 boolean_t set_PG_ZERO)
1619 m->flags |= PG_ZERO;
1621 m->flags &= ~PG_ZERO;
1622 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1626 * Inserts the specified page table page into the specified pmap's collection
1627 * of idle page table pages. Each of a pmap's page table pages is responsible
1628 * for mapping a distinct range of virtual addresses. The pmap's collection is
1629 * ordered by this virtual address range.
1632 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1635 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1636 return (vm_radix_insert(&pmap->pm_root, mpte));
1640 * Looks for a page table page mapping the specified virtual address in the
1641 * specified pmap's collection of idle page table pages. Returns NULL if there
1642 * is no page table page corresponding to the specified virtual address.
1644 static __inline vm_page_t
1645 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1648 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1649 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1653 * Removes the specified page table page from the specified pmap's collection
1654 * of idle page table pages. The specified page table page must be a member of
1655 * the pmap's collection.
1657 static __inline void
1658 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1661 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1662 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1666 * Decrements a page table page's wire count, which is used to record the
1667 * number of valid page table entries within the page. If the wire count
1668 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1669 * page table page was unmapped and FALSE otherwise.
1671 static inline boolean_t
1672 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1676 if (m->wire_count == 0) {
1677 _pmap_unwire_ptp(pmap, m, free);
1684 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1689 * unmap the page table page
1691 pmap->pm_pdir[m->pindex] = 0;
1692 --pmap->pm_stats.resident_count;
1695 * This is a release store so that the ordinary store unmapping
1696 * the page table page is globally performed before TLB shoot-
1699 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1702 * Do an invltlb to make the invalidated mapping
1703 * take effect immediately.
1705 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1706 pmap_invalidate_page(pmap, pteva);
1709 * Put page on a list so that it is released after
1710 * *ALL* TLB shootdown is done
1712 pmap_add_delayed_free_list(m, free, TRUE);
1716 * After removing a page table entry, this routine is used to
1717 * conditionally free the page, and manage the hold/wire counts.
1720 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1725 if (va >= VM_MAXUSER_ADDRESS)
1727 ptepde = *pmap_pde(pmap, va);
1728 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1729 return (pmap_unwire_ptp(pmap, mpte, free));
1733 * Initialize the pmap for the swapper process.
1736 pmap_pinit0(pmap_t pmap)
1739 PMAP_LOCK_INIT(pmap);
1741 * Since the page table directory is shared with the kernel pmap,
1742 * which is already included in the list "allpmaps", this pmap does
1743 * not need to be inserted into that list.
1745 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1746 #if defined(PAE) || defined(PAE_TABLES)
1747 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1749 pmap->pm_root.rt_root = 0;
1750 CPU_ZERO(&pmap->pm_active);
1751 PCPU_SET(curpmap, pmap);
1752 TAILQ_INIT(&pmap->pm_pvchunk);
1753 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1757 * Initialize a preallocated and zeroed pmap structure,
1758 * such as one in a vmspace structure.
1761 pmap_pinit(pmap_t pmap)
1763 vm_page_t m, ptdpg[NPGPTD];
1768 * No need to allocate page table space yet but we do need a valid
1769 * page directory table.
1771 if (pmap->pm_pdir == NULL) {
1772 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1773 if (pmap->pm_pdir == NULL)
1775 #if defined(PAE) || defined(PAE_TABLES)
1776 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1777 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1778 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1779 ("pmap_pinit: pdpt misaligned"));
1780 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1781 ("pmap_pinit: pdpt above 4g"));
1783 pmap->pm_root.rt_root = 0;
1785 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1786 ("pmap_pinit: pmap has reserved page table page(s)"));
1789 * allocate the page directory page(s)
1791 for (i = 0; i < NPGPTD;) {
1792 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1793 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1801 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1803 for (i = 0; i < NPGPTD; i++)
1804 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1805 pagezero(pmap->pm_pdir + (i * NPDEPG));
1807 mtx_lock_spin(&allpmaps_lock);
1808 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1809 /* Copy the kernel page table directory entries. */
1810 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1811 mtx_unlock_spin(&allpmaps_lock);
1813 /* install self-referential address mapping entry(s) */
1814 for (i = 0; i < NPGPTD; i++) {
1815 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1816 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1817 #if defined(PAE) || defined(PAE_TABLES)
1818 pmap->pm_pdpt[i] = pa | PG_V;
1822 CPU_ZERO(&pmap->pm_active);
1823 TAILQ_INIT(&pmap->pm_pvchunk);
1824 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1830 * this routine is called if the page table page is not
1834 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1840 * Allocate a page table page.
1842 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1843 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1844 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1846 rw_wunlock(&pvh_global_lock);
1848 rw_wlock(&pvh_global_lock);
1853 * Indicate the need to retry. While waiting, the page table
1854 * page may have been allocated.
1858 if ((m->flags & PG_ZERO) == 0)
1862 * Map the pagetable page into the process address space, if
1863 * it isn't already there.
1866 pmap->pm_stats.resident_count++;
1868 ptepa = VM_PAGE_TO_PHYS(m);
1869 pmap->pm_pdir[ptepindex] =
1870 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1876 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1883 * Calculate pagetable page index
1885 ptepindex = va >> PDRSHIFT;
1888 * Get the page directory entry
1890 ptepa = pmap->pm_pdir[ptepindex];
1893 * This supports switching from a 4MB page to a
1896 if (ptepa & PG_PS) {
1897 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1898 ptepa = pmap->pm_pdir[ptepindex];
1902 * If the page table page is mapped, we just increment the
1903 * hold count, and activate it.
1906 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1910 * Here if the pte page isn't mapped, or if it has
1913 m = _pmap_allocpte(pmap, ptepindex, flags);
1914 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1921 /***************************************************
1922 * Pmap allocation/deallocation routines.
1923 ***************************************************/
1927 * Deal with a SMP shootdown of other users of the pmap that we are
1928 * trying to dispose of. This can be a bit hairy.
1930 static cpuset_t *lazymask;
1931 static u_int lazyptd;
1932 static volatile u_int lazywait;
1934 void pmap_lazyfix_action(void);
1937 pmap_lazyfix_action(void)
1941 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1943 if (rcr3() == lazyptd)
1944 load_cr3(curpcb->pcb_cr3);
1945 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1946 atomic_store_rel_int(&lazywait, 1);
1950 pmap_lazyfix_self(u_int cpuid)
1953 if (rcr3() == lazyptd)
1954 load_cr3(curpcb->pcb_cr3);
1955 CPU_CLR_ATOMIC(cpuid, lazymask);
1960 pmap_lazyfix(pmap_t pmap)
1962 cpuset_t mymask, mask;
1966 mask = pmap->pm_active;
1967 while (!CPU_EMPTY(&mask)) {
1970 /* Find least significant set bit. */
1971 lsb = CPU_FFS(&mask);
1974 CPU_SETOF(lsb, &mask);
1975 mtx_lock_spin(&smp_ipi_mtx);
1976 #if defined(PAE) || defined(PAE_TABLES)
1977 lazyptd = vtophys(pmap->pm_pdpt);
1979 lazyptd = vtophys(pmap->pm_pdir);
1981 cpuid = PCPU_GET(cpuid);
1983 /* Use a cpuset just for having an easy check. */
1984 CPU_SETOF(cpuid, &mymask);
1985 if (!CPU_CMP(&mask, &mymask)) {
1986 lazymask = &pmap->pm_active;
1987 pmap_lazyfix_self(cpuid);
1989 atomic_store_rel_int((u_int *)&lazymask,
1990 (u_int)&pmap->pm_active);
1991 atomic_store_rel_int(&lazywait, 0);
1992 ipi_selected(mask, IPI_LAZYPMAP);
1993 while (lazywait == 0) {
1999 mtx_unlock_spin(&smp_ipi_mtx);
2001 printf("pmap_lazyfix: spun for 50000000\n");
2002 mask = pmap->pm_active;
2009 * Cleaning up on uniprocessor is easy. For various reasons, we're
2010 * unlikely to have to even execute this code, including the fact
2011 * that the cleanup is deferred until the parent does a wait(2), which
2012 * means that another userland process has run.
2015 pmap_lazyfix(pmap_t pmap)
2019 cr3 = vtophys(pmap->pm_pdir);
2020 if (cr3 == rcr3()) {
2021 load_cr3(curpcb->pcb_cr3);
2022 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2028 * Release any resources held by the given physical map.
2029 * Called when a pmap initialized by pmap_pinit is being released.
2030 * Should only be called if the map contains no valid mappings.
2033 pmap_release(pmap_t pmap)
2035 vm_page_t m, ptdpg[NPGPTD];
2038 KASSERT(pmap->pm_stats.resident_count == 0,
2039 ("pmap_release: pmap resident count %ld != 0",
2040 pmap->pm_stats.resident_count));
2041 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2042 ("pmap_release: pmap has reserved page table page(s)"));
2045 mtx_lock_spin(&allpmaps_lock);
2046 LIST_REMOVE(pmap, pm_list);
2047 mtx_unlock_spin(&allpmaps_lock);
2049 for (i = 0; i < NPGPTD; i++)
2050 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2053 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2054 sizeof(*pmap->pm_pdir));
2056 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2058 for (i = 0; i < NPGPTD; i++) {
2060 #if defined(PAE) || defined(PAE_TABLES)
2061 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2062 ("pmap_release: got wrong ptd page"));
2065 atomic_subtract_int(&cnt.v_wire_count, 1);
2066 vm_page_free_zero(m);
2071 kvm_size(SYSCTL_HANDLER_ARGS)
2073 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2075 return (sysctl_handle_long(oidp, &ksize, 0, req));
2077 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2078 0, 0, kvm_size, "IU", "Size of KVM");
2081 kvm_free(SYSCTL_HANDLER_ARGS)
2083 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2085 return (sysctl_handle_long(oidp, &kfree, 0, req));
2087 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2088 0, 0, kvm_free, "IU", "Amount of KVM free");
2091 * grow the number of kernel page table entries, if needed
2094 pmap_growkernel(vm_offset_t addr)
2096 vm_paddr_t ptppaddr;
2100 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2101 addr = roundup2(addr, NBPDR);
2102 if (addr - 1 >= kernel_map->max_offset)
2103 addr = kernel_map->max_offset;
2104 while (kernel_vm_end < addr) {
2105 if (pdir_pde(PTD, kernel_vm_end)) {
2106 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2107 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2108 kernel_vm_end = kernel_map->max_offset;
2114 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2115 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2118 panic("pmap_growkernel: no memory to grow kernel");
2122 if ((nkpg->flags & PG_ZERO) == 0)
2123 pmap_zero_page(nkpg);
2124 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2125 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2126 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2128 pmap_kenter_pde(kernel_vm_end, newpdir);
2129 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2130 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2131 kernel_vm_end = kernel_map->max_offset;
2138 /***************************************************
2139 * page management routines.
2140 ***************************************************/
2142 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2143 CTASSERT(_NPCM == 11);
2144 CTASSERT(_NPCPV == 336);
2146 static __inline struct pv_chunk *
2147 pv_to_chunk(pv_entry_t pv)
2150 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2153 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2155 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2156 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2158 static const uint32_t pc_freemask[_NPCM] = {
2159 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2160 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2161 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2162 PC_FREE0_9, PC_FREE10
2165 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2166 "Current number of pv entries");
2169 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2171 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2172 "Current number of pv entry chunks");
2173 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2174 "Current number of pv entry chunks allocated");
2175 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2176 "Current number of pv entry chunks frees");
2177 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2178 "Number of times tried to get a chunk page but failed.");
2180 static long pv_entry_frees, pv_entry_allocs;
2181 static int pv_entry_spare;
2183 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2184 "Current number of pv entry frees");
2185 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2186 "Current number of pv entry allocs");
2187 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2188 "Current number of spare pv entries");
2192 * We are in a serious low memory condition. Resort to
2193 * drastic measures to free some pages so we can allocate
2194 * another pv entry chunk.
2197 pmap_pv_reclaim(pmap_t locked_pmap)
2200 struct pv_chunk *pc;
2201 struct md_page *pvh;
2204 pt_entry_t *pte, tpte;
2208 struct spglist free;
2210 int bit, field, freed;
2212 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2216 TAILQ_INIT(&newtail);
2217 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2218 SLIST_EMPTY(&free))) {
2219 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2220 if (pmap != pc->pc_pmap) {
2222 pmap_invalidate_all(pmap);
2223 if (pmap != locked_pmap)
2227 /* Avoid deadlock and lock recursion. */
2228 if (pmap > locked_pmap)
2230 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2232 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2238 * Destroy every non-wired, 4 KB page mapping in the chunk.
2241 for (field = 0; field < _NPCM; field++) {
2242 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2243 inuse != 0; inuse &= ~(1UL << bit)) {
2245 pv = &pc->pc_pventry[field * 32 + bit];
2247 pde = pmap_pde(pmap, va);
2248 if ((*pde & PG_PS) != 0)
2250 pte = pmap_pte(pmap, va);
2252 if ((tpte & PG_W) == 0)
2253 tpte = pte_load_clear(pte);
2254 pmap_pte_release(pte);
2255 if ((tpte & PG_W) != 0)
2258 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2260 if ((tpte & PG_G) != 0)
2261 pmap_invalidate_page(pmap, va);
2262 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2263 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2265 if ((tpte & PG_A) != 0)
2266 vm_page_aflag_set(m, PGA_REFERENCED);
2267 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2268 if (TAILQ_EMPTY(&m->md.pv_list) &&
2269 (m->flags & PG_FICTITIOUS) == 0) {
2270 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2271 if (TAILQ_EMPTY(&pvh->pv_list)) {
2272 vm_page_aflag_clear(m,
2276 pc->pc_map[field] |= 1UL << bit;
2277 pmap_unuse_pt(pmap, va, &free);
2282 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2285 /* Every freed mapping is for a 4 KB page. */
2286 pmap->pm_stats.resident_count -= freed;
2287 PV_STAT(pv_entry_frees += freed);
2288 PV_STAT(pv_entry_spare += freed);
2289 pv_entry_count -= freed;
2290 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2291 for (field = 0; field < _NPCM; field++)
2292 if (pc->pc_map[field] != pc_freemask[field]) {
2293 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2295 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2298 * One freed pv entry in locked_pmap is
2301 if (pmap == locked_pmap)
2305 if (field == _NPCM) {
2306 PV_STAT(pv_entry_spare -= _NPCPV);
2307 PV_STAT(pc_chunk_count--);
2308 PV_STAT(pc_chunk_frees++);
2309 /* Entire chunk is free; return it. */
2310 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2311 pmap_qremove((vm_offset_t)pc, 1);
2312 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2317 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2319 pmap_invalidate_all(pmap);
2320 if (pmap != locked_pmap)
2323 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2324 m_pc = SLIST_FIRST(&free);
2325 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2326 /* Recycle a freed page table page. */
2327 m_pc->wire_count = 1;
2328 atomic_add_int(&cnt.v_wire_count, 1);
2330 pmap_free_zero_pages(&free);
2335 * free the pv_entry back to the free list
2338 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2340 struct pv_chunk *pc;
2341 int idx, field, bit;
2343 rw_assert(&pvh_global_lock, RA_WLOCKED);
2344 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2345 PV_STAT(pv_entry_frees++);
2346 PV_STAT(pv_entry_spare++);
2348 pc = pv_to_chunk(pv);
2349 idx = pv - &pc->pc_pventry[0];
2352 pc->pc_map[field] |= 1ul << bit;
2353 for (idx = 0; idx < _NPCM; idx++)
2354 if (pc->pc_map[idx] != pc_freemask[idx]) {
2356 * 98% of the time, pc is already at the head of the
2357 * list. If it isn't already, move it to the head.
2359 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2361 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2362 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2367 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2372 free_pv_chunk(struct pv_chunk *pc)
2376 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2377 PV_STAT(pv_entry_spare -= _NPCPV);
2378 PV_STAT(pc_chunk_count--);
2379 PV_STAT(pc_chunk_frees++);
2380 /* entire chunk is free, return it */
2381 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2382 pmap_qremove((vm_offset_t)pc, 1);
2383 vm_page_unwire(m, 0);
2385 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2389 * get a new pv_entry, allocating a block from the system
2393 get_pv_entry(pmap_t pmap, boolean_t try)
2395 static const struct timeval printinterval = { 60, 0 };
2396 static struct timeval lastprint;
2399 struct pv_chunk *pc;
2402 rw_assert(&pvh_global_lock, RA_WLOCKED);
2403 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2404 PV_STAT(pv_entry_allocs++);
2406 if (pv_entry_count > pv_entry_high_water)
2407 if (ratecheck(&lastprint, &printinterval))
2408 printf("Approaching the limit on PV entries, consider "
2409 "increasing either the vm.pmap.shpgperproc or the "
2410 "vm.pmap.pv_entry_max tunable.\n");
2412 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2414 for (field = 0; field < _NPCM; field++) {
2415 if (pc->pc_map[field]) {
2416 bit = bsfl(pc->pc_map[field]);
2420 if (field < _NPCM) {
2421 pv = &pc->pc_pventry[field * 32 + bit];
2422 pc->pc_map[field] &= ~(1ul << bit);
2423 /* If this was the last item, move it to tail */
2424 for (field = 0; field < _NPCM; field++)
2425 if (pc->pc_map[field] != 0) {
2426 PV_STAT(pv_entry_spare--);
2427 return (pv); /* not full, return */
2429 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2430 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2431 PV_STAT(pv_entry_spare--);
2436 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2437 * global lock. If "pv_vafree" is currently non-empty, it will
2438 * remain non-empty until pmap_ptelist_alloc() completes.
2440 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2441 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2444 PV_STAT(pc_chunk_tryfail++);
2447 m = pmap_pv_reclaim(pmap);
2451 PV_STAT(pc_chunk_count++);
2452 PV_STAT(pc_chunk_allocs++);
2453 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2454 pmap_qenter((vm_offset_t)pc, &m, 1);
2456 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2457 for (field = 1; field < _NPCM; field++)
2458 pc->pc_map[field] = pc_freemask[field];
2459 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2460 pv = &pc->pc_pventry[0];
2461 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2462 PV_STAT(pv_entry_spare += _NPCPV - 1);
2466 static __inline pv_entry_t
2467 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2471 rw_assert(&pvh_global_lock, RA_WLOCKED);
2472 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2473 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2474 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2482 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2484 struct md_page *pvh;
2486 vm_offset_t va_last;
2489 rw_assert(&pvh_global_lock, RA_WLOCKED);
2490 KASSERT((pa & PDRMASK) == 0,
2491 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2494 * Transfer the 4mpage's pv entry for this mapping to the first
2497 pvh = pa_to_pvh(pa);
2498 va = trunc_4mpage(va);
2499 pv = pmap_pvh_remove(pvh, pmap, va);
2500 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2501 m = PHYS_TO_VM_PAGE(pa);
2502 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2503 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2504 va_last = va + NBPDR - PAGE_SIZE;
2507 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2508 ("pmap_pv_demote_pde: page %p is not managed", m));
2510 pmap_insert_entry(pmap, va, m);
2511 } while (va < va_last);
2515 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2517 struct md_page *pvh;
2519 vm_offset_t va_last;
2522 rw_assert(&pvh_global_lock, RA_WLOCKED);
2523 KASSERT((pa & PDRMASK) == 0,
2524 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2527 * Transfer the first page's pv entry for this mapping to the
2528 * 4mpage's pv list. Aside from avoiding the cost of a call
2529 * to get_pv_entry(), a transfer avoids the possibility that
2530 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2531 * removes one of the mappings that is being promoted.
2533 m = PHYS_TO_VM_PAGE(pa);
2534 va = trunc_4mpage(va);
2535 pv = pmap_pvh_remove(&m->md, pmap, va);
2536 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2537 pvh = pa_to_pvh(pa);
2538 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2539 /* Free the remaining NPTEPG - 1 pv entries. */
2540 va_last = va + NBPDR - PAGE_SIZE;
2544 pmap_pvh_free(&m->md, pmap, va);
2545 } while (va < va_last);
2549 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2553 pv = pmap_pvh_remove(pvh, pmap, va);
2554 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2555 free_pv_entry(pmap, pv);
2559 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2561 struct md_page *pvh;
2563 rw_assert(&pvh_global_lock, RA_WLOCKED);
2564 pmap_pvh_free(&m->md, pmap, va);
2565 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2566 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2567 if (TAILQ_EMPTY(&pvh->pv_list))
2568 vm_page_aflag_clear(m, PGA_WRITEABLE);
2573 * Create a pv entry for page at pa for
2577 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2581 rw_assert(&pvh_global_lock, RA_WLOCKED);
2582 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2583 pv = get_pv_entry(pmap, FALSE);
2585 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2589 * Conditionally create a pv entry.
2592 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2596 rw_assert(&pvh_global_lock, RA_WLOCKED);
2597 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2598 if (pv_entry_count < pv_entry_high_water &&
2599 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2601 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2608 * Create the pv entries for each of the pages within a superpage.
2611 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2613 struct md_page *pvh;
2616 rw_assert(&pvh_global_lock, RA_WLOCKED);
2617 if (pv_entry_count < pv_entry_high_water &&
2618 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2620 pvh = pa_to_pvh(pa);
2621 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2628 * Fills a page table page with mappings to consecutive physical pages.
2631 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2635 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2637 newpte += PAGE_SIZE;
2642 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2643 * 2- or 4MB page mapping is invalidated.
2646 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2648 pd_entry_t newpde, oldpde;
2649 pt_entry_t *firstpte, newpte;
2652 struct spglist free;
2654 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2656 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2657 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2658 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2660 pmap_remove_pt_page(pmap, mpte);
2662 KASSERT((oldpde & PG_W) == 0,
2663 ("pmap_demote_pde: page table page for a wired mapping"
2667 * Invalidate the 2- or 4MB page mapping and return
2668 * "failure" if the mapping was never accessed or the
2669 * allocation of the new page table page fails.
2671 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2672 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2673 VM_ALLOC_WIRED)) == NULL) {
2675 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2676 pmap_invalidate_page(pmap, trunc_4mpage(va));
2677 pmap_free_zero_pages(&free);
2678 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2679 " in pmap %p", va, pmap);
2682 if (va < VM_MAXUSER_ADDRESS)
2683 pmap->pm_stats.resident_count++;
2685 mptepa = VM_PAGE_TO_PHYS(mpte);
2688 * If the page mapping is in the kernel's address space, then the
2689 * KPTmap can provide access to the page table page. Otherwise,
2690 * temporarily map the page table page (mpte) into the kernel's
2691 * address space at either PADDR1 or PADDR2.
2694 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2695 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2696 if ((*PMAP1 & PG_FRAME) != mptepa) {
2697 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2699 PMAP1cpu = PCPU_GET(cpuid);
2705 if (PMAP1cpu != PCPU_GET(cpuid)) {
2706 PMAP1cpu = PCPU_GET(cpuid);
2714 mtx_lock(&PMAP2mutex);
2715 if ((*PMAP2 & PG_FRAME) != mptepa) {
2716 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2717 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2721 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2722 KASSERT((oldpde & PG_A) != 0,
2723 ("pmap_demote_pde: oldpde is missing PG_A"));
2724 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2725 ("pmap_demote_pde: oldpde is missing PG_M"));
2726 newpte = oldpde & ~PG_PS;
2727 if ((newpte & PG_PDE_PAT) != 0)
2728 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2731 * If the page table page is new, initialize it.
2733 if (mpte->wire_count == 1) {
2734 mpte->wire_count = NPTEPG;
2735 pmap_fill_ptp(firstpte, newpte);
2737 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2738 ("pmap_demote_pde: firstpte and newpte map different physical"
2742 * If the mapping has changed attributes, update the page table
2745 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2746 pmap_fill_ptp(firstpte, newpte);
2749 * Demote the mapping. This pmap is locked. The old PDE has
2750 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2751 * set. Thus, there is no danger of a race with another
2752 * processor changing the setting of PG_A and/or PG_M between
2753 * the read above and the store below.
2755 if (workaround_erratum383)
2756 pmap_update_pde(pmap, va, pde, newpde);
2757 else if (pmap == kernel_pmap)
2758 pmap_kenter_pde(va, newpde);
2760 pde_store(pde, newpde);
2761 if (firstpte == PADDR2)
2762 mtx_unlock(&PMAP2mutex);
2765 * Invalidate the recursive mapping of the page table page.
2767 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2770 * Demote the pv entry. This depends on the earlier demotion
2771 * of the mapping. Specifically, the (re)creation of a per-
2772 * page pv entry might trigger the execution of pmap_collect(),
2773 * which might reclaim a newly (re)created per-page pv entry
2774 * and destroy the associated mapping. In order to destroy
2775 * the mapping, the PDE must have already changed from mapping
2776 * the 2mpage to referencing the page table page.
2778 if ((oldpde & PG_MANAGED) != 0)
2779 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2781 pmap_pde_demotions++;
2782 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2783 " in pmap %p", va, pmap);
2788 * Removes a 2- or 4MB page mapping from the kernel pmap.
2791 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2798 mpte = pmap_lookup_pt_page(pmap, va);
2800 panic("pmap_remove_kernel_pde: Missing pt page.");
2802 pmap_remove_pt_page(pmap, mpte);
2803 mptepa = VM_PAGE_TO_PHYS(mpte);
2804 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2807 * Initialize the page table page.
2809 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2812 * Remove the mapping.
2814 if (workaround_erratum383)
2815 pmap_update_pde(pmap, va, pde, newpde);
2817 pmap_kenter_pde(va, newpde);
2820 * Invalidate the recursive mapping of the page table page.
2822 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2826 * pmap_remove_pde: do the things to unmap a superpage in a process
2829 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2830 struct spglist *free)
2832 struct md_page *pvh;
2834 vm_offset_t eva, va;
2837 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2838 KASSERT((sva & PDRMASK) == 0,
2839 ("pmap_remove_pde: sva is not 4mpage aligned"));
2840 oldpde = pte_load_clear(pdq);
2842 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2845 * Machines that don't support invlpg, also don't support
2849 pmap_invalidate_page(kernel_pmap, sva);
2850 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2851 if (oldpde & PG_MANAGED) {
2852 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2853 pmap_pvh_free(pvh, pmap, sva);
2855 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2856 va < eva; va += PAGE_SIZE, m++) {
2857 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2860 vm_page_aflag_set(m, PGA_REFERENCED);
2861 if (TAILQ_EMPTY(&m->md.pv_list) &&
2862 TAILQ_EMPTY(&pvh->pv_list))
2863 vm_page_aflag_clear(m, PGA_WRITEABLE);
2866 if (pmap == kernel_pmap) {
2867 pmap_remove_kernel_pde(pmap, pdq, sva);
2869 mpte = pmap_lookup_pt_page(pmap, sva);
2871 pmap_remove_pt_page(pmap, mpte);
2872 pmap->pm_stats.resident_count--;
2873 KASSERT(mpte->wire_count == NPTEPG,
2874 ("pmap_remove_pde: pte page wire count error"));
2875 mpte->wire_count = 0;
2876 pmap_add_delayed_free_list(mpte, free, FALSE);
2877 atomic_subtract_int(&cnt.v_wire_count, 1);
2883 * pmap_remove_pte: do the things to unmap a page in a process
2886 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2887 struct spglist *free)
2892 rw_assert(&pvh_global_lock, RA_WLOCKED);
2893 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2894 oldpte = pte_load_clear(ptq);
2895 KASSERT(oldpte != 0,
2896 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2898 pmap->pm_stats.wired_count -= 1;
2900 * Machines that don't support invlpg, also don't support
2904 pmap_invalidate_page(kernel_pmap, va);
2905 pmap->pm_stats.resident_count -= 1;
2906 if (oldpte & PG_MANAGED) {
2907 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2908 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2911 vm_page_aflag_set(m, PGA_REFERENCED);
2912 pmap_remove_entry(pmap, m, va);
2914 return (pmap_unuse_pt(pmap, va, free));
2918 * Remove a single page from a process address space
2921 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2925 rw_assert(&pvh_global_lock, RA_WLOCKED);
2926 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2927 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2928 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2930 pmap_remove_pte(pmap, pte, va, free);
2931 pmap_invalidate_page(pmap, va);
2935 * Remove the given range of addresses from the specified map.
2937 * It is assumed that the start and end are properly
2938 * rounded to the page size.
2941 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2946 struct spglist free;
2950 * Perform an unsynchronized read. This is, however, safe.
2952 if (pmap->pm_stats.resident_count == 0)
2958 rw_wlock(&pvh_global_lock);
2963 * special handling of removing one page. a very
2964 * common operation and easy to short circuit some
2967 if ((sva + PAGE_SIZE == eva) &&
2968 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2969 pmap_remove_page(pmap, sva, &free);
2973 for (; sva < eva; sva = pdnxt) {
2977 * Calculate index for next page table.
2979 pdnxt = (sva + NBPDR) & ~PDRMASK;
2982 if (pmap->pm_stats.resident_count == 0)
2985 pdirindex = sva >> PDRSHIFT;
2986 ptpaddr = pmap->pm_pdir[pdirindex];
2989 * Weed out invalid mappings. Note: we assume that the page
2990 * directory table is always allocated, and in kernel virtual.
2996 * Check for large page.
2998 if ((ptpaddr & PG_PS) != 0) {
3000 * Are we removing the entire large page? If not,
3001 * demote the mapping and fall through.
3003 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3005 * The TLB entry for a PG_G mapping is
3006 * invalidated by pmap_remove_pde().
3008 if ((ptpaddr & PG_G) == 0)
3010 pmap_remove_pde(pmap,
3011 &pmap->pm_pdir[pdirindex], sva, &free);
3013 } else if (!pmap_demote_pde(pmap,
3014 &pmap->pm_pdir[pdirindex], sva)) {
3015 /* The large page mapping was destroyed. */
3021 * Limit our scan to either the end of the va represented
3022 * by the current page table page, or to the end of the
3023 * range being removed.
3028 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3034 * The TLB entry for a PG_G mapping is invalidated
3035 * by pmap_remove_pte().
3037 if ((*pte & PG_G) == 0)
3039 if (pmap_remove_pte(pmap, pte, sva, &free))
3046 pmap_invalidate_all(pmap);
3047 rw_wunlock(&pvh_global_lock);
3049 pmap_free_zero_pages(&free);
3053 * Routine: pmap_remove_all
3055 * Removes this physical page from
3056 * all physical maps in which it resides.
3057 * Reflects back modify bits to the pager.
3060 * Original versions of this routine were very
3061 * inefficient because they iteratively called
3062 * pmap_remove (slow...)
3066 pmap_remove_all(vm_page_t m)
3068 struct md_page *pvh;
3071 pt_entry_t *pte, tpte;
3074 struct spglist free;
3076 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3077 ("pmap_remove_all: page %p is not managed", m));
3079 rw_wlock(&pvh_global_lock);
3081 if ((m->flags & PG_FICTITIOUS) != 0)
3082 goto small_mappings;
3083 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3084 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3088 pde = pmap_pde(pmap, va);
3089 (void)pmap_demote_pde(pmap, pde, va);
3093 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3096 pmap->pm_stats.resident_count--;
3097 pde = pmap_pde(pmap, pv->pv_va);
3098 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3099 " a 4mpage in page %p's pv list", m));
3100 pte = pmap_pte_quick(pmap, pv->pv_va);
3101 tpte = pte_load_clear(pte);
3102 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3105 pmap->pm_stats.wired_count--;
3107 vm_page_aflag_set(m, PGA_REFERENCED);
3110 * Update the vm_page_t clean and reference bits.
3112 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3114 pmap_unuse_pt(pmap, pv->pv_va, &free);
3115 pmap_invalidate_page(pmap, pv->pv_va);
3116 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3117 free_pv_entry(pmap, pv);
3120 vm_page_aflag_clear(m, PGA_WRITEABLE);
3122 rw_wunlock(&pvh_global_lock);
3123 pmap_free_zero_pages(&free);
3127 * pmap_protect_pde: do the things to protect a 4mpage in a process
3130 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3132 pd_entry_t newpde, oldpde;
3133 vm_offset_t eva, va;
3135 boolean_t anychanged;
3137 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3138 KASSERT((sva & PDRMASK) == 0,
3139 ("pmap_protect_pde: sva is not 4mpage aligned"));
3142 oldpde = newpde = *pde;
3143 if (oldpde & PG_MANAGED) {
3145 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3146 va < eva; va += PAGE_SIZE, m++)
3147 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3150 if ((prot & VM_PROT_WRITE) == 0)
3151 newpde &= ~(PG_RW | PG_M);
3152 #if defined(PAE) || defined(PAE_TABLES)
3153 if ((prot & VM_PROT_EXECUTE) == 0)
3156 if (newpde != oldpde) {
3157 if (!pde_cmpset(pde, oldpde, newpde))
3160 pmap_invalidate_page(pmap, sva);
3164 return (anychanged);
3168 * Set the physical protection on the
3169 * specified range of this map as requested.
3172 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3177 boolean_t anychanged, pv_lists_locked;
3179 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3180 if (prot == VM_PROT_NONE) {
3181 pmap_remove(pmap, sva, eva);
3185 #if defined(PAE) || defined(PAE_TABLES)
3186 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3187 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3190 if (prot & VM_PROT_WRITE)
3194 if (pmap_is_current(pmap))
3195 pv_lists_locked = FALSE;
3197 pv_lists_locked = TRUE;
3199 rw_wlock(&pvh_global_lock);
3205 for (; sva < eva; sva = pdnxt) {
3206 pt_entry_t obits, pbits;
3209 pdnxt = (sva + NBPDR) & ~PDRMASK;
3213 pdirindex = sva >> PDRSHIFT;
3214 ptpaddr = pmap->pm_pdir[pdirindex];
3217 * Weed out invalid mappings. Note: we assume that the page
3218 * directory table is always allocated, and in kernel virtual.
3224 * Check for large page.
3226 if ((ptpaddr & PG_PS) != 0) {
3228 * Are we protecting the entire large page? If not,
3229 * demote the mapping and fall through.
3231 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3233 * The TLB entry for a PG_G mapping is
3234 * invalidated by pmap_protect_pde().
3236 if (pmap_protect_pde(pmap,
3237 &pmap->pm_pdir[pdirindex], sva, prot))
3241 if (!pv_lists_locked) {
3242 pv_lists_locked = TRUE;
3243 if (!rw_try_wlock(&pvh_global_lock)) {
3245 pmap_invalidate_all(
3252 if (!pmap_demote_pde(pmap,
3253 &pmap->pm_pdir[pdirindex], sva)) {
3255 * The large page mapping was
3266 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3272 * Regardless of whether a pte is 32 or 64 bits in
3273 * size, PG_RW, PG_A, and PG_M are among the least
3274 * significant 32 bits.
3276 obits = pbits = *pte;
3277 if ((pbits & PG_V) == 0)
3280 if ((prot & VM_PROT_WRITE) == 0) {
3281 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3282 (PG_MANAGED | PG_M | PG_RW)) {
3283 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3286 pbits &= ~(PG_RW | PG_M);
3288 #if defined(PAE) || defined(PAE_TABLES)
3289 if ((prot & VM_PROT_EXECUTE) == 0)
3293 if (pbits != obits) {
3294 #if defined(PAE) || defined(PAE_TABLES)
3295 if (!atomic_cmpset_64(pte, obits, pbits))
3298 if (!atomic_cmpset_int((u_int *)pte, obits,
3303 pmap_invalidate_page(pmap, sva);
3310 pmap_invalidate_all(pmap);
3311 if (pv_lists_locked) {
3313 rw_wunlock(&pvh_global_lock);
3319 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3320 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3321 * For promotion to occur, two conditions must be met: (1) the 4KB page
3322 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3323 * mappings must have identical characteristics.
3325 * Managed (PG_MANAGED) mappings within the kernel address space are not
3326 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3327 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3331 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3334 pt_entry_t *firstpte, oldpte, pa, *pte;
3335 vm_offset_t oldpteva;
3338 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3341 * Examine the first PTE in the specified PTP. Abort if this PTE is
3342 * either invalid, unused, or does not map the first 4KB physical page
3343 * within a 2- or 4MB page.
3345 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3348 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3349 pmap_pde_p_failures++;
3350 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3351 " in pmap %p", va, pmap);
3354 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3355 pmap_pde_p_failures++;
3356 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3357 " in pmap %p", va, pmap);
3360 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3362 * When PG_M is already clear, PG_RW can be cleared without
3363 * a TLB invalidation.
3365 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3372 * Examine each of the other PTEs in the specified PTP. Abort if this
3373 * PTE maps an unexpected 4KB physical page or does not have identical
3374 * characteristics to the first PTE.
3376 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3377 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3380 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3381 pmap_pde_p_failures++;
3382 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3383 " in pmap %p", va, pmap);
3386 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3388 * When PG_M is already clear, PG_RW can be cleared
3389 * without a TLB invalidation.
3391 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3395 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3397 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3398 " in pmap %p", oldpteva, pmap);
3400 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3401 pmap_pde_p_failures++;
3402 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3403 " in pmap %p", va, pmap);
3410 * Save the page table page in its current state until the PDE
3411 * mapping the superpage is demoted by pmap_demote_pde() or
3412 * destroyed by pmap_remove_pde().
3414 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3415 KASSERT(mpte >= vm_page_array &&
3416 mpte < &vm_page_array[vm_page_array_size],
3417 ("pmap_promote_pde: page table page is out of range"));
3418 KASSERT(mpte->pindex == va >> PDRSHIFT,
3419 ("pmap_promote_pde: page table page's pindex is wrong"));
3420 if (pmap_insert_pt_page(pmap, mpte)) {
3421 pmap_pde_p_failures++;
3423 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3429 * Promote the pv entries.
3431 if ((newpde & PG_MANAGED) != 0)
3432 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3435 * Propagate the PAT index to its proper position.
3437 if ((newpde & PG_PTE_PAT) != 0)
3438 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3441 * Map the superpage.
3443 if (workaround_erratum383)
3444 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3445 else if (pmap == kernel_pmap)
3446 pmap_kenter_pde(va, PG_PS | newpde);
3448 pde_store(pde, PG_PS | newpde);
3450 pmap_pde_promotions++;
3451 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3452 " in pmap %p", va, pmap);
3456 * Insert the given physical page (p) at
3457 * the specified virtual address (v) in the
3458 * target physical map with the protection requested.
3460 * If specified, the page will be wired down, meaning
3461 * that the related pte can not be reclaimed.
3463 * NB: This is the only routine which MAY NOT lazy-evaluate
3464 * or lose information. That is, this routine must actually
3465 * insert this page into the given map NOW.
3468 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3469 u_int flags, int8_t psind)
3473 pt_entry_t newpte, origpte;
3477 boolean_t invlva, wired;
3479 va = trunc_page(va);
3481 wired = (flags & PMAP_ENTER_WIRED) != 0;
3483 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3484 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3485 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3487 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3488 VM_OBJECT_ASSERT_LOCKED(m->object);
3490 rw_wlock(&pvh_global_lock);
3495 * In the case that a page table page is not
3496 * resident, we are creating it here.
3498 if (va < VM_MAXUSER_ADDRESS) {
3499 mpte = pmap_allocpte(pmap, va, flags);
3501 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3502 ("pmap_allocpte failed with sleep allowed"));
3504 rw_wunlock(&pvh_global_lock);
3506 return (KERN_RESOURCE_SHORTAGE);
3510 pde = pmap_pde(pmap, va);
3511 if ((*pde & PG_PS) != 0)
3512 panic("pmap_enter: attempted pmap_enter on 4MB page");
3513 pte = pmap_pte_quick(pmap, va);
3516 * Page Directory table entry not valid, we need a new PT page
3519 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3520 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3523 pa = VM_PAGE_TO_PHYS(m);
3526 opa = origpte & PG_FRAME;
3529 * Mapping has not changed, must be protection or wiring change.
3531 if (origpte && (opa == pa)) {
3533 * Wiring change, just update stats. We don't worry about
3534 * wiring PT pages as they remain resident as long as there
3535 * are valid mappings in them. Hence, if a user page is wired,
3536 * the PT page will be also.
3538 if (wired && ((origpte & PG_W) == 0))
3539 pmap->pm_stats.wired_count++;
3540 else if (!wired && (origpte & PG_W))
3541 pmap->pm_stats.wired_count--;
3544 * Remove extra pte reference
3549 if (origpte & PG_MANAGED) {
3559 * Mapping has changed, invalidate old range and fall through to
3560 * handle validating new mapping.
3564 pmap->pm_stats.wired_count--;
3565 if (origpte & PG_MANAGED) {
3566 om = PHYS_TO_VM_PAGE(opa);
3567 pv = pmap_pvh_remove(&om->md, pmap, va);
3571 KASSERT(mpte->wire_count > 0,
3572 ("pmap_enter: missing reference to page table page,"
3576 pmap->pm_stats.resident_count++;
3579 * Enter on the PV list if part of our managed memory.
3581 if ((m->oflags & VPO_UNMANAGED) == 0) {
3582 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3583 ("pmap_enter: managed mapping within the clean submap"));
3585 pv = get_pv_entry(pmap, FALSE);
3587 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3589 } else if (pv != NULL)
3590 free_pv_entry(pmap, pv);
3593 * Increment counters
3596 pmap->pm_stats.wired_count++;
3600 * Now validate mapping with desired protection/wiring.
3602 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3603 if ((prot & VM_PROT_WRITE) != 0) {
3605 if ((newpte & PG_MANAGED) != 0)
3606 vm_page_aflag_set(m, PGA_WRITEABLE);
3608 #if defined(PAE) || defined(PAE_TABLES)
3609 if ((prot & VM_PROT_EXECUTE) == 0)
3614 if (va < VM_MAXUSER_ADDRESS)
3616 if (pmap == kernel_pmap)
3620 * if the mapping or permission bits are different, we need
3621 * to update the pte.
3623 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3625 if ((flags & VM_PROT_WRITE) != 0)
3627 if (origpte & PG_V) {
3629 origpte = pte_load_store(pte, newpte);
3630 if (origpte & PG_A) {
3631 if (origpte & PG_MANAGED)
3632 vm_page_aflag_set(om, PGA_REFERENCED);
3633 if (opa != VM_PAGE_TO_PHYS(m))
3635 #if defined(PAE) || defined(PAE_TABLES)
3636 if ((origpte & PG_NX) == 0 &&
3637 (newpte & PG_NX) != 0)
3641 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3642 if ((origpte & PG_MANAGED) != 0)
3644 if ((prot & VM_PROT_WRITE) == 0)
3647 if ((origpte & PG_MANAGED) != 0 &&
3648 TAILQ_EMPTY(&om->md.pv_list) &&
3649 ((om->flags & PG_FICTITIOUS) != 0 ||
3650 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3651 vm_page_aflag_clear(om, PGA_WRITEABLE);
3653 pmap_invalidate_page(pmap, va);
3655 pte_store(pte, newpte);
3659 * If both the page table page and the reservation are fully
3660 * populated, then attempt promotion.
3662 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3663 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3664 vm_reserv_level_iffullpop(m) == 0)
3665 pmap_promote_pde(pmap, pde, va);
3668 rw_wunlock(&pvh_global_lock);
3670 return (KERN_SUCCESS);
3674 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3675 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3676 * blocking, (2) a mapping already exists at the specified virtual address, or
3677 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3680 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3682 pd_entry_t *pde, newpde;
3684 rw_assert(&pvh_global_lock, RA_WLOCKED);
3685 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3686 pde = pmap_pde(pmap, va);
3688 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3689 " in pmap %p", va, pmap);
3692 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3694 if ((m->oflags & VPO_UNMANAGED) == 0) {
3695 newpde |= PG_MANAGED;
3698 * Abort this mapping if its PV entry could not be created.
3700 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3701 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3702 " in pmap %p", va, pmap);
3706 #if defined(PAE) || defined(PAE_TABLES)
3707 if ((prot & VM_PROT_EXECUTE) == 0)
3710 if (va < VM_MAXUSER_ADDRESS)
3714 * Increment counters.
3716 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3719 * Map the superpage.
3721 pde_store(pde, newpde);
3723 pmap_pde_mappings++;
3724 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3725 " in pmap %p", va, pmap);
3730 * Maps a sequence of resident pages belonging to the same object.
3731 * The sequence begins with the given page m_start. This page is
3732 * mapped at the given virtual address start. Each subsequent page is
3733 * mapped at a virtual address that is offset from start by the same
3734 * amount as the page is offset from m_start within the object. The
3735 * last page in the sequence is the page with the largest offset from
3736 * m_start that can be mapped at a virtual address less than the given
3737 * virtual address end. Not every virtual page between start and end
3738 * is mapped; only those for which a resident page exists with the
3739 * corresponding offset from m_start are mapped.
3742 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3743 vm_page_t m_start, vm_prot_t prot)
3747 vm_pindex_t diff, psize;
3749 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3751 psize = atop(end - start);
3754 rw_wlock(&pvh_global_lock);
3756 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3757 va = start + ptoa(diff);
3758 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3759 m->psind == 1 && pg_ps_enabled &&
3760 pmap_enter_pde(pmap, va, m, prot))
3761 m = &m[NBPDR / PAGE_SIZE - 1];
3763 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3765 m = TAILQ_NEXT(m, listq);
3767 rw_wunlock(&pvh_global_lock);
3772 * this code makes some *MAJOR* assumptions:
3773 * 1. Current pmap & pmap exists.
3776 * 4. No page table pages.
3777 * but is *MUCH* faster than pmap_enter...
3781 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3784 rw_wlock(&pvh_global_lock);
3786 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3787 rw_wunlock(&pvh_global_lock);
3792 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3793 vm_prot_t prot, vm_page_t mpte)
3797 struct spglist free;
3799 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3800 (m->oflags & VPO_UNMANAGED) != 0,
3801 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3802 rw_assert(&pvh_global_lock, RA_WLOCKED);
3803 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3806 * In the case that a page table page is not
3807 * resident, we are creating it here.
3809 if (va < VM_MAXUSER_ADDRESS) {
3814 * Calculate pagetable page index
3816 ptepindex = va >> PDRSHIFT;
3817 if (mpte && (mpte->pindex == ptepindex)) {
3821 * Get the page directory entry
3823 ptepa = pmap->pm_pdir[ptepindex];
3826 * If the page table page is mapped, we just increment
3827 * the hold count, and activate it.
3832 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3835 mpte = _pmap_allocpte(pmap, ptepindex,
3836 PMAP_ENTER_NOSLEEP);
3846 * This call to vtopte makes the assumption that we are
3847 * entering the page into the current pmap. In order to support
3848 * quick entry into any pmap, one would likely use pmap_pte_quick.
3849 * But that isn't as quick as vtopte.
3861 * Enter on the PV list if part of our managed memory.
3863 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3864 !pmap_try_insert_pv_entry(pmap, va, m)) {
3867 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3868 pmap_invalidate_page(pmap, va);
3869 pmap_free_zero_pages(&free);
3878 * Increment counters
3880 pmap->pm_stats.resident_count++;
3882 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3883 #if defined(PAE) || defined(PAE_TABLES)
3884 if ((prot & VM_PROT_EXECUTE) == 0)
3889 * Now validate mapping with RO protection
3891 if ((m->oflags & VPO_UNMANAGED) != 0)
3892 pte_store(pte, pa | PG_V | PG_U);
3894 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3899 * Make a temporary mapping for a physical address. This is only intended
3900 * to be used for panic dumps.
3903 pmap_kenter_temporary(vm_paddr_t pa, int i)
3907 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3908 pmap_kenter(va, pa);
3910 return ((void *)crashdumpmap);
3914 * This code maps large physical mmap regions into the
3915 * processor address space. Note that some shortcuts
3916 * are taken, but the code works.
3919 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3920 vm_pindex_t pindex, vm_size_t size)
3923 vm_paddr_t pa, ptepa;
3927 VM_OBJECT_ASSERT_WLOCKED(object);
3928 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3929 ("pmap_object_init_pt: non-device object"));
3931 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3932 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3934 p = vm_page_lookup(object, pindex);
3935 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3936 ("pmap_object_init_pt: invalid page %p", p));
3937 pat_mode = p->md.pat_mode;
3940 * Abort the mapping if the first page is not physically
3941 * aligned to a 2/4MB page boundary.
3943 ptepa = VM_PAGE_TO_PHYS(p);
3944 if (ptepa & (NBPDR - 1))
3948 * Skip the first page. Abort the mapping if the rest of
3949 * the pages are not physically contiguous or have differing
3950 * memory attributes.
3952 p = TAILQ_NEXT(p, listq);
3953 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3955 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3956 ("pmap_object_init_pt: invalid page %p", p));
3957 if (pa != VM_PAGE_TO_PHYS(p) ||
3958 pat_mode != p->md.pat_mode)
3960 p = TAILQ_NEXT(p, listq);
3964 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3965 * "size" is a multiple of 2/4M, adding the PAT setting to
3966 * "pa" will not affect the termination of this loop.
3969 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3970 size; pa += NBPDR) {
3971 pde = pmap_pde(pmap, addr);
3973 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3974 PG_U | PG_RW | PG_V);
3975 pmap->pm_stats.resident_count += NBPDR /
3977 pmap_pde_mappings++;
3979 /* Else continue on if the PDE is already valid. */
3987 * Clear the wired attribute from the mappings for the specified range of
3988 * addresses in the given pmap. Every valid mapping within that range
3989 * must have the wired attribute set. In contrast, invalid mappings
3990 * cannot have the wired attribute set, so they are ignored.
3992 * The wired attribute of the page table entry is not a hardware feature,
3993 * so there is no need to invalidate any TLB entries.
3996 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4001 boolean_t pv_lists_locked;
4003 if (pmap_is_current(pmap))
4004 pv_lists_locked = FALSE;
4006 pv_lists_locked = TRUE;
4008 rw_wlock(&pvh_global_lock);
4012 for (; sva < eva; sva = pdnxt) {
4013 pdnxt = (sva + NBPDR) & ~PDRMASK;
4016 pde = pmap_pde(pmap, sva);
4017 if ((*pde & PG_V) == 0)
4019 if ((*pde & PG_PS) != 0) {
4020 if ((*pde & PG_W) == 0)
4021 panic("pmap_unwire: pde %#jx is missing PG_W",
4025 * Are we unwiring the entire large page? If not,
4026 * demote the mapping and fall through.
4028 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4030 * Regardless of whether a pde (or pte) is 32
4031 * or 64 bits in size, PG_W is among the least
4032 * significant 32 bits.
4034 atomic_clear_int((u_int *)pde, PG_W);
4035 pmap->pm_stats.wired_count -= NBPDR /
4039 if (!pv_lists_locked) {
4040 pv_lists_locked = TRUE;
4041 if (!rw_try_wlock(&pvh_global_lock)) {
4048 if (!pmap_demote_pde(pmap, pde, sva))
4049 panic("pmap_unwire: demotion failed");
4054 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4056 if ((*pte & PG_V) == 0)
4058 if ((*pte & PG_W) == 0)
4059 panic("pmap_unwire: pte %#jx is missing PG_W",
4063 * PG_W must be cleared atomically. Although the pmap
4064 * lock synchronizes access to PG_W, another processor
4065 * could be setting PG_M and/or PG_A concurrently.
4067 * PG_W is among the least significant 32 bits.
4069 atomic_clear_int((u_int *)pte, PG_W);
4070 pmap->pm_stats.wired_count--;
4073 if (pv_lists_locked) {
4075 rw_wunlock(&pvh_global_lock);
4082 * Copy the range specified by src_addr/len
4083 * from the source map to the range dst_addr/len
4084 * in the destination map.
4086 * This routine is only advisory and need not do anything.
4090 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4091 vm_offset_t src_addr)
4093 struct spglist free;
4095 vm_offset_t end_addr = src_addr + len;
4098 if (dst_addr != src_addr)
4101 if (!pmap_is_current(src_pmap))
4104 rw_wlock(&pvh_global_lock);
4105 if (dst_pmap < src_pmap) {
4106 PMAP_LOCK(dst_pmap);
4107 PMAP_LOCK(src_pmap);
4109 PMAP_LOCK(src_pmap);
4110 PMAP_LOCK(dst_pmap);
4113 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4114 pt_entry_t *src_pte, *dst_pte;
4115 vm_page_t dstmpte, srcmpte;
4116 pd_entry_t srcptepaddr;
4119 KASSERT(addr < UPT_MIN_ADDRESS,
4120 ("pmap_copy: invalid to pmap_copy page tables"));
4122 pdnxt = (addr + NBPDR) & ~PDRMASK;
4125 ptepindex = addr >> PDRSHIFT;
4127 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4128 if (srcptepaddr == 0)
4131 if (srcptepaddr & PG_PS) {
4132 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4134 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4135 ((srcptepaddr & PG_MANAGED) == 0 ||
4136 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4138 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4140 dst_pmap->pm_stats.resident_count +=
4146 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4147 KASSERT(srcmpte->wire_count > 0,
4148 ("pmap_copy: source page table page is unused"));
4150 if (pdnxt > end_addr)
4153 src_pte = vtopte(addr);
4154 while (addr < pdnxt) {
4158 * we only virtual copy managed pages
4160 if ((ptetemp & PG_MANAGED) != 0) {
4161 dstmpte = pmap_allocpte(dst_pmap, addr,
4162 PMAP_ENTER_NOSLEEP);
4163 if (dstmpte == NULL)
4165 dst_pte = pmap_pte_quick(dst_pmap, addr);
4166 if (*dst_pte == 0 &&
4167 pmap_try_insert_pv_entry(dst_pmap, addr,
4168 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4170 * Clear the wired, modified, and
4171 * accessed (referenced) bits
4174 *dst_pte = ptetemp & ~(PG_W | PG_M |
4176 dst_pmap->pm_stats.resident_count++;
4179 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4181 pmap_invalidate_page(dst_pmap,
4183 pmap_free_zero_pages(&free);
4187 if (dstmpte->wire_count >= srcmpte->wire_count)
4196 rw_wunlock(&pvh_global_lock);
4197 PMAP_UNLOCK(src_pmap);
4198 PMAP_UNLOCK(dst_pmap);
4201 static __inline void
4202 pagezero(void *page)
4204 #if defined(I686_CPU)
4205 if (cpu_class == CPUCLASS_686) {
4206 #if defined(CPU_ENABLE_SSE)
4207 if (cpu_feature & CPUID_SSE2)
4208 sse2_pagezero(page);
4211 i686_pagezero(page);
4214 bzero(page, PAGE_SIZE);
4218 * pmap_zero_page zeros the specified hardware page by mapping
4219 * the page into KVM and using bzero to clear its contents.
4222 pmap_zero_page(vm_page_t m)
4224 struct sysmaps *sysmaps;
4226 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4227 mtx_lock(&sysmaps->lock);
4228 if (*sysmaps->CMAP2)
4229 panic("pmap_zero_page: CMAP2 busy");
4231 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4232 pmap_cache_bits(m->md.pat_mode, 0);
4233 invlcaddr(sysmaps->CADDR2);
4234 pagezero(sysmaps->CADDR2);
4235 *sysmaps->CMAP2 = 0;
4237 mtx_unlock(&sysmaps->lock);
4241 * pmap_zero_page_area zeros the specified hardware page by mapping
4242 * the page into KVM and using bzero to clear its contents.
4244 * off and size may not cover an area beyond a single hardware page.
4247 pmap_zero_page_area(vm_page_t m, int off, int size)
4249 struct sysmaps *sysmaps;
4251 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4252 mtx_lock(&sysmaps->lock);
4253 if (*sysmaps->CMAP2)
4254 panic("pmap_zero_page_area: CMAP2 busy");
4256 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4257 pmap_cache_bits(m->md.pat_mode, 0);
4258 invlcaddr(sysmaps->CADDR2);
4259 if (off == 0 && size == PAGE_SIZE)
4260 pagezero(sysmaps->CADDR2);
4262 bzero((char *)sysmaps->CADDR2 + off, size);
4263 *sysmaps->CMAP2 = 0;
4265 mtx_unlock(&sysmaps->lock);
4269 * pmap_zero_page_idle zeros the specified hardware page by mapping
4270 * the page into KVM and using bzero to clear its contents. This
4271 * is intended to be called from the vm_pagezero process only and
4275 pmap_zero_page_idle(vm_page_t m)
4279 panic("pmap_zero_page_idle: CMAP3 busy");
4281 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4282 pmap_cache_bits(m->md.pat_mode, 0);
4290 * pmap_copy_page copies the specified (machine independent)
4291 * page by mapping the page into virtual memory and using
4292 * bcopy to copy the page, one machine dependent page at a
4296 pmap_copy_page(vm_page_t src, vm_page_t dst)
4298 struct sysmaps *sysmaps;
4300 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4301 mtx_lock(&sysmaps->lock);
4302 if (*sysmaps->CMAP1)
4303 panic("pmap_copy_page: CMAP1 busy");
4304 if (*sysmaps->CMAP2)
4305 panic("pmap_copy_page: CMAP2 busy");
4307 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4308 pmap_cache_bits(src->md.pat_mode, 0);
4309 invlcaddr(sysmaps->CADDR1);
4310 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4311 pmap_cache_bits(dst->md.pat_mode, 0);
4312 invlcaddr(sysmaps->CADDR2);
4313 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4314 *sysmaps->CMAP1 = 0;
4315 *sysmaps->CMAP2 = 0;
4317 mtx_unlock(&sysmaps->lock);
4320 int unmapped_buf_allowed = 1;
4323 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4324 vm_offset_t b_offset, int xfersize)
4326 struct sysmaps *sysmaps;
4327 vm_page_t a_pg, b_pg;
4329 vm_offset_t a_pg_offset, b_pg_offset;
4332 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4333 mtx_lock(&sysmaps->lock);
4334 if (*sysmaps->CMAP1 != 0)
4335 panic("pmap_copy_pages: CMAP1 busy");
4336 if (*sysmaps->CMAP2 != 0)
4337 panic("pmap_copy_pages: CMAP2 busy");
4339 while (xfersize > 0) {
4340 a_pg = ma[a_offset >> PAGE_SHIFT];
4341 a_pg_offset = a_offset & PAGE_MASK;
4342 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4343 b_pg = mb[b_offset >> PAGE_SHIFT];
4344 b_pg_offset = b_offset & PAGE_MASK;
4345 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4346 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4347 pmap_cache_bits(a_pg->md.pat_mode, 0);
4348 invlcaddr(sysmaps->CADDR1);
4349 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4350 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4351 invlcaddr(sysmaps->CADDR2);
4352 a_cp = sysmaps->CADDR1 + a_pg_offset;
4353 b_cp = sysmaps->CADDR2 + b_pg_offset;
4354 bcopy(a_cp, b_cp, cnt);
4359 *sysmaps->CMAP1 = 0;
4360 *sysmaps->CMAP2 = 0;
4362 mtx_unlock(&sysmaps->lock);
4366 * Returns true if the pmap's pv is one of the first
4367 * 16 pvs linked to from this page. This count may
4368 * be changed upwards or downwards in the future; it
4369 * is only necessary that true be returned for a small
4370 * subset of pmaps for proper page aging.
4373 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4375 struct md_page *pvh;
4380 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4381 ("pmap_page_exists_quick: page %p is not managed", m));
4383 rw_wlock(&pvh_global_lock);
4384 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4385 if (PV_PMAP(pv) == pmap) {
4393 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4394 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4395 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4396 if (PV_PMAP(pv) == pmap) {
4405 rw_wunlock(&pvh_global_lock);
4410 * pmap_page_wired_mappings:
4412 * Return the number of managed mappings to the given physical page
4416 pmap_page_wired_mappings(vm_page_t m)
4421 if ((m->oflags & VPO_UNMANAGED) != 0)
4423 rw_wlock(&pvh_global_lock);
4424 count = pmap_pvh_wired_mappings(&m->md, count);
4425 if ((m->flags & PG_FICTITIOUS) == 0) {
4426 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4429 rw_wunlock(&pvh_global_lock);
4434 * pmap_pvh_wired_mappings:
4436 * Return the updated number "count" of managed mappings that are wired.
4439 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4445 rw_assert(&pvh_global_lock, RA_WLOCKED);
4447 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4450 pte = pmap_pte_quick(pmap, pv->pv_va);
4451 if ((*pte & PG_W) != 0)
4460 * Returns TRUE if the given page is mapped individually or as part of
4461 * a 4mpage. Otherwise, returns FALSE.
4464 pmap_page_is_mapped(vm_page_t m)
4468 if ((m->oflags & VPO_UNMANAGED) != 0)
4470 rw_wlock(&pvh_global_lock);
4471 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4472 ((m->flags & PG_FICTITIOUS) == 0 &&
4473 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4474 rw_wunlock(&pvh_global_lock);
4479 * Remove all pages from specified address space
4480 * this aids process exit speeds. Also, this code
4481 * is special cased for current process only, but
4482 * can have the more generic (and slightly slower)
4483 * mode enabled. This is much faster than pmap_remove
4484 * in the case of running down an entire address space.
4487 pmap_remove_pages(pmap_t pmap)
4489 pt_entry_t *pte, tpte;
4490 vm_page_t m, mpte, mt;
4492 struct md_page *pvh;
4493 struct pv_chunk *pc, *npc;
4494 struct spglist free;
4497 uint32_t inuse, bitmask;
4500 if (pmap != PCPU_GET(curpmap)) {
4501 printf("warning: pmap_remove_pages called with non-current pmap\n");
4505 rw_wlock(&pvh_global_lock);
4508 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4509 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4512 for (field = 0; field < _NPCM; field++) {
4513 inuse = ~pc->pc_map[field] & pc_freemask[field];
4514 while (inuse != 0) {
4516 bitmask = 1UL << bit;
4517 idx = field * 32 + bit;
4518 pv = &pc->pc_pventry[idx];
4521 pte = pmap_pde(pmap, pv->pv_va);
4523 if ((tpte & PG_PS) == 0) {
4524 pte = vtopte(pv->pv_va);
4525 tpte = *pte & ~PG_PTE_PAT;
4530 "TPTE at %p IS ZERO @ VA %08x\n",
4536 * We cannot remove wired pages from a process' mapping at this time
4543 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4544 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4545 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4546 m, (uintmax_t)m->phys_addr,
4549 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4550 m < &vm_page_array[vm_page_array_size],
4551 ("pmap_remove_pages: bad tpte %#jx",
4557 * Update the vm_page_t clean/reference bits.
4559 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4560 if ((tpte & PG_PS) != 0) {
4561 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4568 PV_STAT(pv_entry_frees++);
4569 PV_STAT(pv_entry_spare++);
4571 pc->pc_map[field] |= bitmask;
4572 if ((tpte & PG_PS) != 0) {
4573 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4574 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4575 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4576 if (TAILQ_EMPTY(&pvh->pv_list)) {
4577 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4578 if (TAILQ_EMPTY(&mt->md.pv_list))
4579 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4581 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4583 pmap_remove_pt_page(pmap, mpte);
4584 pmap->pm_stats.resident_count--;
4585 KASSERT(mpte->wire_count == NPTEPG,
4586 ("pmap_remove_pages: pte page wire count error"));
4587 mpte->wire_count = 0;
4588 pmap_add_delayed_free_list(mpte, &free, FALSE);
4589 atomic_subtract_int(&cnt.v_wire_count, 1);
4592 pmap->pm_stats.resident_count--;
4593 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4594 if (TAILQ_EMPTY(&m->md.pv_list) &&
4595 (m->flags & PG_FICTITIOUS) == 0) {
4596 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4597 if (TAILQ_EMPTY(&pvh->pv_list))
4598 vm_page_aflag_clear(m, PGA_WRITEABLE);
4600 pmap_unuse_pt(pmap, pv->pv_va, &free);
4605 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4610 pmap_invalidate_all(pmap);
4611 rw_wunlock(&pvh_global_lock);
4613 pmap_free_zero_pages(&free);
4619 * Return whether or not the specified physical page was modified
4620 * in any physical maps.
4623 pmap_is_modified(vm_page_t m)
4627 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4628 ("pmap_is_modified: page %p is not managed", m));
4631 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4632 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4633 * is clear, no PTEs can have PG_M set.
4635 VM_OBJECT_ASSERT_WLOCKED(m->object);
4636 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4638 rw_wlock(&pvh_global_lock);
4639 rv = pmap_is_modified_pvh(&m->md) ||
4640 ((m->flags & PG_FICTITIOUS) == 0 &&
4641 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4642 rw_wunlock(&pvh_global_lock);
4647 * Returns TRUE if any of the given mappings were used to modify
4648 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4649 * mappings are supported.
4652 pmap_is_modified_pvh(struct md_page *pvh)
4659 rw_assert(&pvh_global_lock, RA_WLOCKED);
4662 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4665 pte = pmap_pte_quick(pmap, pv->pv_va);
4666 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4676 * pmap_is_prefaultable:
4678 * Return whether or not the specified virtual address is elgible
4682 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4690 pde = pmap_pde(pmap, addr);
4691 if (*pde != 0 && (*pde & PG_PS) == 0) {
4700 * pmap_is_referenced:
4702 * Return whether or not the specified physical page was referenced
4703 * in any physical maps.
4706 pmap_is_referenced(vm_page_t m)
4710 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4711 ("pmap_is_referenced: page %p is not managed", m));
4712 rw_wlock(&pvh_global_lock);
4713 rv = pmap_is_referenced_pvh(&m->md) ||
4714 ((m->flags & PG_FICTITIOUS) == 0 &&
4715 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4716 rw_wunlock(&pvh_global_lock);
4721 * Returns TRUE if any of the given mappings were referenced and FALSE
4722 * otherwise. Both page and 4mpage mappings are supported.
4725 pmap_is_referenced_pvh(struct md_page *pvh)
4732 rw_assert(&pvh_global_lock, RA_WLOCKED);
4735 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4738 pte = pmap_pte_quick(pmap, pv->pv_va);
4739 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4749 * Clear the write and modified bits in each of the given page's mappings.
4752 pmap_remove_write(vm_page_t m)
4754 struct md_page *pvh;
4755 pv_entry_t next_pv, pv;
4758 pt_entry_t oldpte, *pte;
4761 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4762 ("pmap_remove_write: page %p is not managed", m));
4765 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4766 * set by another thread while the object is locked. Thus,
4767 * if PGA_WRITEABLE is clear, no page table entries need updating.
4769 VM_OBJECT_ASSERT_WLOCKED(m->object);
4770 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4772 rw_wlock(&pvh_global_lock);
4774 if ((m->flags & PG_FICTITIOUS) != 0)
4775 goto small_mappings;
4776 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4777 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4781 pde = pmap_pde(pmap, va);
4782 if ((*pde & PG_RW) != 0)
4783 (void)pmap_demote_pde(pmap, pde, va);
4787 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4790 pde = pmap_pde(pmap, pv->pv_va);
4791 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4792 " a 4mpage in page %p's pv list", m));
4793 pte = pmap_pte_quick(pmap, pv->pv_va);
4796 if ((oldpte & PG_RW) != 0) {
4798 * Regardless of whether a pte is 32 or 64 bits
4799 * in size, PG_RW and PG_M are among the least
4800 * significant 32 bits.
4802 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4803 oldpte & ~(PG_RW | PG_M)))
4805 if ((oldpte & PG_M) != 0)
4807 pmap_invalidate_page(pmap, pv->pv_va);
4811 vm_page_aflag_clear(m, PGA_WRITEABLE);
4813 rw_wunlock(&pvh_global_lock);
4816 #define PMAP_TS_REFERENCED_MAX 5
4819 * pmap_ts_referenced:
4821 * Return a count of reference bits for a page, clearing those bits.
4822 * It is not necessary for every reference bit to be cleared, but it
4823 * is necessary that 0 only be returned when there are truly no
4824 * reference bits set.
4826 * XXX: The exact number of bits to check and clear is a matter that
4827 * should be tested and standardized at some point in the future for
4828 * optimal aging of shared pages.
4831 pmap_ts_referenced(vm_page_t m)
4833 struct md_page *pvh;
4841 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4842 ("pmap_ts_referenced: page %p is not managed", m));
4843 pa = VM_PAGE_TO_PHYS(m);
4844 pvh = pa_to_pvh(pa);
4845 rw_wlock(&pvh_global_lock);
4847 if ((m->flags & PG_FICTITIOUS) != 0 ||
4848 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4849 goto small_mappings;
4854 pde = pmap_pde(pmap, pv->pv_va);
4855 if ((*pde & PG_A) != 0) {
4857 * Since this reference bit is shared by either 1024
4858 * or 512 4KB pages, it should not be cleared every
4859 * time it is tested. Apply a simple "hash" function
4860 * on the physical page number, the virtual superpage
4861 * number, and the pmap address to select one 4KB page
4862 * out of the 1024 or 512 on which testing the
4863 * reference bit will result in clearing that bit.
4864 * This function is designed to avoid the selection of
4865 * the same 4KB page for every 2- or 4MB page mapping.
4867 * On demotion, a mapping that hasn't been referenced
4868 * is simply destroyed. To avoid the possibility of a
4869 * subsequent page fault on a demoted wired mapping,
4870 * always leave its reference bit set. Moreover,
4871 * since the superpage is wired, the current state of
4872 * its reference bit won't affect page replacement.
4874 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4875 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4876 (*pde & PG_W) == 0) {
4877 atomic_clear_int((u_int *)pde, PG_A);
4878 pmap_invalidate_page(pmap, pv->pv_va);
4883 /* Rotate the PV list if it has more than one entry. */
4884 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4885 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4886 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4888 if (rtval >= PMAP_TS_REFERENCED_MAX)
4890 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4892 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4898 pde = pmap_pde(pmap, pv->pv_va);
4899 KASSERT((*pde & PG_PS) == 0,
4900 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4902 pte = pmap_pte_quick(pmap, pv->pv_va);
4903 if ((*pte & PG_A) != 0) {
4904 atomic_clear_int((u_int *)pte, PG_A);
4905 pmap_invalidate_page(pmap, pv->pv_va);
4909 /* Rotate the PV list if it has more than one entry. */
4910 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4911 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4912 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4914 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4915 PMAP_TS_REFERENCED_MAX);
4918 rw_wunlock(&pvh_global_lock);
4923 * Apply the given advice to the specified range of addresses within the
4924 * given pmap. Depending on the advice, clear the referenced and/or
4925 * modified flags in each mapping and set the mapped page's dirty field.
4928 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4930 pd_entry_t oldpde, *pde;
4934 boolean_t anychanged, pv_lists_locked;
4936 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4938 if (pmap_is_current(pmap))
4939 pv_lists_locked = FALSE;
4941 pv_lists_locked = TRUE;
4943 rw_wlock(&pvh_global_lock);
4948 for (; sva < eva; sva = pdnxt) {
4949 pdnxt = (sva + NBPDR) & ~PDRMASK;
4952 pde = pmap_pde(pmap, sva);
4954 if ((oldpde & PG_V) == 0)
4956 else if ((oldpde & PG_PS) != 0) {
4957 if ((oldpde & PG_MANAGED) == 0)
4959 if (!pv_lists_locked) {
4960 pv_lists_locked = TRUE;
4961 if (!rw_try_wlock(&pvh_global_lock)) {
4963 pmap_invalidate_all(pmap);
4969 if (!pmap_demote_pde(pmap, pde, sva)) {
4971 * The large page mapping was destroyed.
4977 * Unless the page mappings are wired, remove the
4978 * mapping to a single page so that a subsequent
4979 * access may repromote. Since the underlying page
4980 * table page is fully populated, this removal never
4981 * frees a page table page.
4983 if ((oldpde & PG_W) == 0) {
4984 pte = pmap_pte_quick(pmap, sva);
4985 KASSERT((*pte & PG_V) != 0,
4986 ("pmap_advise: invalid PTE"));
4987 pmap_remove_pte(pmap, pte, sva, NULL);
4993 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4995 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4998 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4999 if (advice == MADV_DONTNEED) {
5001 * Future calls to pmap_is_modified()
5002 * can be avoided by making the page
5005 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5008 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5009 } else if ((*pte & PG_A) != 0)
5010 atomic_clear_int((u_int *)pte, PG_A);
5013 if ((*pte & PG_G) != 0)
5014 pmap_invalidate_page(pmap, sva);
5020 pmap_invalidate_all(pmap);
5021 if (pv_lists_locked) {
5023 rw_wunlock(&pvh_global_lock);
5029 * Clear the modify bits on the specified physical page.
5032 pmap_clear_modify(vm_page_t m)
5034 struct md_page *pvh;
5035 pv_entry_t next_pv, pv;
5037 pd_entry_t oldpde, *pde;
5038 pt_entry_t oldpte, *pte;
5041 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5042 ("pmap_clear_modify: page %p is not managed", m));
5043 VM_OBJECT_ASSERT_WLOCKED(m->object);
5044 KASSERT(!vm_page_xbusied(m),
5045 ("pmap_clear_modify: page %p is exclusive busied", m));
5048 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5049 * If the object containing the page is locked and the page is not
5050 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5052 if ((m->aflags & PGA_WRITEABLE) == 0)
5054 rw_wlock(&pvh_global_lock);
5056 if ((m->flags & PG_FICTITIOUS) != 0)
5057 goto small_mappings;
5058 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5059 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5063 pde = pmap_pde(pmap, va);
5065 if ((oldpde & PG_RW) != 0) {
5066 if (pmap_demote_pde(pmap, pde, va)) {
5067 if ((oldpde & PG_W) == 0) {
5069 * Write protect the mapping to a
5070 * single page so that a subsequent
5071 * write access may repromote.
5073 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5075 pte = pmap_pte_quick(pmap, va);
5077 if ((oldpte & PG_V) != 0) {
5079 * Regardless of whether a pte is 32 or 64 bits
5080 * in size, PG_RW and PG_M are among the least
5081 * significant 32 bits.
5083 while (!atomic_cmpset_int((u_int *)pte,
5085 oldpte & ~(PG_M | PG_RW)))
5088 pmap_invalidate_page(pmap, va);
5096 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5099 pde = pmap_pde(pmap, pv->pv_va);
5100 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5101 " a 4mpage in page %p's pv list", m));
5102 pte = pmap_pte_quick(pmap, pv->pv_va);
5103 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5105 * Regardless of whether a pte is 32 or 64 bits
5106 * in size, PG_M is among the least significant
5109 atomic_clear_int((u_int *)pte, PG_M);
5110 pmap_invalidate_page(pmap, pv->pv_va);
5115 rw_wunlock(&pvh_global_lock);
5119 * Miscellaneous support routines follow
5122 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5123 static __inline void
5124 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5129 * The cache mode bits are all in the low 32-bits of the
5130 * PTE, so we can just spin on updating the low 32-bits.
5133 opte = *(u_int *)pte;
5134 npte = opte & ~PG_PTE_CACHE;
5136 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5139 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5140 static __inline void
5141 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5146 * The cache mode bits are all in the low 32-bits of the
5147 * PDE, so we can just spin on updating the low 32-bits.
5150 opde = *(u_int *)pde;
5151 npde = opde & ~PG_PDE_CACHE;
5153 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5157 * Map a set of physical memory pages into the kernel virtual
5158 * address space. Return a pointer to where it is mapped. This
5159 * routine is intended to be used for mapping device memory,
5163 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5165 vm_offset_t va, offset;
5168 offset = pa & PAGE_MASK;
5169 size = round_page(offset + size);
5172 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5175 va = kva_alloc(size);
5177 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5179 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5180 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5181 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5182 pmap_invalidate_cache_range(va, va + size, FALSE);
5183 return ((void *)(va + offset));
5187 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5190 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5194 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5197 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5201 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5203 vm_offset_t base, offset;
5205 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5207 base = trunc_page(va);
5208 offset = va & PAGE_MASK;
5209 size = round_page(offset + size);
5210 kva_free(base, size);
5214 * Sets the memory attribute for the specified page.
5217 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5220 m->md.pat_mode = ma;
5221 if ((m->flags & PG_FICTITIOUS) != 0)
5225 * If "m" is a normal page, flush it from the cache.
5226 * See pmap_invalidate_cache_range().
5228 * First, try to find an existing mapping of the page by sf
5229 * buffer. sf_buf_invalidate_cache() modifies mapping and
5230 * flushes the cache.
5232 if (sf_buf_invalidate_cache(m))
5236 * If page is not mapped by sf buffer, but CPU does not
5237 * support self snoop, map the page transient and do
5238 * invalidation. In the worst case, whole cache is flushed by
5239 * pmap_invalidate_cache_range().
5241 if ((cpu_feature & CPUID_SS) == 0)
5246 pmap_flush_page(vm_page_t m)
5248 struct sysmaps *sysmaps;
5249 vm_offset_t sva, eva;
5251 if ((cpu_feature & CPUID_CLFSH) != 0) {
5252 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5253 mtx_lock(&sysmaps->lock);
5254 if (*sysmaps->CMAP2)
5255 panic("pmap_flush_page: CMAP2 busy");
5257 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5258 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5259 invlcaddr(sysmaps->CADDR2);
5260 sva = (vm_offset_t)sysmaps->CADDR2;
5261 eva = sva + PAGE_SIZE;
5264 * Use mfence despite the ordering implied by
5265 * mtx_{un,}lock() because clflush is not guaranteed
5266 * to be ordered by any other instruction.
5269 for (; sva < eva; sva += cpu_clflush_line_size)
5272 *sysmaps->CMAP2 = 0;
5274 mtx_unlock(&sysmaps->lock);
5276 pmap_invalidate_cache();
5280 * Changes the specified virtual address range's memory type to that given by
5281 * the parameter "mode". The specified virtual address range must be
5282 * completely contained within either the kernel map.
5284 * Returns zero if the change completed successfully, and either EINVAL or
5285 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5286 * of the virtual address range was not mapped, and ENOMEM is returned if
5287 * there was insufficient memory available to complete the change.
5290 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5292 vm_offset_t base, offset, tmpva;
5295 int cache_bits_pte, cache_bits_pde;
5298 base = trunc_page(va);
5299 offset = va & PAGE_MASK;
5300 size = round_page(offset + size);
5303 * Only supported on kernel virtual addresses above the recursive map.
5305 if (base < VM_MIN_KERNEL_ADDRESS)
5308 cache_bits_pde = pmap_cache_bits(mode, 1);
5309 cache_bits_pte = pmap_cache_bits(mode, 0);
5313 * Pages that aren't mapped aren't supported. Also break down
5314 * 2/4MB pages into 4KB pages if required.
5316 PMAP_LOCK(kernel_pmap);
5317 for (tmpva = base; tmpva < base + size; ) {
5318 pde = pmap_pde(kernel_pmap, tmpva);
5320 PMAP_UNLOCK(kernel_pmap);
5325 * If the current 2/4MB page already has
5326 * the required memory type, then we need not
5327 * demote this page. Just increment tmpva to
5328 * the next 2/4MB page frame.
5330 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5331 tmpva = trunc_4mpage(tmpva) + NBPDR;
5336 * If the current offset aligns with a 2/4MB
5337 * page frame and there is at least 2/4MB left
5338 * within the range, then we need not break
5339 * down this page into 4KB pages.
5341 if ((tmpva & PDRMASK) == 0 &&
5342 tmpva + PDRMASK < base + size) {
5346 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5347 PMAP_UNLOCK(kernel_pmap);
5351 pte = vtopte(tmpva);
5353 PMAP_UNLOCK(kernel_pmap);
5358 PMAP_UNLOCK(kernel_pmap);
5361 * Ok, all the pages exist, so run through them updating their
5362 * cache mode if required.
5364 for (tmpva = base; tmpva < base + size; ) {
5365 pde = pmap_pde(kernel_pmap, tmpva);
5367 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5368 pmap_pde_attr(pde, cache_bits_pde);
5371 tmpva = trunc_4mpage(tmpva) + NBPDR;
5373 pte = vtopte(tmpva);
5374 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5375 pmap_pte_attr(pte, cache_bits_pte);
5383 * Flush CPU caches to make sure any data isn't cached that
5384 * shouldn't be, etc.
5387 pmap_invalidate_range(kernel_pmap, base, tmpva);
5388 pmap_invalidate_cache_range(base, tmpva, FALSE);
5394 * perform the pmap work for mincore
5397 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5400 pt_entry_t *ptep, pte;
5406 pdep = pmap_pde(pmap, addr);
5408 if (*pdep & PG_PS) {
5410 /* Compute the physical address of the 4KB page. */
5411 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5413 val = MINCORE_SUPER;
5415 ptep = pmap_pte(pmap, addr);
5417 pmap_pte_release(ptep);
5418 pa = pte & PG_FRAME;
5426 if ((pte & PG_V) != 0) {
5427 val |= MINCORE_INCORE;
5428 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5429 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5430 if ((pte & PG_A) != 0)
5431 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5433 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5434 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5435 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5436 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5437 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5440 PA_UNLOCK_COND(*locked_pa);
5446 pmap_activate(struct thread *td)
5448 pmap_t pmap, oldpmap;
5453 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5454 oldpmap = PCPU_GET(curpmap);
5455 cpuid = PCPU_GET(cpuid);
5457 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5458 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5460 CPU_CLR(cpuid, &oldpmap->pm_active);
5461 CPU_SET(cpuid, &pmap->pm_active);
5463 #if defined(PAE) || defined(PAE_TABLES)
5464 cr3 = vtophys(pmap->pm_pdpt);
5466 cr3 = vtophys(pmap->pm_pdir);
5469 * pmap_activate is for the current thread on the current cpu
5471 td->td_pcb->pcb_cr3 = cr3;
5473 PCPU_SET(curpmap, pmap);
5478 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5483 * Increase the starting virtual address of the given mapping if a
5484 * different alignment might result in more superpage mappings.
5487 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5488 vm_offset_t *addr, vm_size_t size)
5490 vm_offset_t superpage_offset;
5494 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5495 offset += ptoa(object->pg_color);
5496 superpage_offset = offset & PDRMASK;
5497 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5498 (*addr & PDRMASK) == superpage_offset)
5500 if ((*addr & PDRMASK) < superpage_offset)
5501 *addr = (*addr & ~PDRMASK) + superpage_offset;
5503 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5507 #if defined(PMAP_DEBUG)
5508 pmap_pid_dump(int pid)
5515 sx_slock(&allproc_lock);
5516 FOREACH_PROC_IN_SYSTEM(p) {
5517 if (p->p_pid != pid)
5523 pmap = vmspace_pmap(p->p_vmspace);
5524 for (i = 0; i < NPDEPTD; i++) {
5527 vm_offset_t base = i << PDRSHIFT;
5529 pde = &pmap->pm_pdir[i];
5530 if (pde && pmap_pde_v(pde)) {
5531 for (j = 0; j < NPTEPG; j++) {
5532 vm_offset_t va = base + (j << PAGE_SHIFT);
5533 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5538 sx_sunlock(&allproc_lock);
5541 pte = pmap_pte(pmap, va);
5542 if (pte && pmap_pte_v(pte)) {
5546 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5547 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5548 va, pa, m->hold_count, m->wire_count, m->flags);
5563 sx_sunlock(&allproc_lock);
5570 static void pads(pmap_t pm);
5571 void pmap_pvdump(vm_paddr_t pa);
5573 /* print address space of pmap*/
5581 if (pm == kernel_pmap)
5583 for (i = 0; i < NPDEPTD; i++)
5585 for (j = 0; j < NPTEPG; j++) {
5586 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5587 if (pm == kernel_pmap && va < KERNBASE)
5589 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5591 ptep = pmap_pte(pm, va);
5592 if (pmap_pte_v(ptep))
5593 printf("%x:%x ", va, *ptep);
5599 pmap_pvdump(vm_paddr_t pa)
5605 printf("pa %x", pa);
5606 m = PHYS_TO_VM_PAGE(pa);
5607 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5609 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);