2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <mips/atheros/ar933x_uart.h>
45 * Default system clock is 25MHz; see ar933x_chip.c for how
46 * the startup process determines whether it's 25MHz or 40MHz.
48 #define DEFAULT_RCLK (25 * 1000 * 1000)
50 #define ar933x_getreg(bas, reg) \
51 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
52 #define ar933x_setreg(bas, reg, value) \
53 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
58 ar933x_drain(struct uart_bas *bas, int what)
62 if (what & UART_DRAIN_TRANSMITTER) {
65 /* Loop over until the TX FIFO shows entirely clear */
67 if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
68 & AR933X_UART_CS_TX_BUSY) == 0)
76 if (what & UART_DRAIN_RECEIVER) {
80 /* XXX duplicated from ar933x_getc() */
81 /* XXX TODO: refactor! */
83 /* If there's nothing to read, stop! */
84 if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
85 AR933X_UART_DATA_RX_CSR) == 0) {
89 /* Read the top of the RX FIFO */
90 (void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
92 /* Remove that entry from said RX FIFO */
93 ar933x_setreg(bas, AR933X_UART_DATA_REG,
94 AR933X_UART_DATA_RX_CSR);
107 * Calculate the baud from the given chip configuration parameters.
110 ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
116 div = (2 << 16) * (scale + 1);
126 * Calculate the scale/step with the lowest possible deviation from
127 * the target baudrate.
130 ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
131 unsigned int *scale, unsigned int *step)
142 for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
146 tstep = baud * (tscale + 1);
150 if (tstep > AR933X_UART_MAX_STEP)
153 diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
154 if (diff < min_diff) {
163 ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
166 /* UART always 8 bits */
168 /* UART always 1 stop bit */
170 /* UART parity is controllable by bits 0:1, ignore for now */
172 /* Set baudrate if required. */
174 uint32_t clock_scale, clock_step;
176 /* Find the best fit for the given baud rate */
177 ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
181 * Program the clock register in its entirety - no need
182 * for Read-Modify-Write.
184 ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
185 ((clock_scale & AR933X_UART_CLOCK_SCALE_M)
186 << AR933X_UART_CLOCK_SCALE_S) |
187 (clock_step & AR933X_UART_CLOCK_STEP_M));
196 * Low-level UART interface.
198 static int ar933x_probe(struct uart_bas *bas);
199 static void ar933x_init(struct uart_bas *bas, int, int, int, int);
200 static void ar933x_term(struct uart_bas *bas);
201 static void ar933x_putc(struct uart_bas *bas, int);
202 static int ar933x_rxready(struct uart_bas *bas);
203 static int ar933x_getc(struct uart_bas *bas, struct mtx *);
205 static struct uart_ops uart_ar933x_ops = {
206 .probe = ar933x_probe,
210 .rxready = ar933x_rxready,
215 ar933x_probe(struct uart_bas *bas)
218 /* We always know this will be here */
223 ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
228 /* Setup default parameters */
229 ar933x_param(bas, baudrate, databits, stopbits, parity);
231 /* XXX Force enable UART in case it was disabled */
233 /* Disable all interrupts */
234 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
236 /* Disable the host interrupt */
237 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
238 reg &= ~AR933X_UART_CS_HOST_INT_EN;
239 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
243 /* XXX Set RTS/DTR? */
247 * Detach from console.
250 ar933x_term(struct uart_bas *bas)
257 ar933x_putc(struct uart_bas *bas, int c)
263 /* Wait for space in the TX FIFO */
264 while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
265 AR933X_UART_DATA_TX_CSR) == 0) && --limit)
268 /* Write the actual byte */
269 ar933x_setreg(bas, AR933X_UART_DATA_REG,
270 (c & 0xff) | AR933X_UART_DATA_TX_CSR);
274 ar933x_rxready(struct uart_bas *bas)
277 /* Wait for a character to come ready */
278 return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
279 & AR933X_UART_DATA_RX_CSR));
283 ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
289 /* Wait for a character to come ready */
290 while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
291 AR933X_UART_DATA_RX_CSR) == 0) {
297 /* Read the top of the RX FIFO */
298 c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
300 /* Remove that entry from said RX FIFO */
301 ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
309 * High-level UART interface.
311 struct ar933x_softc {
312 struct uart_softc base;
317 static int ar933x_bus_attach(struct uart_softc *);
318 static int ar933x_bus_detach(struct uart_softc *);
319 static int ar933x_bus_flush(struct uart_softc *, int);
320 static int ar933x_bus_getsig(struct uart_softc *);
321 static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
322 static int ar933x_bus_ipend(struct uart_softc *);
323 static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
324 static int ar933x_bus_probe(struct uart_softc *);
325 static int ar933x_bus_receive(struct uart_softc *);
326 static int ar933x_bus_setsig(struct uart_softc *, int);
327 static int ar933x_bus_transmit(struct uart_softc *);
328 static void ar933x_bus_grab(struct uart_softc *);
329 static void ar933x_bus_ungrab(struct uart_softc *);
331 static kobj_method_t ar933x_methods[] = {
332 KOBJMETHOD(uart_attach, ar933x_bus_attach),
333 KOBJMETHOD(uart_detach, ar933x_bus_detach),
334 KOBJMETHOD(uart_flush, ar933x_bus_flush),
335 KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
336 KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
337 KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
338 KOBJMETHOD(uart_param, ar933x_bus_param),
339 KOBJMETHOD(uart_probe, ar933x_bus_probe),
340 KOBJMETHOD(uart_receive, ar933x_bus_receive),
341 KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
342 KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
343 KOBJMETHOD(uart_grab, ar933x_bus_grab),
344 KOBJMETHOD(uart_ungrab, ar933x_bus_ungrab),
348 struct uart_class uart_ar933x_class = {
351 sizeof(struct ar933x_softc),
352 .uc_ops = &uart_ar933x_ops,
354 .uc_rclk = DEFAULT_RCLK
357 #define SIGCHG(c, i, s, d) \
359 i |= (i & s) ? s : s | d; \
361 i = (i & s) ? (i & ~s) | d : i; \
365 ar933x_bus_attach(struct uart_softc *sc)
367 struct ar933x_softc *u = (struct ar933x_softc *)sc;
368 struct uart_bas *bas = &sc->sc_bas;
371 /* XXX TODO: flush transmitter */
374 * Setup initial interrupt notifications.
376 * XXX for now, just RX FIFO valid.
377 * Later on (when they're handled), also handle
378 * RX errors/overflow.
380 u->u_ier = AR933X_UART_INT_RX_VALID;
382 /* Enable RX interrupts to kick-start things */
383 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
385 /* Enable the host interrupt now */
386 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
387 reg |= AR933X_UART_CS_HOST_INT_EN;
388 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
394 ar933x_bus_detach(struct uart_softc *sc)
396 struct uart_bas *bas = &sc->sc_bas;
399 /* Disable all interrupts */
400 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
402 /* Disable the host interrupt */
403 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
404 reg &= ~AR933X_UART_CS_HOST_INT_EN;
405 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
412 ar933x_bus_flush(struct uart_softc *sc, int what)
414 struct uart_bas *bas;
417 uart_lock(sc->sc_hwmtx);
418 ar933x_drain(bas, what);
419 uart_unlock(sc->sc_hwmtx);
425 ar933x_bus_getsig(struct uart_softc *sc)
427 uint32_t sig = sc->sc_hwsig;
430 * For now, let's just return that DSR/DCD/CTS is asserted.
432 * XXX TODO: actually verify whether this is correct!
434 SIGCHG(1, sig, SER_DSR, SER_DDSR);
435 SIGCHG(1, sig, SER_CTS, SER_DCTS);
436 SIGCHG(1, sig, SER_DCD, SER_DDCD);
437 SIGCHG(1, sig, SER_RI, SER_DRI);
439 sc->sc_hwsig = sig & ~SER_MASK_DELTA;
445 ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
448 struct uart_bas *bas;
449 int baudrate, divisor, error;
454 uart_lock(sc->sc_hwmtx);
456 case UART_IOCTL_BREAK:
457 lcr = uart_getreg(bas, REG_LCR);
462 uart_setreg(bas, REG_LCR, lcr);
465 case UART_IOCTL_IFLOW:
466 lcr = uart_getreg(bas, REG_LCR);
468 uart_setreg(bas, REG_LCR, 0xbf);
470 efr = uart_getreg(bas, REG_EFR);
475 uart_setreg(bas, REG_EFR, efr);
477 uart_setreg(bas, REG_LCR, lcr);
480 case UART_IOCTL_OFLOW:
481 lcr = uart_getreg(bas, REG_LCR);
483 uart_setreg(bas, REG_LCR, 0xbf);
485 efr = uart_getreg(bas, REG_EFR);
490 uart_setreg(bas, REG_EFR, efr);
492 uart_setreg(bas, REG_LCR, lcr);
495 case UART_IOCTL_BAUD:
496 lcr = uart_getreg(bas, REG_LCR);
497 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
499 divisor = uart_getreg(bas, REG_DLL) |
500 (uart_getreg(bas, REG_DLH) << 8);
502 uart_setreg(bas, REG_LCR, lcr);
504 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
506 *(int*)data = baudrate;
514 uart_unlock(sc->sc_hwmtx);
521 * Bus interrupt handler.
523 * For now, system interrupts are disabled.
524 * So this is just called from a callout in uart_core.c
525 * to poll various state.
528 ar933x_bus_ipend(struct uart_softc *sc)
530 struct ar933x_softc *u = (struct ar933x_softc *)sc;
531 struct uart_bas *bas = &sc->sc_bas;
535 uart_lock(sc->sc_hwmtx);
538 * Fetch/ACK the ISR status.
540 isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
541 ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
545 * RX ready - notify upper layer.
547 if (isr & AR933X_UART_INT_RX_VALID) {
548 ipend |= SER_INT_RXREADY;
552 * If we get this interrupt, we should disable
553 * it from the interrupt mask and inform the uart
554 * driver appropriately.
556 * We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
557 * all the time or IO stops working. So we will always
558 * clear this interrupt if we get it, then we only signal
559 * the upper layer if we were doing active TX in the
562 * Also, the name is misleading. This actually means
563 * "the FIFO is almost empty." So if we just write some
564 * more data to the FIFO without checking whether it can
565 * take said data, we'll overflow the thing.
567 * Unfortunately the FreeBSD uart device has no concept of
568 * partial UART writes - it expects that the whole buffer
569 * is written to the hardware. Thus for now, ar933x_bus_transmit()
570 * will wait for the FIFO to finish draining before it pushes
571 * more frames into it.
573 if (isr & AR933X_UART_INT_TX_EMPTY) {
575 * Update u_ier to disable TX notifications; update hardware
577 u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
578 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
583 * Only signal TX idle if we're not busy transmitting.
586 if (isr & AR933X_UART_INT_TX_EMPTY) {
587 ipend |= SER_INT_TXIDLE;
589 ipend |= SER_INT_SIGCHG;
593 uart_unlock(sc->sc_hwmtx);
598 ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
599 int stopbits, int parity)
601 struct uart_bas *bas;
605 uart_lock(sc->sc_hwmtx);
606 error = ar933x_param(bas, baudrate, databits, stopbits, parity);
607 uart_unlock(sc->sc_hwmtx);
612 ar933x_bus_probe(struct uart_softc *sc)
614 struct uart_bas *bas;
619 error = ar933x_probe(bas);
624 ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
626 /* XXX TODO: actually find out what the FIFO depth is! */
627 sc->sc_rxfifosz = 16;
628 sc->sc_txfifosz = 16;
634 ar933x_bus_receive(struct uart_softc *sc)
636 struct uart_bas *bas = &sc->sc_bas;
639 uart_lock(sc->sc_hwmtx);
641 /* Loop over until we are full, or no data is available */
642 while (ar933x_rxready(bas)) {
643 if (uart_rx_full(sc)) {
644 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
648 /* Read the top of the RX FIFO */
649 xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
651 /* Remove that entry from said RX FIFO */
652 ar933x_setreg(bas, AR933X_UART_DATA_REG,
653 AR933X_UART_DATA_RX_CSR);
656 /* XXX frame, parity error */
661 * XXX TODO: Discard everything left in the Rx FIFO?
662 * XXX only if we've hit an overrun condition?
665 uart_unlock(sc->sc_hwmtx);
671 ar933x_bus_setsig(struct uart_softc *sc, int sig)
674 struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
675 struct uart_bas *bas;
682 if (sig & SER_DDTR) {
683 SIGCHG(sig & SER_DTR, new, SER_DTR,
686 if (sig & SER_DRTS) {
687 SIGCHG(sig & SER_RTS, new, SER_RTS,
690 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
691 uart_lock(sc->sc_hwmtx);
692 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
694 ns8250->mcr |= MCR_DTR;
696 ns8250->mcr |= MCR_RTS;
697 uart_setreg(bas, REG_MCR, ns8250->mcr);
699 uart_unlock(sc->sc_hwmtx);
705 * Write the current transmit buffer to the TX FIFO.
707 * Unfortunately the FreeBSD uart device has no concept of
708 * partial UART writes - it expects that the whole buffer
709 * is written to the hardware. Thus for now, this will wait for
710 * the FIFO to finish draining before it pushes more frames into it.
712 * If non-blocking operation is truely needed here, either
713 * the FreeBSD uart device will need to handle partial writes
714 * in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
718 ar933x_bus_transmit(struct uart_softc *sc)
720 struct uart_bas *bas = &sc->sc_bas;
721 struct ar933x_softc *u = (struct ar933x_softc *)sc;
724 uart_lock(sc->sc_hwmtx);
726 /* Wait for the FIFO to be clear - see above */
727 while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
728 AR933X_UART_CS_TX_BUSY)
734 for (i = 0; i < sc->sc_txdatasz; i++) {
735 /* Write the TX data */
736 ar933x_setreg(bas, AR933X_UART_DATA_REG,
737 (sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
742 * Now that we're transmitting, get interrupt notification
743 * when the FIFO is (almost) empty - see above.
745 u->u_ier |= AR933X_UART_INT_TX_EMPTY;
746 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
750 * Inform the upper layer that we are presently transmitting
751 * data to the hardware; this will be cleared when the
752 * TXIDLE interrupt occurs.
755 uart_unlock(sc->sc_hwmtx);
761 ar933x_bus_grab(struct uart_softc *sc)
763 struct uart_bas *bas = &sc->sc_bas;
766 /* Disable the host interrupt now */
767 uart_lock(sc->sc_hwmtx);
768 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
769 reg &= ~AR933X_UART_CS_HOST_INT_EN;
770 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
771 uart_unlock(sc->sc_hwmtx);
775 ar933x_bus_ungrab(struct uart_softc *sc)
777 struct uart_bas *bas = &sc->sc_bas;
780 /* Enable the host interrupt now */
781 uart_lock(sc->sc_hwmtx);
782 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
783 reg |= AR933X_UART_CS_HOST_INT_EN;
784 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
785 uart_unlock(sc->sc_hwmtx);