sys/ofed/drivers/net/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33 #include "opt_inet.h"
  34 #include <linux/mlx4/cq.h>
  35 #include <linux/slab.h>
  36 #include <linux/mlx4/qp.h>
  37 #include <linux/if_ether.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/vmalloc.h>
  40 #include <linux/mlx4/driver.h>
  41 #ifdef CONFIG_NET_RX_BUSY_POLL
  42 #include <net/busy_poll.h>
  43 #endif
  44
  45 #include "mlx4_en.h"
  46
  47
  48 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  49                                  struct mlx4_en_rx_ring *ring,
  50                                  int index)
  51 {
  52         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  53         int possible_frags;
  54         int i;
  55
  56
  57         /* Set size and memtype fields */
  58         for (i = 0; i < priv->num_frags; i++) {
  59                 rx_desc->data[i].byte_count =
  60                         cpu_to_be32(priv->frag_info[i].frag_size);
  61                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  62         }
  63
  64         /* If the number of used fragments does not fill up the ring stride,
  65          *          * remaining (unused) fragments must be padded with null address/size
  66          *                   * and a special memory key */
  67         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  68         for (i = priv->num_frags; i < possible_frags; i++) {
  69                 rx_desc->data[i].byte_count = 0;
  70                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  71                 rx_desc->data[i].addr = 0;
  72         }
  73
  74 }
  75
  76 static int mlx4_en_alloc_buf(struct mlx4_en_priv *priv,
  77                              struct mlx4_en_rx_desc *rx_desc,
  78                              struct mbuf **mb_list,
  79                              int i)
  80 {
  81         struct mlx4_en_dev *mdev = priv->mdev;
  82         struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  83         struct mbuf *mb;
  84         dma_addr_t dma;
  85
  86         if (i == 0)
  87                 mb = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, frag_info->frag_size);
  88         else
  89                 mb = m_getjcl(M_NOWAIT, MT_DATA, 0, frag_info->frag_size);
  90         if (mb == NULL) {
  91                 priv->port_stats.rx_alloc_failed++;
  92                 return -ENOMEM;
  93         }
  94         dma = pci_map_single(mdev->pdev, mb->m_data, frag_info->frag_size,
  95                              PCI_DMA_FROMDEVICE);
  96         rx_desc->data[i].addr = cpu_to_be64(dma);
  97         mb_list[i] = mb;
  98         return 0;
  99 }
 100
 101
 102 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 103                                    struct mlx4_en_rx_ring *ring, int index)
 104 {
 105         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 106         struct mbuf **mb_list = ring->rx_info + (index << priv->log_rx_info);
 107         int i;
 108
 109         for (i = 0; i < priv->num_frags; i++)
 110                 if (mlx4_en_alloc_buf(priv, rx_desc, mb_list, i))
 111                         goto err;
 112
 113         return 0;
 114
 115 err:
 116         while (i--)
 117                 m_free(mb_list[i]);
 118         return -ENOMEM;
 119 }
 120
 121 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 122 {
 123         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 124 }
 125
 126 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 127                                  struct mlx4_en_rx_ring *ring,
 128                                  int index)
 129 {
 130         struct mlx4_en_frag_info *frag_info;
 131         struct mlx4_en_dev *mdev = priv->mdev;
 132         struct mbuf **mb_list;
 133         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
 134         dma_addr_t dma;
 135         int nr;
 136
 137         mb_list = ring->rx_info + (index << priv->log_rx_info);
 138         for (nr = 0; nr < priv->num_frags; nr++) {
 139                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 140                 frag_info = &priv->frag_info[nr];
 141                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 142
 143 #if BITS_PER_LONG == 64
 144                 en_dbg(DRV, priv, "Unmaping buffer at dma:0x%lx\n", (u64) dma);
 145 #elif BITS_PER_LONG == 32
 146                 en_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
 147 #endif
 148                 pci_unmap_single(mdev->pdev, dma, frag_info->frag_size,
 149                                  PCI_DMA_FROMDEVICE);
 150                 m_free(mb_list[nr]);
 151         }
 152 }
 153
 154 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 155 {
 156         struct mlx4_en_rx_ring *ring;
 157         int ring_ind;
 158         int buf_ind;
 159         int new_size;
 160         int err;
 161
 162         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 163                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 164                         ring = priv->rx_ring[ring_ind];
 165
 166                         err = mlx4_en_prepare_rx_desc(priv, ring,
 167                                                       ring->actual_size);
 168                         if (err) {
 169                                 if (ring->actual_size == 0) {
 170                                         en_err(priv, "Failed to allocate "
 171                                                      "enough rx buffers\n");
 172                                         return -ENOMEM;
 173                                 } else {
 174                                         new_size =
 175                                                 rounddown_pow_of_two(ring->actual_size);
 176                                         en_warn(priv, "Only %d buffers allocated "
 177                                                       "reducing ring size to %d\n",
 178                                                 ring->actual_size, new_size);
 179                                         goto reduce_rings;
 180                                 }
 181                         }
 182                         ring->actual_size++;
 183                         ring->prod++;
 184                 }
 185         }
 186         return 0;
 187
 188 reduce_rings:
 189         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 190                 ring = priv->rx_ring[ring_ind];
 191                 while (ring->actual_size > new_size) {
 192                         ring->actual_size--;
 193                         ring->prod--;
 194                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 195                 }
 196         }
 197
 198         return 0;
 199 }
 200
 201 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 202                                 struct mlx4_en_rx_ring *ring)
 203 {
 204         int index;
 205
 206         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 207                ring->cons, ring->prod);
 208
 209         /* Unmap and free Rx buffers */
 210         BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
 211         while (ring->cons != ring->prod) {
 212                 index = ring->cons & ring->size_mask;
 213                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 214                 mlx4_en_free_rx_desc(priv, ring, index);
 215                 ++ring->cons;
 216         }
 217 }
 218
 219 #if MLX4_EN_MAX_RX_FRAGS == 3
 220 static int frag_sizes[] = {
 221         FRAG_SZ0,
 222         FRAG_SZ1,
 223         FRAG_SZ2,
 224 };
 225 #elif MLX4_EN_MAX_RX_FRAGS == 2
 226 static int frag_sizes[] = {
 227         FRAG_SZ0,
 228         FRAG_SZ1,
 229 };
 230 #else
 231 #error "Unknown MAX_RX_FRAGS"
 232 #endif
 233
 234 void mlx4_en_calc_rx_buf(struct net_device *dev)
 235 {
 236         struct mlx4_en_priv *priv = netdev_priv(dev);
 237         int eff_mtu = dev->if_mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
 238         int buf_size = 0;
 239         int i, frag;
 240
 241         for (i = 0, frag = 0; buf_size < eff_mtu; frag++, i++) {
 242                 /*
 243                  * Allocate small to large but only as much as is needed for
 244                  * the tail.
 245                  */
 246                 while (i > 0 && eff_mtu - buf_size <= frag_sizes[i - 1])
 247                         i--;
 248                 priv->frag_info[frag].frag_size = frag_sizes[i];
 249                 priv->frag_info[frag].frag_prefix_size = buf_size;
 250                 buf_size += priv->frag_info[frag].frag_size;
 251         }
 252
 253         priv->num_frags = frag;
 254         priv->rx_mb_size = eff_mtu;
 255         priv->log_rx_info =
 256             ROUNDUP_LOG2(priv->num_frags * sizeof(struct mbuf *));
 257
 258         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
 259                   "num_frags:%d):\n", eff_mtu, priv->num_frags);
 260         for (i = 0; i < priv->num_frags; i++) {
 261                 en_dbg(DRV, priv, "  frag:%d - size:%d prefix:%d\n", i,
 262                                 priv->frag_info[i].frag_size,
 263                                 priv->frag_info[i].frag_prefix_size);
 264         }
 265 }
 266
 267
 268 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 269                            struct mlx4_en_rx_ring **pring,
 270                            u32 size, int node)
 271 {
 272         struct mlx4_en_dev *mdev = priv->mdev;
 273         struct mlx4_en_rx_ring *ring;
 274         int err = -ENOMEM;
 275         int tmp;
 276
 277         ring = kzalloc(sizeof(struct mlx4_en_rx_ring), GFP_KERNEL);
 278         if (!ring) {
 279                 en_err(priv, "Failed to allocate RX ring structure\n");
 280                 return -ENOMEM;
 281         }
 282
 283         ring->prod = 0;
 284         ring->cons = 0;
 285         ring->size = size;
 286         ring->size_mask = size - 1;
 287         ring->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 288                                                   DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
 289         ring->log_stride = ffs(ring->stride) - 1;
 290         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 291
 292         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 293                                                 sizeof(struct mbuf *));
 294
 295         ring->rx_info = kmalloc(tmp, GFP_KERNEL);
 296         if (!ring->rx_info) {
 297                 err = -ENOMEM;
 298                 goto err_ring;
 299         }
 300
 301         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 302                  ring->rx_info, tmp);
 303
 304         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
 305                                  ring->buf_size, 2 * PAGE_SIZE);
 306         if (err)
 307                 goto err_info;
 308
 309         err = mlx4_en_map_buffer(&ring->wqres.buf);
 310         if (err) {
 311                 en_err(priv, "Failed to map RX buffer\n");
 312                 goto err_hwq;
 313         }
 314         ring->buf = ring->wqres.buf.direct.buf;
 315         *pring = ring;
 316         return 0;
 317
 318 err_hwq:
 319         mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 320 err_info:
 321         vfree(ring->rx_info);
 322 err_ring:
 323         kfree(ring);
 324
 325         return err;
 326 }
 327
 328
 329 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 330 {
 331         struct mlx4_en_rx_ring *ring;
 332         int i;
 333         int ring_ind;
 334         int err;
 335         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 336                                                 DS_SIZE * priv->num_frags);
 337
 338         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 339                 ring = priv->rx_ring[ring_ind];
 340
 341                 ring->prod = 0;
 342                 ring->cons = 0;
 343                 ring->actual_size = 0;
 344                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 345                 ring->rx_alloc_order = priv->rx_alloc_order;
 346                 ring->rx_alloc_size = priv->rx_alloc_size;
 347                 ring->rx_buf_size = priv->rx_buf_size;
 348                 ring->rx_mb_size = priv->rx_mb_size;
 349
 350                 ring->stride = stride;
 351                 if (ring->stride <= TXBB_SIZE)
 352                         ring->buf += TXBB_SIZE;
 353
 354                 ring->log_stride = ffs(ring->stride) - 1;
 355                 ring->buf_size = ring->size * ring->stride;
 356
 357                 memset(ring->buf, 0, ring->buf_size);
 358                 mlx4_en_update_rx_prod_db(ring);
 359
 360                 /* Initialize all descriptors */
 361                 for (i = 0; i < ring->size; i++)
 362                         mlx4_en_init_rx_desc(priv, ring, i);
 363
 364 #ifdef INET
 365                 /* Configure lro mngr */
 366                 if (priv->dev->if_capenable & IFCAP_LRO) {
 367                         if (tcp_lro_init(&ring->lro))
 368                                 priv->dev->if_capenable &= ~IFCAP_LRO;
 369                         else
 370                                 ring->lro.ifp = priv->dev;
 371                 }
 372 #endif
 373         }
 374
 375
 376         err = mlx4_en_fill_rx_buffers(priv);
 377         if (err)
 378                 goto err_buffers;
 379
 380         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 381                 ring = priv->rx_ring[ring_ind];
 382
 383                 ring->size_mask = ring->actual_size - 1;
 384                 mlx4_en_update_rx_prod_db(ring);
 385         }
 386
 387         return 0;
 388
 389 err_buffers:
 390         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 391                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 392
 393         ring_ind = priv->rx_ring_num - 1;
 394
 395         while (ring_ind >= 0) {
 396                 ring = priv->rx_ring[ring_ind];
 397                 if (ring->stride <= TXBB_SIZE)
 398                         ring->buf -= TXBB_SIZE;
 399                 ring_ind--;
 400         }
 401
 402         return err;
 403 }
 404
 405
 406 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 407                              struct mlx4_en_rx_ring **pring,
 408                              u32 size, u16 stride)
 409 {
 410         struct mlx4_en_dev *mdev = priv->mdev;
 411         struct mlx4_en_rx_ring *ring = *pring;
 412
 413         mlx4_en_unmap_buffer(&ring->wqres.buf);
 414         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 415         vfree(ring->rx_info);
 416         kfree(ring);
 417         *pring = NULL;
 418 #ifdef CONFIG_RFS_ACCEL
 419         mlx4_en_cleanup_filters(priv, ring);
 420 #endif
 421 }
 422
 423
 424 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 425                                 struct mlx4_en_rx_ring *ring)
 426 {
 427 #ifdef INET
 428         tcp_lro_free(&ring->lro);
 429 #endif
 430         mlx4_en_free_rx_buf(priv, ring);
 431         if (ring->stride <= TXBB_SIZE)
 432                 ring->buf -= TXBB_SIZE;
 433 }
 434
 435
 436 static void validate_loopback(struct mlx4_en_priv *priv, struct mbuf *mb)
 437 {
 438         int i;
 439         int offset = ETHER_HDR_LEN;
 440
 441         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 442                 if (*(mb->m_data + offset) != (unsigned char) (i & 0xff))
 443                         goto out_loopback;
 444         }
 445         /* Loopback found */
 446         priv->loopback_ok = 1;
 447
 448 out_loopback:
 449         m_freem(mb);
 450 }
 451
 452
 453 static inline int invalid_cqe(struct mlx4_en_priv *priv,
 454                               struct mlx4_cqe *cqe)
 455 {
 456         /* Drop packet on bad receive or bad checksum */
 457         if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 458                      MLX4_CQE_OPCODE_ERROR)) {
 459                 en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 460                        ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 461                        ((struct mlx4_err_cqe *)cqe)->syndrome);
 462                 return 1;
 463         }
 464         if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 465                 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 466                 return 1;
 467         }
 468
 469         return 0;
 470 }
 471
 472
 473 /* Unmap a completed descriptor and free unused pages */
 474 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 475                                     struct mlx4_en_rx_desc *rx_desc,
 476                                     struct mbuf **mb_list,
 477                                     int length)
 478 {
 479         struct mlx4_en_dev *mdev = priv->mdev;
 480         struct mlx4_en_frag_info *frag_info;
 481         dma_addr_t dma;
 482         struct mbuf *mb;
 483         int nr;
 484
 485         mb = mb_list[0];
 486         mb->m_pkthdr.len = length;
 487         /* Collect used fragments while replacing them in the HW descirptors */
 488         for (nr = 0; nr < priv->num_frags; nr++) {
 489                 frag_info = &priv->frag_info[nr];
 490                 if (length <= frag_info->frag_prefix_size)
 491                         break;
 492                 if (nr)
 493                         mb->m_next = mb_list[nr];
 494                 mb = mb_list[nr];
 495                 mb->m_len = frag_info->frag_size;
 496                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 497
 498                 /* Allocate a replacement page */
 499                 if (mlx4_en_alloc_buf(priv, rx_desc, mb_list, nr))
 500                         goto fail;
 501
 502                 /* Unmap buffer */
 503                 pci_unmap_single(mdev->pdev, dma, frag_info->frag_size,
 504                                  PCI_DMA_FROMDEVICE);
 505         }
 506         /* Adjust size of last fragment to match actual length */
 507         mb->m_len = length - priv->frag_info[nr - 1].frag_prefix_size;
 508         mb->m_next = NULL;
 509         return 0;
 510
 511 fail:
 512         /* Drop all accumulated fragments (which have already been replaced in
 513          * the descriptor) of this packet; remaining fragments are reused... */
 514         while (nr > 0) {
 515                 nr--;
 516                 m_free(mb_list[nr]);
 517         }
 518         return -ENOMEM;
 519
 520 }
 521
 522 static struct mbuf *mlx4_en_rx_mb(struct mlx4_en_priv *priv,
 523                                   struct mlx4_en_rx_desc *rx_desc,
 524                                   struct mbuf **mb_list,
 525                                   unsigned int length)
 526 {
 527         struct mbuf *mb;
 528
 529         mb = mb_list[0];
 530         /* Move relevant fragments to mb */
 531         if (unlikely(mlx4_en_complete_rx_desc(priv, rx_desc, mb_list, length)))
 532                 return NULL;
 533
 534         return mb;
 535 }
 536
 537 /* For cpu arch with cache line of 64B the performance is better when cqe size==64B
 538  * To enlarge cqe size from 32B to 64B --> 32B of garbage (i.e. 0xccccccc)
 539  * was added in the beginning of each cqe (the real data is in the corresponding 32B).
 540  * The following calc ensures that when factor==1, it means we are alligned to 64B
 541  * and we get the real cqe data*/
 542 #define CQE_FACTOR_INDEX(index, factor) ((index << factor) + factor)
 543 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 544 {
 545         struct mlx4_en_priv *priv = netdev_priv(dev);
 546         struct mlx4_cqe *cqe;
 547         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 548         struct mbuf **mb_list;
 549         struct mlx4_en_rx_desc *rx_desc;
 550         struct mbuf *mb;
 551         struct mlx4_cq *mcq = &cq->mcq;
 552         struct mlx4_cqe *buf = cq->buf;
 553 #ifdef INET
 554         struct lro_entry *queued;
 555 #endif
 556         int index;
 557         unsigned int length;
 558         int polled = 0;
 559         u32 cons_index = mcq->cons_index;
 560         u32 size_mask = ring->size_mask;
 561         int size = cq->size;
 562         int factor = priv->cqe_factor;
 563
 564         if (!priv->port_up)
 565                 return 0;
 566
 567         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 568          * descriptor offset can be deducted from the CQE index instead of
 569          * reading 'cqe->index' */
 570         index = cons_index & size_mask;
 571         cqe = &buf[CQE_FACTOR_INDEX(index, factor)];
 572
 573         /* Process all completed CQEs */
 574         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 575                     cons_index & size)) {
 576                 mb_list = ring->rx_info + (index << priv->log_rx_info);
 577                 rx_desc = ring->buf + (index << ring->log_stride);
 578
 579                 /*
 580                  * make sure we read the CQE after we read the ownership bit
 581                  */
 582                 rmb();
 583
 584                 if (invalid_cqe(priv, cqe)) {
 585                         goto next;
 586                 }
 587                 /*
 588                  * Packet is OK - process it.
 589                  */
 590                 length = be32_to_cpu(cqe->byte_cnt);
 591                 length -= ring->fcs_del;
 592                 mb = mlx4_en_rx_mb(priv, rx_desc, mb_list, length);
 593                 if (!mb) {
 594                         ring->errors++;
 595                         goto next;
 596                 }
 597
 598                 ring->bytes += length;
 599                 ring->packets++;
 600
 601                 if (unlikely(priv->validate_loopback)) {
 602                         validate_loopback(priv, mb);
 603                         goto next;
 604                 }
 605
 606                 mb->m_pkthdr.flowid = cq->ring;
 607                 M_HASHTYPE_SET(mb, M_HASHTYPE_OPAQUE);
 608                 mb->m_pkthdr.rcvif = dev;
 609                 if (be32_to_cpu(cqe->vlan_my_qpn) &
 610                     MLX4_CQE_VLAN_PRESENT_MASK) {
 611                         mb->m_pkthdr.ether_vtag = be16_to_cpu(cqe->sl_vid);
 612                         mb->m_flags |= M_VLANTAG;
 613                 }
 614                 if (likely(dev->if_capabilities & IFCAP_RXCSUM) &&
 615                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 616                     (cqe->checksum == cpu_to_be16(0xffff))) {
 617                         priv->port_stats.rx_chksum_good++;
 618                         mb->m_pkthdr.csum_flags =
 619                             CSUM_IP_CHECKED | CSUM_IP_VALID |
 620                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 621                         mb->m_pkthdr.csum_data = htons(0xffff);
 622                         /* This packet is eligible for LRO if it is:
 623                          * - DIX Ethernet (type interpretation)
 624                          * - TCP/IP (v4)
 625                          * - without IP options
 626                          * - not an IP fragment
 627                          */
 628 #ifdef INET
 629                         if (mlx4_en_can_lro(cqe->status) &&
 630                                         (dev->if_capenable & IFCAP_LRO)) {
 631                                 if (ring->lro.lro_cnt != 0 &&
 632                                                 tcp_lro_rx(&ring->lro, mb, 0) == 0)
 633                                         goto next;
 634                         }
 635
 636 #endif
 637                         /* LRO not possible, complete processing here */
 638                         INC_PERF_COUNTER(priv->pstats.lro_misses);
 639                 } else {
 640                         mb->m_pkthdr.csum_flags = 0;
 641                         priv->port_stats.rx_chksum_none++;
 642                 }
 643
 644                 /* Push it up the stack */
 645                 dev->if_input(dev, mb);
 646
 647 next:
 648                 ++cons_index;
 649                 index = cons_index & size_mask;
 650                 cqe = &buf[CQE_FACTOR_INDEX(index, factor)];
 651                 if (++polled == budget)
 652                         goto out;
 653         }
 654         /* Flush all pending IP reassembly sessions */
 655 out:
 656 #ifdef INET
 657         while ((queued = SLIST_FIRST(&ring->lro.lro_active)) != NULL) {
 658                 SLIST_REMOVE_HEAD(&ring->lro.lro_active, next);
 659                 tcp_lro_flush(&ring->lro, queued);
 660         }
 661 #endif
 662         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
 663         mcq->cons_index = cons_index;
 664         mlx4_cq_set_ci(mcq);
 665         wmb(); /* ensure HW sees CQ consumer before we post new buffers */
 666         ring->cons = mcq->cons_index;
 667         ring->prod += polled; /* Polled descriptors were realocated in place */
 668         mlx4_en_update_rx_prod_db(ring);
 669         return polled;
 670
 671 }
 672
 673 /* Rx CQ polling - called by NAPI */
 674 static int mlx4_en_poll_rx_cq(struct mlx4_en_cq *cq, int budget)
 675 {
 676         struct net_device *dev = cq->dev;
 677         int done;
 678
 679         done = mlx4_en_process_rx_cq(dev, cq, budget);
 680         cq->tot_rx += done;
 681
 682         return done;
 683
 684 }
 685 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
 686 {
 687         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
 688         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
 689         int done;
 690
 691         // Shoot one within the irq context
 692         // Because there is no NAPI in freeBSD
 693         done = mlx4_en_poll_rx_cq(cq, MLX4_EN_RX_BUDGET);
 694         if (priv->port_up  && (done == MLX4_EN_RX_BUDGET) ) {
 695                 taskqueue_enqueue(cq->tq, &cq->cq_task);
 696         }
 697         else {
 698                 mlx4_en_arm_cq(priv, cq);
 699         }
 700 }
 701
 702 void mlx4_en_rx_que(void *context, int pending)
 703 {
 704         struct mlx4_en_cq *cq;
 705
 706         cq = context;
 707         while (mlx4_en_poll_rx_cq(cq, MLX4_EN_RX_BUDGET)
 708                         == MLX4_EN_RX_BUDGET);
 709         mlx4_en_arm_cq(cq->dev->if_softc, cq);
 710 }
 711
 712
 713 /* RSS related functions */
 714
 715 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
 716                                  struct mlx4_en_rx_ring *ring,
 717                                  enum mlx4_qp_state *state,
 718                                  struct mlx4_qp *qp)
 719 {
 720         struct mlx4_en_dev *mdev = priv->mdev;
 721         struct mlx4_qp_context *context;
 722         int err = 0;
 723
 724         context = kmalloc(sizeof *context , GFP_KERNEL);
 725         if (!context) {
 726                 en_err(priv, "Failed to allocate qp context\n");
 727                 return -ENOMEM;
 728         }
 729
 730         err = mlx4_qp_alloc(mdev->dev, qpn, qp);
 731         if (err) {
 732                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
 733                 goto out;
 734         }
 735         qp->event = mlx4_en_sqp_event;
 736
 737         memset(context, 0, sizeof *context);
 738         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
 739                                 qpn, ring->cqn, -1, context);
 740         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
 741
 742         /* Cancel FCS removal if FW allows */
 743         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
 744                 context->param3 |= cpu_to_be32(1 << 29);
 745                 ring->fcs_del = ETH_FCS_LEN;
 746         } else
 747                 ring->fcs_del = 0;
 748
 749         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
 750         if (err) {
 751                 mlx4_qp_remove(mdev->dev, qp);
 752                 mlx4_qp_free(mdev->dev, qp);
 753         }
 754         mlx4_en_update_rx_prod_db(ring);
 755 out:
 756         kfree(context);
 757         return err;
 758 }
 759
 760 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
 761 {
 762         int err;
 763         u32 qpn;
 764
 765         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn, 0);
 766         if (err) {
 767                 en_err(priv, "Failed reserving drop qpn\n");
 768                 return err;
 769         }
 770         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
 771         if (err) {
 772                 en_err(priv, "Failed allocating drop qp\n");
 773                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 774                 return err;
 775         }
 776
 777         return 0;
 778 }
 779
 780 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
 781 {
 782         u32 qpn;
 783
 784         qpn = priv->drop_qp.qpn;
 785         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
 786         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
 787         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
 788 }
 789
 790 /* Allocate rx qp's and configure them according to rss map */
 791 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
 792 {
 793         struct mlx4_en_dev *mdev = priv->mdev;
 794         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
 795         struct mlx4_qp_context context;
 796         struct mlx4_rss_context *rss_context;
 797         int rss_rings;
 798         void *ptr;
 799         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
 800                         MLX4_RSS_TCP_IPV6);
 801         int i;
 802         int err = 0;
 803         int good_qps = 0;
 804         static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
 805                                 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
 806                                 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
 807
 808         en_dbg(DRV, priv, "Configuring rss steering\n");
 809         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
 810                                     priv->rx_ring_num,
 811                                     &rss_map->base_qpn, 0);
 812         if (err) {
 813                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
 814                 return err;
 815         }
 816
 817         for (i = 0; i < priv->rx_ring_num; i++) {
 818                 priv->rx_ring[i]->qpn = rss_map->base_qpn + i;
 819                 err = mlx4_en_config_rss_qp(priv, priv->rx_ring[i]->qpn,
 820                                             priv->rx_ring[i],
 821                                             &rss_map->state[i],
 822                                             &rss_map->qps[i]);
 823                 if (err)
 824                         goto rss_err;
 825
 826                 ++good_qps;
 827         }
 828
 829         /* Configure RSS indirection qp */
 830         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
 831         if (err) {
 832                 en_err(priv, "Failed to allocate RSS indirection QP\n");
 833                 goto rss_err;
 834         }
 835         rss_map->indir_qp.event = mlx4_en_sqp_event;
 836         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
 837                                 priv->rx_ring[0]->cqn, -1, &context);
 838
 839         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
 840                 rss_rings = priv->rx_ring_num;
 841         else
 842                 rss_rings = priv->prof->rss_rings;
 843
 844         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
 845                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
 846         rss_context = ptr;
 847         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
 848                                             (rss_map->base_qpn));
 849         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
 850         if (priv->mdev->profile.udp_rss) {
 851                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
 852                 rss_context->base_qpn_udp = rss_context->default_qpn;
 853         }
 854         rss_context->flags = rss_mask;
 855         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
 856         for (i = 0; i < 10; i++)
 857                 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
 858
 859         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
 860                                &rss_map->indir_qp, &rss_map->indir_state);
 861         if (err)
 862                 goto indir_err;
 863
 864         return 0;
 865
 866 indir_err:
 867         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
 868                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
 869         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
 870         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
 871 rss_err:
 872         for (i = 0; i < good_qps; i++) {
 873                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
 874                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
 875                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
 876                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
 877         }
 878         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
 879         return err;
 880 }
 881
 882 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
 883 {
 884         struct mlx4_en_dev *mdev = priv->mdev;
 885         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
 886         int i;
 887
 888         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
 889                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
 890         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
 891         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
 892
 893         for (i = 0; i < priv->rx_ring_num; i++) {
 894                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
 895                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
 896                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
 897                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
 898         }
 899         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
 900 }
 901