2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kmod.h>
38 * kmod.h must be included before module.h since it includes (indirectly) sys/module.h
39 * To use the FBSD macro sys/module.h should define MODULE_VERSION before linux/module does.
41 #include <linux/module.h>
42 #include <linux/errno.h>
43 #include <linux/pci.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <linux/io-mapping.h>
47 #include <linux/delay.h>
48 #include <linux/netdevice.h>
49 #include <linux/string.h>
52 #include <linux/mlx4/device.h>
53 #include <linux/mlx4/doorbell.h>
58 #include "mlx4_stats.h"
60 MODULE_AUTHOR("Roland Dreier");
61 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
62 MODULE_LICENSE("Dual BSD/GPL");
64 struct workqueue_struct *mlx4_wq;
66 #ifdef CONFIG_MLX4_DEBUG
68 int mlx4_debug_level = 0;
69 module_param_named(debug_level, mlx4_debug_level, int, 0644);
70 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
72 #endif /* CONFIG_MLX4_DEBUG */
77 module_param(msi_x, int, 0444);
78 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x (non-SRIOV only)");
80 #else /* CONFIG_PCI_MSI */
84 #endif /* CONFIG_PCI_MSI */
86 static int enable_sys_tune = 0;
87 module_param(enable_sys_tune, int, 0444);
88 MODULE_PARM_DESC(enable_sys_tune, "Tune the cpu's for better performance (default 0)");
91 module_param_named(block_loopback, mlx4_blck_lb, int, 0644);
92 MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0 "
96 BDF_STR_SIZE = 8, /* bb:dd.f- */
97 DBDF_STR_SIZE = 13 /* mmmm:bb:dd.f- */
114 struct mlx4_dbdf2val_lst dbdf2val;
117 static struct param_data num_vfs = {
120 .name = "num_vfs param",
123 .range = {0, MLX4_MAX_NUM_VF}
126 module_param_string(num_vfs, num_vfs.dbdf2val.str,
127 sizeof(num_vfs.dbdf2val.str), 0444);
128 MODULE_PARM_DESC(num_vfs,
129 "Either single value (e.g. '5') to define uniform num_vfs value for all devices functions\n"
130 "\t\tor a string to map device function numbers to their num_vfs values (e.g. '0000:04:00.0-5,002b:1c:0b.a-15').\n"
131 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for num_vfs value (e.g. 15).");
133 static struct param_data probe_vf = {
136 .name = "probe_vf param",
139 .range = {0, MLX4_MAX_NUM_VF}
142 module_param_string(probe_vf, probe_vf.dbdf2val.str,
143 sizeof(probe_vf.dbdf2val.str), 0444);
144 MODULE_PARM_DESC(probe_vf,
145 "Either single value (e.g. '3') to define uniform number of VFs to probe by the pf driver for all devices functions\n"
146 "\t\tor a string to map device function numbers to their probe_vf values (e.g. '0000:04:00.0-3,002b:1c:0b.a-13').\n"
147 "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for probe_vf value (e.g. 13).");
149 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
151 module_param_named(log_num_mgm_entry_size,
152 mlx4_log_num_mgm_entry_size, int, 0444);
153 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
154 " of qp per mcg, for example:"
155 " 10 gives 248.range: 7 <="
156 " log_num_mgm_entry_size <= 12."
157 " To activate device managed"
158 " flow steering when available, set to -1");
160 static int high_rate_steer;
161 module_param(high_rate_steer, int, 0444);
162 MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate"
165 static int fast_drop;
166 module_param_named(fast_drop, fast_drop, int, 0444);
167 MODULE_PARM_DESC(fast_drop,
168 "Enable fast packet drop when no recieve WQEs are posted");
170 int mlx4_enable_64b_cqe_eqe = 1;
171 module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644);
172 MODULE_PARM_DESC(enable_64b_cqe_eqe,
173 "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)");
175 #define HCA_GLOBAL_CAP_MASK 0
177 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
179 static char mlx4_version[] __devinitdata =
180 DRV_NAME ": Mellanox ConnectX core driver v"
181 DRV_VERSION " (" DRV_RELDATE ")\n";
183 static int log_num_mac = 7;
184 module_param_named(log_num_mac, log_num_mac, int, 0444);
185 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
187 static int log_num_vlan;
188 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
189 MODULE_PARM_DESC(log_num_vlan,
190 "(Obsolete) Log2 max number of VLANs per ETH port (0-7)");
191 /* Log2 max number of VLANs per ETH port (0-7) */
192 #define MLX4_LOG_NUM_VLANS 7
194 int log_mtts_per_seg = ilog2(1);
195 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
196 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
197 "(0-7) (default: 0)");
199 static struct param_data port_type_array = {
200 .id = PORT_TYPE_ARRAY,
202 .name = "port_type_array param",
204 .def_val = {MLX4_PORT_TYPE_ETH, MLX4_PORT_TYPE_ETH},
205 .range = {MLX4_PORT_TYPE_IB, MLX4_PORT_TYPE_NA}
208 module_param_string(port_type_array, port_type_array.dbdf2val.str,
209 sizeof(port_type_array.dbdf2val.str), 0444);
210 MODULE_PARM_DESC(port_type_array,
211 "Either pair of values (e.g. '1,2') to define uniform port1/port2 types configuration for all devices functions\n"
212 "\t\tor a string to map device function numbers to their pair of port types values (e.g. '0000:04:00.0-1;2,002b:1c:0b.a-1;1').\n"
213 "\t\tValid port types: 1-ib, 2-eth, 3-auto, 4-N/A\n"
214 "\t\tIn case that only one port is available use the N/A port type for port2 (e.g '1,4').");
217 struct mlx4_port_config {
218 struct list_head list;
219 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
220 struct pci_dev *pdev;
223 #define MLX4_LOG_NUM_MTT 20
224 /* We limit to 30 as of a bit map issue which uses int and not uint.
225 see mlx4_buddy_init -> bitmap_zero which gets int.
227 #define MLX4_MAX_LOG_NUM_MTT 30
228 static struct mlx4_profile mod_param_profile = {
235 .num_mtt_segs = 0, /* max(20, 2*MTTs for host memory)) */
238 module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444);
239 MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA (default: 19)");
241 module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444);
242 MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA "
245 module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int,
247 MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP "
250 module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444);
251 MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA (default: 16)");
253 module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444);
254 MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA "
257 module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444);
258 MODULE_PARM_DESC(log_num_mpt,
259 "log maximum number of memory protection table entries per "
260 "HCA (default: 19)");
262 module_param_named(log_num_mtt, mod_param_profile.num_mtt_segs, int, 0444);
263 MODULE_PARM_DESC(log_num_mtt,
264 "log maximum number of memory translation table segments per "
265 "HCA (default: max(20, 2*MTTs for register all of the host memory limited to 30))");
269 MLX4_IF_STATE_EXTENDED
272 static inline u64 dbdf_to_u64(int domain, int bus, int dev, int fn)
274 return (domain << 20) | (bus << 12) | (dev << 4) | fn;
277 static inline void pr_bdf_err(const char *dbdf, const char *pname)
279 pr_warn("mlx4_core: '%s' is not valid bdf in '%s'\n", dbdf, pname);
282 static inline void pr_val_err(const char *dbdf, const char *pname,
285 pr_warn("mlx4_core: value '%s' of bdf '%s' in '%s' is not valid\n"
289 static inline void pr_out_of_range_bdf(const char *dbdf, int val,
290 struct mlx4_dbdf2val_lst *dbdf2val)
292 pr_warn("mlx4_core: value %d in bdf '%s' of '%s' is out of its valid range (%d,%d)\n"
293 , val, dbdf, dbdf2val->name , dbdf2val->range.min,
294 dbdf2val->range.max);
297 static inline void pr_out_of_range(struct mlx4_dbdf2val_lst *dbdf2val)
299 pr_warn("mlx4_core: value of '%s' is out of its valid range (%d,%d)\n"
300 , dbdf2val->name , dbdf2val->range.min, dbdf2val->range.max);
303 static inline int is_in_range(int val, struct mlx4_range *r)
305 return (val >= r->min && val <= r->max);
308 static int update_defaults(struct param_data *pdata)
310 long int val[MLX4_MAX_BDF_VALS];
312 char *t, *p = pdata->dbdf2val.str;
316 if (!strlen(p) || strchr(p, ':') || strchr(p, '.') || strchr(p, ';'))
320 case PORT_TYPE_ARRAY:
322 if (!t || t == p || (t - p) > sizeof(sval))
326 strncpy(sval, p, val_len);
329 ret = kstrtol(sval, 0, &val[0]);
332 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
333 pr_out_of_range(&pdata->dbdf2val);
337 ret = kstrtol(t + 1, 0, &val[1]);
340 if (ret || !is_in_range(val[1], &pdata->dbdf2val.range)) {
341 pr_out_of_range(&pdata->dbdf2val);
345 pdata->dbdf2val.tbl[0].val[0] = val[0];
346 pdata->dbdf2val.tbl[0].val[1] = val[1];
351 ret = kstrtol(p, 0, &val[0]);
354 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
355 pr_out_of_range(&pdata->dbdf2val);
358 pdata->dbdf2val.tbl[0].val[0] = val[0];
361 pdata->dbdf2val.tbl[1].dbdf = MLX4_ENDOF_TBL;
366 int mlx4_fill_dbdf2val_tbl(struct mlx4_dbdf2val_lst *dbdf2val_lst)
368 int domain, bus, dev, fn;
374 int j, k, str_size, i = 1;
377 p = dbdf2val_lst->str;
379 for (j = 0; j < dbdf2val_lst->num_vals; j++)
380 dbdf2val_lst->tbl[0].val[j] = dbdf2val_lst->def_val[j];
381 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
383 str_size = strlen(dbdf2val_lst->str);
389 prfx_size = BDF_STR_SIZE;
391 strncpy(sbdf, p, prfx_size);
392 domain = DEFAULT_DOMAIN;
393 if (sscanf(sbdf, "%02x:%02x.%x-", &bus, &dev, &fn) != 3) {
394 prfx_size = DBDF_STR_SIZE;
396 strncpy(sbdf, p, prfx_size);
397 if (sscanf(sbdf, "%04x:%02x:%02x.%x-", &domain, &bus,
399 pr_bdf_err(sbdf, dbdf2val_lst->name);
402 sprintf(tmp, "%04x:%02x:%02x.%x-", domain, bus, dev,
405 sprintf(tmp, "%02x:%02x.%x-", bus, dev, fn);
408 if (strnicmp(sbdf, tmp, sizeof(tmp))) {
409 pr_bdf_err(sbdf, dbdf2val_lst->name);
413 dbdf = dbdf_to_u64(domain, bus, dev, fn);
415 for (j = 1; j < i; j++)
416 if (dbdf2val_lst->tbl[j].dbdf == dbdf) {
417 pr_warn("mlx4_core: in '%s', %s appears multiple times\n"
418 , dbdf2val_lst->name, sbdf);
422 if (i >= MLX4_DEVS_TBL_SIZE) {
423 pr_warn("mlx4_core: Too many devices in '%s'\n"
424 , dbdf2val_lst->name);
430 t = t ? t : p + strlen(p);
432 pr_val_err(sbdf, dbdf2val_lst->name, "");
436 for (k = 0; k < dbdf2val_lst->num_vals; k++) {
442 v = (k == dbdf2val_lst->num_vals - 1) ? t : strchr(p, vsep);
443 if (!v || v > t || v == p || (v - p) > sizeof(sval)) {
444 pr_val_err(sbdf, dbdf2val_lst->name, p);
448 strncpy(sval, p, val_len);
451 ret = kstrtol(sval, 0, &val);
454 pr_warn("mlx4_core: too many vals in bdf '%s' of '%s'\n"
455 , sbdf, dbdf2val_lst->name);
457 pr_val_err(sbdf, dbdf2val_lst->name,
461 if (!is_in_range(val, &dbdf2val_lst->range)) {
462 pr_out_of_range_bdf(sbdf, val, dbdf2val_lst);
466 dbdf2val_lst->tbl[i].val[k] = val;
472 dbdf2val_lst->tbl[i].dbdf = dbdf;
475 pr_warn("mlx4_core: expect separator '%c' before '%s' in '%s'\n"
476 , sep, p, dbdf2val_lst->name);
482 if (i < MLX4_DEVS_TBL_SIZE)
483 dbdf2val_lst->tbl[i].dbdf = MLX4_ENDOF_TBL;
489 dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
490 pr_warn("mlx4_core: The value of '%s' is incorrect. The value is discarded!\n"
491 , dbdf2val_lst->name);
495 EXPORT_SYMBOL(mlx4_fill_dbdf2val_tbl);
497 int mlx4_get_val(struct mlx4_dbdf2val *tbl, struct pci_dev *pdev, int idx,
503 *val = tbl[0].val[idx];
507 dbdf = dbdf_to_u64(pci_get_domain(pdev->dev.bsddev), pci_get_bus(pdev->dev.bsddev),
508 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
510 while ((i < MLX4_DEVS_TBL_SIZE) && (tbl[i].dbdf != MLX4_ENDOF_TBL)) {
511 if (tbl[i].dbdf == dbdf) {
512 *val = tbl[i].val[idx];
520 EXPORT_SYMBOL(mlx4_get_val);
522 static void process_mod_param_profile(struct mlx4_profile *profile)
526 TUNABLE_ULONG_FETCH("hw.realmem", (u_long *) &hwphyssz);
528 profile->num_qp = 1 << mod_param_profile.num_qp;
529 profile->num_srq = 1 << mod_param_profile.num_srq;
530 profile->rdmarc_per_qp = 1 << mod_param_profile.rdmarc_per_qp;
531 profile->num_cq = 1 << mod_param_profile.num_cq;
532 profile->num_mcg = 1 << mod_param_profile.num_mcg;
533 profile->num_mpt = 1 << mod_param_profile.num_mpt;
535 * We want to scale the number of MTTs with the size of the
536 * system memory, since it makes sense to register a lot of
537 * memory on a system with a lot of memory. As a heuristic,
538 * make sure we have enough MTTs to register twice the system
539 * memory (with PAGE_SIZE entries).
541 * This number has to be a power of two and fit into 32 bits
542 * due to device limitations. We cap this at 2^30 as of bit map
543 * limitation to work with int instead of uint (mlx4_buddy_init -> bitmap_zero)
544 * That limits us to 4TB of memory registration per HCA with
545 * 4KB pages, which is probably OK for the next few months.
547 if (mod_param_profile.num_mtt_segs)
548 profile->num_mtt_segs = 1 << mod_param_profile.num_mtt_segs;
550 profile->num_mtt_segs =
551 roundup_pow_of_two(max_t(unsigned,
552 1 << (MLX4_LOG_NUM_MTT - log_mtts_per_seg),
554 (MLX4_MAX_LOG_NUM_MTT -
557 >> log_mtts_per_seg)));
558 /* set the actual value, so it will be reflected to the user
560 mod_param_profile.num_mtt_segs = ilog2(profile->num_mtt_segs);
564 int mlx4_check_port_params(struct mlx4_dev *dev,
565 enum mlx4_port_type *port_type)
569 for (i = 0; i < dev->caps.num_ports - 1; i++) {
570 if (port_type[i] != port_type[i + 1]) {
571 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
572 mlx4_err(dev, "Only same port types supported "
573 "on this HCA, aborting.\n");
579 for (i = 0; i < dev->caps.num_ports; i++) {
580 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
581 mlx4_err(dev, "Requested port type for port %d is not "
582 "supported on this HCA\n", i + 1);
589 static void mlx4_set_port_mask(struct mlx4_dev *dev)
593 for (i = 1; i <= dev->caps.num_ports; ++i)
594 dev->caps.port_mask[i] = dev->caps.port_type[i];
597 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
602 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
604 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
608 if (dev_cap->min_page_sz > PAGE_SIZE) {
609 mlx4_err(dev, "HCA minimum page size of %d bigger than "
610 "kernel PAGE_SIZE of %d, aborting.\n",
611 dev_cap->min_page_sz, PAGE_SIZE);
614 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
615 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
617 dev_cap->num_ports, MLX4_MAX_PORTS);
621 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
622 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
623 "PCI resource 2 size of 0x%llx, aborting.\n",
625 (unsigned long long) pci_resource_len(dev->pdev, 2));
629 dev->caps.num_ports = dev_cap->num_ports;
630 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
631 for (i = 1; i <= dev->caps.num_ports; ++i) {
632 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
633 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
634 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
635 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
636 /* set gid and pkey table operating lengths by default
637 * to non-sriov values */
638 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
639 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
640 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
641 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
642 dev->caps.def_mac[i] = dev_cap->def_mac[i];
643 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
644 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
645 dev->caps.default_sense[i] = dev_cap->default_sense[i];
646 dev->caps.trans_type[i] = dev_cap->trans_type[i];
647 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
648 dev->caps.wavelength[i] = dev_cap->wavelength[i];
649 dev->caps.trans_code[i] = dev_cap->trans_code[i];
652 dev->caps.uar_page_size = PAGE_SIZE;
653 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
654 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
655 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
656 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
657 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
658 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
659 dev->caps.max_wqes = dev_cap->max_qp_sz;
660 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
661 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
662 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
663 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
664 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
665 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
667 * Subtract 1 from the limit because we need to allocate a
668 * spare CQE to enable resizing the CQ
670 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
671 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
672 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
673 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
674 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
676 /* The first 128 UARs are used for EQ doorbells */
677 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
678 dev->caps.reserved_pds = dev_cap->reserved_pds;
679 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
680 dev_cap->reserved_xrcds : 0;
681 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
682 dev_cap->max_xrcds : 0;
683 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
685 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
686 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
687 dev->caps.flags = dev_cap->flags;
688 dev->caps.flags2 = dev_cap->flags2;
689 dev->caps.bmme_flags = dev_cap->bmme_flags;
690 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
691 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
692 dev->caps.cq_timestamp = dev_cap->timestamp_support;
693 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
694 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
696 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
697 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
698 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
699 /* Don't do sense port on multifunction devices (for now at least) */
700 if (mlx4_is_mfunc(dev))
701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
703 dev->caps.log_num_macs = log_num_mac;
704 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
706 dev->caps.fast_drop = fast_drop ?
707 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FAST_DROP) :
710 for (i = 1; i <= dev->caps.num_ports; ++i) {
711 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
712 if (dev->caps.supported_type[i]) {
713 /* if only ETH is supported - assign ETH */
714 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
715 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
716 /* if only IB is supported, assign IB */
717 else if (dev->caps.supported_type[i] ==
719 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
722 * if IB and ETH are supported, we set the port
723 * type according to user selection of port type;
724 * if there is no user selection, take the FW hint
727 mlx4_get_val(port_type_array.dbdf2val.tbl,
728 pci_physfn(dev->pdev), i - 1,
730 if (pta == MLX4_PORT_TYPE_NONE) {
731 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
732 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
733 } else if (pta == MLX4_PORT_TYPE_NA) {
734 mlx4_err(dev, "Port %d is valid port. "
735 "It is not allowed to configure its type to N/A(%d)\n",
736 i, MLX4_PORT_TYPE_NA);
739 dev->caps.port_type[i] = pta;
744 * Link sensing is allowed on the port if 3 conditions are true:
745 * 1. Both protocols are supported on the port.
746 * 2. Different types are supported on the port
747 * 3. FW declared that it supports link sensing
749 mlx4_priv(dev)->sense.sense_allowed[i] =
750 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
751 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
752 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
754 /* Disablling auto sense for default Eth ports support */
755 mlx4_priv(dev)->sense.sense_allowed[i] = 0;
758 * If "default_sense" bit is set, we move the port to "AUTO" mode
759 * and perform sense_port FW command to try and set the correct
760 * port type from beginning
762 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
763 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
764 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
765 mlx4_SENSE_PORT(dev, i, &sensed_port);
766 if (sensed_port != MLX4_PORT_TYPE_NONE)
767 dev->caps.port_type[i] = sensed_port;
769 dev->caps.possible_type[i] = dev->caps.port_type[i];
772 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
773 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
774 mlx4_warn(dev, "Requested number of MACs is too much "
775 "for port %d, reducing to %d.\n",
776 i, 1 << dev->caps.log_num_macs);
778 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
779 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
780 mlx4_warn(dev, "Requested number of VLANs is too much "
781 "for port %d, reducing to %d.\n",
782 i, 1 << dev->caps.log_num_vlans);
786 dev->caps.max_basic_counters = dev_cap->max_basic_counters;
787 dev->caps.max_extended_counters = dev_cap->max_extended_counters;
788 /* support extended counters if available */
789 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS_EXT)
790 dev->caps.max_counters = dev->caps.max_extended_counters;
792 dev->caps.max_counters = dev->caps.max_basic_counters;
794 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
795 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
796 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
797 (1 << dev->caps.log_num_macs) *
798 (1 << dev->caps.log_num_vlans) *
800 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
802 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
803 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
804 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
805 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
807 dev->caps.sync_qp = dev_cap->sync_qp;
808 if (dev->pdev->device == 0x1003)
809 dev->caps.cq_flags |= MLX4_DEV_CAP_CQ_FLAG_IO;
811 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
813 if (!mlx4_enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
815 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
816 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
817 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
818 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
822 if ((dev->caps.flags &
823 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
825 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
827 if (!mlx4_is_slave(dev)) {
828 for (i = 0; i < dev->caps.num_ports; ++i)
829 dev->caps.def_counter_index[i] = i << 1;
834 /*The function checks if there are live vf, return the num of them*/
835 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
837 struct mlx4_priv *priv = mlx4_priv(dev);
838 struct mlx4_slave_state *s_state;
842 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
843 s_state = &priv->mfunc.master.slave_state[i];
844 if (s_state->active && s_state->last_cmd !=
845 MLX4_COMM_CMD_RESET) {
846 mlx4_warn(dev, "%s: slave: %d is still active\n",
854 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
856 u32 qk = MLX4_RESERVED_QKEY_BASE;
858 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
859 qpn < dev->phys_caps.base_proxy_sqpn)
862 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
864 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
866 qk += qpn - dev->phys_caps.base_proxy_sqpn;
870 EXPORT_SYMBOL(mlx4_get_parav_qkey);
872 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
874 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
876 if (!mlx4_is_master(dev))
879 priv->virt2phys_pkey[slave][port - 1][i] = val;
881 EXPORT_SYMBOL(mlx4_sync_pkey_table);
883 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
885 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
887 if (!mlx4_is_master(dev))
890 priv->slave_node_guids[slave] = guid;
892 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
894 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
896 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
898 if (!mlx4_is_master(dev))
901 return priv->slave_node_guids[slave];
903 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
905 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
907 struct mlx4_priv *priv = mlx4_priv(dev);
908 struct mlx4_slave_state *s_slave;
910 if (!mlx4_is_master(dev))
913 s_slave = &priv->mfunc.master.slave_state[slave];
914 return !!s_slave->active;
916 EXPORT_SYMBOL(mlx4_is_slave_active);
918 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
919 struct mlx4_dev_cap *dev_cap,
920 struct mlx4_init_hca_param *hca_param)
922 dev->caps.steering_mode = hca_param->steering_mode;
923 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED)
924 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
926 dev->caps.num_qp_per_mgm =
927 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
929 mlx4_dbg(dev, "Steering mode is: %s\n",
930 mlx4_steering_mode_str(dev->caps.steering_mode));
933 static int mlx4_slave_cap(struct mlx4_dev *dev)
937 struct mlx4_dev_cap dev_cap;
938 struct mlx4_func_cap func_cap;
939 struct mlx4_init_hca_param hca_param;
942 memset(&hca_param, 0, sizeof(hca_param));
943 err = mlx4_QUERY_HCA(dev, &hca_param);
945 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
949 /*fail if the hca has an unknown capability */
950 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
951 HCA_GLOBAL_CAP_MASK) {
952 mlx4_err(dev, "Unknown hca global capabilities\n");
956 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
958 dev->caps.hca_core_clock = hca_param.hca_core_clock;
960 memset(&dev_cap, 0, sizeof(dev_cap));
961 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
962 err = mlx4_dev_cap(dev, &dev_cap);
964 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
968 err = mlx4_QUERY_FW(dev);
970 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
972 if (!hca_param.mw_enable) {
973 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
974 dev->caps.bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
977 page_size = ~dev->caps.page_size_cap + 1;
978 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
979 if (page_size > PAGE_SIZE) {
980 mlx4_err(dev, "HCA minimum page size of %d bigger than "
981 "kernel PAGE_SIZE of %d, aborting.\n",
982 page_size, PAGE_SIZE);
986 /* slave gets uar page size from QUERY_HCA fw command */
987 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
989 /* TODO: relax this assumption */
990 if (dev->caps.uar_page_size != PAGE_SIZE) {
991 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %d\n",
992 dev->caps.uar_page_size, PAGE_SIZE);
996 memset(&func_cap, 0, sizeof(func_cap));
997 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
999 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
1004 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
1005 PF_CONTEXT_BEHAVIOUR_MASK) {
1006 mlx4_err(dev, "Unknown pf context behaviour\n");
1010 dev->caps.num_ports = func_cap.num_ports;
1011 dev->quotas.qp = func_cap.qp_quota;
1012 dev->quotas.srq = func_cap.srq_quota;
1013 dev->quotas.cq = func_cap.cq_quota;
1014 dev->quotas.mpt = func_cap.mpt_quota;
1015 dev->quotas.mtt = func_cap.mtt_quota;
1016 dev->caps.num_qps = 1 << hca_param.log_num_qps;
1017 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
1018 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
1019 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
1020 dev->caps.num_eqs = func_cap.max_eq;
1021 dev->caps.reserved_eqs = func_cap.reserved_eq;
1022 dev->caps.num_pds = MLX4_NUM_PDS;
1023 dev->caps.num_mgms = 0;
1024 dev->caps.num_amgms = 0;
1026 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1027 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
1028 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
1032 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1033 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1034 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1035 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1037 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
1038 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
1043 for (i = 1; i <= dev->caps.num_ports; ++i) {
1044 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
1046 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
1047 " port %d, aborting (%d).\n", i, err);
1050 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
1051 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
1052 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
1053 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
1054 dev->caps.def_counter_index[i - 1] = func_cap.def_counter_index;
1056 dev->caps.port_mask[i] = dev->caps.port_type[i];
1057 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
1058 &dev->caps.gid_table_len[i],
1059 &dev->caps.pkey_table_len[i]);
1064 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1065 dev->caps.reserved_uars) >
1066 pci_resource_len(dev->pdev, 2)) {
1067 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
1068 "PCI resource 2 size of 0x%llx, aborting.\n",
1069 dev->caps.uar_page_size * dev->caps.num_uars,
1070 (unsigned long long) pci_resource_len(dev->pdev, 2));
1075 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
1076 dev->caps.eqe_size = 64;
1077 dev->caps.eqe_factor = 1;
1079 dev->caps.eqe_size = 32;
1080 dev->caps.eqe_factor = 0;
1083 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
1084 dev->caps.cqe_size = 64;
1085 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1087 dev->caps.cqe_size = 32;
1090 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1091 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
1093 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
1098 kfree(dev->caps.qp0_tunnel);
1099 kfree(dev->caps.qp0_proxy);
1100 kfree(dev->caps.qp1_tunnel);
1101 kfree(dev->caps.qp1_proxy);
1102 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
1103 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
1108 static void mlx4_request_modules(struct mlx4_dev *dev)
1111 int has_ib_port = false;
1112 int has_eth_port = false;
1113 #define EN_DRV_NAME "mlx4_en"
1114 #define IB_DRV_NAME "mlx4_ib"
1116 for (port = 1; port <= dev->caps.num_ports; port++) {
1117 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1119 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1120 has_eth_port = true;
1124 request_module_nowait(IB_DRV_NAME);
1126 request_module_nowait(EN_DRV_NAME);
1130 * Change the port configuration of the device.
1131 * Every user of this function must hold the port mutex.
1133 int mlx4_change_port_types(struct mlx4_dev *dev,
1134 enum mlx4_port_type *port_types)
1140 for (port = 0; port < dev->caps.num_ports; port++) {
1141 /* Change the port type only if the new type is different
1142 * from the current, and not set to Auto */
1143 if (port_types[port] != dev->caps.port_type[port + 1])
1147 mlx4_unregister_device(dev);
1148 for (port = 1; port <= dev->caps.num_ports; port++) {
1149 mlx4_CLOSE_PORT(dev, port);
1150 dev->caps.port_type[port] = port_types[port - 1];
1151 err = mlx4_SET_PORT(dev, port, -1);
1153 mlx4_err(dev, "Failed to set port %d, "
1154 "aborting\n", port);
1158 mlx4_set_port_mask(dev);
1159 err = mlx4_register_device(dev);
1161 mlx4_err(dev, "Failed to register device\n");
1164 mlx4_request_modules(dev);
1171 static ssize_t show_port_type(struct device *dev,
1172 struct device_attribute *attr,
1175 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1177 struct mlx4_dev *mdev = info->dev;
1181 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1183 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1184 sprintf(buf, "auto (%s)\n", type);
1186 sprintf(buf, "%s\n", type);
1191 static ssize_t set_port_type(struct device *dev,
1192 struct device_attribute *attr,
1193 const char *buf, size_t count)
1195 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1197 struct mlx4_dev *mdev = info->dev;
1198 struct mlx4_priv *priv = mlx4_priv(mdev);
1199 enum mlx4_port_type types[MLX4_MAX_PORTS];
1200 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1204 if (!strcmp(buf, "ib\n"))
1205 info->tmp_type = MLX4_PORT_TYPE_IB;
1206 else if (!strcmp(buf, "eth\n"))
1207 info->tmp_type = MLX4_PORT_TYPE_ETH;
1208 else if (!strcmp(buf, "auto\n"))
1209 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1211 mlx4_err(mdev, "%s is not supported port type\n", buf);
1215 if ((info->tmp_type & mdev->caps.supported_type[info->port]) !=
1217 mlx4_err(mdev, "Requested port type for port %d is not supported on this HCA\n",
1222 mlx4_stop_sense(mdev);
1223 mutex_lock(&priv->port_mutex);
1224 /* Possible type is always the one that was delivered */
1225 mdev->caps.possible_type[info->port] = info->tmp_type;
1227 for (i = 0; i < mdev->caps.num_ports; i++) {
1228 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1229 mdev->caps.possible_type[i+1];
1230 if (types[i] == MLX4_PORT_TYPE_AUTO)
1231 types[i] = mdev->caps.port_type[i+1];
1234 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1235 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1236 for (i = 1; i <= mdev->caps.num_ports; i++) {
1237 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1238 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1244 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
1245 "Set only 'eth' or 'ib' for both ports "
1246 "(should be the same)\n");
1250 mlx4_do_sense_ports(mdev, new_types, types);
1252 err = mlx4_check_port_params(mdev, new_types);
1256 /* We are about to apply the changes after the configuration
1257 * was verified, no need to remember the temporary types
1259 for (i = 0; i < mdev->caps.num_ports; i++)
1260 priv->port[i + 1].tmp_type = 0;
1262 err = mlx4_change_port_types(mdev, new_types);
1265 mlx4_start_sense(mdev);
1266 mutex_unlock(&priv->port_mutex);
1267 return err ? err : count;
1278 static inline int int_to_ibta_mtu(int mtu)
1281 case 256: return IB_MTU_256;
1282 case 512: return IB_MTU_512;
1283 case 1024: return IB_MTU_1024;
1284 case 2048: return IB_MTU_2048;
1285 case 4096: return IB_MTU_4096;
1290 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1293 case IB_MTU_256: return 256;
1294 case IB_MTU_512: return 512;
1295 case IB_MTU_1024: return 1024;
1296 case IB_MTU_2048: return 2048;
1297 case IB_MTU_4096: return 4096;
1302 static ssize_t show_port_ib_mtu(struct device *dev,
1303 struct device_attribute *attr,
1306 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1308 struct mlx4_dev *mdev = info->dev;
1310 /* When port type is eth, port mtu value isn't used. */
1311 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1314 sprintf(buf, "%d\n",
1315 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1319 static ssize_t set_port_ib_mtu(struct device *dev,
1320 struct device_attribute *attr,
1321 const char *buf, size_t count)
1323 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1325 struct mlx4_dev *mdev = info->dev;
1326 struct mlx4_priv *priv = mlx4_priv(mdev);
1327 int err, port, mtu, ibta_mtu = -1;
1329 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1330 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1334 mtu = (int) simple_strtol(buf, NULL, 0);
1335 ibta_mtu = int_to_ibta_mtu(mtu);
1338 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1342 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1344 mlx4_stop_sense(mdev);
1345 mutex_lock(&priv->port_mutex);
1346 mlx4_unregister_device(mdev);
1347 for (port = 1; port <= mdev->caps.num_ports; port++) {
1348 mlx4_CLOSE_PORT(mdev, port);
1349 err = mlx4_SET_PORT(mdev, port, -1);
1351 mlx4_err(mdev, "Failed to set port %d, "
1352 "aborting\n", port);
1356 err = mlx4_register_device(mdev);
1358 mutex_unlock(&priv->port_mutex);
1359 mlx4_start_sense(mdev);
1360 return err ? err : count;
1363 static int mlx4_load_fw(struct mlx4_dev *dev)
1365 struct mlx4_priv *priv = mlx4_priv(dev);
1366 int err, unmap_flag = 0;
1368 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1369 GFP_HIGHUSER | __GFP_NOWARN, 0);
1370 if (!priv->fw.fw_icm) {
1371 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
1375 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1377 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1381 err = mlx4_RUN_FW(dev);
1383 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1390 unmap_flag = mlx4_UNMAP_FA(dev);
1392 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1396 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1400 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1403 struct mlx4_priv *priv = mlx4_priv(dev);
1407 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1409 ((u64) (MLX4_CMPT_TYPE_QP *
1410 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1411 cmpt_entry_sz, dev->caps.num_qps,
1412 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1417 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1419 ((u64) (MLX4_CMPT_TYPE_SRQ *
1420 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1421 cmpt_entry_sz, dev->caps.num_srqs,
1422 dev->caps.reserved_srqs, 0, 0);
1426 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1428 ((u64) (MLX4_CMPT_TYPE_CQ *
1429 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1430 cmpt_entry_sz, dev->caps.num_cqs,
1431 dev->caps.reserved_cqs, 0, 0);
1435 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1437 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1439 ((u64) (MLX4_CMPT_TYPE_EQ *
1440 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1441 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1448 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1451 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1454 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1460 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1461 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1463 struct mlx4_priv *priv = mlx4_priv(dev);
1466 int err, unmap_flag = 0;
1468 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1470 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1474 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1475 (unsigned long long) icm_size >> 10,
1476 (unsigned long long) aux_pages << 2);
1478 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1479 GFP_HIGHUSER | __GFP_NOWARN, 0);
1480 if (!priv->fw.aux_icm) {
1481 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1485 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1487 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1491 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1493 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1498 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1500 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1501 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1502 num_eqs, num_eqs, 0, 0);
1504 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1505 goto err_unmap_cmpt;
1509 * Reserved MTT entries must be aligned up to a cacheline
1510 * boundary, since the FW will write to them, while the driver
1511 * writes to all other MTT entries. (The variable
1512 * dev->caps.mtt_entry_sz below is really the MTT segment
1513 * size, not the raw entry size)
1515 dev->caps.reserved_mtts =
1516 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1517 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1519 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1521 dev->caps.mtt_entry_sz,
1523 dev->caps.reserved_mtts, 1, 0);
1525 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1529 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1530 init_hca->dmpt_base,
1531 dev_cap->dmpt_entry_sz,
1533 dev->caps.reserved_mrws, 1, 1);
1535 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1539 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1541 dev_cap->qpc_entry_sz,
1543 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1546 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1547 goto err_unmap_dmpt;
1550 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1551 init_hca->auxc_base,
1552 dev_cap->aux_entry_sz,
1554 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1557 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1561 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1562 init_hca->altc_base,
1563 dev_cap->altc_entry_sz,
1565 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1568 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1569 goto err_unmap_auxc;
1572 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1573 init_hca->rdmarc_base,
1574 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1576 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1579 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1580 goto err_unmap_altc;
1583 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1585 dev_cap->cqc_entry_sz,
1587 dev->caps.reserved_cqs, 0, 0);
1589 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1590 goto err_unmap_rdmarc;
1593 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1594 init_hca->srqc_base,
1595 dev_cap->srq_entry_sz,
1597 dev->caps.reserved_srqs, 0, 0);
1599 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1604 * For flow steering device managed mode it is required to use
1605 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1606 * required, but for simplicity just map the whole multicast
1607 * group table now. The table isn't very big and it's a lot
1608 * easier than trying to track ref counts.
1610 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1612 mlx4_get_mgm_entry_size(dev),
1613 dev->caps.num_mgms + dev->caps.num_amgms,
1614 dev->caps.num_mgms + dev->caps.num_amgms,
1617 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1624 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1627 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1630 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1633 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1636 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1639 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1642 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1645 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1648 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1651 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1652 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1653 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1654 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1657 unmap_flag = mlx4_UNMAP_ICM_AUX(dev);
1659 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1663 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1668 static void mlx4_free_icms(struct mlx4_dev *dev)
1670 struct mlx4_priv *priv = mlx4_priv(dev);
1672 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1673 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1674 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1675 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1676 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1677 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1678 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1679 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1680 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1681 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1682 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1683 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1684 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1685 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1687 if (!mlx4_UNMAP_ICM_AUX(dev))
1688 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1690 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1693 static void mlx4_slave_exit(struct mlx4_dev *dev)
1695 struct mlx4_priv *priv = mlx4_priv(dev);
1697 mutex_lock(&priv->cmd.slave_cmd_mutex);
1698 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1699 mlx4_warn(dev, "Failed to close slave function.\n");
1700 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1703 static int map_bf_area(struct mlx4_dev *dev)
1705 struct mlx4_priv *priv = mlx4_priv(dev);
1706 resource_size_t bf_start;
1707 resource_size_t bf_len;
1710 if (!dev->caps.bf_reg_size)
1713 bf_start = pci_resource_start(dev->pdev, 2) +
1714 (dev->caps.num_uars << PAGE_SHIFT);
1715 bf_len = pci_resource_len(dev->pdev, 2) -
1716 (dev->caps.num_uars << PAGE_SHIFT);
1717 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1718 if (!priv->bf_mapping)
1724 static void unmap_bf_area(struct mlx4_dev *dev)
1726 if (mlx4_priv(dev)->bf_mapping)
1727 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1730 int mlx4_read_clock(struct mlx4_dev *dev)
1732 u32 clockhi, clocklo, clockhi1;
1735 struct mlx4_priv *priv = mlx4_priv(dev);
1737 if (!priv->clock_mapping)
1740 for (i = 0; i < 10; i++) {
1741 clockhi = swab32(readl(priv->clock_mapping));
1742 clocklo = swab32(readl(priv->clock_mapping + 4));
1743 clockhi1 = swab32(readl(priv->clock_mapping));
1744 if (clockhi == clockhi1)
1748 cycles = (u64) clockhi << 32 | (u64) clocklo;
1752 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1755 static int map_internal_clock(struct mlx4_dev *dev)
1757 struct mlx4_priv *priv = mlx4_priv(dev);
1759 priv->clock_mapping = ioremap(pci_resource_start(dev->pdev,
1760 priv->fw.clock_bar) +
1761 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1763 if (!priv->clock_mapping)
1770 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1771 struct mlx4_clock_params *params)
1773 struct mlx4_priv *priv = mlx4_priv(dev);
1775 if (mlx4_is_slave(dev))
1780 params->bar = priv->fw.clock_bar;
1781 params->offset = priv->fw.clock_offset;
1782 params->size = MLX4_CLOCK_SIZE;
1786 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1788 static void unmap_internal_clock(struct mlx4_dev *dev)
1790 struct mlx4_priv *priv = mlx4_priv(dev);
1792 if (priv->clock_mapping)
1793 iounmap(priv->clock_mapping);
1796 static void mlx4_close_hca(struct mlx4_dev *dev)
1798 unmap_internal_clock(dev);
1800 if (mlx4_is_slave(dev)) {
1801 mlx4_slave_exit(dev);
1803 mlx4_CLOSE_HCA(dev, 0);
1804 mlx4_free_icms(dev);
1806 if (!mlx4_UNMAP_FA(dev))
1807 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1809 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1813 static int mlx4_init_slave(struct mlx4_dev *dev)
1815 struct mlx4_priv *priv = mlx4_priv(dev);
1816 u64 dma = (u64) priv->mfunc.vhcr_dma;
1817 int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1818 int ret_from_reset = 0;
1820 u32 cmd_channel_ver;
1822 mutex_lock(&priv->cmd.slave_cmd_mutex);
1823 priv->cmd.max_cmds = 1;
1824 mlx4_warn(dev, "Sending reset\n");
1825 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1827 /* if we are in the middle of flr the slave will try
1828 * NUM_OF_RESET_RETRIES times before leaving.*/
1829 if (ret_from_reset) {
1830 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1831 msleep(SLEEP_TIME_IN_RESET);
1832 while (ret_from_reset && num_of_reset_retries) {
1833 mlx4_warn(dev, "slave is currently in the"
1834 "middle of FLR. retrying..."
1836 (NUM_OF_RESET_RETRIES -
1837 num_of_reset_retries + 1));
1839 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1841 num_of_reset_retries = num_of_reset_retries - 1;
1847 /* check the driver version - the slave I/F revision
1848 * must match the master's */
1849 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1850 cmd_channel_ver = mlx4_comm_get_version();
1852 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1853 MLX4_COMM_GET_IF_REV(slave_read)) {
1854 mlx4_err(dev, "slave driver version is not supported"
1855 " by the master\n");
1859 mlx4_warn(dev, "Sending vhcr0\n");
1860 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1863 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1866 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1869 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1872 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1876 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1877 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1881 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1885 for (i = 1; i <= dev->caps.num_ports; i++) {
1886 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1887 dev->caps.gid_table_len[i] =
1888 mlx4_get_slave_num_gids(dev, 0);
1890 dev->caps.gid_table_len[i] = 1;
1891 dev->caps.pkey_table_len[i] =
1892 dev->phys_caps.pkey_phys_table_len[i] - 1;
1896 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1898 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1900 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1902 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1906 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1909 static void choose_steering_mode(struct mlx4_dev *dev,
1910 struct mlx4_dev_cap *dev_cap)
1914 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(dev->pdev), 0, &nvfs);
1915 if (high_rate_steer && !mlx4_is_mfunc(dev)) {
1916 dev->caps.flags &= ~(MLX4_DEV_CAP_FLAG_VEP_MC_STEER |
1917 MLX4_DEV_CAP_FLAG_VEP_UC_STEER);
1918 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_FS_EN;
1921 if (mlx4_log_num_mgm_entry_size == -1 &&
1922 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1923 (!mlx4_is_mfunc(dev) ||
1924 (dev_cap->fs_max_num_qp_per_entry >= (nvfs + 1))) &&
1925 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1926 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1927 dev->oper_log_mgm_entry_size =
1928 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1929 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1930 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1932 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1933 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1934 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1936 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1938 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1939 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1940 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1941 "set to use B0 steering. Falling back to A0 steering mode.\n");
1943 dev->oper_log_mgm_entry_size =
1944 mlx4_log_num_mgm_entry_size > 0 ?
1945 mlx4_log_num_mgm_entry_size :
1946 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1947 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1949 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1950 "log_num_mgm_entry_size = %d\n",
1951 mlx4_steering_mode_str(dev->caps.steering_mode),
1952 dev->oper_log_mgm_entry_size, mlx4_log_num_mgm_entry_size);
1955 static int mlx4_init_hca(struct mlx4_dev *dev)
1957 struct mlx4_priv *priv = mlx4_priv(dev);
1958 struct mlx4_dev_cap *dev_cap = NULL;
1959 struct mlx4_adapter adapter;
1960 struct mlx4_mod_stat_cfg mlx4_cfg;
1961 struct mlx4_profile profile;
1962 struct mlx4_init_hca_param init_hca;
1966 if (!mlx4_is_slave(dev)) {
1967 err = mlx4_QUERY_FW(dev);
1970 mlx4_info(dev, "non-primary physical function, skipping.\n");
1972 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1976 err = mlx4_load_fw(dev);
1978 mlx4_err(dev, "Failed to start FW, aborting.\n");
1982 mlx4_cfg.log_pg_sz_m = 1;
1983 mlx4_cfg.log_pg_sz = 0;
1984 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1986 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1988 dev_cap = kzalloc(sizeof *dev_cap, GFP_KERNEL);
1990 mlx4_err(dev, "Failed to allocate memory for dev_cap\n");
1995 err = mlx4_dev_cap(dev, dev_cap);
1997 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
2001 choose_steering_mode(dev, dev_cap);
2003 if (mlx4_is_master(dev))
2004 mlx4_parav_master_pf_caps(dev);
2006 process_mod_param_profile(&profile);
2007 if (dev->caps.steering_mode ==
2008 MLX4_STEERING_MODE_DEVICE_MANAGED)
2009 profile.num_mcg = MLX4_FS_NUM_MCG;
2011 icm_size = mlx4_make_profile(dev, &profile, dev_cap,
2013 if ((long long) icm_size < 0) {
2018 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2020 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2021 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2023 err = mlx4_init_icm(dev, dev_cap, &init_hca, icm_size);
2027 init_hca.mw_enable = 1;
2029 err = mlx4_INIT_HCA(dev, &init_hca);
2031 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
2036 * Read HCA frequency by QUERY_HCA command
2038 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2039 memset(&init_hca, 0, sizeof(init_hca));
2040 err = mlx4_QUERY_HCA(dev, &init_hca);
2042 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
2043 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2045 dev->caps.hca_core_clock =
2046 init_hca.hca_core_clock;
2049 /* In case we got HCA frequency 0 - disable timestamping
2050 * to avoid dividing by zero
2052 if (!dev->caps.hca_core_clock) {
2053 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2054 mlx4_err(dev, "HCA frequency is 0. Timestamping is not supported.");
2055 } else if (map_internal_clock(dev)) {
2056 /* Map internal clock,
2057 * in case of failure disable timestamping
2059 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2060 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
2064 err = mlx4_init_slave(dev);
2066 mlx4_err(dev, "Failed to initialize slave\n");
2070 err = mlx4_slave_cap(dev);
2072 mlx4_err(dev, "Failed to obtain slave caps\n");
2077 if (map_bf_area(dev))
2078 mlx4_dbg(dev, "Failed to map blue flame area\n");
2080 /* Only the master set the ports, all the rest got it from it.*/
2081 if (!mlx4_is_slave(dev))
2082 mlx4_set_port_mask(dev);
2084 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2086 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
2090 priv->eq_table.inta_pin = adapter.inta_pin;
2091 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2092 memcpy(dev->vsd, adapter.vsd, sizeof(dev->vsd));
2093 dev->vsd_vendor_id = adapter.vsd_vendor_id;
2095 if (!mlx4_is_slave(dev))
2101 if (!mlx4_is_slave(dev))
2102 unmap_internal_clock(dev);
2105 if (mlx4_is_slave(dev)) {
2106 kfree(dev->caps.qp0_tunnel);
2107 kfree(dev->caps.qp0_proxy);
2108 kfree(dev->caps.qp1_tunnel);
2109 kfree(dev->caps.qp1_proxy);
2113 if (mlx4_is_slave(dev))
2114 mlx4_slave_exit(dev);
2116 mlx4_CLOSE_HCA(dev, 0);
2119 if (!mlx4_is_slave(dev))
2120 mlx4_free_icms(dev);
2123 if (!mlx4_is_slave(dev)) {
2124 if (!mlx4_UNMAP_FA(dev))
2125 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
2127 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
2133 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2135 struct mlx4_priv *priv = mlx4_priv(dev);
2136 int nent_pow2, port_indx, vf_index, num_counters;
2138 struct counter_index *new_counter_index;
2141 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2144 if (!mlx4_is_slave(dev) &&
2145 dev->caps.max_counters == dev->caps.max_extended_counters) {
2146 res = mlx4_cmd(dev, MLX4_IF_STATE_EXTENDED, 0, 0,
2147 MLX4_CMD_SET_IF_STAT,
2148 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2150 mlx4_err(dev, "Failed to set extended counters (err=%d)\n", res);
2155 mutex_init(&priv->counters_table.mutex);
2157 if (mlx4_is_slave(dev)) {
2158 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2159 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2160 if (dev->caps.def_counter_index[port_indx] != 0xFF) {
2161 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2162 if (!new_counter_index)
2164 new_counter_index->index = dev->caps.def_counter_index[port_indx];
2165 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port_indx]);
2168 mlx4_dbg(dev, "%s: slave allocated %d counters for %d ports\n",
2169 __func__, dev->caps.num_ports, dev->caps.num_ports);
2173 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2175 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2176 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2177 /* allocating 2 counters per port for PFs */
2178 /* For the PF, the ETH default counters are 0,2; */
2179 /* and the RoCE default counters are 1,3 */
2180 for (num_counters = 0; num_counters < 2; num_counters++, index++) {
2181 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2182 if (!new_counter_index)
2184 new_counter_index->index = index;
2185 list_add_tail(&new_counter_index->list,
2186 &priv->counters_table.global_port_list[port_indx]);
2190 if (mlx4_is_master(dev)) {
2191 for (vf_index = 0; vf_index < dev->num_vfs; vf_index++) {
2192 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2193 INIT_LIST_HEAD(&priv->counters_table.vf_list[vf_index][port_indx]);
2194 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2195 if (!new_counter_index)
2197 if (index < nent_pow2 - 2) {
2198 new_counter_index->index = index;
2201 new_counter_index->index = MLX4_SINK_COUNTER_INDEX;
2204 list_add_tail(&new_counter_index->list,
2205 &priv->counters_table.vf_list[vf_index][port_indx]);
2209 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2210 nent_pow2, nent_pow2 - 1,
2212 mlx4_dbg(dev, "%s: master allocated %d counters for %d VFs\n",
2213 __func__, index, dev->num_vfs);
2215 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2216 nent_pow2, nent_pow2 - 1,
2218 mlx4_dbg(dev, "%s: native allocated %d counters for %d ports\n",
2219 __func__, index, dev->caps.num_ports);
2226 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2228 struct mlx4_priv *priv = mlx4_priv(dev);
2230 struct counter_index *port, *tmp_port;
2231 struct counter_index *vf, *tmp_vf;
2233 mutex_lock(&priv->counters_table.mutex);
2235 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) {
2236 for (i = 0; i < dev->caps.num_ports; i++) {
2237 list_for_each_entry_safe(port, tmp_port,
2238 &priv->counters_table.global_port_list[i],
2240 list_del(&port->list);
2244 if (!mlx4_is_slave(dev)) {
2245 for (i = 0; i < dev->num_vfs; i++) {
2246 for (j = 0; j < dev->caps.num_ports; j++) {
2247 list_for_each_entry_safe(vf, tmp_vf,
2248 &priv->counters_table.vf_list[i][j],
2250 /* clear the counter statistic */
2251 if (__mlx4_clear_if_stat(dev, vf->index))
2252 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2253 __func__, vf->index);
2254 list_del(&vf->list);
2259 mlx4_bitmap_cleanup(&priv->counters_table.bitmap);
2262 mutex_unlock(&priv->counters_table.mutex);
2265 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave)
2267 struct mlx4_priv *priv = mlx4_priv(dev);
2269 struct counter_index *vf, *tmp_vf;
2271 /* clean VF's counters for the next useg */
2272 if (slave > 0 && slave <= dev->num_vfs) {
2273 mlx4_dbg(dev, "%s: free counters of slave(%d)\n"
2276 mutex_lock(&priv->counters_table.mutex);
2277 for (i = 0; i < dev->caps.num_ports; i++) {
2279 list_for_each_entry_safe(vf, tmp_vf,
2280 &priv->counters_table.vf_list[slave - 1][i],
2282 /* clear the counter statistic */
2283 if (__mlx4_clear_if_stat(dev, vf->index))
2284 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2285 __func__, vf->index);
2286 if (first++ && vf->index != MLX4_SINK_COUNTER_INDEX) {
2287 mlx4_dbg(dev, "%s: delete counter index %d for slave %d and port %d\n"
2288 , __func__, vf->index, slave, i + 1);
2289 mlx4_bitmap_free(&priv->counters_table.bitmap, vf->index, MLX4_USE_RR);
2290 list_del(&vf->list);
2293 mlx4_dbg(dev, "%s: can't delete default counter index %d for slave %d and port %d\n"
2294 , __func__, vf->index, slave, i + 1);
2298 mutex_unlock(&priv->counters_table.mutex);
2304 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx)
2306 struct mlx4_priv *priv = mlx4_priv(dev);
2307 struct counter_index *new_counter_index;
2309 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2312 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2313 (port < 0) || (port > MLX4_MAX_PORTS)) {
2314 mlx4_dbg(dev, "%s: invalid slave(%d) or port(%d) index\n",
2315 __func__, slave, port);
2319 /* handle old guest request does not support request by port index */
2321 *idx = MLX4_SINK_COUNTER_INDEX;
2322 mlx4_dbg(dev, "%s: allocated default counter index %d for slave %d port %d\n"
2323 , __func__, *idx, slave, port);
2327 mutex_lock(&priv->counters_table.mutex);
2329 *idx = mlx4_bitmap_alloc(&priv->counters_table.bitmap);
2330 /* if no resources return the default counter of the slave and port */
2332 if (slave == 0) { /* its the ethernet counter ?????? */
2333 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2334 struct counter_index,
2337 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2338 struct counter_index,
2342 *idx = new_counter_index->index;
2343 mlx4_dbg(dev, "%s: allocated defualt counter index %d for slave %d port %d\n"
2344 , __func__, *idx, slave, port);
2348 if (slave == 0) { /* native or master */
2349 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2350 if (!new_counter_index)
2352 new_counter_index->index = *idx;
2353 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2355 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2356 if (!new_counter_index)
2358 new_counter_index->index = *idx;
2359 list_add_tail(&new_counter_index->list, &priv->counters_table.vf_list[slave - 1][port - 1]);
2362 mlx4_dbg(dev, "%s: allocated counter index %d for slave %d port %d\n"
2363 , __func__, *idx, slave, port);
2365 mutex_unlock(&priv->counters_table.mutex);
2369 mlx4_bitmap_free(&priv->counters_table.bitmap, *idx, MLX4_USE_RR);
2370 mutex_unlock(&priv->counters_table.mutex);
2371 *idx = MLX4_SINK_COUNTER_INDEX;
2372 mlx4_dbg(dev, "%s: failed err (%d)\n"
2373 , __func__, -ENOMEM);
2377 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx)
2381 struct mlx4_priv *priv = mlx4_priv(dev);
2382 struct counter_index *new_counter_index, *c_index;
2384 if (mlx4_is_mfunc(dev)) {
2385 err = mlx4_cmd_imm(dev, 0, &out_param,
2386 ((u32) port) << 8 | (u32) RES_COUNTER,
2387 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2388 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2390 *idx = get_param_l(&out_param);
2391 if (*idx == MLX4_SINK_COUNTER_INDEX)
2394 mutex_lock(&priv->counters_table.mutex);
2395 c_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2396 struct counter_index,
2398 mutex_unlock(&priv->counters_table.mutex);
2399 if (c_index->index == *idx)
2402 if (mlx4_is_slave(dev)) {
2403 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2404 if (!new_counter_index) {
2405 mlx4_counter_free(dev, port, *idx);
2408 new_counter_index->index = *idx;
2409 mutex_lock(&priv->counters_table.mutex);
2410 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2411 mutex_unlock(&priv->counters_table.mutex);
2412 mlx4_dbg(dev, "%s: allocated counter index %d for port %d\n"
2413 , __func__, *idx, port);
2418 return __mlx4_counter_alloc(dev, 0, port, idx);
2420 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2422 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx)
2424 /* check if native or slave and deletes acordingly */
2425 struct mlx4_priv *priv = mlx4_priv(dev);
2426 struct counter_index *pf, *tmp_pf;
2427 struct counter_index *vf, *tmp_vf;
2431 if (idx == MLX4_SINK_COUNTER_INDEX) {
2432 mlx4_dbg(dev, "%s: try to delete default counter index %d for port %d\n"
2433 , __func__, idx, port);
2437 if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2438 (port < 0) || (port > MLX4_MAX_PORTS)) {
2439 mlx4_warn(dev, "%s: deletion failed due to invalid slave(%d) or port(%d) index\n"
2440 , __func__, slave, idx);
2444 mutex_lock(&priv->counters_table.mutex);
2447 list_for_each_entry_safe(pf, tmp_pf,
2448 &priv->counters_table.global_port_list[port - 1],
2450 /* the first 2 counters are reserved */
2451 if (pf->index == idx) {
2452 /* clear the counter statistic */
2453 if (__mlx4_clear_if_stat(dev, pf->index))
2454 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2455 __func__, pf->index);
2456 if (1 < first && idx != MLX4_SINK_COUNTER_INDEX) {
2457 list_del(&pf->list);
2459 mlx4_dbg(dev, "%s: delete counter index %d for native device (%d) port %d\n"
2460 , __func__, idx, slave, port);
2461 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2464 mlx4_dbg(dev, "%s: can't delete default counter index %d for native device (%d) port %d\n"
2465 , __func__, idx, slave, port);
2471 mlx4_dbg(dev, "%s: can't delete counter index %d for native device (%d) port %d\n"
2472 , __func__, idx, slave, port);
2475 list_for_each_entry_safe(vf, tmp_vf,
2476 &priv->counters_table.vf_list[slave - 1][port - 1],
2478 /* the first element is reserved */
2479 if (vf->index == idx) {
2480 /* clear the counter statistic */
2481 if (__mlx4_clear_if_stat(dev, vf->index))
2482 mlx4_dbg(dev, "%s: reset counter %d failed\n",
2483 __func__, vf->index);
2485 list_del(&vf->list);
2487 mlx4_dbg(dev, "%s: delete counter index %d for slave %d port %d\n",
2488 __func__, idx, slave, port);
2489 mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2492 mlx4_dbg(dev, "%s: can't delete default slave (%d) counter index %d for port %d\n"
2493 , __func__, slave, idx, port);
2499 mlx4_dbg(dev, "%s: can't delete slave (%d) counter index %d for port %d\n"
2500 , __func__, slave, idx, port);
2504 mutex_unlock(&priv->counters_table.mutex);
2507 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx)
2510 struct mlx4_priv *priv = mlx4_priv(dev);
2511 struct counter_index *counter, *tmp_counter;
2514 if (mlx4_is_mfunc(dev)) {
2515 set_param_l(&in_param, idx);
2516 mlx4_cmd(dev, in_param,
2517 ((u32) port) << 8 | (u32) RES_COUNTER,
2519 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2522 if (mlx4_is_slave(dev) && idx != MLX4_SINK_COUNTER_INDEX) {
2523 mutex_lock(&priv->counters_table.mutex);
2524 list_for_each_entry_safe(counter, tmp_counter,
2525 &priv->counters_table.global_port_list[port - 1],
2527 if (counter->index == idx && first++) {
2528 list_del(&counter->list);
2530 mlx4_dbg(dev, "%s: delete counter index %d for port %d\n"
2531 , __func__, idx, port);
2532 mutex_unlock(&priv->counters_table.mutex);
2536 mutex_unlock(&priv->counters_table.mutex);
2541 __mlx4_counter_free(dev, 0, port, idx);
2543 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2545 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2548 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2550 u32 if_stat_in_mod = (counter_index & 0xff) | (1 << 31);
2552 if (counter_index == MLX4_SINK_COUNTER_INDEX)
2555 if (mlx4_is_slave(dev))
2558 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2559 if (IS_ERR(if_stat_mailbox)) {
2560 err = PTR_ERR(if_stat_mailbox);
2564 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2565 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2568 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2572 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port)
2574 struct mlx4_priv *priv = mlx4_priv(dev);
2575 struct counter_index *new_counter_index;
2577 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) {
2578 mlx4_dbg(dev, "%s: return counter index %d for slave %d port (MLX4_PORT_TYPE_IB) %d\n",
2579 __func__, MLX4_SINK_COUNTER_INDEX, slave, port);
2580 return (u8)MLX4_SINK_COUNTER_INDEX;
2583 mutex_lock(&priv->counters_table.mutex);
2585 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2586 struct counter_index,
2589 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2590 struct counter_index,
2593 mutex_unlock(&priv->counters_table.mutex);
2595 mlx4_dbg(dev, "%s: return counter index %d for slave %d port %d\n",
2596 __func__, new_counter_index->index, slave, port);
2599 return (u8)new_counter_index->index;
2602 int mlx4_get_vport_ethtool_stats(struct mlx4_dev *dev, int port,
2603 struct mlx4_en_vport_stats *vport_stats,
2606 struct mlx4_priv *priv = mlx4_priv(dev);
2607 struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2608 union mlx4_counter *counter;
2611 struct counter_index *vport, *tmp_vport;
2616 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2617 if (IS_ERR(if_stat_mailbox)) {
2618 err = PTR_ERR(if_stat_mailbox);
2622 mutex_lock(&priv->counters_table.mutex);
2623 list_for_each_entry_safe(vport, tmp_vport,
2624 &priv->counters_table.global_port_list[port - 1],
2626 if (vport->index == MLX4_SINK_COUNTER_INDEX)
2629 memset(if_stat_mailbox->buf, 0, sizeof(union mlx4_counter));
2630 if_stat_in_mod = (vport->index & 0xff) | ((reset & 1) << 31);
2631 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma,
2633 MLX4_CMD_QUERY_IF_STAT,
2634 MLX4_CMD_TIME_CLASS_C,
2637 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
2638 __func__, vport->index);
2641 counter = (union mlx4_counter *)if_stat_mailbox->buf;
2642 if ((counter->control.cnt_mode & 0xf) == 1) {
2643 vport_stats->rx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastFrames);
2644 vport_stats->rx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxUnicastFrames);
2645 vport_stats->rx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxMulticastFrames);
2646 vport_stats->tx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastFrames);
2647 vport_stats->tx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxUnicastFrames);
2648 vport_stats->tx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxMulticastFrames);
2649 vport_stats->rx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastOctets);
2650 vport_stats->rx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxUnicastOctets);
2651 vport_stats->rx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxMulticastOctets);
2652 vport_stats->tx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastOctets);
2653 vport_stats->tx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxUnicastOctets);
2654 vport_stats->tx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxMulticastOctets);
2655 vport_stats->rx_errors += be64_to_cpu(counter->ext.counters[0].IfRxErrorFrames);
2656 vport_stats->rx_dropped += be64_to_cpu(counter->ext.counters[0].IfRxNoBufferFrames);
2657 vport_stats->tx_errors += be64_to_cpu(counter->ext.counters[0].IfTxDroppedFrames);
2662 mutex_unlock(&priv->counters_table.mutex);
2663 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2667 EXPORT_SYMBOL_GPL(mlx4_get_vport_ethtool_stats);
2669 static int mlx4_setup_hca(struct mlx4_dev *dev)
2671 struct mlx4_priv *priv = mlx4_priv(dev);
2674 __be32 ib_port_default_caps;
2676 err = mlx4_init_uar_table(dev);
2678 mlx4_err(dev, "Failed to initialize "
2679 "user access region table (err=%d), aborting.\n",
2684 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2686 mlx4_err(dev, "Failed to allocate driver access region "
2687 "(err=%d), aborting.\n", err);
2688 goto err_uar_table_free;
2691 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2693 mlx4_err(dev, "Couldn't map kernel access region, "
2699 err = mlx4_init_pd_table(dev);
2701 mlx4_err(dev, "Failed to initialize "
2702 "protection domain table (err=%d), aborting.\n", err);
2706 err = mlx4_init_xrcd_table(dev);
2708 mlx4_err(dev, "Failed to initialize "
2709 "reliable connection domain table (err=%d), "
2710 "aborting.\n", err);
2711 goto err_pd_table_free;
2714 err = mlx4_init_mr_table(dev);
2716 mlx4_err(dev, "Failed to initialize "
2717 "memory region table (err=%d), aborting.\n", err);
2718 goto err_xrcd_table_free;
2721 if (!mlx4_is_slave(dev)) {
2722 err = mlx4_init_mcg_table(dev);
2724 mlx4_err(dev, "Failed to initialize "
2725 "multicast group table (err=%d), aborting.\n",
2727 goto err_mr_table_free;
2731 err = mlx4_init_eq_table(dev);
2733 mlx4_err(dev, "Failed to initialize "
2734 "event queue table (err=%d), aborting.\n", err);
2735 goto err_mcg_table_free;
2738 err = mlx4_cmd_use_events(dev);
2740 mlx4_err(dev, "Failed to switch to event-driven "
2741 "firmware commands (err=%d), aborting.\n", err);
2742 goto err_eq_table_free;
2745 err = mlx4_NOP(dev);
2747 if (dev->flags & MLX4_FLAG_MSI_X) {
2748 mlx4_warn(dev, "NOP command failed to generate MSI-X "
2749 "interrupt IRQ %d).\n",
2750 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2751 mlx4_warn(dev, "Trying again without MSI-X.\n");
2753 mlx4_err(dev, "NOP command failed to generate interrupt "
2754 "(IRQ %d), aborting.\n",
2755 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2756 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2762 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2764 err = mlx4_init_cq_table(dev);
2766 mlx4_err(dev, "Failed to initialize "
2767 "completion queue table (err=%d), aborting.\n", err);
2771 err = mlx4_init_srq_table(dev);
2773 mlx4_err(dev, "Failed to initialize "
2774 "shared receive queue table (err=%d), aborting.\n",
2776 goto err_cq_table_free;
2779 err = mlx4_init_qp_table(dev);
2781 mlx4_err(dev, "Failed to initialize "
2782 "queue pair table (err=%d), aborting.\n", err);
2783 goto err_srq_table_free;
2786 err = mlx4_init_counters_table(dev);
2787 if (err && err != -ENOENT) {
2788 mlx4_err(dev, "Failed to initialize counters table (err=%d), "
2789 "aborting.\n", err);
2790 goto err_qp_table_free;
2793 if (!mlx4_is_slave(dev)) {
2794 for (port = 1; port <= dev->caps.num_ports; port++) {
2795 ib_port_default_caps = 0;
2796 err = mlx4_get_port_ib_caps(dev, port,
2797 &ib_port_default_caps);
2799 mlx4_warn(dev, "failed to get port %d default "
2800 "ib capabilities (%d). Continuing "
2801 "with caps = 0\n", port, err);
2802 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2804 /* initialize per-slave default ib port capabilities */
2805 if (mlx4_is_master(dev)) {
2807 for (i = 0; i < dev->num_slaves; i++) {
2808 if (i == mlx4_master_func_num(dev))
2810 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2811 ib_port_default_caps;
2815 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2817 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2818 dev->caps.pkey_table_len[port] : -1);
2820 mlx4_err(dev, "Failed to set port %d (err=%d), "
2821 "aborting\n", port, err);
2822 goto err_counters_table_free;
2829 err_counters_table_free:
2830 mlx4_cleanup_counters_table(dev);
2833 mlx4_cleanup_qp_table(dev);
2836 mlx4_cleanup_srq_table(dev);
2839 mlx4_cleanup_cq_table(dev);
2842 mlx4_cmd_use_polling(dev);
2845 mlx4_cleanup_eq_table(dev);
2848 if (!mlx4_is_slave(dev))
2849 mlx4_cleanup_mcg_table(dev);
2852 mlx4_cleanup_mr_table(dev);
2854 err_xrcd_table_free:
2855 mlx4_cleanup_xrcd_table(dev);
2858 mlx4_cleanup_pd_table(dev);
2864 mlx4_uar_free(dev, &priv->driver_uar);
2867 mlx4_cleanup_uar_table(dev);
2871 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2873 struct mlx4_priv *priv = mlx4_priv(dev);
2874 struct msix_entry *entries;
2875 int nreq = min_t(int, dev->caps.num_ports *
2876 min_t(int, num_possible_cpus() + 1, MAX_MSIX_P_PORT)
2877 + MSIX_LEGACY_SZ, MAX_MSIX);
2882 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2885 if (msi_x > 1 && !mlx4_is_mfunc(dev))
2886 nreq = min_t(int, nreq, msi_x);
2888 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2892 for (i = 0; i < nreq; ++i)
2893 entries[i].entry = i;
2896 err = pci_enable_msix(dev->pdev, entries, nreq);
2898 /* Try again if at least 2 vectors are available */
2900 mlx4_info(dev, "Requested %d vectors, "
2901 "but only %d MSI-X vectors available, "
2902 "trying again\n", nreq, err);
2907 /* if error, or can't alloc even 1 IRQ */
2909 mlx4_err(dev, "No IRQs left, device can't "
2917 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
2918 /*Working in legacy mode , all EQ's shared*/
2919 dev->caps.comp_pool = 0;
2920 dev->caps.num_comp_vectors = nreq - 1;
2922 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2923 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2925 for (i = 0; i < nreq; ++i)
2926 priv->eq_table.eq[i].irq = entries[i].vector;
2928 dev->flags |= MLX4_FLAG_MSI_X;
2935 dev->caps.num_comp_vectors = 1;
2936 dev->caps.comp_pool = 0;
2938 for (i = 0; i < 2; ++i)
2939 priv->eq_table.eq[i].irq = dev->pdev->irq;
2942 dev->caps.num_comp_vectors = 0;
2943 dev->caps.comp_pool = 0;
2946 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2948 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2953 if (!mlx4_is_slave(dev)) {
2954 mlx4_init_mac_table(dev, &info->mac_table);
2955 mlx4_init_vlan_table(dev, &info->vlan_table);
2956 info->base_qpn = mlx4_get_base_qpn(dev, port);
2959 sprintf(info->dev_name, "mlx4_port%d", port);
2960 info->port_attr.attr.name = info->dev_name;
2961 if (mlx4_is_mfunc(dev))
2962 info->port_attr.attr.mode = S_IRUGO;
2964 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2965 info->port_attr.store = set_port_type;
2967 info->port_attr.show = show_port_type;
2968 sysfs_attr_init(&info->port_attr.attr);
2970 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2972 mlx4_err(dev, "Failed to create file for port %d\n", port);
2976 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2977 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2978 if (mlx4_is_mfunc(dev))
2979 info->port_mtu_attr.attr.mode = S_IRUGO;
2981 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2982 info->port_mtu_attr.store = set_port_ib_mtu;
2984 info->port_mtu_attr.show = show_port_ib_mtu;
2985 sysfs_attr_init(&info->port_mtu_attr.attr);
2987 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2989 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2990 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2997 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3002 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
3003 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
3006 static int mlx4_init_steering(struct mlx4_dev *dev)
3008 struct mlx4_priv *priv = mlx4_priv(dev);
3009 int num_entries = dev->caps.num_ports;
3012 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3016 for (i = 0; i < num_entries; i++)
3017 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3018 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3019 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3024 static void mlx4_clear_steering(struct mlx4_dev *dev)
3026 struct mlx4_priv *priv = mlx4_priv(dev);
3027 struct mlx4_steer_index *entry, *tmp_entry;
3028 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3029 int num_entries = dev->caps.num_ports;
3032 for (i = 0; i < num_entries; i++) {
3033 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3034 list_for_each_entry_safe(pqp, tmp_pqp,
3035 &priv->steer[i].promisc_qps[j],
3037 list_del(&pqp->list);
3040 list_for_each_entry_safe(entry, tmp_entry,
3041 &priv->steer[i].steer_entries[j],
3043 list_del(&entry->list);
3044 list_for_each_entry_safe(pqp, tmp_pqp,
3047 list_del(&pqp->list);
3057 static int extended_func_num(struct pci_dev *pdev)
3059 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3062 #define MLX4_OWNER_BASE 0x8069c
3063 #define MLX4_OWNER_SIZE 4
3065 static int mlx4_get_ownership(struct mlx4_dev *dev)
3067 void __iomem *owner;
3070 if (pci_channel_offline(dev->pdev))
3073 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3076 mlx4_err(dev, "Failed to obtain ownership bit\n");
3085 static void mlx4_free_ownership(struct mlx4_dev *dev)
3087 void __iomem *owner;
3089 if (pci_channel_offline(dev->pdev))
3092 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3095 mlx4_err(dev, "Failed to obtain ownership bit\n");
3103 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
3105 struct mlx4_priv *priv;
3106 struct mlx4_dev *dev;
3111 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3113 err = pci_enable_device(pdev);
3115 dev_err(&pdev->dev, "Cannot enable PCI device, "
3120 mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(pdev), 0, &nvfs);
3121 mlx4_get_val(probe_vf.dbdf2val.tbl, pci_physfn(pdev), 0, &prb_vf);
3122 if (nvfs > MLX4_MAX_NUM_VF) {
3123 dev_err(&pdev->dev, "There are more VF's (%d) than allowed(%d)\n",
3124 nvfs, MLX4_MAX_NUM_VF);
3129 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3135 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3136 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3137 dev_err(&pdev->dev, "Missing DCS, aborting."
3138 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%x)\n",
3139 pci_dev_data, pci_resource_flags(pdev, 0));
3141 goto err_disable_pdev;
3143 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3144 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
3146 goto err_disable_pdev;
3149 err = pci_request_regions(pdev, DRV_NAME);
3151 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3152 goto err_disable_pdev;
3155 pci_set_master(pdev);
3157 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3159 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
3160 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3162 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
3163 goto err_release_regions;
3166 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3168 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
3169 "consistent PCI DMA mask.\n");
3170 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3172 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
3174 goto err_release_regions;
3178 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3179 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3181 priv = kzalloc(sizeof *priv, GFP_KERNEL);
3183 dev_err(&pdev->dev, "Device struct alloc failed, "
3186 goto err_release_regions;
3191 INIT_LIST_HEAD(&priv->dev_list);
3192 INIT_LIST_HEAD(&priv->ctx_list);
3193 spin_lock_init(&priv->ctx_lock);
3195 mutex_init(&priv->port_mutex);
3197 INIT_LIST_HEAD(&priv->pgdir_list);
3198 mutex_init(&priv->pgdir_mutex);
3200 INIT_LIST_HEAD(&priv->bf_list);
3201 mutex_init(&priv->bf_mutex);
3203 dev->rev_id = pdev->revision;
3204 dev->numa_node = dev_to_node(&pdev->dev);
3205 /* Detect if this device is a virtual function */
3206 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3207 /* When acting as pf, we normally skip vfs unless explicitly
3208 * requested to probe them. */
3209 if (nvfs && extended_func_num(pdev) > prb_vf) {
3210 mlx4_warn(dev, "Skipping virtual function:%d\n",
3211 extended_func_num(pdev));
3215 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3216 dev->flags |= MLX4_FLAG_SLAVE;
3218 /* We reset the device and enable SRIOV only for physical
3219 * devices. Try to claim ownership on the device;
3220 * if already taken, skip -- do not allow multiple PFs */
3221 err = mlx4_get_ownership(dev);
3226 mlx4_warn(dev, "Multiple PFs not yet supported."
3234 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", nvfs);
3235 err = pci_enable_sriov(pdev, nvfs);
3237 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
3241 mlx4_warn(dev, "Running in master mode\n");
3242 dev->flags |= MLX4_FLAG_SRIOV |
3244 dev->num_vfs = nvfs;
3248 atomic_set(&priv->opreq_count, 0);
3249 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3252 * Now reset the HCA before we touch the PCI capabilities or
3253 * attempt a firmware command, since a boot ROM may have left
3254 * the HCA in an undefined state.
3256 err = mlx4_reset(dev);
3258 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3264 err = mlx4_cmd_init(dev);
3266 mlx4_err(dev, "Failed to init command interface, aborting.\n");
3270 /* In slave functions, the communication channel must be initialized
3271 * before posting commands. Also, init num_slaves before calling
3273 if (mlx4_is_mfunc(dev)) {
3274 if (mlx4_is_master(dev))
3275 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3277 dev->num_slaves = 0;
3278 err = mlx4_multi_func_init(dev);
3280 mlx4_err(dev, "Failed to init slave mfunc"
3281 " interface, aborting.\n");
3287 err = mlx4_init_hca(dev);
3289 if (err == -EACCES) {
3290 /* Not primary Physical function
3291 * Running in slave mode */
3292 mlx4_cmd_cleanup(dev);
3293 dev->flags |= MLX4_FLAG_SLAVE;
3294 dev->flags &= ~MLX4_FLAG_MASTER;
3300 /* In master functions, the communication channel must be initialized
3301 * after obtaining its address from fw */
3302 if (mlx4_is_master(dev)) {
3303 err = mlx4_multi_func_init(dev);
3305 mlx4_err(dev, "Failed to init master mfunc"
3306 "interface, aborting.\n");
3311 err = mlx4_alloc_eq_table(dev);
3313 goto err_master_mfunc;
3315 priv->msix_ctl.pool_bm = 0;
3316 mutex_init(&priv->msix_ctl.pool_lock);
3318 mlx4_enable_msi_x(dev);
3320 /* no MSIX and no shared IRQ */
3321 if (!dev->caps.num_comp_vectors && !dev->caps.comp_pool) {
3326 if ((mlx4_is_mfunc(dev)) &&
3327 !(dev->flags & MLX4_FLAG_MSI_X)) {
3329 mlx4_err(dev, "INTx is not supported in multi-function mode."
3334 if (!mlx4_is_slave(dev)) {
3335 err = mlx4_init_steering(dev);
3340 err = mlx4_setup_hca(dev);
3341 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3342 !mlx4_is_mfunc(dev)) {
3343 dev->flags &= ~MLX4_FLAG_MSI_X;
3344 dev->caps.num_comp_vectors = 1;
3345 dev->caps.comp_pool = 0;
3346 pci_disable_msix(pdev);
3347 err = mlx4_setup_hca(dev);
3353 mlx4_init_quotas(dev);
3355 for (port = 1; port <= dev->caps.num_ports; port++) {
3356 err = mlx4_init_port_info(dev, port);
3361 err = mlx4_register_device(dev);
3365 mlx4_request_modules(dev);
3367 mlx4_sense_init(dev);
3368 mlx4_start_sense(dev);
3370 priv->pci_dev_data = pci_dev_data;
3371 pci_set_drvdata(pdev, dev);
3376 for (--port; port >= 1; --port)
3377 mlx4_cleanup_port_info(&priv->port[port]);
3379 mlx4_cleanup_counters_table(dev);
3380 mlx4_cleanup_qp_table(dev);
3381 mlx4_cleanup_srq_table(dev);
3382 mlx4_cleanup_cq_table(dev);
3383 mlx4_cmd_use_polling(dev);
3384 mlx4_cleanup_eq_table(dev);
3385 mlx4_cleanup_mcg_table(dev);
3386 mlx4_cleanup_mr_table(dev);
3387 mlx4_cleanup_xrcd_table(dev);
3388 mlx4_cleanup_pd_table(dev);
3389 mlx4_cleanup_uar_table(dev);
3392 if (!mlx4_is_slave(dev))
3393 mlx4_clear_steering(dev);
3396 mlx4_free_eq_table(dev);
3399 if (mlx4_is_master(dev)) {
3400 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3401 mlx4_multi_func_cleanup(dev);
3404 if (mlx4_is_slave(dev)) {
3405 kfree(dev->caps.qp0_tunnel);
3406 kfree(dev->caps.qp0_proxy);
3407 kfree(dev->caps.qp1_tunnel);
3408 kfree(dev->caps.qp1_proxy);
3412 if (dev->flags & MLX4_FLAG_MSI_X)
3413 pci_disable_msix(pdev);
3415 mlx4_close_hca(dev);
3418 if (mlx4_is_slave(dev))
3419 mlx4_multi_func_cleanup(dev);
3422 mlx4_cmd_cleanup(dev);
3425 if (dev->flags & MLX4_FLAG_SRIOV)
3426 pci_disable_sriov(pdev);
3428 if (!mlx4_is_slave(dev))
3429 mlx4_free_ownership(dev);
3434 err_release_regions:
3435 pci_release_regions(pdev);
3438 pci_disable_device(pdev);
3439 pci_set_drvdata(pdev, NULL);
3443 static int __devinit mlx4_init_one(struct pci_dev *pdev,
3444 const struct pci_device_id *id)
3446 printk_once(KERN_INFO "%s", mlx4_version);
3448 return __mlx4_init_one(pdev, id->driver_data);
3451 static void mlx4_remove_one(struct pci_dev *pdev)
3453 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3454 struct mlx4_priv *priv = mlx4_priv(dev);
3458 /* in SRIOV it is not allowed to unload the pf's
3459 * driver while there are alive vf's */
3460 if (mlx4_is_master(dev)) {
3461 if (mlx4_how_many_lives_vf(dev))
3462 mlx4_err(dev, "Removing PF when there are assigned VF's !!!\n");
3464 mlx4_stop_sense(dev);
3465 mlx4_unregister_device(dev);
3467 for (p = 1; p <= dev->caps.num_ports; p++) {
3468 mlx4_cleanup_port_info(&priv->port[p]);
3469 mlx4_CLOSE_PORT(dev, p);
3472 if (mlx4_is_master(dev))
3473 mlx4_free_resource_tracker(dev,
3474 RES_TR_FREE_SLAVES_ONLY);
3476 mlx4_cleanup_counters_table(dev);
3477 mlx4_cleanup_qp_table(dev);
3478 mlx4_cleanup_srq_table(dev);
3479 mlx4_cleanup_cq_table(dev);
3480 mlx4_cmd_use_polling(dev);
3481 mlx4_cleanup_eq_table(dev);
3482 mlx4_cleanup_mcg_table(dev);
3483 mlx4_cleanup_mr_table(dev);
3484 mlx4_cleanup_xrcd_table(dev);
3485 mlx4_cleanup_pd_table(dev);
3487 if (mlx4_is_master(dev))
3488 mlx4_free_resource_tracker(dev,
3489 RES_TR_FREE_STRUCTS_ONLY);
3492 mlx4_uar_free(dev, &priv->driver_uar);
3493 mlx4_cleanup_uar_table(dev);
3494 if (!mlx4_is_slave(dev))
3495 mlx4_clear_steering(dev);
3496 mlx4_free_eq_table(dev);
3497 if (mlx4_is_master(dev))
3498 mlx4_multi_func_cleanup(dev);
3499 mlx4_close_hca(dev);
3500 if (mlx4_is_slave(dev))
3501 mlx4_multi_func_cleanup(dev);
3502 mlx4_cmd_cleanup(dev);
3504 if (dev->flags & MLX4_FLAG_MSI_X)
3505 pci_disable_msix(pdev);
3506 if (dev->flags & MLX4_FLAG_SRIOV) {
3507 mlx4_warn(dev, "Disabling SR-IOV\n");
3508 pci_disable_sriov(pdev);
3511 if (!mlx4_is_slave(dev))
3512 mlx4_free_ownership(dev);
3514 kfree(dev->caps.qp0_tunnel);
3515 kfree(dev->caps.qp0_proxy);
3516 kfree(dev->caps.qp1_tunnel);
3517 kfree(dev->caps.qp1_proxy);
3520 pci_release_regions(pdev);
3521 pci_disable_device(pdev);
3522 pci_set_drvdata(pdev, NULL);
3526 static int restore_current_port_types(struct mlx4_dev *dev,
3527 enum mlx4_port_type *types,
3528 enum mlx4_port_type *poss_types)
3530 struct mlx4_priv *priv = mlx4_priv(dev);
3533 mlx4_stop_sense(dev);
3534 mutex_lock(&priv->port_mutex);
3535 for (i = 0; i < dev->caps.num_ports; i++)
3536 dev->caps.possible_type[i + 1] = poss_types[i];
3537 err = mlx4_change_port_types(dev, types);
3538 mlx4_start_sense(dev);
3539 mutex_unlock(&priv->port_mutex);
3543 int mlx4_restart_one(struct pci_dev *pdev)
3545 struct mlx4_dev *dev = pci_get_drvdata(pdev);
3546 struct mlx4_priv *priv = mlx4_priv(dev);
3547 enum mlx4_port_type curr_type[MLX4_MAX_PORTS];
3548 enum mlx4_port_type poss_type[MLX4_MAX_PORTS];
3549 int pci_dev_data, err, i;
3551 pci_dev_data = priv->pci_dev_data;
3552 for (i = 0; i < dev->caps.num_ports; i++) {
3553 curr_type[i] = dev->caps.port_type[i + 1];
3554 poss_type[i] = dev->caps.possible_type[i + 1];
3557 mlx4_remove_one(pdev);
3558 err = __mlx4_init_one(pdev, pci_dev_data);
3562 dev = pci_get_drvdata(pdev);
3563 err = restore_current_port_types(dev, curr_type, poss_type);
3565 mlx4_err(dev, "mlx4_restart_one: could not restore original port types (%d)\n",
3570 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
3571 /* MT25408 "Hermon" SDR */
3572 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3573 /* MT25408 "Hermon" DDR */
3574 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3575 /* MT25408 "Hermon" QDR */
3576 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3577 /* MT25408 "Hermon" DDR PCIe gen2 */
3578 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3579 /* MT25408 "Hermon" QDR PCIe gen2 */
3580 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3581 /* MT25408 "Hermon" EN 10GigE */
3582 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3583 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3584 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3585 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3586 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3587 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3588 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3589 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3590 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3591 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3592 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3593 /* MT26478 ConnectX2 40GigE PCIe gen2 */
3594 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3595 /* MT25400 Family [ConnectX-2 Virtual Function] */
3596 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3597 /* MT27500 Family [ConnectX-3] */
3598 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3599 /* MT27500 Family [ConnectX-3 Virtual Function] */
3600 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3601 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3602 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3603 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3604 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3605 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3606 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3607 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3608 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3609 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3610 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3611 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3612 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3616 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3618 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3619 pci_channel_state_t state)
3621 mlx4_remove_one(pdev);
3623 return state == pci_channel_io_perm_failure ?
3624 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3627 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3629 int ret = __mlx4_init_one(pdev, 0);
3631 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3634 static const struct pci_error_handlers mlx4_err_handler = {
3635 .error_detected = mlx4_pci_err_detected,
3636 .slot_reset = mlx4_pci_slot_reset,
3639 static int suspend(struct pci_dev *pdev, pm_message_t state)
3641 mlx4_remove_one(pdev);
3646 static int resume(struct pci_dev *pdev)
3648 return __mlx4_init_one(pdev, 0);
3651 static struct pci_driver mlx4_driver = {
3653 .id_table = mlx4_pci_table,
3654 .probe = mlx4_init_one,
3655 .remove = __devexit_p(mlx4_remove_one),
3658 .err_handler = &mlx4_err_handler,
3661 static int __init mlx4_verify_params(void)
3665 status = update_defaults(&port_type_array);
3666 if (status == INVALID_STR) {
3667 if (mlx4_fill_dbdf2val_tbl(&port_type_array.dbdf2val))
3669 } else if (status == INVALID_DATA) {
3673 status = update_defaults(&num_vfs);
3674 if (status == INVALID_STR) {
3675 if (mlx4_fill_dbdf2val_tbl(&num_vfs.dbdf2val))
3677 } else if (status == INVALID_DATA) {
3681 status = update_defaults(&probe_vf);
3682 if (status == INVALID_STR) {
3683 if (mlx4_fill_dbdf2val_tbl(&probe_vf.dbdf2val))
3685 } else if (status == INVALID_DATA) {
3690 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
3694 if ((log_num_mac < 0) || (log_num_mac > 7)) {
3695 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
3699 if (log_num_vlan != 0)
3700 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3701 MLX4_LOG_NUM_VLANS);
3703 if (mlx4_set_4k_mtu != -1)
3704 pr_warning("mlx4_core: set_4k_mtu - obsolete module param\n");
3706 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
3707 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
3711 if (mlx4_log_num_mgm_entry_size != -1 &&
3712 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3713 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
3714 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
3715 "in legal range (-1 or %d..%d)\n",
3716 mlx4_log_num_mgm_entry_size,
3717 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3718 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3722 if (mod_param_profile.num_qp < 18 || mod_param_profile.num_qp > 23) {
3723 pr_warning("mlx4_core: bad log_num_qp: %d\n",
3724 mod_param_profile.num_qp);
3728 if (mod_param_profile.num_srq < 10) {
3729 pr_warning("mlx4_core: too low log_num_srq: %d\n",
3730 mod_param_profile.num_srq);
3734 if (mod_param_profile.num_cq < 10) {
3735 pr_warning("mlx4_core: too low log_num_cq: %d\n",
3736 mod_param_profile.num_cq);
3740 if (mod_param_profile.num_mpt < 10) {
3741 pr_warning("mlx4_core: too low log_num_mpt: %d\n",
3742 mod_param_profile.num_mpt);
3746 if (mod_param_profile.num_mtt_segs &&
3747 mod_param_profile.num_mtt_segs < 15) {
3748 pr_warning("mlx4_core: too low log_num_mtt: %d\n",
3749 mod_param_profile.num_mtt_segs);
3753 if (mod_param_profile.num_mtt_segs > MLX4_MAX_LOG_NUM_MTT) {
3754 pr_warning("mlx4_core: too high log_num_mtt: %d\n",
3755 mod_param_profile.num_mtt_segs);
3761 static int __init mlx4_init(void)
3765 if (mlx4_verify_params())
3770 mlx4_wq = create_singlethread_workqueue("mlx4");
3774 if (enable_sys_tune)
3777 ret = pci_register_driver(&mlx4_driver);
3784 if (enable_sys_tune)
3787 destroy_workqueue(mlx4_wq);
3792 static void __exit mlx4_cleanup(void)
3794 if (enable_sys_tune)
3797 pci_unregister_driver(&mlx4_driver);
3798 destroy_workqueue(mlx4_wq);
3801 module_init_order(mlx4_init, SI_ORDER_MIDDLE);
3802 module_exit(mlx4_cleanup);
3804 #include <sys/module.h>
3806 mlx4_evhand(module_t mod, int event, void *arg)
3811 static moduledata_t mlx4_mod = {
3813 .evhand = mlx4_evhand,
3815 MODULE_VERSION(mlx4, 1);
3816 DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_OFED_PREINIT, SI_ORDER_ANY);