2 * Copyright (c) 2001 Matt Thomas.
3 * Copyright (c) 2001 Tsubai Masanari.
4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by
18 * Internet Research Institute, Inc.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (C) 2003 Benno Rice.
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
61 #include <sys/param.h>
62 #include <sys/systm.h>
66 #include <sys/kernel.h>
68 #include <sys/sysctl.h>
70 #include <machine/bus.h>
71 #include <machine/cpu.h>
72 #include <machine/hid.h>
73 #include <machine/md_var.h>
74 #include <machine/smp.h>
75 #include <machine/spr.h>
77 #include <dev/ofw/openfirm.h>
79 static void cpu_6xx_setup(int cpuid, uint16_t vers);
80 static void cpu_970_setup(int cpuid, uint16_t vers);
81 static void cpu_booke_setup(int cpuid, uint16_t vers);
83 int powerpc_pow_enabled;
84 void (*cpu_idle_hook)(sbintime_t) = NULL;
85 static void cpu_idle_60x(sbintime_t);
86 static void cpu_idle_booke(sbintime_t);
92 int features; /* Do not include PPC_FEATURE_32 or
93 * PPC_FEATURE_HAS_MMU */
94 void (*cpu_setup)(int cpuid, uint16_t vers);
96 #define REVFMT_MAJMIN 1 /* %u.%u */
97 #define REVFMT_HEX 2 /* 0x%04x */
98 #define REVFMT_DEC 3 /* %u */
99 static const struct cputab models[] = {
100 { "Motorola PowerPC 601", MPC601, REVFMT_DEC,
101 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, cpu_6xx_setup },
102 { "Motorola PowerPC 602", MPC602, REVFMT_DEC,
103 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
104 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
105 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
106 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
107 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
108 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
109 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
110 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
111 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
112 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
113 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
114 { "Motorola PowerPC 620", MPC620, REVFMT_HEX,
115 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
116 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
117 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
118 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
119 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
120 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
121 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
123 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
124 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
126 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
127 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
129 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
130 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
132 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN,
133 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
134 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN,
135 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
136 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN,
137 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
138 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN,
139 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
140 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN,
141 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
143 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN,
144 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
146 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN,
147 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
149 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN,
150 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
152 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
153 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
154 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
155 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
156 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
157 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
158 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
159 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
160 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
161 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
162 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
163 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
164 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
165 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
166 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
167 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
168 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
169 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
170 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
171 0, cpu_booke_setup },
172 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
173 0, cpu_booke_setup },
174 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
175 0, cpu_booke_setup },
176 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
177 0, cpu_booke_setup },
178 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
179 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
181 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL },
184 static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
185 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
187 static char model[64];
188 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
190 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
191 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD,
192 &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
194 /* Provide some user-friendly aliases for bits in cpu_features */
195 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
196 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
197 "Floating point instructions executed in hardware");
198 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
199 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
202 cpu_setup(u_int cpuid)
205 uint16_t vers, rev, revfmt;
207 const struct cputab *cp;
215 min = (pvr >> 0) & 0xff;
216 maj = min <= 4 ? 1 : 2;
222 maj = (pvr >> 4) & 0xf;
223 min = (pvr >> 0) & 0xf;
226 maj = (pvr >> 8) & 0xf;
227 min = (pvr >> 0) & 0xf;
230 for (cp = models; cp->version != 0; cp++) {
231 if (cp->version == vers)
237 if (rev == MPC750 && pvr == 15) {
238 name = "Motorola MPC755";
241 strncpy(model, name, sizeof(model) - 1);
243 printf("cpu%d: %s revision ", cpuid, name);
247 printf("%u.%u", maj, min);
250 printf("0x%04x", rev);
257 if (cpu_est_clockrate(0, &cps) == 0)
258 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
261 cpu_features |= cp->features;
262 printf("cpu%d: Features %b\n", cpuid, cpu_features,
263 PPC_FEATURE_BITMASK);
268 if (cp->cpu_setup != NULL)
269 cp->cpu_setup(cpuid, vers);
272 /* Get current clock frequency for the given cpu id. */
274 cpu_est_clockrate(int cpu_id, uint64_t *cps)
278 phandle_t cpu, dev, root;
282 vers = mfpvr() >> 16;
284 mtmsr(msr & ~PSL_EE);
296 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
298 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
300 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
301 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
309 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
311 mtspr(SPR_970MMCR1, 0);
312 mtspr(SPR_970MMCRA, 0);
313 mtspr(SPR_970PMC1, 0);
315 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
319 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
320 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
330 dev = OF_child(root);
332 res = OF_getprop(dev, "name", buf, sizeof(buf));
333 if (res > 0 && strcmp(buf, "cpus") == 0)
339 res = OF_getprop(cpu, "device_type", buf,
341 if (res > 0 && strcmp(buf, "cpu") == 0)
347 if (OF_getprop(cpu, "ibm,extended-clock-frequency",
348 cps, sizeof(*cps)) >= 0) {
350 } else if (OF_getprop(cpu, "clock-frequency", cps,
351 sizeof(cell_t)) >= 0) {
361 cpu_6xx_setup(int cpuid, uint16_t vers)
363 register_t hid0, pvr;
366 hid0 = mfspr(SPR_HID0);
370 * Configure power-saving mode.
383 /* Select DOZE mode. */
384 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
385 hid0 |= HID0_DOZE | HID0_DPM;
386 powerpc_pow_enabled = 1;
394 /* Enable the 7450 branch caches */
395 hid0 |= HID0_SGE | HID0_BTIC;
396 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
397 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
398 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
399 || (pvr >> 16) == MPC7457)
401 /* Select NAP mode. */
402 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
403 hid0 |= HID0_NAP | HID0_DPM;
404 powerpc_pow_enabled = 1;
408 /* No power-saving mode is available. */ ;
414 hid0 &= ~HID0_DBP; /* XXX correct? */
415 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
421 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
427 mtspr(SPR_HID0, hid0);
430 cpu_6xx_print_cacheinfo(cpuid, vers);
438 bitmask = HID0_7450_BITMASK;
441 bitmask = HID0_BITMASK;
445 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
447 if (cpu_idle_hook == NULL)
448 cpu_idle_hook = cpu_idle_60x;
453 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
457 hid = mfspr(SPR_HID0);
458 printf("cpu%u: ", cpuid);
459 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
460 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
462 printf("cpu%u: ", cpuid);
463 if (mfspr(SPR_L2CR) & L2CR_L2E) {
468 printf("256KB L2 cache, ");
469 if (mfspr(SPR_L3CR) & L3CR_L3E)
470 printf("%cMB L3 backside cache",
471 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
473 printf("L3 cache disabled");
477 printf("512KB L2 cache\n");
480 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
491 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
492 ? "through" : "back");
493 if (mfspr(SPR_L2CR) & L2CR_L2PE)
494 printf(", with parity");
495 printf(" backside cache\n");
499 printf("L2 cache disabled\n");
503 cpu_booke_setup(int cpuid, uint16_t vers)
508 hid0 = mfspr(SPR_HID0);
510 /* Programe power-management mode. */
511 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
514 mtspr(SPR_HID0, hid0);
516 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
519 if (cpu_idle_hook == NULL)
520 cpu_idle_hook = cpu_idle_booke;
524 cpu_970_setup(int cpuid, uint16_t vers)
527 uint32_t hid0_hi, hid0_lo;
529 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
530 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
532 /* Configure power-saving mode */
535 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
536 hid0_hi &= ~HID0_DOZE;
539 hid0_hi |= (HID0_NAP | HID0_DPM);
540 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
543 powerpc_pow_enabled = 1;
545 __asm __volatile (" \
547 sldi %0,%0,32; or %0,%0,%1; \
549 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
550 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
552 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
554 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
555 : "=r" (hid0_hi) : "K" (SPR_HID0));
556 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
559 cpu_idle_hook = cpu_idle_60x;
563 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
567 result = (cpu_features & arg2) ? 1 : 0;
569 return (sysctl_handle_int(oidp, &result, 0, req));
578 if ((mfmsr() & PSL_EE) != PSL_EE) {
579 struct thread *td = curthread;
580 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
581 panic("ints disabled in idleproc!");
585 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
588 if (cpu_idle_hook != NULL) {
591 sbt = cpu_idleclock();
600 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
605 cpu_idle_wakeup(int cpu)
611 cpu_idle_60x(sbintime_t sbt)
616 if (!powerpc_pow_enabled)
620 vers = mfpvr() >> 16;
633 dssall; sync; mtmsr %0; isync"
634 :: "r"(msr | PSL_POW));
638 mtmsr(msr | PSL_POW);
646 cpu_idle_booke(sbintime_t sbt)
653 /* Freescale E500 core RM section 6.4.1. */
654 __asm __volatile("msync; mtmsr %0; isync" ::