2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from BSDI: locore.s,v 1.36.2.15 1999/08/23 22:34:41 cp Exp
31 * Copyright (c) 2002 Jake Burkholder.
32 * Copyright (c) 2007 - 2010 Marius Strobl <marius@FreeBSD.org>
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/kernel.h>
66 #include <sys/mutex.h>
69 #include <sys/sched.h>
73 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_extern.h>
77 #include <vm/vm_map.h>
79 #include <dev/ofw/openfirm.h>
81 #include <machine/asi.h>
82 #include <machine/atomic.h>
83 #include <machine/bus.h>
84 #include <machine/cpu.h>
85 #include <machine/cpufunc.h>
86 #include <machine/md_var.h>
87 #include <machine/metadata.h>
88 #include <machine/ofw_machdep.h>
89 #include <machine/pcb.h>
90 #include <machine/smp.h>
91 #include <machine/tick.h>
92 #include <machine/tlb.h>
93 #include <machine/tsb.h>
94 #include <machine/tte.h>
95 #include <machine/ver.h>
97 #define SUNW_STARTCPU "SUNW,start-cpu"
98 #define SUNW_STOPSELF "SUNW,stop-self"
100 static ih_func_t cpu_ipi_ast;
101 static ih_func_t cpu_ipi_hardclock;
102 static ih_func_t cpu_ipi_preempt;
103 static ih_func_t cpu_ipi_stop;
106 * Argument area used to pass data to non-boot processors as they start up.
107 * This must be statically initialized with a known invalid CPU module ID,
108 * since the other processors will use it before the boot CPU enters the
111 struct cpu_start_args cpu_start_args = { 0, -1, -1, 0, 0, 0 };
112 struct ipi_cache_args ipi_cache_args;
113 struct ipi_rd_args ipi_rd_args;
114 struct ipi_tlb_args ipi_tlb_args;
115 struct pcb stoppcbs[MAXCPU];
119 cpu_ipi_selected_t *cpu_ipi_selected;
120 cpu_ipi_single_t *cpu_ipi_single;
122 static vm_offset_t mp_tramp;
123 static u_int cpuid_to_mid[MAXCPU];
124 static volatile cpuset_t shutdown_cpus;
126 static void ap_count(phandle_t node, u_int mid, u_int cpu_impl);
127 static void ap_start(phandle_t node, u_int mid, u_int cpu_impl);
128 static void cpu_mp_unleash(void *v);
129 static void foreach_ap(phandle_t node, void (*func)(phandle_t node,
130 u_int mid, u_int cpu_impl));
131 static void sun4u_startcpu(phandle_t cpu, void *func, u_long arg);
133 static cpu_ipi_selected_t cheetah_ipi_selected;
134 static cpu_ipi_single_t cheetah_ipi_single;
135 static cpu_ipi_selected_t jalapeno_ipi_selected;
136 static cpu_ipi_single_t jalapeno_ipi_single;
137 static cpu_ipi_selected_t spitfire_ipi_selected;
138 static cpu_ipi_single_t spitfire_ipi_single;
140 SYSINIT(cpu_mp_unleash, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
148 mp_tramp = (vm_offset_t)OF_claim(NULL, PAGE_SIZE, PAGE_SIZE);
149 if (mp_tramp == (vm_offset_t)-1)
150 panic("%s", __func__);
151 bcopy(mp_tramp_code, (void *)mp_tramp, mp_tramp_code_len);
152 *(vm_offset_t *)(mp_tramp + mp_tramp_tlb_slots) = kernel_tlb_slots;
153 *(vm_offset_t *)(mp_tramp + mp_tramp_func) = (vm_offset_t)mp_startup;
154 tp = (struct tte *)(mp_tramp + mp_tramp_code_len);
155 for (i = 0; i < kernel_tlb_slots; i++) {
156 tp[i].tte_vpn = TV_VPN(kernel_tlbs[i].te_va, TS_4M);
157 tp[i].tte_data = TD_V | TD_4M | TD_PA(kernel_tlbs[i].te_pa) |
158 TD_L | TD_CP | TD_CV | TD_P | TD_W;
160 for (i = 0; i < PAGE_SIZE; i += sizeof(vm_offset_t))
165 foreach_ap(phandle_t node, void (*func)(phandle_t node, u_int mid,
168 char type[sizeof("cpu")];
173 /* There's no need to traverse the whole OFW tree twice. */
174 if (mp_maxid > 0 && mp_ncpus >= mp_maxid + 1)
177 for (; node != 0; node = OF_peer(node)) {
178 child = OF_child(node);
180 foreach_ap(child, func);
182 if (OF_getprop(node, "device_type", type,
185 if (strcmp(type, "cpu") != 0)
187 if (OF_getprop(node, "implementation#", &cpu_impl,
188 sizeof(cpu_impl)) <= 0)
189 panic("%s: couldn't determine CPU "
190 "implementation", __func__);
191 if (OF_getprop(node, cpu_cpuid_prop(cpu_impl), &cpuid,
193 panic("%s: couldn't determine CPU module ID",
195 if (cpuid == PCPU_GET(mid))
197 (*func)(node, cpuid, cpu_impl);
203 * Probe for other CPUs.
206 cpu_mp_setmaxid(void)
209 CPU_SETOF(curcpu, &all_cpus);
213 foreach_ap(OF_child(OF_peer(0)), ap_count);
217 ap_count(phandle_t node __unused, u_int mid __unused, u_int cpu_impl __unused)
227 return (mp_maxid > 0);
234 return (smp_topo_none());
238 sun4u_startcpu(phandle_t cpu, void *func, u_long arg)
248 (cell_t)SUNW_STARTCPU,
253 args.func = (cell_t)func;
254 args.arg = (cell_t)arg;
259 * Fire up any non-boot processors.
264 u_int cpu_impl, isjbus;
266 mtx_init(&ipi_mtx, "ipi", NULL, MTX_SPIN);
269 cpu_impl = PCPU_GET(impl);
270 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIi ||
271 cpu_impl == CPU_IMPL_ULTRASPARCIIIip) {
273 cpu_ipi_selected = jalapeno_ipi_selected;
274 cpu_ipi_single = jalapeno_ipi_single;
275 } else if (cpu_impl == CPU_IMPL_SPARC64V ||
276 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
277 cpu_ipi_selected = cheetah_ipi_selected;
278 cpu_ipi_single = cheetah_ipi_single;
280 cpu_ipi_selected = spitfire_ipi_selected;
281 cpu_ipi_single = spitfire_ipi_single;
284 intr_setup(PIL_AST, cpu_ipi_ast, -1, NULL, NULL);
285 intr_setup(PIL_RENDEZVOUS, (ih_func_t *)smp_rendezvous_action,
287 intr_setup(PIL_STOP, cpu_ipi_stop, -1, NULL, NULL);
288 intr_setup(PIL_PREEMPT, cpu_ipi_preempt, -1, NULL, NULL);
289 intr_setup(PIL_HARDCLOCK, cpu_ipi_hardclock, -1, NULL, NULL);
291 cpuid_to_mid[curcpu] = PCPU_GET(mid);
293 foreach_ap(OF_child(OF_peer(0)), ap_start);
294 KASSERT(!isjbus || mp_ncpus <= IDR_JALAPENO_MAX_BN_PAIRS,
295 ("%s: can only IPI a maximum of %d JBus-CPUs",
296 __func__, IDR_JALAPENO_MAX_BN_PAIRS));
300 ap_start(phandle_t node, u_int mid, u_int cpu_impl)
302 volatile struct cpu_start_args *csa;
309 if (mp_ncpus > MAXCPU)
312 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) <= 0)
313 panic("%s: couldn't determine CPU frequency", __func__);
314 if (clock != PCPU_GET(clock))
315 tick_et_use_stick = 1;
317 csa = &cpu_start_args;
319 sun4u_startcpu(node, (void *)mp_tramp, 0);
321 while (csa->csa_state != CPU_TICKSYNC)
324 csa->csa_tick = rd(tick);
325 if (cpu_impl == CPU_IMPL_SPARC64V ||
326 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
327 while (csa->csa_state != CPU_STICKSYNC)
330 csa->csa_stick = rdstick();
332 while (csa->csa_state != CPU_INIT)
334 csa->csa_tick = csa->csa_stick = 0;
338 cpuid_to_mid[cpuid] = mid;
339 cpu_identify(csa->csa_ver, clock, cpuid);
341 va = kmem_malloc(kernel_arena, PCPU_PAGES * PAGE_SIZE,
343 pc = (struct pcpu *)(va + (PCPU_PAGES * PAGE_SIZE)) - 1;
344 pcpu_init(pc, cpuid, sizeof(*pc));
345 dpcpu_init((void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
346 M_WAITOK | M_ZERO), cpuid);
348 pc->pc_clock = clock;
349 pc->pc_impl = cpu_impl;
355 CPU_SET(cpuid, &all_cpus);
360 cpu_mp_announce(void)
366 cpu_mp_unleash(void *v __unused)
368 volatile struct cpu_start_args *csa;
377 ctx_min = TLB_CTX_USER_MIN;
378 ctx_inc = (TLB_CTX_USER_MAX - 1) / mp_ncpus;
379 csa = &cpu_start_args;
380 csa->csa_count = mp_ncpus;
381 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
382 pc->pc_tlb_ctx = ctx_min;
383 pc->pc_tlb_ctx_min = ctx_min;
384 pc->pc_tlb_ctx_max = ctx_min + ctx_inc;
387 if (pc->pc_cpuid == curcpu)
389 KASSERT(pc->pc_idlethread != NULL,
390 ("%s: idlethread", __func__));
391 pc->pc_curthread = pc->pc_idlethread;
392 pc->pc_curpcb = pc->pc_curthread->td_pcb;
393 for (i = 0; i < PCPU_PAGES; i++) {
394 va = pc->pc_addr + i * PAGE_SIZE;
395 pa = pmap_kextract(va);
397 panic("%s: pmap_kextract", __func__);
398 csa->csa_ttes[i].tte_vpn = TV_VPN(va, TS_8K);
399 csa->csa_ttes[i].tte_data = TD_V | TD_8K | TD_PA(pa) |
400 TD_L | TD_CP | TD_CV | TD_P | TD_W;
403 csa->csa_pcpu = pc->pc_addr;
404 csa->csa_mid = pc->pc_mid;
406 while (csa->csa_state != CPU_BOOTSTRAP)
416 cpu_mp_bootstrap(struct pcpu *pc)
418 volatile struct cpu_start_args *csa;
420 csa = &cpu_start_args;
422 /* Do CPU-specific initialization. */
423 if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
424 cheetah_init(pc->pc_impl);
425 else if (pc->pc_impl == CPU_IMPL_SPARC64V)
426 zeus_init(pc->pc_impl);
429 * Enable the caches. Note that his may include applying workarounds.
431 cache_enable(pc->pc_impl);
434 * Clear (S)TICK timer(s) (including NPT) and ensure they are stopped.
436 tick_clear(pc->pc_impl);
437 tick_stop(pc->pc_impl);
439 /* Set the kernel context. */
442 /* Lock the kernel TSB in the TLB if necessary. */
443 if (tsb_kernel_ldd_phys == 0)
447 * Flush all non-locked TLB entries possibly left over by the
450 tlb_flush_nonlocked();
454 * Note that the PIL we be lowered indirectly via sched_throw(NULL)
455 * when fake spinlock held by the idle thread eventually is released.
457 wrpr(pstate, 0, PSTATE_KERNEL);
460 KASSERT(curthread != NULL, ("%s: curthread", __func__));
461 printf("SMP: AP CPU #%d Launched!\n", curcpu);
465 csa->csa_state = CPU_BOOTSTRAP;
466 while (csa->csa_count != 0)
469 if (smp_cpus == mp_ncpus)
470 atomic_store_rel_int(&smp_started, 1);
472 /* Start per-CPU event timers. */
475 /* Ok, now enter the scheduler. */
480 cpu_mp_shutdown(void)
486 shutdown_cpus = all_cpus;
487 CPU_CLR(PCPU_GET(cpuid), &shutdown_cpus);
488 cpus = shutdown_cpus;
490 /* XXX: Stop all the CPUs which aren't already. */
491 if (CPU_CMP(&stopped_cpus, &cpus)) {
493 /* cpus is just a flat "on" mask without curcpu. */
494 CPU_NAND(&cpus, &stopped_cpus);
498 while (!CPU_EMPTY(&shutdown_cpus)) {
500 printf("timeout shutting down CPUs.\n");
508 cpu_ipi_ast(struct trapframe *tf __unused)
514 cpu_ipi_stop(struct trapframe *tf __unused)
518 CTR2(KTR_SMP, "%s: stopped %d", __func__, curcpu);
520 savectx(&stoppcbs[curcpu]);
521 cpuid = PCPU_GET(cpuid);
522 CPU_SET_ATOMIC(cpuid, &stopped_cpus);
523 while (!CPU_ISSET(cpuid, &started_cpus)) {
524 if (CPU_ISSET(cpuid, &shutdown_cpus)) {
525 CPU_CLR_ATOMIC(cpuid, &shutdown_cpus);
526 (void)intr_disable();
531 CPU_CLR_ATOMIC(cpuid, &started_cpus);
532 CPU_CLR_ATOMIC(cpuid, &stopped_cpus);
534 CTR2(KTR_SMP, "%s: restarted %d", __func__, curcpu);
538 cpu_ipi_preempt(struct trapframe *tf __unused)
541 sched_preempt(curthread);
545 cpu_ipi_hardclock(struct trapframe *tf)
547 struct trapframe *oldframe;
552 td->td_intr_nesting_level++;
553 oldframe = td->td_intr_frame;
554 td->td_intr_frame = tf;
556 td->td_intr_frame = oldframe;
557 td->td_intr_nesting_level--;
562 spitfire_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
566 while ((cpu = CPU_FFS(&cpus)) != 0) {
569 spitfire_ipi_single(cpu, d0, d1, d2);
574 spitfire_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
581 mtx_assert(&ipi_mtx, MA_OWNED);
582 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
583 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) & IDR_BUSY) == 0,
584 ("%s: outstanding dispatch", __func__));
586 mid = cpuid_to_mid[cpu];
587 for (i = 0; i < IPI_RETRIES; i++) {
589 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
590 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
591 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
593 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
596 * Workaround for SpitFire erratum #54; do a dummy read
597 * from a SDB internal register before the MEMBAR #Sync
598 * for the write to ASI_SDB_INTR_W (requiring another
599 * MEMBAR #Sync in order to make sure the write has
600 * occurred before the load).
603 (void)ldxa(AA_SDB_CNTL_HIGH, ASI_SDB_CONTROL_R);
605 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
609 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
612 if (kdb_active != 0 || panicstr != NULL)
613 printf("%s: couldn't send IPI to module 0x%u\n",
616 panic("%s: couldn't send IPI to module 0x%u",
621 cheetah_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
628 mtx_assert(&ipi_mtx, MA_OWNED);
629 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
630 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
631 IDR_CHEETAH_ALL_BUSY) == 0,
632 ("%s: outstanding dispatch", __func__));
634 mid = cpuid_to_mid[cpu];
635 for (i = 0; i < IPI_RETRIES; i++) {
637 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
638 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
639 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
641 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
644 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
648 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
651 if (kdb_active != 0 || panicstr != NULL)
652 printf("%s: couldn't send IPI to module 0x%u\n",
655 panic("%s: couldn't send IPI to module 0x%u",
660 cheetah_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
662 char pbuf[CPUSETBUFSIZ];
669 mtx_assert(&ipi_mtx, MA_OWNED);
670 KASSERT(!CPU_EMPTY(&cpus), ("%s: no CPUs to IPI", __func__));
671 KASSERT(!CPU_ISSET(curcpu, &cpus), ("%s: CPU can't IPI itself",
673 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
674 IDR_CHEETAH_ALL_BUSY) == 0,
675 ("%s: outstanding dispatch", __func__));
678 for (i = 0; i < IPI_RETRIES * mp_ncpus; i++) {
680 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
681 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
682 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
685 for (cpu = 0; cpu < mp_ncpus; cpu++) {
686 if (CPU_ISSET(cpu, &cpus)) {
687 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
688 IDC_ITID_SHIFT) | bnp << IDC_BN_SHIFT,
692 if (bnp == IDR_CHEETAH_MAX_BN_PAIRS)
696 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
697 IDR_CHEETAH_ALL_BUSY) != 0)
701 for (cpu = 0; cpu < mp_ncpus; cpu++) {
702 if (CPU_ISSET(cpu, &cpus)) {
703 if ((ids & (IDR_NACK << (2 * bnp))) == 0)
708 if (CPU_EMPTY(&cpus))
711 if (kdb_active != 0 || panicstr != NULL)
712 printf("%s: couldn't send IPI (cpus=%s ids=0x%lu)\n",
713 __func__, cpusetobj_strprint(pbuf, &cpus), ids);
715 panic("%s: couldn't send IPI (cpus=%s ids=0x%lu)",
716 __func__, cpusetobj_strprint(pbuf, &cpus), ids);
720 jalapeno_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
724 u_int busy, busynack, mid;
727 mtx_assert(&ipi_mtx, MA_OWNED);
728 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
729 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
730 IDR_CHEETAH_ALL_BUSY) == 0,
731 ("%s: outstanding dispatch", __func__));
733 mid = cpuid_to_mid[cpu];
734 busy = IDR_BUSY << (2 * mid);
735 busynack = (IDR_BUSY | IDR_NACK) << (2 * mid);
736 for (i = 0; i < IPI_RETRIES; i++) {
738 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
739 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
740 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
742 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
745 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
749 if ((ids & busynack) == 0)
752 if (kdb_active != 0 || panicstr != NULL)
753 printf("%s: couldn't send IPI to module 0x%u\n",
756 panic("%s: couldn't send IPI to module 0x%u",
761 jalapeno_ipi_selected(cpuset_t cpus, u_long d0, u_long d1, u_long d2)
763 char pbuf[CPUSETBUFSIZ];
769 mtx_assert(&ipi_mtx, MA_OWNED);
770 KASSERT(!CPU_EMPTY(&cpus), ("%s: no CPUs to IPI", __func__));
771 KASSERT(!CPU_ISSET(curcpu, &cpus), ("%s: CPU can't IPI itself",
773 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
774 IDR_CHEETAH_ALL_BUSY) == 0,
775 ("%s: outstanding dispatch", __func__));
778 for (i = 0; i < IPI_RETRIES * mp_ncpus; i++) {
780 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
781 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
782 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
784 for (cpu = 0; cpu < mp_ncpus; cpu++) {
785 if (CPU_ISSET(cpu, &cpus)) {
786 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
787 IDC_ITID_SHIFT), ASI_SDB_INTR_W, 0);
791 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
792 IDR_CHEETAH_ALL_BUSY) != 0)
796 (IDR_CHEETAH_ALL_BUSY | IDR_CHEETAH_ALL_NACK)) == 0)
798 for (cpu = 0; cpu < mp_ncpus; cpu++)
799 if (CPU_ISSET(cpu, &cpus))
800 if ((ids & (IDR_NACK <<
801 (2 * cpuid_to_mid[cpu]))) == 0)
804 if (kdb_active != 0 || panicstr != NULL)
805 printf("%s: couldn't send IPI (cpus=%s ids=0x%lu)\n",
806 __func__, cpusetobj_strprint(pbuf, &cpus), ids);
808 panic("%s: couldn't send IPI (cpus=%s ids=0x%lu)",
809 __func__, cpusetobj_strprint(pbuf, &cpus), ids);