1 Pull in r211627 from upstream llvm trunk (by Bill Schmidt):
3 [PPC64] Fix PR20071 (fctiduz generated for targets lacking that
6 PR20071 identifies a problem in PowerPC's fast-isel implementation
7 for floating-point conversion to integer. The fctiduz instruction
8 was added in Power ISA 2.06 (i.e., Power7 and later). However, this
9 instruction is being generated regardless of which 64-bit PowerPC
12 The intent is for fast-isel to punt to DAG selection when this
13 instruction is not available. This patch implements that change.
14 For testing purposes, the existing fast-isel-conversion.ll test adds
15 a RUN line for -mcpu=970 and tests for the expected code generation.
16 Additionally, the existing test fast-isel-conversion-p5.ll was found
17 to be incorrectly expecting the unavailable instruction to be
18 generated. I've removed these test variants since we have adequate
19 coverage in fast-isel-conversion.ll.
21 This is needed to compile clang with debug+asserts on older powerpc64
24 Introduced here: http://svnweb.freebsd.org/changeset/base/267981
26 Index: lib/Target/PowerPC/PPCFastISel.cpp
27 ===================================================================
28 --- lib/Target/PowerPC/PPCFastISel.cpp (revision 106)
29 +++ lib/Target/PowerPC/PPCFastISel.cpp (revision 107)
30 @@ -1026,6 +1026,10 @@ bool PPCFastISel::SelectFPToI(const Instruction *I
31 if (DstVT != MVT::i32 && DstVT != MVT::i64)
34 + // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
35 + if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget.hasFPCVT())
38 Value *Src = I->getOperand(0);
39 Type *SrcTy = Src->getType();
40 if (!isTypeLegal(SrcTy, SrcVT))
41 Index: test/CodeGen/PowerPC/fast-isel-conversion-p5.ll
42 ===================================================================
43 --- test/CodeGen/PowerPC/fast-isel-conversion-p5.ll (revision 106)
44 +++ test/CodeGen/PowerPC/fast-isel-conversion-p5.ll (revision 107)
45 @@ -116,18 +116,6 @@ entry:
49 -define void @fptoui_float_i64(float %a) nounwind ssp {
51 -; ELF64: fptoui_float_i64
52 - %b.addr = alloca i64, align 4
53 - %conv = fptoui float %a to i64
57 - store i64 %conv, i64* %b.addr, align 4
61 define void @fptoui_double_i32(double %a) nounwind ssp {
63 ; ELF64: fptoui_double_i32
64 @@ -140,14 +128,3 @@ entry:
68 -define void @fptoui_double_i64(double %a) nounwind ssp {
70 -; ELF64: fptoui_double_i64
71 - %b.addr = alloca i64, align 8
72 - %conv = fptoui double %a to i64
76 - store i64 %conv, i64* %b.addr, align 8
79 Index: test/CodeGen/PowerPC/fast-isel-conversion.ll
80 ===================================================================
81 --- test/CodeGen/PowerPC/fast-isel-conversion.ll (revision 106)
82 +++ test/CodeGen/PowerPC/fast-isel-conversion.ll (revision 107)
84 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
85 +; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970
87 +;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
88 +;; to SelectionDAG in some cases.
92 define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
94 ; ELF64: sitofp_single_i64
95 +; PPC970: sitofp_single_i64
96 %b.addr = alloca float, align 4
97 %conv = sitofp i64 %a to float
105 store float %conv, float* %b.addr, align 4
108 @@ -17,11 +26,16 @@ entry:
109 define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
111 ; ELF64: sitofp_single_i32
112 +; PPC970: sitofp_single_i32
113 %b.addr = alloca float, align 4
114 %conv = sitofp i32 %a to float
122 store float %conv, float* %b.addr, align 4
125 @@ -29,6 +43,7 @@ entry:
126 define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
128 ; ELF64: sitofp_single_i16
129 +; PPC970: sitofp_single_i16
130 %b.addr = alloca float, align 4
131 %conv = sitofp i16 %a to float
133 @@ -35,6 +50,11 @@ entry:
142 store float %conv, float* %b.addr, align 4
145 @@ -42,6 +62,7 @@ entry:
146 define void @sitofp_single_i8(i8 %a) nounwind ssp {
148 ; ELF64: sitofp_single_i8
149 +; PPC970: sitofp_single_i8
150 %b.addr = alloca float, align 4
151 %conv = sitofp i8 %a to float
153 @@ -48,6 +69,11 @@ entry:
162 store float %conv, float* %b.addr, align 4
165 @@ -55,11 +81,15 @@ entry:
166 define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
168 ; ELF64: sitofp_double_i32
169 +; PPC970: sitofp_double_i32
170 %b.addr = alloca double, align 8
171 %conv = sitofp i32 %a to double
178 store double %conv, double* %b.addr, align 8
181 @@ -67,11 +97,15 @@ entry:
182 define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
184 ; ELF64: sitofp_double_i64
185 +; PPC970: sitofp_double_i64
186 %b.addr = alloca double, align 8
187 %conv = sitofp i64 %a to double
194 store double %conv, double* %b.addr, align 8
197 @@ -79,6 +113,7 @@ entry:
198 define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
200 ; ELF64: sitofp_double_i16
201 +; PPC970: sitofp_double_i16
202 %b.addr = alloca double, align 8
203 %conv = sitofp i16 %a to double
205 @@ -85,6 +120,10 @@ entry:
213 store double %conv, double* %b.addr, align 8
216 @@ -92,6 +131,7 @@ entry:
217 define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
219 ; ELF64: sitofp_double_i8
220 +; PPC970: sitofp_double_i8
221 %b.addr = alloca double, align 8
222 %conv = sitofp i8 %a to double
224 @@ -98,6 +138,10 @@ entry:
232 store double %conv, double* %b.addr, align 8
235 @@ -107,11 +151,13 @@ entry:
236 define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
238 ; ELF64: uitofp_single_i64
239 +; PPC970: uitofp_single_i64
240 %b.addr = alloca float, align 4
241 %conv = uitofp i64 %a to float
245 +; PPC970-NOT: fcfidus
246 store float %conv, float* %b.addr, align 4
249 @@ -119,11 +165,14 @@ entry:
250 define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
252 ; ELF64: uitofp_single_i32
253 +; PPC970: uitofp_single_i32
254 %b.addr = alloca float, align 4
255 %conv = uitofp i32 %a to float
259 +; PPC970-NOT: lfiwzx
260 +; PPC970-NOT: fcfidus
261 store float %conv, float* %b.addr, align 4
264 @@ -131,6 +180,7 @@ entry:
265 define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
267 ; ELF64: uitofp_single_i16
268 +; PPC970: uitofp_single_i16
269 %b.addr = alloca float, align 4
270 %conv = uitofp i16 %a to float
271 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
272 @@ -137,6 +187,11 @@ entry:
276 +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
281 store float %conv, float* %b.addr, align 4
284 @@ -144,6 +199,7 @@ entry:
285 define void @uitofp_single_i8(i8 %a) nounwind ssp {
287 ; ELF64: uitofp_single_i8
288 +; PPC970: uitofp_single_i8
289 %b.addr = alloca float, align 4
290 %conv = uitofp i8 %a to float
291 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
292 @@ -150,6 +206,11 @@ entry:
296 +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
301 store float %conv, float* %b.addr, align 4
304 @@ -157,11 +218,13 @@ entry:
305 define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
307 ; ELF64: uitofp_double_i64
308 +; PPC970: uitofp_double_i64
309 %b.addr = alloca double, align 8
310 %conv = uitofp i64 %a to double
314 +; PPC970-NOT: fcfidu
315 store double %conv, double* %b.addr, align 8
318 @@ -169,11 +232,14 @@ entry:
319 define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
321 ; ELF64: uitofp_double_i32
322 +; PPC970: uitofp_double_i32
323 %b.addr = alloca double, align 8
324 %conv = uitofp i32 %a to double
328 +; PPC970-NOT: lfiwzx
329 +; PPC970-NOT: fcfidu
330 store double %conv, double* %b.addr, align 8
333 @@ -181,6 +247,7 @@ entry:
334 define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
336 ; ELF64: uitofp_double_i16
337 +; PPC970: uitofp_double_i16
338 %b.addr = alloca double, align 8
339 %conv = uitofp i16 %a to double
340 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
341 @@ -187,6 +254,10 @@ entry:
345 +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
349 store double %conv, double* %b.addr, align 8
352 @@ -194,6 +265,7 @@ entry:
353 define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
355 ; ELF64: uitofp_double_i8
356 +; PPC970: uitofp_double_i8
357 %b.addr = alloca double, align 8
358 %conv = uitofp i8 %a to double
359 ; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
360 @@ -200,6 +272,10 @@ entry:
364 +; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
368 store double %conv, double* %b.addr, align 8
371 @@ -209,11 +285,15 @@ entry:
372 define void @fptosi_float_i32(float %a) nounwind ssp {
374 ; ELF64: fptosi_float_i32
375 +; PPC970: fptosi_float_i32
376 %b.addr = alloca i32, align 4
377 %conv = fptosi float %a to i32
384 store i32 %conv, i32* %b.addr, align 4
387 @@ -221,11 +301,15 @@ entry:
388 define void @fptosi_float_i64(float %a) nounwind ssp {
390 ; ELF64: fptosi_float_i64
391 +; PPC970: fptosi_float_i64
392 %b.addr = alloca i64, align 4
393 %conv = fptosi float %a to i64
400 store i64 %conv, i64* %b.addr, align 4
403 @@ -233,11 +317,15 @@ entry:
404 define void @fptosi_double_i32(double %a) nounwind ssp {
406 ; ELF64: fptosi_double_i32
407 +; PPC970: fptosi_double_i32
408 %b.addr = alloca i32, align 8
409 %conv = fptosi double %a to i32
416 store i32 %conv, i32* %b.addr, align 8
419 @@ -245,11 +333,15 @@ entry:
420 define void @fptosi_double_i64(double %a) nounwind ssp {
422 ; ELF64: fptosi_double_i64
423 +; PPC970: fptosi_double_i64
424 %b.addr = alloca i64, align 8
425 %conv = fptosi double %a to i64
432 store i64 %conv, i64* %b.addr, align 8
435 @@ -259,11 +351,15 @@ entry:
436 define void @fptoui_float_i32(float %a) nounwind ssp {
438 ; ELF64: fptoui_float_i32
439 +; PPC970: fptoui_float_i32
440 %b.addr = alloca i32, align 4
441 %conv = fptoui float %a to i32
448 store i32 %conv, i32* %b.addr, align 4
451 @@ -271,11 +367,13 @@ entry:
452 define void @fptoui_float_i64(float %a) nounwind ssp {
454 ; ELF64: fptoui_float_i64
455 +; PPC970: fptoui_float_i64
456 %b.addr = alloca i64, align 4
457 %conv = fptoui float %a to i64
461 +; PPC970-NOT: fctiduz
462 store i64 %conv, i64* %b.addr, align 4
465 @@ -283,11 +381,15 @@ entry:
466 define void @fptoui_double_i32(double %a) nounwind ssp {
468 ; ELF64: fptoui_double_i32
469 +; PPC970: fptoui_double_i32
470 %b.addr = alloca i32, align 8
471 %conv = fptoui double %a to i32
478 store i32 %conv, i32* %b.addr, align 8
481 @@ -295,11 +397,13 @@ entry:
482 define void @fptoui_double_i64(double %a) nounwind ssp {
484 ; ELF64: fptoui_double_i64
485 +; PPC970: fptoui_double_i64
486 %b.addr = alloca i64, align 8
487 %conv = fptoui double %a to i64
491 +; PPC970-NOT: fctiduz
492 store i64 %conv, i64* %b.addr, align 8