2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/cpuset.h>
43 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
51 #include <sys/sched.h>
53 #include <sys/sysctl.h>
56 #include <vm/vm_param.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
74 #define WARMBOOT_TARGET 0
75 #define WARMBOOT_OFF (KERNBASE + 0x0467)
76 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78 #define CMOS_REG (0x70)
79 #define CMOS_DATA (0x71)
80 #define BIOS_RESET (0x0f)
81 #define BIOS_WARM (0x0a)
83 /* lock region used by kernel profiling */
86 int mp_naps; /* # of Applications processors */
87 int boot_cpu_id = -1; /* designated BSP */
89 extern struct pcpu __pcpu[];
91 /* AP uses this during bootstrap. Do not staticize. */
95 /* Free these after use */
96 void *bootstacks[MAXCPU];
98 /* Temporary variables for init_secondary() */
99 char *doublefault_stack;
103 struct pcb stoppcbs[MAXCPU];
104 struct susppcb **susppcbs;
106 /* Variables needed for SMP tlb shootdown. */
107 vm_offset_t smp_tlb_addr2;
108 struct invpcid_descr smp_tlb_invpcid;
109 volatile int smp_tlb_wait;
112 extern int invpcid_works;
115 /* Interrupt counts. */
116 static u_long *ipi_preempt_counts[MAXCPU];
117 static u_long *ipi_ast_counts[MAXCPU];
118 u_long *ipi_invltlb_counts[MAXCPU];
119 u_long *ipi_invlrng_counts[MAXCPU];
120 u_long *ipi_invlpg_counts[MAXCPU];
121 u_long *ipi_invlcache_counts[MAXCPU];
122 u_long *ipi_rendezvous_counts[MAXCPU];
123 static u_long *ipi_hardclock_counts[MAXCPU];
126 /* Default cpu_ops implementation. */
127 struct cpu_ops cpu_ops = {
128 .ipi_vectored = lapic_ipi_vectored
131 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
133 extern int pmap_pcid_enabled;
136 * Local data and functions.
139 static volatile cpuset_t ipi_nmi_pending;
141 /* used to hold the AP's until we are ready to release them */
142 static struct mtx ap_boot_mtx;
144 /* Set to 1 once we're ready to let the APs out of the pen. */
145 static volatile int aps_ready = 0;
148 * Store data from cpu_add() until later in the boot when we actually setup
155 int cpu_hyperthread:1;
156 } static cpu_info[MAX_APIC_ID + 1];
157 int cpu_apic_ids[MAXCPU];
158 int apic_cpuids[MAX_APIC_ID + 1];
160 /* Holds pending bitmap based IPIs per CPU */
161 volatile u_int cpu_ipi_pending[MAXCPU];
163 static u_int boot_address;
164 static int cpu_logical; /* logical cpus per core */
165 static int cpu_cores; /* cores per package */
167 static void assign_cpu_ids(void);
168 static void set_interrupt_apic_ids(void);
169 static int start_all_aps(void);
170 static int start_ap(int apic_id);
171 static void release_aps(void *dummy);
173 static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */
174 static int hyperthreading_allowed = 1;
175 static u_int bootMP_size;
178 mem_range_AP_init(void)
180 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
181 mem_range_softc.mr_op->initAP(&mem_range_softc);
190 /* AMD processors do not support HTT. */
193 if ((amd_feature2 & AMDID2_CMP) == 0) {
198 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
199 AMDID_COREID_SIZE_SHIFT;
200 if (core_id_bits == 0) {
201 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
205 /* Fam 10h and newer should get here. */
206 for (id = 0; id <= MAX_APIC_ID; id++) {
207 /* Check logical CPU availability. */
208 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
210 /* Check if logical CPU has the same package ID. */
211 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
218 * Round up to the next power of two, if necessary, and then
220 * Returns -1 if argument is zero.
226 return (fls(x << (1 - powerof2(x))) - 1);
239 /* Both zero and one here mean one logical processor per package. */
240 max_logical = (cpu_feature & CPUID_HTT) != 0 ?
241 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
242 if (max_logical <= 1)
246 * Because of uniformity assumption we examine only
247 * those logical processors that belong to the same
248 * package as BSP. Further, we count number of
249 * logical processors that belong to the same core
250 * as BSP thus deducing number of threads per core.
252 if (cpu_high >= 0x4) {
253 cpuid_count(0x04, 0, p);
254 max_cores = ((p[0] >> 26) & 0x3f) + 1;
257 core_id_bits = mask_width(max_logical/max_cores);
258 if (core_id_bits < 0)
260 pkg_id_bits = core_id_bits + mask_width(max_cores);
262 for (id = 0; id <= MAX_APIC_ID; id++) {
263 /* Check logical CPU availability. */
264 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
266 /* Check if logical CPU has the same package ID. */
267 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
270 /* Check if logical CPU has the same package and core IDs. */
271 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
275 KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
276 ("topo_probe_0x4 couldn't find BSP"));
278 cpu_cores /= cpu_logical;
279 hyperthreading_cpus = cpu_logical;
293 /* We only support three levels for now. */
294 for (i = 0; i < 3; i++) {
295 cpuid_count(0x0b, i, p);
297 /* Fall back if CPU leaf 11 doesn't really exist. */
298 if (i == 0 && p[1] == 0) {
304 logical = p[1] &= 0xffff;
305 type = (p[2] >> 8) & 0xff;
306 if (type == 0 || logical == 0)
309 * Because of uniformity assumption we examine only
310 * those logical processors that belong to the same
313 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
314 if (!cpu_info[x].cpu_present ||
315 cpu_info[x].cpu_disabled)
317 if (x >> bits == boot_cpu_id >> bits)
320 if (type == CPUID_TYPE_SMT)
322 else if (type == CPUID_TYPE_CORE)
325 if (cpu_logical == 0)
327 cpu_cores /= cpu_logical;
331 * Both topology discovery code and code that consumes topology
332 * information assume top-down uniformity of the topology.
333 * That is, all physical packages must be identical and each
334 * core in a package must have the same number of threads.
335 * Topology information is queried only on BSP, on which this
336 * code runs and for which it can query CPUID information.
337 * Then topology is extrapolated on all packages using the
338 * uniformity assumption.
343 static int cpu_topo_probed = 0;
348 CPU_ZERO(&logical_cpus_mask);
350 cpu_cores = cpu_logical = 1;
351 else if (cpu_vendor_id == CPU_VENDOR_AMD)
353 else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
355 * See Intel(R) 64 Architecture Processor
356 * Topology Enumeration article for details.
358 * Note that 0x1 <= cpu_high < 4 case should be
359 * compatible with topo_probe_0x4() logic when
360 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
361 * or it should trigger the fallback otherwise.
365 else if (cpu_high >= 0x1)
370 * Fallback: assume each logical CPU is in separate
371 * physical package. That is, no multi-core, no SMT.
373 if (cpu_cores == 0 || cpu_logical == 0)
374 cpu_cores = cpu_logical = 1;
384 * Determine whether any threading flags are
388 if (cpu_logical > 1 && hyperthreading_cpus)
389 cg_flags = CG_FLAG_HTT;
390 else if (cpu_logical > 1)
391 cg_flags = CG_FLAG_SMT;
394 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
395 printf("WARNING: Non-uniform processors.\n");
396 printf("WARNING: Using suboptimal topology.\n");
397 return (smp_topo_none());
400 * No multi-core or hyper-threaded.
402 if (cpu_logical * cpu_cores == 1)
403 return (smp_topo_none());
405 * Only HTT no multi-core.
407 if (cpu_logical > 1 && cpu_cores == 1)
408 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
410 * Only multi-core no HTT.
412 if (cpu_cores > 1 && cpu_logical == 1)
413 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
415 * Both HTT and multi-core.
417 return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
418 CG_SHARE_L1, cpu_logical, cg_flags));
422 * Calculate usable address in base memory for AP trampoline code.
425 mp_bootaddress(u_int basemem)
428 bootMP_size = mptramp_end - mptramp_start;
429 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
430 if (((basemem * 1024) - boot_address) < bootMP_size)
431 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
432 /* 3 levels of page table pages */
433 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
435 return mptramp_pagetables;
439 cpu_add(u_int apic_id, char boot_cpu)
442 if (apic_id > MAX_APIC_ID) {
443 panic("SMP: APIC ID %d too high", apic_id);
446 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
448 cpu_info[apic_id].cpu_present = 1;
450 KASSERT(boot_cpu_id == -1,
451 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
453 boot_cpu_id = apic_id;
454 cpu_info[apic_id].cpu_bsp = 1;
456 if (mp_ncpus < MAXCPU) {
458 mp_maxid = mp_ncpus - 1;
461 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
466 cpu_mp_setmaxid(void)
470 * mp_maxid should be already set by calls to cpu_add().
471 * Just sanity check its value here.
474 KASSERT(mp_maxid == 0,
475 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
476 else if (mp_ncpus == 1)
479 KASSERT(mp_maxid >= mp_ncpus - 1,
480 ("%s: counters out of sync: max %d, count %d", __func__,
481 mp_maxid, mp_ncpus));
489 * Always record BSP in CPU map so that the mbuf init code works
492 CPU_SETOF(0, &all_cpus);
495 * No CPUs were found, so this must be a UP system. Setup
496 * the variables to represent a system with a single CPU
503 /* At least one CPU was found. */
506 * One CPU was found, so this must be a UP system with
513 /* At least two CPUs were found. */
518 * Initialize the IPI handlers and start up the AP's.
525 /* Initialize the logical ID to APIC ID table. */
526 for (i = 0; i < MAXCPU; i++) {
527 cpu_apic_ids[i] = -1;
528 cpu_ipi_pending[i] = 0;
531 /* Install an inter-CPU IPI for TLB invalidation */
532 if (pmap_pcid_enabled) {
533 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT,
535 setidt(IPI_INVLPG, IDTVEC(invlpg_pcid), SDT_SYSIGT,
538 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
539 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
541 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
543 /* Install an inter-CPU IPI for cache invalidation. */
544 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
546 /* Install an inter-CPU IPI for all-CPU rendezvous */
547 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
549 /* Install generic inter-CPU IPI handler */
550 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
551 SDT_SYSIGT, SEL_KPL, 0);
553 /* Install an inter-CPU IPI for CPU stop/restart */
554 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
556 /* Install an inter-CPU IPI for CPU suspend/resume */
557 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
559 /* Set boot_cpu_id if needed. */
560 if (boot_cpu_id == -1) {
561 boot_cpu_id = PCPU_GET(apic_id);
562 cpu_info[boot_cpu_id].cpu_bsp = 1;
564 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
565 ("BSP's APIC ID doesn't match boot_cpu_id"));
567 /* Probe logical/physical core configuration. */
572 /* Start each Application Processor */
575 set_interrupt_apic_ids();
580 * Print various information about the SMP system hardware and setup.
583 cpu_mp_announce(void)
585 const char *hyperthread;
588 printf("FreeBSD/SMP: %d package(s) x %d core(s)",
589 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
590 if (hyperthreading_cpus > 1)
591 printf(" x %d HTT threads", cpu_logical);
592 else if (cpu_logical > 1)
593 printf(" x %d SMT threads", cpu_logical);
596 /* List active CPUs first. */
597 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
598 for (i = 1; i < mp_ncpus; i++) {
599 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
603 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
607 /* List disabled CPUs last. */
608 for (i = 0; i <= MAX_APIC_ID; i++) {
609 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
611 if (cpu_info[i].cpu_hyperthread)
615 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
621 * AP CPU's call this to initialize themselves.
630 int cpu, gsel_tss, x;
631 struct region_descriptor ap_gdt;
633 /* Set by the startup code for us to use */
637 common_tss[cpu] = common_tss[0];
638 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
639 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
641 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
643 /* The NMI stack runs on IST2. */
644 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
645 common_tss[cpu].tss_ist2 = (long) np;
647 /* Prepare private GDT */
648 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
649 for (x = 0; x < NGDT; x++) {
650 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
651 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
652 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
654 ssdtosyssd(&gdt_segs[GPROC0_SEL],
655 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
656 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
657 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
658 lgdt(&ap_gdt); /* does magic intra-segment return */
660 /* Get per-cpu data */
663 /* prime data page for it to use */
664 pcpu_init(pc, cpu, sizeof(struct pcpu));
665 dpcpu_init(dpcpu, cpu);
666 pc->pc_apic_id = cpu_apic_ids[cpu];
667 pc->pc_prvspace = pc;
668 pc->pc_curthread = 0;
669 pc->pc_tssp = &common_tss[cpu];
670 pc->pc_commontssp = &common_tss[cpu];
672 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
674 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
675 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
676 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
679 /* Save the per-cpu pointer for use by the NMI handler. */
680 np->np_pcpu = (register_t) pc;
682 wrmsr(MSR_FSBASE, 0); /* User value */
683 wrmsr(MSR_GSBASE, (u_int64_t)pc);
684 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
689 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
693 * Set to a known state:
694 * Set by mpboot.s: CR0_PG, CR0_PE
695 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
698 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
701 /* Set up the fast syscall stuff */
702 msr = rdmsr(MSR_EFER) | EFER_SCE;
703 wrmsr(MSR_EFER, msr);
704 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
705 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
706 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
707 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
708 wrmsr(MSR_STAR, msr);
709 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
711 /* Disable local APIC just to be sure. */
714 /* signal our startup to the BSP. */
717 /* Spin until the BSP releases the AP's. */
721 /* Initialize the PAT MSR. */
724 /* set up CPU registers and state */
730 /* set up FPU state on the AP */
733 if (cpu_ops.cpu_init)
736 /* A quick check from sanity claus */
737 cpuid = PCPU_GET(cpuid);
738 if (PCPU_GET(apic_id) != lapic_id()) {
739 printf("SMP: cpuid = %d\n", cpuid);
740 printf("SMP: actual apic_id = %d\n", lapic_id());
741 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
742 panic("cpuid mismatch! boom!!");
745 /* Initialize curthread. */
746 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
747 PCPU_SET(curthread, PCPU_GET(idlethread));
751 mtx_lock_spin(&ap_boot_mtx);
753 /* Init local apic for irq's */
756 /* Set memory range attributes for this CPU to match the BSP */
761 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
762 printf("SMP: AP CPU #%d Launched!\n", cpuid);
764 /* Determine if we are a logical CPU. */
765 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
766 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
767 CPU_SET(cpuid, &logical_cpus_mask);
772 if (smp_cpus == mp_ncpus) {
773 /* enable IPI's, tlb shootdown, freezes etc */
774 atomic_store_rel_int(&smp_started, 1);
778 * Enable global pages TLB extension
779 * This also implicitly flushes the TLB
782 load_cr4(rcr4() | CR4_PGE);
783 if (pmap_pcid_enabled)
784 load_cr4(rcr4() | CR4_PCIDE);
788 mtx_unlock_spin(&ap_boot_mtx);
790 /* Wait until all the AP's are up. */
791 while (smp_started == 0)
794 /* Start per-CPU event timers. */
799 panic("scheduler returned us to %s", __func__);
803 /*******************************************************************
804 * local functions and data
808 * We tell the I/O APIC code about all the CPUs we want to receive
809 * interrupts. If we don't want certain CPUs to receive IRQs we
810 * can simply not tell the I/O APIC code about them in this function.
811 * We also do not tell it about the BSP since it tells itself about
812 * the BSP internally to work with UP kernels and on UP machines.
815 set_interrupt_apic_ids(void)
819 for (i = 0; i < MAXCPU; i++) {
820 apic_id = cpu_apic_ids[i];
823 if (cpu_info[apic_id].cpu_bsp)
825 if (cpu_info[apic_id].cpu_disabled)
828 /* Don't let hyperthreads service interrupts. */
829 if (hyperthreading_cpus > 1 &&
830 apic_id % hyperthreading_cpus != 0)
838 * Assign logical CPU IDs to local APICs.
845 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
846 &hyperthreading_allowed);
848 /* Check for explicitly disabled CPUs. */
849 for (i = 0; i <= MAX_APIC_ID; i++) {
850 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
853 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
854 cpu_info[i].cpu_hyperthread = 1;
857 * Don't use HT CPU if it has been disabled by a
860 if (hyperthreading_allowed == 0) {
861 cpu_info[i].cpu_disabled = 1;
866 /* Don't use this CPU if it has been disabled by a tunable. */
867 if (resource_disabled("lapic", i)) {
868 cpu_info[i].cpu_disabled = 1;
873 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
874 hyperthreading_cpus = 0;
879 * Assign CPU IDs to local APIC IDs and disable any CPUs
880 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
882 * To minimize confusion for userland, we attempt to number
883 * CPUs such that all threads and cores in a package are
884 * grouped together. For now we assume that the BSP is always
885 * the first thread in a package and just start adding APs
886 * starting with the BSP's APIC ID.
889 cpu_apic_ids[0] = boot_cpu_id;
890 apic_cpuids[boot_cpu_id] = 0;
891 for (i = boot_cpu_id + 1; i != boot_cpu_id;
892 i == MAX_APIC_ID ? i = 0 : i++) {
893 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
894 cpu_info[i].cpu_disabled)
897 if (mp_ncpus < MAXCPU) {
898 cpu_apic_ids[mp_ncpus] = i;
899 apic_cpuids[i] = mp_ncpus;
902 cpu_info[i].cpu_disabled = 1;
904 KASSERT(mp_maxid >= mp_ncpus - 1,
905 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
910 * start each AP in our list
915 vm_offset_t va = boot_address + KERNBASE;
916 u_int64_t *pt4, *pt3, *pt2;
917 u_int32_t mpbioswarmvec;
921 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
923 /* install the AP 1st level boot code */
924 pmap_kenter(va, boot_address);
925 pmap_invalidate_page(kernel_pmap, va);
926 bcopy(mptramp_start, (void *)va, bootMP_size);
928 /* Locate the page tables, they'll be below the trampoline */
929 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
930 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
931 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
933 /* Create the initial 1GB replicated page tables */
934 for (i = 0; i < 512; i++) {
935 /* Each slot of the level 4 pages points to the same level 3 page */
936 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
937 pt4[i] |= PG_V | PG_RW | PG_U;
939 /* Each slot of the level 3 pages points to the same level 2 page */
940 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
941 pt3[i] |= PG_V | PG_RW | PG_U;
943 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
944 pt2[i] = i * (2 * 1024 * 1024);
945 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
948 /* save the current value of the warm-start vector */
949 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
950 outb(CMOS_REG, BIOS_RESET);
951 mpbiosreason = inb(CMOS_DATA);
953 /* setup a vector to our boot code */
954 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
955 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
956 outb(CMOS_REG, BIOS_RESET);
957 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
960 for (cpu = 1; cpu < mp_ncpus; cpu++) {
961 apic_id = cpu_apic_ids[cpu];
963 /* allocate and set up an idle stack data page */
964 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
965 KSTACK_PAGES * PAGE_SIZE, M_WAITOK | M_ZERO);
966 doublefault_stack = (char *)kmem_malloc(kernel_arena,
967 PAGE_SIZE, M_WAITOK | M_ZERO);
968 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
970 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
973 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
976 /* attempt to start the Application Processor */
977 if (!start_ap(apic_id)) {
978 /* restore the warmstart vector */
979 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
980 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
983 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
986 /* restore the warmstart vector */
987 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
989 outb(CMOS_REG, BIOS_RESET);
990 outb(CMOS_DATA, mpbiosreason);
992 /* number of APs actually started */
998 * This function starts the AP (application processor) identified
999 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1000 * to accomplish this. This is necessary because of the nuances
1001 * of the different hardware we might encounter. It isn't pretty,
1002 * but it seems to work.
1005 start_ap(int apic_id)
1010 /* calculate the vector */
1011 vector = (boot_address >> 12) & 0xff;
1013 /* used as a watchpoint to signal AP startup */
1016 ipi_startup(apic_id, vector);
1018 /* Wait up to 5 seconds for it to start. */
1019 for (ms = 0; ms < 5000; ms++) {
1021 return 1; /* return SUCCESS */
1024 return 0; /* return FAILURE */
1027 #ifdef COUNT_XINVLTLB_HITS
1028 u_int xhits_gbl[MAXCPU];
1029 u_int xhits_pg[MAXCPU];
1030 u_int xhits_rng[MAXCPU];
1031 static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
1032 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1033 sizeof(xhits_gbl), "IU", "");
1034 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1035 sizeof(xhits_pg), "IU", "");
1036 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1037 sizeof(xhits_rng), "IU", "");
1042 u_int ipi_range_size;
1043 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1044 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1045 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1046 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW,
1047 &ipi_range_size, 0, "");
1049 u_int ipi_masked_global;
1050 u_int ipi_masked_page;
1051 u_int ipi_masked_range;
1052 u_int ipi_masked_range_size;
1053 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1054 &ipi_masked_global, 0, "");
1055 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1056 &ipi_masked_page, 0, "");
1057 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1058 &ipi_masked_range, 0, "");
1059 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1060 &ipi_masked_range_size, 0, "");
1061 #endif /* COUNT_XINVLTLB_HITS */
1064 * Init and startup IPI.
1067 ipi_startup(int apic_id, int vector)
1071 * This attempts to follow the algorithm described in the
1072 * Intel Multiprocessor Specification v1.4 in section B.4.
1073 * For each IPI, we allow the local APIC ~20us to deliver the
1074 * IPI. If that times out, we panic.
1078 * first we do an INIT IPI: this INIT IPI might be run, resetting
1079 * and running the target CPU. OR this INIT IPI might be latched (P5
1080 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1083 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1084 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
1085 lapic_ipi_wait(100);
1087 /* Explicitly deassert the INIT IPI. */
1088 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL |
1089 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT,
1092 DELAY(10000); /* wait ~10mS */
1095 * next we do a STARTUP IPI: the previous INIT IPI might still be
1096 * latched, (P5 bug) this 1st STARTUP would then terminate
1097 * immediately, and the previously started INIT IPI would continue. OR
1098 * the previous INIT IPI has already run. and this STARTUP IPI will
1099 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1102 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1103 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1105 if (!lapic_ipi_wait(100))
1106 panic("Failed to deliver first STARTUP IPI to APIC %d",
1108 DELAY(200); /* wait ~200uS */
1111 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1112 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1113 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1114 * recognized after hardware RESET or INIT IPI.
1116 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
1117 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
1119 if (!lapic_ipi_wait(100))
1120 panic("Failed to deliver second STARTUP IPI to APIC %d",
1123 DELAY(200); /* wait ~200uS */
1127 * Send an IPI to specified CPU handling the bitmap logic.
1130 ipi_send_cpu(int cpu, u_int ipi)
1132 u_int bitmap, old_pending, new_pending;
1134 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
1136 if (IPI_IS_BITMAPED(ipi)) {
1138 ipi = IPI_BITMAP_VECTOR;
1140 old_pending = cpu_ipi_pending[cpu];
1141 new_pending = old_pending | bitmap;
1142 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
1143 old_pending, new_pending));
1147 cpu_ops.ipi_vectored(ipi, cpu_apic_ids[cpu]);
1151 * Flush the TLB on all other CPU's
1154 smp_tlb_shootdown(u_int vector, pmap_t pmap, vm_offset_t addr1,
1159 ncpu = mp_ncpus - 1; /* does not shootdown self */
1161 return; /* no other cpus */
1162 if (!(read_rflags() & PSL_I))
1163 panic("%s: interrupts disabled", __func__);
1164 mtx_lock_spin(&smp_ipi_mtx);
1165 smp_tlb_invpcid.addr = addr1;
1167 smp_tlb_invpcid.pcid = 0;
1169 smp_tlb_invpcid.pcid = pmap->pm_pcid;
1170 pcid_cr3 = pmap->pm_cr3;
1172 smp_tlb_addr2 = addr2;
1173 smp_tlb_pmap = pmap;
1174 atomic_store_rel_int(&smp_tlb_wait, 0);
1175 ipi_all_but_self(vector);
1176 while (smp_tlb_wait < ncpu)
1178 mtx_unlock_spin(&smp_ipi_mtx);
1182 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
1183 vm_offset_t addr1, vm_offset_t addr2)
1185 int cpu, ncpu, othercpus;
1187 othercpus = mp_ncpus - 1;
1188 if (CPU_ISFULLSET(&mask)) {
1192 CPU_CLR(PCPU_GET(cpuid), &mask);
1193 if (CPU_EMPTY(&mask))
1196 if (!(read_rflags() & PSL_I))
1197 panic("%s: interrupts disabled", __func__);
1198 mtx_lock_spin(&smp_ipi_mtx);
1199 smp_tlb_invpcid.addr = addr1;
1201 smp_tlb_invpcid.pcid = 0;
1203 smp_tlb_invpcid.pcid = pmap->pm_pcid;
1204 pcid_cr3 = pmap->pm_cr3;
1206 smp_tlb_addr2 = addr2;
1207 smp_tlb_pmap = pmap;
1208 atomic_store_rel_int(&smp_tlb_wait, 0);
1209 if (CPU_ISFULLSET(&mask)) {
1211 ipi_all_but_self(vector);
1214 while ((cpu = CPU_FFS(&mask)) != 0) {
1216 CPU_CLR(cpu, &mask);
1217 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
1219 ipi_send_cpu(cpu, vector);
1223 while (smp_tlb_wait < ncpu)
1225 mtx_unlock_spin(&smp_ipi_mtx);
1229 smp_cache_flush(void)
1233 smp_tlb_shootdown(IPI_INVLCACHE, NULL, 0, 0);
1237 smp_invltlb(pmap_t pmap)
1241 smp_tlb_shootdown(IPI_INVLTLB, pmap, 0, 0);
1242 #ifdef COUNT_XINVLTLB_HITS
1249 smp_invlpg(pmap_t pmap, vm_offset_t addr)
1253 smp_tlb_shootdown(IPI_INVLPG, pmap, addr, 0);
1254 #ifdef COUNT_XINVLTLB_HITS
1261 smp_invlpg_range(pmap_t pmap, vm_offset_t addr1, vm_offset_t addr2)
1265 smp_tlb_shootdown(IPI_INVLRNG, pmap, addr1, addr2);
1266 #ifdef COUNT_XINVLTLB_HITS
1268 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1274 smp_masked_invltlb(cpuset_t mask, pmap_t pmap)
1278 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, pmap, 0, 0);
1279 #ifdef COUNT_XINVLTLB_HITS
1280 ipi_masked_global++;
1286 smp_masked_invlpg(cpuset_t mask, pmap_t pmap, vm_offset_t addr)
1290 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, pmap, addr, 0);
1291 #ifdef COUNT_XINVLTLB_HITS
1298 smp_masked_invlpg_range(cpuset_t mask, pmap_t pmap, vm_offset_t addr1,
1303 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, pmap, addr1,
1305 #ifdef COUNT_XINVLTLB_HITS
1307 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1313 ipi_bitmap_handler(struct trapframe frame)
1315 struct trapframe *oldframe;
1317 int cpu = PCPU_GET(cpuid);
1322 td->td_intr_nesting_level++;
1323 oldframe = td->td_intr_frame;
1324 td->td_intr_frame = &frame;
1325 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1326 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1328 (*ipi_preempt_counts[cpu])++;
1332 if (ipi_bitmap & (1 << IPI_AST)) {
1334 (*ipi_ast_counts[cpu])++;
1336 /* Nothing to do for AST */
1338 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
1340 (*ipi_hardclock_counts[cpu])++;
1344 td->td_intr_frame = oldframe;
1345 td->td_intr_nesting_level--;
1350 * send an IPI to a set of cpus.
1353 ipi_selected(cpuset_t cpus, u_int ipi)
1358 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1359 * of help in order to understand what is the source.
1360 * Set the mask of receiving CPUs for this purpose.
1362 if (ipi == IPI_STOP_HARD)
1363 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
1365 while ((cpu = CPU_FFS(&cpus)) != 0) {
1367 CPU_CLR(cpu, &cpus);
1368 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1369 ipi_send_cpu(cpu, ipi);
1374 * send an IPI to a specific CPU.
1377 ipi_cpu(int cpu, u_int ipi)
1381 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1382 * of help in order to understand what is the source.
1383 * Set the mask of receiving CPUs for this purpose.
1385 if (ipi == IPI_STOP_HARD)
1386 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
1388 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
1389 ipi_send_cpu(cpu, ipi);
1393 * send an IPI to all CPUs EXCEPT myself
1396 ipi_all_but_self(u_int ipi)
1398 cpuset_t other_cpus;
1400 other_cpus = all_cpus;
1401 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
1403 if (IPI_IS_BITMAPED(ipi)) {
1404 ipi_selected(other_cpus, ipi);
1409 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
1410 * of help in order to understand what is the source.
1411 * Set the mask of receiving CPUs for this purpose.
1413 if (ipi == IPI_STOP_HARD)
1414 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
1416 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1417 cpu_ops.ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1426 * As long as there is not a simple way to know about a NMI's
1427 * source, if the bitmask for the current CPU is present in
1428 * the global pending bitword an IPI_STOP_HARD has been issued
1429 * and should be handled.
1431 cpuid = PCPU_GET(cpuid);
1432 if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
1435 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
1441 * Handle an IPI_STOP by saving our current context and spinning until we
1445 cpustop_handler(void)
1449 cpu = PCPU_GET(cpuid);
1451 savectx(&stoppcbs[cpu]);
1453 /* Indicate that we are stopped */
1454 CPU_SET_ATOMIC(cpu, &stopped_cpus);
1456 /* Wait for restart */
1457 while (!CPU_ISSET(cpu, &started_cpus))
1460 CPU_CLR_ATOMIC(cpu, &started_cpus);
1461 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
1464 amd64_db_resume_dbreg();
1467 if (cpu == 0 && cpustop_restartfunc != NULL) {
1468 cpustop_restartfunc();
1469 cpustop_restartfunc = NULL;
1474 * Handle an IPI_SUSPEND by saving our current context and spinning until we
1478 cpususpend_handler(void)
1482 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED);
1484 cpu = PCPU_GET(cpuid);
1485 if (savectx(&susppcbs[cpu]->sp_pcb)) {
1486 fpususpend(susppcbs[cpu]->sp_fpususpend);
1488 CPU_SET_ATOMIC(cpu, &suspended_cpus);
1490 fpuresume(susppcbs[cpu]->sp_fpususpend);
1493 PCPU_SET(switchtime, 0);
1494 PCPU_SET(switchticks, ticks);
1496 /* Indicate that we are resumed */
1497 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1500 /* Wait for resume */
1501 while (!CPU_ISSET(cpu, &started_cpus))
1504 if (cpu_ops.cpu_resume)
1505 cpu_ops.cpu_resume();
1509 /* Resume MCA and local APIC */
1513 CPU_CLR_ATOMIC(cpu, &started_cpus);
1514 /* Indicate that we are resumed */
1515 CPU_CLR_ATOMIC(cpu, &suspended_cpus);
1519 * Handlers for TLB related IPIs
1522 invltlb_handler(void)
1524 #ifdef COUNT_XINVLTLB_HITS
1525 xhits_gbl[PCPU_GET(cpuid)]++;
1526 #endif /* COUNT_XINVLTLB_HITS */
1528 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1529 #endif /* COUNT_IPIS */
1532 atomic_add_int(&smp_tlb_wait, 1);
1536 invltlb_pcid_handler(void)
1540 #ifdef COUNT_XINVLTLB_HITS
1541 xhits_gbl[PCPU_GET(cpuid)]++;
1542 #endif /* COUNT_XINVLTLB_HITS */
1544 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
1545 #endif /* COUNT_IPIS */
1547 if (smp_tlb_invpcid.pcid != (uint64_t)-1 &&
1548 smp_tlb_invpcid.pcid != 0) {
1549 if (invpcid_works) {
1550 invpcid(&smp_tlb_invpcid, INVPCID_CTX);
1552 /* Otherwise reload %cr3 twice. */
1554 if (cr3 != pcid_cr3) {
1556 cr3 |= CR3_PCID_SAVE;
1563 if (smp_tlb_pmap != NULL) {
1564 cpuid = PCPU_GET(cpuid);
1565 if (!CPU_ISSET(cpuid, &smp_tlb_pmap->pm_active))
1566 CPU_CLR_ATOMIC(cpuid, &smp_tlb_pmap->pm_save);
1569 atomic_add_int(&smp_tlb_wait, 1);
1573 invlpg_handler(void)
1575 #ifdef COUNT_XINVLTLB_HITS
1576 xhits_pg[PCPU_GET(cpuid)]++;
1577 #endif /* COUNT_XINVLTLB_HITS */
1579 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1580 #endif /* COUNT_IPIS */
1582 invlpg(smp_tlb_invpcid.addr);
1583 atomic_add_int(&smp_tlb_wait, 1);
1587 invlpg_pcid_handler(void)
1590 #ifdef COUNT_XINVLTLB_HITS
1591 xhits_pg[PCPU_GET(cpuid)]++;
1592 #endif /* COUNT_XINVLTLB_HITS */
1594 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
1595 #endif /* COUNT_IPIS */
1597 if (smp_tlb_invpcid.pcid == (uint64_t)-1) {
1599 } else if (smp_tlb_invpcid.pcid == 0) {
1600 invlpg(smp_tlb_invpcid.addr);
1601 } else if (invpcid_works) {
1602 invpcid(&smp_tlb_invpcid, INVPCID_ADDR);
1605 * PCID supported, but INVPCID is not.
1606 * Temporarily switch to the target address
1607 * space and do INVLPG.
1610 if (cr3 != pcid_cr3)
1611 load_cr3(pcid_cr3 | CR3_PCID_SAVE);
1612 invlpg(smp_tlb_invpcid.addr);
1613 load_cr3(cr3 | CR3_PCID_SAVE);
1616 atomic_add_int(&smp_tlb_wait, 1);
1620 invlpg_range(vm_offset_t start, vm_offset_t end)
1626 } while (start < end);
1630 invlrng_handler(void)
1632 struct invpcid_descr d;
1636 #ifdef COUNT_XINVLTLB_HITS
1637 xhits_rng[PCPU_GET(cpuid)]++;
1638 #endif /* COUNT_XINVLTLB_HITS */
1640 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
1641 #endif /* COUNT_IPIS */
1643 addr = smp_tlb_invpcid.addr;
1644 if (pmap_pcid_enabled) {
1645 if (smp_tlb_invpcid.pcid == 0) {
1647 * kernel pmap - use invlpg to invalidate
1650 invlpg_range(addr, smp_tlb_addr2);
1651 } else if (smp_tlb_invpcid.pcid == (uint64_t)-1) {
1653 if (smp_tlb_pmap != NULL) {
1654 cpuid = PCPU_GET(cpuid);
1655 if (!CPU_ISSET(cpuid, &smp_tlb_pmap->pm_active))
1656 CPU_CLR_ATOMIC(cpuid,
1657 &smp_tlb_pmap->pm_save);
1659 } else if (invpcid_works) {
1660 d = smp_tlb_invpcid;
1662 invpcid(&d, INVPCID_ADDR);
1663 d.addr += PAGE_SIZE;
1664 } while (d.addr <= smp_tlb_addr2);
1667 if (cr3 != pcid_cr3)
1668 load_cr3(pcid_cr3 | CR3_PCID_SAVE);
1669 invlpg_range(addr, smp_tlb_addr2);
1670 load_cr3(cr3 | CR3_PCID_SAVE);
1673 invlpg_range(addr, smp_tlb_addr2);
1676 atomic_add_int(&smp_tlb_wait, 1);
1680 invlcache_handler(void)
1683 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++;
1684 #endif /* COUNT_IPIS */
1687 atomic_add_int(&smp_tlb_wait, 1);
1691 * This is called once the rest of the system is up and running and we're
1692 * ready to let the AP's out of the pen.
1695 release_aps(void *dummy __unused)
1700 atomic_store_rel_int(&aps_ready, 1);
1701 while (smp_started == 0)
1704 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1708 * Setup interrupt counters for IPI handlers.
1711 mp_ipi_intrcnt(void *dummy)
1717 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
1718 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1719 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
1720 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1721 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
1722 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1723 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
1724 intrcnt_add(buf, &ipi_invlcache_counts[i]);
1725 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
1726 intrcnt_add(buf, &ipi_preempt_counts[i]);
1727 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
1728 intrcnt_add(buf, &ipi_ast_counts[i]);
1729 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
1730 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1731 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
1732 intrcnt_add(buf, &ipi_hardclock_counts[i]);
1735 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);