2 * Copyright (c) 2011 NetApp, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 void vmmdev_init(void);
34 int vmmdev_cleanup(void);
39 int segid; /* memory segment */
40 vm_ooffset_t segoff; /* offset into memory segment */
41 size_t len; /* mmap length */
45 #define VM_MEMMAP_F_WIRED 0x01
46 #define VM_MEMMAP_F_IOMMU 0x02
48 #define VM_MEMSEG_NAME(m) ((m)->name[0] != '\0' ? (m)->name : NULL)
52 char name[SPECNAMELEN + 1];
57 int regnum; /* enum vm_reg_name */
61 struct vm_seg_desc { /* data or code segment */
63 int regnum; /* enum vm_reg_name */
69 struct vm_exit vm_exit;
77 int restart_instruction;
90 struct vm_ioapic_irq {
99 struct vm_isa_irq_trigger {
101 enum vm_intr_trigger trigger;
104 struct vm_capability {
106 enum vm_cap_type captype;
117 struct vm_pptdev_mmio {
126 struct vm_pptdev_msi {
131 int numvec; /* 0 means disabled */
136 struct vm_pptdev_msix {
143 uint32_t vector_control;
151 #define MAX_VM_STATS 64
154 int num_entries; /* out */
156 uint64_t statbuf[MAX_VM_STATS];
159 struct vm_stat_desc {
161 char desc[128]; /* out */
166 enum x2apic_state state;
170 uint64_t gpa; /* in */
171 uint64_t pte[4]; /* out */
176 uint32_t capabilities; /* lower 32 bits of HPET capabilities */
180 enum vm_suspend_how how;
184 int vcpuid; /* inputs */
185 int prot; /* PROT_READ or PROT_WRITE */
187 struct vm_guest_paging paging;
188 int fault; /* outputs */
192 struct vm_activate_cpu {
201 #define VM_ACTIVE_CPUS 0
202 #define VM_SUSPENDED_CPUS 1
220 /* general routines */
223 IOCNUM_SET_CAPABILITY = 2,
224 IOCNUM_GET_CAPABILITY = 3,
229 IOCNUM_MAP_MEMORY = 10, /* deprecated */
230 IOCNUM_GET_MEMORY_SEG = 11, /* deprecated */
231 IOCNUM_GET_GPA_PMAP = 12,
233 IOCNUM_ALLOC_MEMSEG = 14,
234 IOCNUM_GET_MEMSEG = 15,
235 IOCNUM_MMAP_MEMSEG = 16,
236 IOCNUM_MMAP_GETNEXT = 17,
238 /* register/state accessors */
239 IOCNUM_SET_REGISTER = 20,
240 IOCNUM_GET_REGISTER = 21,
241 IOCNUM_SET_SEGMENT_DESCRIPTOR = 22,
242 IOCNUM_GET_SEGMENT_DESCRIPTOR = 23,
244 /* interrupt injection */
245 IOCNUM_GET_INTINFO = 28,
246 IOCNUM_SET_INTINFO = 29,
247 IOCNUM_INJECT_EXCEPTION = 30,
248 IOCNUM_LAPIC_IRQ = 31,
249 IOCNUM_INJECT_NMI = 32,
250 IOCNUM_IOAPIC_ASSERT_IRQ = 33,
251 IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
252 IOCNUM_IOAPIC_PULSE_IRQ = 35,
253 IOCNUM_LAPIC_MSI = 36,
254 IOCNUM_LAPIC_LOCAL_IRQ = 37,
255 IOCNUM_IOAPIC_PINCOUNT = 38,
256 IOCNUM_RESTART_INSTRUCTION = 39,
259 IOCNUM_BIND_PPTDEV = 40,
260 IOCNUM_UNBIND_PPTDEV = 41,
261 IOCNUM_MAP_PPTDEV_MMIO = 42,
262 IOCNUM_PPTDEV_MSI = 43,
263 IOCNUM_PPTDEV_MSIX = 44,
266 IOCNUM_VM_STATS = 50,
267 IOCNUM_VM_STAT_DESC = 51,
269 /* kernel device state */
270 IOCNUM_SET_X2APIC_STATE = 60,
271 IOCNUM_GET_X2APIC_STATE = 61,
272 IOCNUM_GET_HPET_CAPABILITIES = 62,
274 /* legacy interrupt injection */
275 IOCNUM_ISA_ASSERT_IRQ = 80,
276 IOCNUM_ISA_DEASSERT_IRQ = 81,
277 IOCNUM_ISA_PULSE_IRQ = 82,
278 IOCNUM_ISA_SET_IRQ_TRIGGER = 83,
281 IOCNUM_ACTIVATE_CPU = 90,
282 IOCNUM_GET_CPUSET = 91,
285 IOCNUM_RTC_READ = 100,
286 IOCNUM_RTC_WRITE = 101,
287 IOCNUM_RTC_SETTIME = 102,
288 IOCNUM_RTC_GETTIME = 103,
292 _IOWR('v', IOCNUM_RUN, struct vm_run)
294 _IOW('v', IOCNUM_SUSPEND, struct vm_suspend)
296 _IO('v', IOCNUM_REINIT)
297 #define VM_ALLOC_MEMSEG \
298 _IOW('v', IOCNUM_ALLOC_MEMSEG, struct vm_memseg)
299 #define VM_GET_MEMSEG \
300 _IOWR('v', IOCNUM_GET_MEMSEG, struct vm_memseg)
301 #define VM_MMAP_MEMSEG \
302 _IOW('v', IOCNUM_MMAP_MEMSEG, struct vm_memmap)
303 #define VM_MMAP_GETNEXT \
304 _IOWR('v', IOCNUM_MMAP_GETNEXT, struct vm_memmap)
305 #define VM_SET_REGISTER \
306 _IOW('v', IOCNUM_SET_REGISTER, struct vm_register)
307 #define VM_GET_REGISTER \
308 _IOWR('v', IOCNUM_GET_REGISTER, struct vm_register)
309 #define VM_SET_SEGMENT_DESCRIPTOR \
310 _IOW('v', IOCNUM_SET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
311 #define VM_GET_SEGMENT_DESCRIPTOR \
312 _IOWR('v', IOCNUM_GET_SEGMENT_DESCRIPTOR, struct vm_seg_desc)
313 #define VM_INJECT_EXCEPTION \
314 _IOW('v', IOCNUM_INJECT_EXCEPTION, struct vm_exception)
315 #define VM_LAPIC_IRQ \
316 _IOW('v', IOCNUM_LAPIC_IRQ, struct vm_lapic_irq)
317 #define VM_LAPIC_LOCAL_IRQ \
318 _IOW('v', IOCNUM_LAPIC_LOCAL_IRQ, struct vm_lapic_irq)
319 #define VM_LAPIC_MSI \
320 _IOW('v', IOCNUM_LAPIC_MSI, struct vm_lapic_msi)
321 #define VM_IOAPIC_ASSERT_IRQ \
322 _IOW('v', IOCNUM_IOAPIC_ASSERT_IRQ, struct vm_ioapic_irq)
323 #define VM_IOAPIC_DEASSERT_IRQ \
324 _IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
325 #define VM_IOAPIC_PULSE_IRQ \
326 _IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
327 #define VM_IOAPIC_PINCOUNT \
328 _IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
329 #define VM_ISA_ASSERT_IRQ \
330 _IOW('v', IOCNUM_ISA_ASSERT_IRQ, struct vm_isa_irq)
331 #define VM_ISA_DEASSERT_IRQ \
332 _IOW('v', IOCNUM_ISA_DEASSERT_IRQ, struct vm_isa_irq)
333 #define VM_ISA_PULSE_IRQ \
334 _IOW('v', IOCNUM_ISA_PULSE_IRQ, struct vm_isa_irq)
335 #define VM_ISA_SET_IRQ_TRIGGER \
336 _IOW('v', IOCNUM_ISA_SET_IRQ_TRIGGER, struct vm_isa_irq_trigger)
337 #define VM_SET_CAPABILITY \
338 _IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
339 #define VM_GET_CAPABILITY \
340 _IOWR('v', IOCNUM_GET_CAPABILITY, struct vm_capability)
341 #define VM_BIND_PPTDEV \
342 _IOW('v', IOCNUM_BIND_PPTDEV, struct vm_pptdev)
343 #define VM_UNBIND_PPTDEV \
344 _IOW('v', IOCNUM_UNBIND_PPTDEV, struct vm_pptdev)
345 #define VM_MAP_PPTDEV_MMIO \
346 _IOW('v', IOCNUM_MAP_PPTDEV_MMIO, struct vm_pptdev_mmio)
347 #define VM_PPTDEV_MSI \
348 _IOW('v', IOCNUM_PPTDEV_MSI, struct vm_pptdev_msi)
349 #define VM_PPTDEV_MSIX \
350 _IOW('v', IOCNUM_PPTDEV_MSIX, struct vm_pptdev_msix)
351 #define VM_INJECT_NMI \
352 _IOW('v', IOCNUM_INJECT_NMI, struct vm_nmi)
354 _IOWR('v', IOCNUM_VM_STATS, struct vm_stats)
355 #define VM_STAT_DESC \
356 _IOWR('v', IOCNUM_VM_STAT_DESC, struct vm_stat_desc)
357 #define VM_SET_X2APIC_STATE \
358 _IOW('v', IOCNUM_SET_X2APIC_STATE, struct vm_x2apic)
359 #define VM_GET_X2APIC_STATE \
360 _IOWR('v', IOCNUM_GET_X2APIC_STATE, struct vm_x2apic)
361 #define VM_GET_HPET_CAPABILITIES \
362 _IOR('v', IOCNUM_GET_HPET_CAPABILITIES, struct vm_hpet_cap)
363 #define VM_GET_GPA_PMAP \
364 _IOWR('v', IOCNUM_GET_GPA_PMAP, struct vm_gpa_pte)
366 _IOWR('v', IOCNUM_GLA2GPA, struct vm_gla2gpa)
367 #define VM_ACTIVATE_CPU \
368 _IOW('v', IOCNUM_ACTIVATE_CPU, struct vm_activate_cpu)
369 #define VM_GET_CPUS \
370 _IOW('v', IOCNUM_GET_CPUSET, struct vm_cpuset)
371 #define VM_SET_INTINFO \
372 _IOW('v', IOCNUM_SET_INTINFO, struct vm_intinfo)
373 #define VM_GET_INTINFO \
374 _IOWR('v', IOCNUM_GET_INTINFO, struct vm_intinfo)
375 #define VM_RTC_WRITE \
376 _IOW('v', IOCNUM_RTC_WRITE, struct vm_rtc_data)
377 #define VM_RTC_READ \
378 _IOWR('v', IOCNUM_RTC_READ, struct vm_rtc_data)
379 #define VM_RTC_SETTIME \
380 _IOW('v', IOCNUM_RTC_SETTIME, struct vm_rtc_time)
381 #define VM_RTC_GETTIME \
382 _IOR('v', IOCNUM_RTC_GETTIME, struct vm_rtc_time)
383 #define VM_RESTART_INSTRUCTION \
384 _IOW('v', IOCNUM_RESTART_INSTRUCTION, int)