1 /* $NetBSD: cpufunc_asm_armv5.S,v 1.3 2007/01/06 00:50:54 christos Exp $ */
4 * Copyright (c) 2002, 2005 ARM Limited
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31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports the set/index
36 #include <machine/asm.h>
37 __FBSDID("$FreeBSD$");
40 * Functions to set the MMU Translation Table Base register
42 * We need to clean and flush the cache as it uses virtual
43 * addresses that are about to change.
47 bl _C_LABEL(armv5_idcache_wbinv_all)
50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
57 * Cache operations. For the entire cache we use the set/index
65 ENTRY_NP(armv5_icache_sync_range)
66 ldr ip, .Larmv5_line_size
68 bcs .Larmv5_icache_sync_all
70 sub r1, r1, #1 /* Don't overrun */
76 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
77 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
81 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
83 END(armv5_icache_sync_range)
85 ENTRY_NP(armv5_icache_sync_all)
86 .Larmv5_icache_sync_all:
88 * We assume that the code here can never be out of sync with the
89 * dcache, so that we can safely flush the Icache and fall through
90 * into the Dcache cleaning code.
92 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
93 /* Fall through to clean Dcache. */
96 ldr ip, .Larmv5_cache_data
97 ldmia ip, {s_max, i_max, s_inc, i_inc}
101 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
103 tst ip, i_max /* Index 0 is last one */
104 bne 2b /* Next index */
105 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
106 subs s_max, s_max, s_inc
107 bpl 1b /* Next set */
108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
110 END(armv5_icache_sync_all)
113 .word _C_LABEL(arm_pdcache_line_size)
115 ENTRY(armv5_dcache_wb_range)
116 ldr ip, .Larmv5_line_size
118 bcs .Larmv5_dcache_wb
120 sub r1, r1, #1 /* Don't overrun */
126 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
130 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
132 END(armv5_dcache_wb_range)
134 ENTRY(armv5_dcache_wbinv_range)
135 ldr ip, .Larmv5_line_size
137 bcs .Larmv5_dcache_wbinv_all
139 sub r1, r1, #1 /* Don't overrun */
145 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
149 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
151 END(armv5_dcache_wbinv_range)
154 * Note, we must not invalidate everything. If the range is too big we
155 * must use wb-inv of the entire cache.
157 ENTRY(armv5_dcache_inv_range)
158 ldr ip, .Larmv5_line_size
160 bcs .Larmv5_dcache_wbinv_all
162 sub r1, r1, #1 /* Don't overrun */
168 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
172 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
174 END(armv5_dcache_inv_range)
176 ENTRY(armv5_idcache_wbinv_range)
177 ldr ip, .Larmv5_line_size
179 bcs .Larmv5_idcache_wbinv_all
181 sub r1, r1, #1 /* Don't overrun */
187 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
188 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
192 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
194 END(armv5_idcache_wbinv_range)
196 ENTRY_NP(armv5_idcache_wbinv_all)
197 .Larmv5_idcache_wbinv_all:
199 * We assume that the code here can never be out of sync with the
200 * dcache, so that we can safely flush the Icache and fall through
201 * into the Dcache purging code.
203 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
204 /* Fall through to purge Dcache. */
206 EENTRY(armv5_dcache_wbinv_all)
207 .Larmv5_dcache_wbinv_all:
208 ldr ip, .Larmv5_cache_data
209 ldmia ip, {s_max, i_max, s_inc, i_inc}
213 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
215 tst ip, i_max /* Index 0 is last one */
216 bne 2b /* Next index */
217 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
218 subs s_max, s_max, s_inc
219 bpl 1b /* Next set */
220 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
222 EEND(armv5_dcache_wbinv_all)
223 END(armv5_idcache_wbinv_all)
226 .word _C_LABEL(armv5_dcache_sets_max)
230 /* XXX The following macros should probably be moved to asm.h */
231 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
232 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
235 * Parameters for the cache cleaning code. Note that the order of these
236 * four variables is assumed in the code above. Hence the reason for
237 * declaring them in the assembler file.
240 C_OBJECT(armv5_dcache_sets_max)
242 C_OBJECT(armv5_dcache_index_max)
244 C_OBJECT(armv5_dcache_sets_inc)
246 C_OBJECT(armv5_dcache_index_inc)