2 * Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
38 #include <sys/socket.h>
39 #include <sys/sockio.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <net/ethernet.h>
45 #include <net/if_arp.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_types.h>
49 #include <net/if_var.h>
50 #include <net/if_vlan_var.h>
53 #include <netinet/in.h>
54 #include <netinet/in_systm.h>
55 #include <netinet/in_var.h>
56 #include <netinet/ip.h>
60 #include <net/bpfdesc.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
65 #include <arm/cavium/cns11xx/if_ecereg.h>
66 #include <arm/cavium/cns11xx/if_ecevar.h>
67 #include <arm/cavium/cns11xx/econa_var.h>
69 #include <machine/bus.h>
70 #include <machine/intr.h>
72 /* "device miibus" required. See GENERIC if you get errors here. */
73 #include "miibus_if.h"
76 vlan0_mac[ETHER_ADDR_LEN] = {0x00, 0xaa, 0xbb, 0xcc, 0xdd, 0x19};
79 * Boot loader expects the hardware state to be the same when we
80 * restart the device (warm boot), so we need to save the initial
83 int initial_switch_config;
84 int initial_cpu_config;
85 int initial_port0_config;
86 int initial_port1_config;
88 static inline uint32_t
89 read_4(struct ece_softc *sc, bus_size_t off)
92 return (bus_read_4(sc->mem_res, off));
96 write_4(struct ece_softc *sc, bus_size_t off, uint32_t val)
99 bus_write_4(sc->mem_res, off, val);
102 #define ECE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
103 #define ECE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
104 #define ECE_LOCK_INIT(_sc) \
105 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
106 MTX_NETWORK_LOCK, MTX_DEF)
108 #define ECE_TXLOCK(_sc) mtx_lock(&(_sc)->sc_mtx_tx)
109 #define ECE_TXUNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx_tx)
110 #define ECE_TXLOCK_INIT(_sc) \
111 mtx_init(&_sc->sc_mtx_tx, device_get_nameunit(_sc->dev), \
112 "ECE TX Lock", MTX_DEF)
114 #define ECE_CLEANUPLOCK(_sc) mtx_lock(&(_sc)->sc_mtx_cleanup)
115 #define ECE_CLEANUPUNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx_cleanup)
116 #define ECE_CLEANUPLOCK_INIT(_sc) \
117 mtx_init(&_sc->sc_mtx_cleanup, device_get_nameunit(_sc->dev), \
118 "ECE cleanup Lock", MTX_DEF)
120 #define ECE_RXLOCK(_sc) mtx_lock(&(_sc)->sc_mtx_rx)
121 #define ECE_RXUNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx_rx)
122 #define ECE_RXLOCK_INIT(_sc) \
123 mtx_init(&_sc->sc_mtx_rx, device_get_nameunit(_sc->dev), \
124 "ECE RX Lock", MTX_DEF)
126 #define ECE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
127 #define ECE_TXLOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx_tx);
128 #define ECE_RXLOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx_rx);
129 #define ECE_CLEANUPLOCK_DESTROY(_sc) \
130 mtx_destroy(&_sc->sc_mtx_cleanup);
132 #define ECE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
133 #define ECE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
135 static devclass_t ece_devclass;
137 /* ifnet entry points */
139 static void eceinit_locked(void *);
140 static void ecestart_locked(struct ifnet *);
142 static void eceinit(void *);
143 static void ecestart(struct ifnet *);
144 static void ecestop(struct ece_softc *);
145 static int eceioctl(struct ifnet * ifp, u_long, caddr_t);
147 /* bus entry points */
149 static int ece_probe(device_t dev);
150 static int ece_attach(device_t dev);
151 static int ece_detach(device_t dev);
152 static void ece_intr(void *);
153 static void ece_intr_qf(void *);
154 static void ece_intr_status(void *xsc);
156 /* helper routines */
157 static int ece_activate(device_t dev);
158 static void ece_deactivate(device_t dev);
159 static int ece_ifmedia_upd(struct ifnet *ifp);
160 static void ece_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
161 static int ece_get_mac(struct ece_softc *sc, u_char *eaddr);
162 static void ece_set_mac(struct ece_softc *sc, u_char *eaddr);
163 static int configure_cpu_port(struct ece_softc *sc);
164 static int configure_lan_port(struct ece_softc *sc, int phy_type);
165 static void set_pvid(struct ece_softc *sc, int port0, int port1, int cpu);
166 static void set_vlan_vid(struct ece_softc *sc, int vlan);
167 static void set_vlan_member(struct ece_softc *sc, int vlan);
168 static void set_vlan_tag(struct ece_softc *sc, int vlan);
169 static int hardware_init(struct ece_softc *sc);
170 static void ece_intr_rx_locked(struct ece_softc *sc, int count);
172 static void ece_free_desc_dma_tx(struct ece_softc *sc);
173 static void ece_free_desc_dma_rx(struct ece_softc *sc);
175 static void ece_intr_task(void *arg, int pending __unused);
176 static void ece_tx_task(void *arg, int pending __unused);
177 static void ece_cleanup_task(void *arg, int pending __unused);
179 static int ece_allocate_dma(struct ece_softc *sc);
181 static void ece_intr_tx(void *xsc);
183 static void clear_mac_entries(struct ece_softc *ec, int include_this_mac);
185 static uint32_t read_mac_entry(struct ece_softc *ec,
189 /*PHY related functions*/
191 phy_read(struct ece_softc *sc, int phy, int reg)
197 write_4(sc, PHY_CONTROL, PHY_RW_OK);
198 write_4(sc, PHY_CONTROL,
199 (PHY_ADDRESS(phy)|PHY_READ_COMMAND |
202 for (ii = 0; ii < 0x1000; ii++) {
203 status = read_4(sc, PHY_CONTROL);
204 if (status & PHY_RW_OK) {
205 /* Clear the rw_ok status, and clear other
207 write_4(sc, PHY_CONTROL, PHY_RW_OK);
208 val = PHY_GET_DATA(status);
216 phy_write(struct ece_softc *sc, int phy, int reg, int data)
220 write_4(sc, PHY_CONTROL, PHY_RW_OK);
221 write_4(sc, PHY_CONTROL,
222 PHY_ADDRESS(phy) | PHY_REGISTER(reg) |
223 PHY_WRITE_COMMAND | PHY_DATA(data));
224 for (ii = 0; ii < 0x1000; ii++) {
225 if (read_4(sc, PHY_CONTROL) & PHY_RW_OK) {
226 /* Clear the rw_ok status, and clear other
229 write_4(sc, PHY_CONTROL, PHY_RW_OK);
235 static int get_phy_type(struct ece_softc *sc)
237 uint16_t phy0_id = 0, phy1_id = 0;
240 * Use SMI (MDC/MDIO) to read Link Partner's PHY Identifier
243 phy0_id = phy_read(sc, 0, 0x2);
244 phy1_id = phy_read(sc, 1, 0x2);
246 if ((phy0_id == 0xFFFF) && (phy1_id == 0x000F))
247 return (ASIX_GIGA_PHY);
248 else if ((phy0_id == 0x0243) && (phy1_id == 0x0243))
249 return (TWO_SINGLE_PHY);
250 else if ((phy0_id == 0xFFFF) && (phy1_id == 0x0007))
251 return (VSC8601_GIGA_PHY);
252 else if ((phy0_id == 0x0243) && (phy1_id == 0xFFFF))
253 return (IC_PLUS_PHY);
255 return (NOT_FOUND_PHY);
259 ece_probe(device_t dev)
262 device_set_desc(dev, "Econa Ethernet Controller");
268 ece_attach(device_t dev)
270 struct ece_softc *sc;
271 struct ifnet *ifp = NULL;
272 struct sysctl_ctx_list *sctx;
273 struct sysctl_oid *soid;
274 u_char eaddr[ETHER_ADDR_LEN];
281 sc = device_get_softc(dev);
286 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
288 if (sc->mem_res == NULL)
291 power_on_network_interface();
294 sc->irq_res_status = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
296 if (sc->irq_res_status == NULL)
300 /*TSTC: Fm-Switch-Tx-Complete*/
301 sc->irq_res_tx = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
303 if (sc->irq_res_tx == NULL)
307 /*FSRC: Fm-Switch-Rx-Complete*/
308 sc->irq_res_rec = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
310 if (sc->irq_res_rec == NULL)
314 /*FSQF: Fm-Switch-Queue-Full*/
315 sc->irq_res_qf = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
317 if (sc->irq_res_qf == NULL)
320 err = ece_activate(dev);
325 sctx = device_get_sysctl_ctx(dev);
326 soid = device_get_sysctl_tree(dev);
330 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
332 if ((err = ece_get_mac(sc, eaddr)) != 0) {
333 /* No MAC address configured. Generate the random one. */
336 "Generating random ethernet address.\n");
339 /*from if_ae.c/if_ate.c*/
341 * Set OUI to convenient locally assigned address. 'b'
342 * is 0x62, which has the locally assigned bit set, and
343 * the broadcast/multicast bit clear.
348 eaddr[3] = (rnd >> 16) & 0xff;
349 eaddr[4] = (rnd >> 8) & 0xff;
350 eaddr[5] = rnd & 0xff;
352 for (i = 0; i < ETHER_ADDR_LEN; i++)
353 eaddr[i] = vlan0_mac[i];
355 ece_set_mac(sc, eaddr);
356 sc->ifp = ifp = if_alloc(IFT_ETHER);
357 /* Only one PHY at address 0 in this device. */
358 err = mii_attach(dev, &sc->miibus, ifp, ece_ifmedia_upd,
359 ece_ifmedia_sts, BMSR_DEFCAPMASK, 0, MII_OFFSET_ANY, 0);
361 device_printf(dev, "attaching PHYs failed\n");
365 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
366 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
368 ifp->if_capabilities = IFCAP_HWCSUM;
370 ifp->if_hwassist = (CSUM_IP | CSUM_TCP | CSUM_UDP);
371 ifp->if_capenable = ifp->if_capabilities;
372 ifp->if_start = ecestart;
373 ifp->if_ioctl = eceioctl;
374 ifp->if_init = eceinit;
375 ifp->if_snd.ifq_drv_maxlen = ECE_MAX_TX_BUFFERS - 1;
376 IFQ_SET_MAXLEN(&ifp->if_snd, ECE_MAX_TX_BUFFERS - 1);
377 IFQ_SET_READY(&ifp->if_snd);
379 /* Create local taskq. */
381 TASK_INIT(&sc->sc_intr_task, 0, ece_intr_task, sc);
382 TASK_INIT(&sc->sc_tx_task, 1, ece_tx_task, ifp);
383 TASK_INIT(&sc->sc_cleanup_task, 2, ece_cleanup_task, sc);
384 sc->sc_tq = taskqueue_create_fast("ece_taskq", M_WAITOK,
385 taskqueue_thread_enqueue,
387 if (sc->sc_tq == NULL) {
388 device_printf(sc->dev, "could not create taskqueue\n");
392 ether_ifattach(ifp, eaddr);
395 * Activate interrupts
397 err = bus_setup_intr(dev, sc->irq_res_rec, INTR_TYPE_NET | INTR_MPSAFE,
398 NULL, ece_intr, sc, &sc->intrhand);
401 ECE_LOCK_DESTROY(sc);
405 err = bus_setup_intr(dev, sc->irq_res_status,
406 INTR_TYPE_NET | INTR_MPSAFE,
407 NULL, ece_intr_status, sc, &sc->intrhand_status);
410 ECE_LOCK_DESTROY(sc);
414 err = bus_setup_intr(dev, sc->irq_res_qf, INTR_TYPE_NET | INTR_MPSAFE,
415 NULL,ece_intr_qf, sc, &sc->intrhand_qf);
419 ECE_LOCK_DESTROY(sc);
423 err = bus_setup_intr(dev, sc->irq_res_tx, INTR_TYPE_NET | INTR_MPSAFE,
424 NULL, ece_intr_tx, sc, &sc->intrhand_tx);
428 ECE_LOCK_DESTROY(sc);
434 ECE_CLEANUPLOCK_INIT(sc);
436 /* Enable all interrupt sources. */
437 write_4(sc, INTERRUPT_MASK, 0x00000000);
440 write_4(sc, PORT_0_CONFIG, read_4(sc, PORT_0_CONFIG) & ~(PORT_DISABLE));
442 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
443 device_get_nameunit(sc->dev));
454 ece_detach(device_t dev)
456 struct ece_softc *sc = device_get_softc(dev);
457 struct ifnet *ifp = sc->ifp;
469 ece_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
472 KASSERT(nsegs == 1, ("wrong number of segments, should be 1"));
474 *paddr = segs->ds_addr;
478 ece_alloc_desc_dma_tx(struct ece_softc *sc)
483 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */
484 error = bus_dma_tag_create(sc->sc_parent_tag, /* parent */
485 16, 0, /* alignment, boundary */
486 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
487 BUS_SPACE_MAXADDR, /* highaddr */
488 NULL, NULL, /* filtfunc, filtfuncarg */
489 sizeof(eth_tx_desc_t)*ECE_MAX_TX_BUFFERS, /* max size */
491 sizeof(eth_tx_desc_t)*ECE_MAX_TX_BUFFERS,
493 NULL, NULL, /* lockfunc, lockfuncarg */
494 &sc->dmatag_data_tx); /* dmat */
496 /* Allocate memory for TX ring. */
497 error = bus_dmamem_alloc(sc->dmatag_data_tx,
498 (void**)&(sc->desc_tx),
499 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
501 &(sc->dmamap_ring_tx));
504 if_printf(sc->ifp, "failed to allocate DMA memory\n");
505 bus_dma_tag_destroy(sc->dmatag_data_tx);
506 sc->dmatag_data_tx = 0;
511 error = bus_dmamap_load(sc->dmatag_data_tx, sc->dmamap_ring_tx,
513 sizeof(eth_tx_desc_t)*ECE_MAX_TX_BUFFERS,
515 &(sc->ring_paddr_tx), BUS_DMA_NOWAIT);
518 if_printf(sc->ifp, "can't load descriptor\n");
519 bus_dmamem_free(sc->dmatag_data_tx, sc->desc_tx,
522 bus_dma_tag_destroy(sc->dmatag_data_tx);
523 sc->dmatag_data_tx = 0;
527 /* Allocate a busdma tag for mbufs. Alignment is 2 bytes */
528 error = bus_dma_tag_create(sc->sc_parent_tag, /* parent */
529 1, 0, /* alignment, boundary */
530 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
531 BUS_SPACE_MAXADDR, /* highaddr */
532 NULL, NULL, /* filtfunc, filtfuncarg */
533 MCLBYTES*MAX_FRAGMENT, /* maxsize */
534 MAX_FRAGMENT, /* nsegments */
535 MCLBYTES, 0, /* maxsegsz, flags */
536 NULL, NULL, /* lockfunc, lockfuncarg */
537 &sc->dmatag_ring_tx); /* dmat */
540 if_printf(sc->ifp, "failed to create busdma tag for mbufs\n");
544 for (i = 0; i < ECE_MAX_TX_BUFFERS; i++) {
545 /* Create dma map for each descriptor. */
546 error = bus_dmamap_create(sc->dmatag_ring_tx, 0,
547 &(sc->tx_desc[i].dmamap));
549 if_printf(sc->ifp, "failed to create map for mbuf\n");
557 ece_free_desc_dma_tx(struct ece_softc *sc)
561 for (i = 0; i < ECE_MAX_TX_BUFFERS; i++) {
562 if (sc->tx_desc[i].buff) {
563 m_freem(sc->tx_desc[i].buff);
564 sc->tx_desc[i].buff= 0;
568 if (sc->dmamap_ring_tx) {
569 bus_dmamap_unload(sc->dmatag_data_tx, sc->dmamap_ring_tx);
571 bus_dmamem_free(sc->dmatag_data_tx,
572 sc->desc_tx, sc->dmamap_ring_tx);
574 sc->dmamap_ring_tx = 0;
577 if (sc->dmatag_data_tx) {
578 bus_dma_tag_destroy(sc->dmatag_data_tx);
579 sc->dmatag_data_tx = 0;
582 if (sc->dmatag_ring_tx) {
583 for (i = 0; i<ECE_MAX_TX_BUFFERS; i++) {
584 bus_dmamap_destroy(sc->dmatag_ring_tx,
585 sc->tx_desc[i].dmamap);
586 sc->tx_desc[i].dmamap = 0;
588 bus_dma_tag_destroy(sc->dmatag_ring_tx);
589 sc->dmatag_ring_tx = 0;
594 ece_alloc_desc_dma_rx(struct ece_softc *sc)
599 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */
600 error = bus_dma_tag_create(sc->sc_parent_tag, /* parent */
601 16, 0, /* alignment, boundary */
602 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
603 BUS_SPACE_MAXADDR, /* highaddr */
604 NULL, NULL, /* filtfunc, filtfuncarg */
605 /* maxsize, nsegments */
606 sizeof(eth_rx_desc_t)*ECE_MAX_RX_BUFFERS, 1,
607 /* maxsegsz, flags */
608 sizeof(eth_rx_desc_t)*ECE_MAX_RX_BUFFERS, 0,
609 NULL, NULL, /* lockfunc, lockfuncarg */
610 &sc->dmatag_data_rx); /* dmat */
612 /* Allocate RX ring. */
613 error = bus_dmamem_alloc(sc->dmatag_data_rx,
614 (void**)&(sc->desc_rx),
615 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
617 &(sc->dmamap_ring_rx));
620 if_printf(sc->ifp, "failed to allocate DMA memory\n");
625 error = bus_dmamap_load(sc->dmatag_data_rx, sc->dmamap_ring_rx,
627 sizeof(eth_rx_desc_t)*ECE_MAX_RX_BUFFERS,
629 &(sc->ring_paddr_rx), BUS_DMA_NOWAIT);
632 if_printf(sc->ifp, "can't load descriptor\n");
633 bus_dmamem_free(sc->dmatag_data_rx, sc->desc_rx,
635 bus_dma_tag_destroy(sc->dmatag_data_rx);
640 /* Allocate a busdma tag for mbufs. */
641 error = bus_dma_tag_create(sc->sc_parent_tag,/* parent */
642 16, 0, /* alignment, boundary */
643 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
644 BUS_SPACE_MAXADDR, /* highaddr */
645 NULL, NULL, /* filtfunc, filtfuncarg */
646 MCLBYTES, 1, /* maxsize, nsegments */
647 MCLBYTES, 0, /* maxsegsz, flags */
648 NULL, NULL, /* lockfunc, lockfuncarg */
649 &sc->dmatag_ring_rx); /* dmat */
652 if_printf(sc->ifp, "failed to create busdma tag for mbufs\n");
656 for (i = 0; i<ECE_MAX_RX_BUFFERS; i++) {
657 error = bus_dmamap_create(sc->dmatag_ring_rx, 0,
658 &sc->rx_desc[i].dmamap);
660 if_printf(sc->ifp, "failed to create map for mbuf\n");
665 error = bus_dmamap_create(sc->dmatag_ring_rx, 0, &sc->rx_sparemap);
667 if_printf(sc->ifp, "failed to create spare map\n");
675 ece_free_desc_dma_rx(struct ece_softc *sc)
679 for (i = 0; i < ECE_MAX_RX_BUFFERS; i++) {
680 if (sc->rx_desc[i].buff) {
681 m_freem(sc->rx_desc[i].buff);
682 sc->rx_desc[i].buff= 0;
686 if (sc->dmatag_data_rx) {
687 bus_dmamap_unload(sc->dmatag_data_rx, sc->dmamap_ring_rx);
688 bus_dmamem_free(sc->dmatag_data_rx, sc->desc_rx,
690 bus_dma_tag_destroy(sc->dmatag_data_rx);
691 sc->dmatag_data_rx = 0;
692 sc->dmamap_ring_rx = 0;
696 if (sc->dmatag_ring_rx) {
697 for (i = 0; i < ECE_MAX_RX_BUFFERS; i++)
698 bus_dmamap_destroy(sc->dmatag_ring_rx,
699 sc->rx_desc[i].dmamap);
700 bus_dmamap_destroy(sc->dmatag_ring_rx, sc->rx_sparemap);
701 bus_dma_tag_destroy(sc->dmatag_ring_rx);
702 sc->dmatag_ring_rx = 0;
707 ece_new_rxbuf(struct ece_softc *sc, struct rx_desc_info* descinfo)
709 struct mbuf *new_mbuf;
710 bus_dma_segment_t seg[1];
716 tag = sc->dmatag_ring_rx;
718 new_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
720 if (new_mbuf == NULL)
723 new_mbuf->m_len = new_mbuf->m_pkthdr.len = MCLBYTES;
725 error = bus_dmamap_load_mbuf_sg(tag, sc->rx_sparemap, new_mbuf,
726 seg, &nsegs, BUS_DMA_NOWAIT);
728 KASSERT(nsegs == 1, ("Too many segments returned!"));
730 if (nsegs != 1 || error) {
735 if (descinfo->buff != NULL) {
736 bus_dmamap_sync(tag, descinfo->dmamap, BUS_DMASYNC_POSTREAD);
737 bus_dmamap_unload(tag, descinfo->dmamap);
740 map = descinfo->dmamap;
741 descinfo->dmamap = sc->rx_sparemap;
742 sc->rx_sparemap = map;
744 bus_dmamap_sync(tag, descinfo->dmamap, BUS_DMASYNC_PREREAD);
746 descinfo->buff = new_mbuf;
747 descinfo->desc->data_ptr = seg->ds_addr;
748 descinfo->desc->length = seg->ds_len - 2;
754 ece_allocate_dma(struct ece_softc *sc)
756 eth_tx_desc_t *desctx;
757 eth_rx_desc_t *descrx;
761 /* Create parent tag for tx and rx */
762 error = bus_dma_tag_create(
763 bus_get_dma_tag(sc->dev),/* parent */
764 1, 0, /* alignment, boundary */
765 BUS_SPACE_MAXADDR, /* lowaddr */
766 BUS_SPACE_MAXADDR, /* highaddr */
767 NULL, NULL, /* filter, filterarg */
768 BUS_SPACE_MAXSIZE_32BIT, 0,/* maxsize, nsegments */
769 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
771 NULL, NULL, /* lockfunc, lockarg */
774 ece_alloc_desc_dma_tx(sc);
776 for (i = 0; i < ECE_MAX_TX_BUFFERS; i++) {
777 desctx = (eth_tx_desc_t *)(&sc->desc_tx[i]);
778 memset(desctx, 0, sizeof(eth_tx_desc_t));
779 desctx->length = MAX_PACKET_LEN;
781 if (i == ECE_MAX_TX_BUFFERS - 1)
785 ece_alloc_desc_dma_rx(sc);
787 for (i = 0; i < ECE_MAX_RX_BUFFERS; i++) {
788 descrx = &(sc->desc_rx[i]);
789 memset(descrx, 0, sizeof(eth_rx_desc_t));
790 sc->rx_desc[i].desc = descrx;
791 sc->rx_desc[i].buff = 0;
792 ece_new_rxbuf(sc, &(sc->rx_desc[i]));
794 if (i == ECE_MAX_RX_BUFFERS - 1)
800 sc->desc_curr_tx = 0;
806 ece_activate(device_t dev)
808 struct ece_softc *sc;
810 uint32_t mac_port_config;
813 sc = device_get_softc(dev);
816 initial_switch_config = read_4(sc, SWITCH_CONFIG);
817 initial_cpu_config = read_4(sc, CPU_PORT_CONFIG);
818 initial_port0_config = read_4(sc, MAC_PORT_0_CONFIG);
819 initial_port1_config = read_4(sc, MAC_PORT_1_CONFIG);
822 mac_port_config = read_4(sc, MAC_PORT_0_CONFIG);
823 mac_port_config |= (PORT_DISABLE);
824 write_4(sc, MAC_PORT_0_CONFIG, mac_port_config);
827 mac_port_config = read_4(sc, MAC_PORT_1_CONFIG);
828 mac_port_config |= (PORT_DISABLE);
829 write_4(sc, MAC_PORT_1_CONFIG, mac_port_config);
831 err = ece_allocate_dma(sc);
833 if_printf(sc->ifp, "failed allocating dma\n");
837 write_4(sc, TS_DESCRIPTOR_POINTER, sc->ring_paddr_tx);
838 write_4(sc, TS_DESCRIPTOR_BASE_ADDR, sc->ring_paddr_tx);
840 write_4(sc, FS_DESCRIPTOR_POINTER, sc->ring_paddr_rx);
841 write_4(sc, FS_DESCRIPTOR_BASE_ADDR, sc->ring_paddr_rx);
843 write_4(sc, FS_DMA_CONTROL, 1);
852 ece_deactivate(device_t dev)
854 struct ece_softc *sc;
856 sc = device_get_softc(dev);
859 bus_teardown_intr(dev, sc->irq_res_rec, sc->intrhand);
864 bus_teardown_intr(dev, sc->irq_res_qf, sc->intrhand_qf);
868 bus_generic_detach(sc->dev);
870 device_delete_child(sc->dev, sc->miibus);
872 bus_release_resource(dev, SYS_RES_IOPORT,
873 rman_get_rid(sc->mem_res), sc->mem_res);
877 bus_release_resource(dev, SYS_RES_IRQ,
878 rman_get_rid(sc->irq_res_rec), sc->irq_res_rec);
881 bus_release_resource(dev, SYS_RES_IRQ,
882 rman_get_rid(sc->irq_res_qf), sc->irq_res_qf);
885 bus_release_resource(dev, SYS_RES_IRQ,
886 rman_get_rid(sc->irq_res_status), sc->irq_res_status);
890 sc->irq_res_status = 0;
891 ECE_TXLOCK_DESTROY(sc);
892 ECE_RXLOCK_DESTROY(sc);
894 ece_free_desc_dma_tx(sc);
895 ece_free_desc_dma_rx(sc);
901 * Change media according to request.
904 ece_ifmedia_upd(struct ifnet *ifp)
906 struct ece_softc *sc = ifp->if_softc;
907 struct mii_data *mii;
910 mii = device_get_softc(sc->miibus);
912 error = mii_mediachg(mii);
918 * Notify the world which media we're using.
921 ece_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
923 struct ece_softc *sc = ifp->if_softc;
924 struct mii_data *mii;
926 mii = device_get_softc(sc->miibus);
929 ifmr->ifm_active = mii->mii_media_active;
930 ifmr->ifm_status = mii->mii_media_status;
937 struct ece_softc *sc = xsc;
938 struct mii_data *mii;
941 mii = device_get_softc(sc->miibus);
942 active = mii->mii_media_active;
946 * Schedule another timeout one second from now.
948 callout_reset(&sc->tick_ch, hz, ece_tick, sc);
952 read_mac_entry(struct ece_softc *ec,
957 struct arl_table_entry_t entry;
959 write_4(ec, ARL_TABLE_ACCESS_CONTROL_0, 0);
960 write_4(ec, ARL_TABLE_ACCESS_CONTROL_1, 0);
961 write_4(ec, ARL_TABLE_ACCESS_CONTROL_2, 0);
963 write_4(ec, ARL_TABLE_ACCESS_CONTROL_0, 0x1);
965 write_4(ec, ARL_TABLE_ACCESS_CONTROL_0, 0x2);
967 for (ii = 0; ii < 0x1000; ii++)
968 if (read_4(ec, ARL_TABLE_ACCESS_CONTROL_1) & (0x1))
971 entry_val = (uint32_t*) (&entry);
972 entry_val[0] = read_4(ec, ARL_TABLE_ACCESS_CONTROL_1);
973 entry_val[1] = read_4(ec, ARL_TABLE_ACCESS_CONTROL_2);
976 memcpy(mac_result, entry.mac_addr, ETHER_ADDR_LEN);
978 return (entry.table_end);
982 write_arl_table_entry(struct ece_softc *ec,
988 const uint8_t *mac_addr)
992 struct arl_table_entry_t entry;
994 memset(&entry, 0, sizeof(entry));
996 entry.filter = filter;
997 entry.vlan_mac = vlan_mac;
998 entry.vlan_gid = vlan_gid;
999 entry.age_field = age_field;
1000 entry.port_map = port_map;
1001 memcpy(entry.mac_addr, mac_addr, ETHER_ADDR_LEN);
1003 entry_val = (uint32_t*) (&entry);
1005 write_4(ec, ARL_TABLE_ACCESS_CONTROL_0, 0);
1006 write_4(ec, ARL_TABLE_ACCESS_CONTROL_1, 0);
1007 write_4(ec, ARL_TABLE_ACCESS_CONTROL_2, 0);
1009 write_4(ec, ARL_TABLE_ACCESS_CONTROL_1, entry_val[0]);
1010 write_4(ec, ARL_TABLE_ACCESS_CONTROL_2, entry_val[1]);
1012 write_4(ec, ARL_TABLE_ACCESS_CONTROL_0, ARL_WRITE_COMMAND);
1014 for (ii = 0; ii < 0x1000; ii++)
1015 if (read_4(ec, ARL_TABLE_ACCESS_CONTROL_1) &
1016 ARL_COMMAND_COMPLETE)
1017 return (1); /* Write OK. */
1024 remove_mac_entry(struct ece_softc *sc,
1028 /* Invalid age_field mean erase this entry. */
1029 write_arl_table_entry(sc, 0, 1, VLAN0_GROUP_ID,
1030 INVALID_ENTRY, VLAN0_GROUP,
1035 add_mac_entry(struct ece_softc *sc,
1039 write_arl_table_entry(sc, 0, 1, VLAN0_GROUP_ID,
1040 NEW_ENTRY, VLAN0_GROUP,
1045 * The behavior of ARL table reading and deletion is not well defined
1046 * in the documentation. To be safe, all mac addresses are put to a
1047 * list, then deleted.
1051 clear_mac_entries(struct ece_softc *ec, int include_this_mac)
1054 struct mac_list * temp;
1055 struct mac_list * mac_list_header;
1056 struct mac_list * current;
1057 char mac[ETHER_ADDR_LEN];
1060 mac_list_header = 0;
1062 table_end = read_mac_entry(ec, mac, 1);
1063 while (!table_end) {
1064 if (!include_this_mac &&
1065 memcmp(mac, vlan0_mac, ETHER_ADDR_LEN) == 0) {
1066 /* Read next entry. */
1067 table_end = read_mac_entry(ec, mac, 0);
1071 temp = (struct mac_list*)malloc(sizeof(struct mac_list),
1074 memcpy(temp->mac_addr, mac, ETHER_ADDR_LEN);
1076 if (mac_list_header) {
1077 current->next = temp;
1080 mac_list_header = temp;
1083 /* Read next Entry */
1084 table_end = read_mac_entry(ec, mac, 0);
1087 current = mac_list_header;
1090 remove_mac_entry(ec, current->mac_addr);
1092 current = current->next;
1093 free(temp, M_DEVBUF);
1098 configure_lan_port(struct ece_softc *sc, int phy_type)
1101 uint32_t mac_port_config;
1106 sw_config = read_4(sc, SWITCH_CONFIG);
1107 /* Enable fast aging. */
1108 sw_config |= FAST_AGING;
1109 /* Enable IVL learning. */
1110 sw_config |= IVL_LEARNING;
1111 /* Disable hardware NAT. */
1112 sw_config &= ~(HARDWARE_NAT);
1114 sw_config |= SKIP_L2_LOOKUP_PORT_0 | SKIP_L2_LOOKUP_PORT_1| NIC_MODE;
1116 write_4(sc, SWITCH_CONFIG, sw_config);
1118 sw_config = read_4(sc, SWITCH_CONFIG);
1120 mac_port_config = read_4(sc, MAC_PORT_0_CONFIG);
1122 if (!(mac_port_config & 0x1) || (mac_port_config & 0x2))
1123 if_printf(sc->ifp, "Link Down\n");
1125 write_4(sc, MAC_PORT_0_CONFIG, mac_port_config);
1130 set_pvid(struct ece_softc *sc, int port0, int port1, int cpu)
1133 val = read_4(sc, VLAN_PORT_PVID) & (~(0x7 << 0));
1134 write_4(sc, VLAN_PORT_PVID, val);
1135 val = read_4(sc, VLAN_PORT_PVID) | ((port0) & 0x07);
1136 write_4(sc, VLAN_PORT_PVID, val);
1137 val = read_4(sc, VLAN_PORT_PVID) & (~(0x7 << 4));
1138 write_4(sc, VLAN_PORT_PVID, val);
1139 val = read_4(sc, VLAN_PORT_PVID) | (((port1) & 0x07) << 4);
1140 write_4(sc, VLAN_PORT_PVID, val);
1142 val = read_4(sc, VLAN_PORT_PVID) & (~(0x7 << 8));
1143 write_4(sc, VLAN_PORT_PVID, val);
1144 val = read_4(sc, VLAN_PORT_PVID) | (((cpu) & 0x07) << 8);
1145 write_4(sc, VLAN_PORT_PVID, val);
1149 /* VLAN related functions */
1151 set_vlan_vid(struct ece_softc *sc, int vlan)
1153 const uint32_t regs[] = {
1164 const int vids[] = {
1183 val = read_4(sc, reg);
1184 write_4(sc, reg, val & (~(0xFFF << 0)));
1185 val = read_4(sc, reg);
1186 write_4(sc, reg, val|((vid & 0xFFF) << 0));
1188 val = read_4(sc, reg);
1189 write_4(sc, reg, val & (~(0xFFF << 12)));
1190 val = read_4(sc, reg);
1191 write_4(sc, reg, val|((vid & 0xFFF) << 12));
1196 set_vlan_member(struct ece_softc *sc, int vlan)
1198 unsigned char shift;
1201 const int groups[] = {
1212 group = groups[vlan];
1215 val = read_4(sc, VLAN_MEMBER_PORT_MAP) & (~(0x7 << shift));
1216 write_4(sc, VLAN_MEMBER_PORT_MAP, val);
1217 val = read_4(sc, VLAN_MEMBER_PORT_MAP);
1218 write_4(sc, VLAN_MEMBER_PORT_MAP, val | ((group & 0x7) << shift));
1222 set_vlan_tag(struct ece_softc *sc, int vlan)
1224 unsigned char shift;
1230 val = read_4(sc, VLAN_TAG_PORT_MAP) & (~(0x7 << shift));
1231 write_4(sc, VLAN_TAG_PORT_MAP, val);
1232 val = read_4(sc, VLAN_TAG_PORT_MAP);
1233 write_4(sc, VLAN_TAG_PORT_MAP, val | ((tag & 0x7) << shift));
1237 configure_cpu_port(struct ece_softc *sc)
1239 uint32_t cpu_port_config;
1242 cpu_port_config = read_4(sc, CPU_PORT_CONFIG);
1243 /* SA learning Disable */
1244 cpu_port_config |= (SA_LEARNING_DISABLE);
1245 /* set data offset + 2 */
1246 cpu_port_config &= ~(1U << 31);
1248 write_4(sc, CPU_PORT_CONFIG, cpu_port_config);
1250 if (!write_arl_table_entry(sc, 0, 1, VLAN0_GROUP_ID,
1251 STATIC_ENTRY, VLAN0_GROUP,
1255 set_pvid(sc, PORT0_PVID, PORT1_PVID, CPU_PORT_PVID);
1257 for (i = 0; i < 8; i++) {
1258 set_vlan_vid(sc, i);
1259 set_vlan_member(sc, i);
1260 set_vlan_tag(sc, i);
1263 /* disable all interrupt status sources */
1264 write_4(sc, INTERRUPT_MASK, 0xffff1fff);
1266 /* clear previous interrupt sources */
1267 write_4(sc, INTERRUPT_STATUS, 0x00001FFF);
1269 write_4(sc, TS_DMA_CONTROL, 0);
1270 write_4(sc, FS_DMA_CONTROL, 0);
1275 hardware_init(struct ece_softc *sc)
1278 static int gw_phy_type;
1280 gw_phy_type = get_phy_type(sc);
1281 /* Currently only ic_plus phy is supported. */
1282 if (gw_phy_type != IC_PLUS_PHY) {
1283 device_printf(sc->dev, "PHY type is not supported (%d)\n",
1287 status = configure_lan_port(sc, gw_phy_type);
1288 configure_cpu_port(sc);
1293 set_mac_address(struct ece_softc *sc, const char *mac, int mac_len)
1296 /* Invalid age_field mean erase this entry. */
1297 write_arl_table_entry(sc, 0, 1, VLAN0_GROUP_ID,
1298 INVALID_ENTRY, VLAN0_GROUP,
1300 memcpy(vlan0_mac, mac, ETHER_ADDR_LEN);
1302 write_arl_table_entry(sc, 0, 1, VLAN0_GROUP_ID,
1303 STATIC_ENTRY, VLAN0_GROUP,
1308 ece_set_mac(struct ece_softc *sc, u_char *eaddr)
1310 memcpy(vlan0_mac, eaddr, ETHER_ADDR_LEN);
1311 set_mac_address(sc, eaddr, ETHER_ADDR_LEN);
1315 * TODO: the device doesn't have MAC stored, we should read the
1316 * configuration stored in FLASH, but the format depends on the
1320 ece_get_mac(struct ece_softc *sc, u_char *eaddr)
1326 ece_intr_rx_locked(struct ece_softc *sc, int count)
1328 struct ifnet *ifp = sc->ifp;
1330 struct rx_desc_info *rxdesc;
1331 eth_rx_desc_t *desc;
1340 fssd_curr = read_4(sc, FS_DESCRIPTOR_POINTER);
1342 fssd = (fssd_curr - (uint32_t)sc->ring_paddr_rx)>>4;
1344 desc = sc->rx_desc[sc->last_rx].desc;
1346 /* Prepare to read the data in the ring. */
1347 bus_dmamap_sync(sc->dmatag_ring_rx,
1349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1351 if (fssd > sc->last_rx)
1352 rxcount = fssd - sc->last_rx;
1353 else if (fssd < sc->last_rx)
1354 rxcount = (ECE_MAX_RX_BUFFERS - sc->last_rx) + fssd;
1356 if (desc->cown == 0)
1359 rxcount = ECE_MAX_RX_BUFFERS;
1362 for (i= 0; i < rxcount; i++) {
1363 status = desc->cown;
1368 rxdesc = &sc->rx_desc[idx];
1371 if (desc->length < ETHER_MIN_LEN - ETHER_CRC_LEN ||
1372 desc->length > ETHER_MAX_LEN - ETHER_CRC_LEN +
1373 ETHER_VLAN_ENCAP_LEN) {
1376 desc->length = MCLBYTES - 2;
1377 /* Invalid packet, skip and process next
1383 if (ece_new_rxbuf(sc, rxdesc) != 0) {
1386 desc->length = MCLBYTES - 2;
1391 * The device will write to addrress + 2 So we need to adjust
1392 * the address after the packet is received.
1395 mb->m_len = mb->m_pkthdr.len = desc->length;
1397 mb->m_flags |= M_PKTHDR;
1398 mb->m_pkthdr.rcvif = ifp;
1399 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1400 /*check for valid checksum*/
1401 if ( (!desc->l4f) && (desc->prot != 3)) {
1402 mb->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1403 mb->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1404 mb->m_pkthdr.csum_data = 0xffff;
1408 (*ifp->if_input)(ifp, mb);
1412 desc->length = MCLBYTES - 2;
1414 bus_dmamap_sync(sc->dmatag_ring_rx,
1416 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1418 if (sc->last_rx == ECE_MAX_RX_BUFFERS - 1)
1423 desc = sc->rx_desc[sc->last_rx].desc;
1426 /* Sync updated flags. */
1427 bus_dmamap_sync(sc->dmatag_ring_rx,
1429 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1435 ece_intr_task(void *arg, int pending __unused)
1437 struct ece_softc *sc = arg;
1439 ece_intr_rx_locked(sc, -1);
1446 struct ece_softc *sc = xsc;
1447 struct ifnet *ifp = sc->ifp;
1449 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1450 write_4(sc, FS_DMA_CONTROL, 0);
1454 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1456 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1457 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
1461 ece_intr_status(void *xsc)
1463 struct ece_softc *sc = xsc;
1464 struct ifnet *ifp = sc->ifp;
1467 stat = read_4(sc, INTERRUPT_STATUS);
1469 write_4(sc, INTERRUPT_STATUS, stat);
1471 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1472 if ((stat & ERROR_MASK) != 0)
1478 ece_cleanup_locked(struct ece_softc *sc)
1480 eth_tx_desc_t *desc;
1482 if (sc->tx_cons == sc->tx_prod) return;
1484 /* Prepare to read the ring (owner bit). */
1485 bus_dmamap_sync(sc->dmatag_ring_tx,
1487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1489 while (sc->tx_cons != sc->tx_prod) {
1490 desc = sc->tx_desc[sc->tx_cons].desc;
1491 if (desc->cown != 0) {
1492 struct tx_desc_info *td = &(sc->tx_desc[sc->tx_cons]);
1493 /* We are finished with this descriptor ... */
1494 bus_dmamap_sync(sc->dmatag_data_tx, td->dmamap,
1495 BUS_DMASYNC_POSTWRITE);
1496 /* ... and unload, so we can reuse. */
1497 bus_dmamap_unload(sc->dmatag_data_tx, td->dmamap);
1500 sc->tx_cons = (sc->tx_cons + 1) % ECE_MAX_TX_BUFFERS;
1509 ece_cleanup_task(void *arg, int pending __unused)
1511 struct ece_softc *sc = arg;
1512 ECE_CLEANUPLOCK(sc);
1513 ece_cleanup_locked(sc);
1514 ECE_CLEANUPUNLOCK(sc);
1518 ece_intr_tx(void *xsc)
1520 struct ece_softc *sc = xsc;
1521 struct ifnet *ifp = sc->ifp;
1522 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1523 /* This should not happen, stop DMA. */
1524 write_4(sc, FS_DMA_CONTROL, 0);
1527 taskqueue_enqueue(sc->sc_tq, &sc->sc_cleanup_task);
1531 ece_intr_qf(void *xsc)
1533 struct ece_softc *sc = xsc;
1534 struct ifnet *ifp = sc->ifp;
1535 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1536 /* This should not happen, stop DMA. */
1537 write_4(sc, FS_DMA_CONTROL, 0);
1540 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1541 write_4(sc, FS_DMA_CONTROL, 1);
1545 * Reset and initialize the chip
1548 eceinit_locked(void *xsc)
1550 struct ece_softc *sc = xsc;
1551 struct ifnet *ifp = sc->ifp;
1552 struct mii_data *mii;
1554 uint32_t cpu_port_config;
1555 uint32_t mac_port_config;
1558 cfg_reg = read_4(sc, BIST_RESULT_TEST_0);
1559 if ((cfg_reg & (1<<17)))
1563 /* Set to default values. */
1564 write_4(sc, SWITCH_CONFIG, 0x007AA7A1);
1565 write_4(sc, MAC_PORT_0_CONFIG, 0x00423D00);
1566 write_4(sc, MAC_PORT_1_CONFIG, 0x00423D80);
1567 write_4(sc, CPU_PORT_CONFIG, 0x004C0000);
1571 mac_port_config = read_4(sc, MAC_PORT_0_CONFIG);
1574 mac_port_config &= (~(PORT_DISABLE));
1575 write_4(sc, MAC_PORT_0_CONFIG, mac_port_config);
1577 cpu_port_config = read_4(sc, CPU_PORT_CONFIG);
1579 cpu_port_config &= ~(PORT_DISABLE);
1580 write_4(sc, CPU_PORT_CONFIG, cpu_port_config);
1583 * Set 'running' flag, and clear output active flag
1584 * and attempt to start the output
1586 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1587 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1589 mii = device_get_softc(sc->miibus);
1592 write_4(sc, FS_DMA_CONTROL, 1);
1594 callout_reset(&sc->tick_ch, hz, ece_tick, sc);
1598 ece_encap(struct ece_softc *sc, struct mbuf *m0)
1601 bus_dma_segment_t segs[MAX_FRAGMENT];
1603 eth_tx_desc_t *desc = 0;
1612 /* Fetch unused map */
1613 mapp = sc->tx_desc[sc->tx_prod].dmamap;
1615 error = bus_dmamap_load_mbuf_sg(sc->dmatag_ring_tx, mapp,
1620 bus_dmamap_unload(sc->dmatag_ring_tx, mapp);
1621 return ((error != 0) ? error : -1);
1624 desc = &(sc->desc_tx[sc->desc_curr_tx]);
1625 sc->tx_desc[sc->tx_prod].desc = desc;
1626 sc->tx_desc[sc->tx_prod].buff = m0;
1627 desc_no = sc->desc_curr_tx;
1629 for (seg = 0; seg < nsegs; seg++) {
1630 if (desc->cown == 0 ) {
1631 if_printf(ifp, "ERROR: descriptor is still used\n");
1635 desc->length = segs[seg].ds_len;
1636 desc->data_ptr = segs[seg].ds_addr;
1643 if (seg == nsegs - 1) {
1649 csum_flags = m0->m_pkthdr.csum_flags;
1657 desc->interrupt = 1;
1659 if (csum_flags & CSUM_IP) {
1661 if (csum_flags & CSUM_TCP)
1663 if (csum_flags & CSUM_UDP)
1668 sc->desc_curr_tx = (sc->desc_curr_tx + 1) % ECE_MAX_TX_BUFFERS;
1669 if (sc->desc_curr_tx == 0) {
1670 desc = (eth_tx_desc_t *)&(sc->desc_tx[0]);
1674 desc = sc->tx_desc[sc->tx_prod].desc;
1676 sc->tx_prod = (sc->tx_prod + 1) % ECE_MAX_TX_BUFFERS;
1679 * After all descriptors are set, we set the flags to start the
1682 for (seg = 0; seg < nsegs; seg++) {
1685 desc_no = (desc_no + 1) % ECE_MAX_TX_BUFFERS;
1687 desc = (eth_tx_desc_t *)&(sc->desc_tx[0]);
1690 bus_dmamap_sync(sc->dmatag_data_tx, mapp, BUS_DMASYNC_PREWRITE);
1695 * dequeu packets and transmit
1698 ecestart_locked(struct ifnet *ifp)
1700 struct ece_softc *sc;
1702 uint32_t queued = 0;
1705 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1709 bus_dmamap_sync(sc->dmatag_ring_tx,
1711 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1714 /* Get packet from the queue */
1715 IF_DEQUEUE(&ifp->if_snd, m0);
1718 if (ece_encap(sc, m0)) {
1719 IF_PREPEND(&ifp->if_snd, m0);
1720 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1727 bus_dmamap_sync(sc->dmatag_ring_tx, sc->dmamap_ring_tx,
1728 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1729 write_4(sc, TS_DMA_CONTROL, 1);
1736 struct ece_softc *sc = xsc;
1743 ece_tx_task(void *arg, int pending __unused)
1746 ifp = (struct ifnet *)arg;
1751 ecestart(struct ifnet *ifp)
1753 struct ece_softc *sc = ifp->if_softc;
1755 ecestart_locked(ifp);
1760 * Turn off interrupts, and stop the nic. Can be called with sc->ifp
1761 * NULL so be careful.
1764 ecestop(struct ece_softc *sc)
1766 struct ifnet *ifp = sc->ifp;
1767 uint32_t mac_port_config;
1769 write_4(sc, TS_DMA_CONTROL, 0);
1770 write_4(sc, FS_DMA_CONTROL, 0);
1773 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1775 callout_stop(&sc->tick_ch);
1778 mac_port_config = read_4(sc, MAC_PORT_0_CONFIG);
1779 mac_port_config |= (PORT_DISABLE);
1780 write_4(sc, MAC_PORT_0_CONFIG, mac_port_config);
1783 mac_port_config = read_4(sc, MAC_PORT_1_CONFIG);
1784 mac_port_config |= (PORT_DISABLE);
1785 write_4(sc, MAC_PORT_1_CONFIG, mac_port_config);
1787 /* Disable all interrupt status sources. */
1788 write_4(sc, INTERRUPT_MASK, 0x00001FFF);
1790 /* Clear previous interrupt sources. */
1791 write_4(sc, INTERRUPT_STATUS, 0x00001FFF);
1793 write_4(sc, SWITCH_CONFIG, initial_switch_config);
1794 write_4(sc, CPU_PORT_CONFIG, initial_cpu_config);
1795 write_4(sc, MAC_PORT_0_CONFIG, initial_port0_config);
1796 write_4(sc, MAC_PORT_1_CONFIG, initial_port1_config);
1798 clear_mac_entries(sc, 1);
1802 ece_restart(struct ece_softc *sc)
1804 struct ifnet *ifp = sc->ifp;
1806 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1807 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1808 /* Enable port 0. */
1809 write_4(sc, PORT_0_CONFIG,
1810 read_4(sc, PORT_0_CONFIG) & ~(PORT_DISABLE));
1811 write_4(sc, INTERRUPT_MASK, 0x00000000);
1812 write_4(sc, FS_DMA_CONTROL, 1);
1813 callout_reset(&sc->tick_ch, hz, ece_tick, sc);
1817 set_filter(struct ece_softc *sc)
1820 struct ifmultiaddr *ifma;
1821 uint32_t mac_port_config;
1825 clear_mac_entries(sc, 0);
1826 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1827 mac_port_config = read_4(sc, MAC_PORT_0_CONFIG);
1828 mac_port_config &= ~(DISABLE_BROADCAST_PACKET);
1829 mac_port_config &= ~(DISABLE_MULTICAST_PACKET);
1830 write_4(sc, MAC_PORT_0_CONFIG, mac_port_config);
1833 if_maddr_rlock(ifp);
1834 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1835 if (ifma->ifma_addr->sa_family != AF_LINK)
1838 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
1840 if_maddr_runlock(ifp);
1844 eceioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1846 struct ece_softc *sc = ifp->if_softc;
1847 struct mii_data *mii;
1848 struct ifreq *ifr = (struct ifreq *)data;
1849 int mask, error = 0;
1854 if ((ifp->if_flags & IFF_UP) == 0 &&
1855 ifp->if_drv_flags & IFF_DRV_RUNNING) {
1856 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1859 /* Reinitialize card on any parameter change. */
1860 if ((ifp->if_flags & IFF_UP) &&
1861 !(ifp->if_drv_flags & IFF_DRV_RUNNING))
1876 mii = device_get_softc(sc->miibus);
1877 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1880 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1881 if (mask & IFCAP_VLAN_MTU) {
1886 error = ether_ioctl(ifp, cmd, data);
1893 ece_child_detached(device_t dev, device_t child)
1895 struct ece_softc *sc;
1897 sc = device_get_softc(dev);
1898 if (child == sc->miibus)
1903 * MII bus support routines.
1906 ece_miibus_readreg(device_t dev, int phy, int reg)
1908 struct ece_softc *sc;
1909 sc = device_get_softc(dev);
1910 return (phy_read(sc, phy, reg));
1914 ece_miibus_writereg(device_t dev, int phy, int reg, int data)
1916 struct ece_softc *sc;
1917 sc = device_get_softc(dev);
1918 phy_write(sc, phy, reg, data);
1922 static device_method_t ece_methods[] = {
1923 /* Device interface */
1924 DEVMETHOD(device_probe, ece_probe),
1925 DEVMETHOD(device_attach, ece_attach),
1926 DEVMETHOD(device_detach, ece_detach),
1929 DEVMETHOD(bus_child_detached, ece_child_detached),
1932 DEVMETHOD(miibus_readreg, ece_miibus_readreg),
1933 DEVMETHOD(miibus_writereg, ece_miibus_writereg),
1938 static driver_t ece_driver = {
1941 sizeof(struct ece_softc),
1944 DRIVER_MODULE(ece, econaarm, ece_driver, ece_devclass, 0, 0);
1945 DRIVER_MODULE(miibus, ece, miibus_driver, miibus_devclass, 0, 0);
1946 MODULE_DEPEND(ece, miibus, 1, 1, 1);
1947 MODULE_DEPEND(ece, ether, 1, 1, 1);