2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
4 * Copyright (c) 2012 Semihalf.
7 * Developed by Semihalf.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/cpuset.h>
42 #include <sys/module.h>
45 #include <machine/bus.h>
46 #include <machine/intr.h>
47 #include <machine/cpufunc.h>
48 #include <machine/smp.h>
50 #include <arm/mv/mvvar.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54 #include <dev/fdt/fdt_common.h>
57 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \
58 printf(fmt,##args); } while (0)
60 #define debugf(fmt, args...)
63 #define MPIC_INT_ERR 4
64 #define MPIC_INT_MSI 96
66 #define IRQ_MASK 0x3ff
69 #define MPIC_SOFT_INT 0x4
70 #define MPIC_SOFT_INT_DRBL1 (1 << 5)
71 #define MPIC_ERR_CAUSE 0x20
76 #define MPIC_IN_DRBL 0x78
77 #define MPIC_IN_DRBL_MASK 0x7c
80 #define MPIC_IIACK 0xb4
83 #define MPIC_ERR_MASK 0xec0
85 struct mv_mpic_softc {
87 struct resource * mpic_res[3];
88 bus_space_tag_t mpic_bst;
89 bus_space_handle_t mpic_bsh;
90 bus_space_tag_t cpu_bst;
91 bus_space_handle_t cpu_bsh;
92 bus_space_tag_t drbl_bst;
93 bus_space_handle_t drbl_bsh;
96 static struct resource_spec mv_mpic_spec[] = {
97 { SYS_RES_MEMORY, 0, RF_ACTIVE },
98 { SYS_RES_MEMORY, 1, RF_ACTIVE },
99 { SYS_RES_MEMORY, 2, RF_ACTIVE },
103 static struct mv_mpic_softc *mv_mpic_sc = NULL;
105 void mpic_send_ipi(int cpus, u_int ipi);
107 static int mv_mpic_probe(device_t);
108 static int mv_mpic_attach(device_t);
109 uint32_t mv_mpic_get_cause(void);
110 uint32_t mv_mpic_get_cause_err(void);
111 uint32_t mv_mpic_get_msi(void);
112 static void arm_mask_irq_err(uintptr_t);
113 static void arm_unmask_irq_err(uintptr_t);
114 static void arm_unmask_msi(void);
116 #define MPIC_CPU_WRITE(softc, reg, val) \
117 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val))
118 #define MPIC_CPU_READ(softc, reg) \
119 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg))
121 #define MPIC_DRBL_WRITE(softc, reg, val) \
122 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val))
123 #define MPIC_DRBL_READ(softc, reg) \
124 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg))
127 mv_mpic_probe(device_t dev)
130 if (!ofw_bus_status_okay(dev))
133 if (!ofw_bus_is_compatible(dev, "mrvl,mpic"))
136 device_set_desc(dev, "Marvell Integrated Interrupt Controller");
141 mv_mpic_attach(device_t dev)
143 struct mv_mpic_softc *sc;
146 sc = (struct mv_mpic_softc *)device_get_softc(dev);
148 if (mv_mpic_sc != NULL)
154 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res);
156 device_printf(dev, "could not allocate resources\n");
160 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]);
161 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]);
163 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]);
164 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]);
166 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]);
167 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]);
169 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
171 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
178 static device_method_t mv_mpic_methods[] = {
179 DEVMETHOD(device_probe, mv_mpic_probe),
180 DEVMETHOD(device_attach, mv_mpic_attach),
184 static driver_t mv_mpic_driver = {
187 sizeof(struct mv_mpic_softc),
190 static devclass_t mv_mpic_devclass;
192 DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0);
195 arm_get_next_irq(int last)
197 u_int irq, next = -1;
199 irq = mv_mpic_get_cause() & IRQ_MASK;
200 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq);
202 if (irq != IRQ_MASK) {
203 if (irq == MPIC_INT_ERR)
204 irq = mv_mpic_get_cause_err();
205 if (irq == MPIC_INT_MSI)
206 irq = mv_mpic_get_msi();
210 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
215 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only
216 * by ISM/ICM and remove access to ICE in masking operation
219 arm_mask_irq(uintptr_t nb)
222 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1);
225 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
227 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
228 } else if (nb < MSI_IRQ)
229 arm_mask_irq_err(nb);
234 arm_mask_irq_err(uintptr_t nb)
239 bit_off = nb - ERR_IRQ;
240 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
241 mask &= ~(1 << bit_off);
242 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
246 arm_unmask_irq(uintptr_t nb)
249 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0);
252 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
254 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
255 } else if (nb < MSI_IRQ)
256 arm_unmask_irq_err(nb);
259 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff);
263 arm_unmask_irq_err(uintptr_t nb)
268 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
269 MPIC_ISE, MPIC_INT_ERR);
270 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR);
272 bit_off = nb - ERR_IRQ;
273 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK);
274 mask |= (1 << bit_off);
275 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask);
282 arm_unmask_irq(MPIC_INT_MSI);
286 mv_mpic_get_cause(void)
289 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK));
293 mv_mpic_get_cause_err(void)
298 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst,
299 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE);
302 bit_off = ffs(err_cause) - 1;
306 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause);
307 return (ERR_IRQ + bit_off);
311 mv_mpic_get_msi(void)
316 cause = MPIC_DRBL_READ(mv_mpic_sc, 0);
319 bit_off = ffs(cause) - 1;
323 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause);
325 cause &= ~(1 << bit_off);
326 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause);
328 return (MSI_IRQ + bit_off);
332 mv_msi_data(int irq, uint64_t *addr, uint32_t *data)
334 u_long phys, base, size;
338 node = ofw_bus_get_node(mv_mpic_sc->sc_dev);
340 /* Get physical addres of register space */
341 error = fdt_get_range(OF_parent(node), 0, &phys, &size);
343 printf("%s: Cannot get register physical address, err:%d",
348 /* Get offset of MPIC register space */
349 error = fdt_regsize(node, &base, &size);
351 printf("%s: Cannot get MPIC register offset, err:%d",
356 *addr = phys + base + MPIC_SOFT_INT;
357 *data = MPIC_SOFT_INT_DRBL1 | irq;
364 pic_ipi_send(cpuset_t cpus, u_int ipi)
369 for (i = 0; i < MAXCPU; i++)
370 if (CPU_ISSET(i, &cpus))
371 val |= (1 << (8 + i));
373 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh,
378 pic_ipi_get(int i __unused)
383 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL);
386 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi));
394 pic_ipi_clear(int ipi)