2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Samsung Exynos 5 Pad Control
29 * Chapter 4, Exynos 5 Dual User's Manual Public Rev 1.00
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/malloc.h>
42 #include <sys/timeet.h>
43 #include <sys/timetc.h>
44 #include <sys/watchdog.h>
45 #include <sys/mutex.h>
48 #include <dev/fdt/fdt_common.h>
49 #include <dev/ofw/openfirm.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
53 #include <machine/bus.h>
54 #include <machine/fdt.h>
55 #include <machine/cpu.h>
56 #include <machine/intr.h>
60 #include <arm/samsung/exynos/exynos5_combiner.h>
61 #include <arm/samsung/exynos/exynos5_pad.h>
63 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
64 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
66 #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
76 #define READ4(_sc, _port, _reg) \
77 bus_space_read_4(_sc->bst[_port], _sc->bsh[_port], _reg)
78 #define WRITE4(_sc, _port, _reg, _val) \
79 bus_space_write_4(_sc->bst[_port], _sc->bsh[_port], _reg, _val)
84 static int pad_pin_max(device_t, int *);
85 static int pad_pin_getcaps(device_t, uint32_t, uint32_t *);
86 static int pad_pin_getname(device_t, uint32_t, char *);
87 static int pad_pin_getflags(device_t, uint32_t, uint32_t *);
88 static int pad_pin_setflags(device_t, uint32_t, uint32_t);
89 static int pad_pin_set(device_t, uint32_t, unsigned int);
90 static int pad_pin_get(device_t, uint32_t, unsigned int *);
91 static int pad_pin_toggle(device_t, uint32_t pin);
94 struct resource *res[NPORTS+4];
95 bus_space_tag_t bst[NPORTS];
96 bus_space_handle_t bsh[NPORTS];
99 struct gpio_pin gpio_pins[NGPIO];
100 void *gpio_ih[NPORTS+4];
104 struct pad_softc *gpio_sc;
106 static struct resource_spec pad_spec[] = {
107 { SYS_RES_MEMORY, 0, RF_ACTIVE },
108 { SYS_RES_MEMORY, 1, RF_ACTIVE },
109 { SYS_RES_MEMORY, 2, RF_ACTIVE },
110 { SYS_RES_MEMORY, 3, RF_ACTIVE },
111 { SYS_RES_IRQ, 0, RF_ACTIVE },
112 { SYS_RES_IRQ, 1, RF_ACTIVE },
113 { SYS_RES_IRQ, 2, RF_ACTIVE },
114 { SYS_RES_IRQ, 3, RF_ACTIVE },
124 static struct pad_intr intr_map[NGPIO];
126 struct interrupt_entry {
128 char *combiner_source_name;
131 struct interrupt_entry interrupt_table[NINTS] = {
155 uint32_t ext_int_grp;
157 uint32_t ext_flt_con;
163 * 253 multi-functional input/output ports
166 static struct gpio_bank gpio_map[] = {
168 { "gpa0", 0, 0x000, 8, 1, 0x700, 0x800, 0x900, 0xA00 },
169 { "gpa1", 0, 0x020, 6, 2, 0x704, 0x808, 0x904, 0xA04 },
170 { "gpa2", 0, 0x040, 8, 3, 0x708, 0x810, 0x908, 0xA08 },
171 { "gpb0", 0, 0x060, 5, 4, 0x70C, 0x818, 0x90C, 0xA0C },
172 { "gpb1", 0, 0x080, 5, 5, 0x710, 0x820, 0x910, 0xA10 },
173 { "gpb2", 0, 0x0A0, 4, 6, 0x714, 0x828, 0x914, 0xA14 },
174 { "gpb3", 0, 0x0C0, 4, 7, 0x718, 0x830, 0x918, 0xA18 },
175 { "gpc0", 0, 0x0E0, 7, 8, 0x71C, 0x838, 0x91C, 0xA1C },
176 { "gpc1", 0, 0x100, 4, 9, 0x720, 0x840, 0x920, 0xA20 },
177 { "gpc2", 0, 0x120, 7, 10, 0x724, 0x848, 0x924, 0xA24 },
178 { "gpc3", 0, 0x140, 7, 11, 0x728, 0x850, 0x928, 0xA28 },
179 { "gpd0", 0, 0x160, 4, 12, 0x72C, 0x858, 0x92C, 0xA2C },
180 { "gpd1", 0, 0x180, 8, 13, 0x730, 0x860, 0x930, 0xA30 },
181 { "gpy0", 0, 0x1A0, 6, 0, 0, 0, 0, 0 },
182 { "gpy1", 0, 0x1C0, 4, 0, 0, 0, 0, 0 },
183 { "gpy2", 0, 0x1E0, 6, 0, 0, 0, 0, 0 },
184 { "gpy3", 0, 0x200, 8, 0, 0, 0, 0, 0 },
185 { "gpy4", 0, 0x220, 8, 0, 0, 0, 0, 0 },
186 { "gpy5", 0, 0x240, 8, 0, 0, 0, 0, 0 },
187 { "gpy6", 0, 0x260, 8, 0, 0, 0, 0, 0 },
188 { "gpc4", 0, 0x2E0, 7, 30, 0x734, 0x868, 0x934, 0xA34 },
191 { "gpx0", 0, 0xC00, 8, 40, 0xE00, 0xE80, 0xF00, 0xF40 },
192 { "gpx1", 0, 0xC20, 8, 41, 0xE04, 0xE88, 0xF04, 0xF44 },
193 { "gpx2", 0, 0xC40, 8, 42, 0xE08, 0xE90, 0xF08, 0xF48 },
194 { "gpx3", 0, 0xC60, 8, 43, 0xE0C, 0xE98, 0xF0C, 0xF4C },
196 { "gpe0", 1, 0x000, 8, 14, 0x700, 0x800, 0x900, 0xA00 },
197 { "gpe1", 1, 0x020, 2, 15, 0x704, 0x808, 0x904, 0xA04 },
198 { "gpf0", 1, 0x040, 4, 16, 0x708, 0x810, 0x908, 0xA08 },
199 { "gpf1", 1, 0x060, 4, 17, 0x70C, 0x818, 0x90C, 0xA0C },
200 { "gpg0", 1, 0x080, 8, 18, 0x710, 0x820, 0x910, 0xA10 },
201 { "gpg1", 1, 0x0A0, 8, 19, 0x714, 0x828, 0x914, 0xA14 },
202 { "gpg2", 1, 0x0C0, 2, 20, 0x718, 0x830, 0x918, 0xA18 },
203 { "gph0", 1, 0x0E0, 4, 21, 0x71C, 0x838, 0x91C, 0xA1C },
204 { "gph1", 1, 0x100, 8, 22, 0x720, 0x840, 0x920, 0xA20 },
206 { "gpv0", 2, 0x000, 8, 60, 0x700, 0x800, 0x900, 0xA00 },
207 { "gpv1", 2, 0x020, 8, 61, 0x704, 0x808, 0x904, 0xA04 },
208 { "gpv2", 2, 0x060, 8, 62, 0x708, 0x810, 0x908, 0xA08 },
209 { "gpv3", 2, 0x080, 8, 63, 0x70C, 0x818, 0x90C, 0xA0C },
210 { "gpv4", 2, 0x0C0, 2, 64, 0x710, 0x820, 0x910, 0xA10 },
212 { "gpz", 3, 0x000, 7, 50, 0x700, 0x800, 0x900, 0xA00 },
216 get_bank(int gpio_number, struct gpio_bank *bank, int *pin_shift)
223 for (i = 0; i < NGRP; i++) {
224 ngpio = gpio_map[i].ngpio;
226 if ((n + ngpio) >= gpio_number) {
228 *pin_shift = (gpio_number - n);
241 struct port_softc *sc;
245 return (FILTER_HANDLED);
251 struct pad_softc *sc;
263 for (i = 0; i < NGRP; i++) {
265 ngpio = gpio_map[i].ngpio;
267 if (gpio_map[i].pend == 0) {
272 reg = READ4(sc, gpio_map[i].port, gpio_map[i].pend);
274 for (j = 0; j < ngpio; j++) {
275 if (reg & (1 << j)) {
279 if (intr_map[k].enabled == 1) {
281 ih_user = intr_map[k].ih_user;
289 WRITE4(sc, gpio_map[i].port, gpio_map[i].pend, reg);
297 pad_setup_intr(int gpio_number, void (*ih)(void *), void *ih_user)
299 struct interrupt_entry *entry;
300 struct pad_intr *pad_irq;
301 struct gpio_bank bank;
302 struct pad_softc *sc;
310 device_printf(sc->dev, "Error: pad is not attached\n");
314 if (get_bank(gpio_number, &bank, &pin_shift) != 0)
318 for (i = 0; i < NINTS; i++)
319 if (interrupt_table[i].gpio_number == gpio_number)
320 entry = &interrupt_table[i];
323 device_printf(sc->dev, "Cant find interrupt source for %d\n",
329 printf("Request interrupt name %s\n", entry->combiner_source_name);
332 pad_irq = &intr_map[gpio_number];
333 pad_irq->enabled = 1;
335 pad_irq->ih_user = ih_user;
337 /* Setup port as external interrupt source */
338 reg = READ4(sc, bank.port, bank.con);
339 reg |= (0xf << (pin_shift * 4));
341 printf("writing 0x%08x to 0x%08x\n", reg, bank.con);
343 WRITE4(sc, bank.port, bank.con, reg);
346 * Configure interrupt pin
348 * 0x0 = Sets Low level
349 * 0x1 = Sets High level
350 * 0x2 = Triggers Falling edge
351 * 0x3 = Triggers Rising edge
352 * 0x4 = Triggers Both edge
354 * TODO: add parameter. For now configure as 0x0
356 reg = READ4(sc, bank.port, bank.ext_con);
357 reg &= ~(0x7 << (pin_shift * 4));
358 WRITE4(sc, bank.port, bank.ext_con, reg);
361 reg = READ4(sc, bank.port, bank.mask);
362 reg &= ~(1 << pin_shift);
363 WRITE4(sc, bank.port, bank.mask, reg);
365 combiner_setup_intr(entry->combiner_source_name, ext_intr, sc);
371 pad_probe(device_t dev)
374 if (!ofw_bus_status_okay(dev))
377 if (!ofw_bus_is_compatible(dev, "exynos,pad"))
380 device_set_desc(dev, "Exynos Pad Control");
381 return (BUS_PROBE_DEFAULT);
385 pad_attach(device_t dev)
387 struct gpio_bank bank;
388 struct pad_softc *sc;
393 sc = device_get_softc(dev);
394 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
396 if (bus_alloc_resources(dev, pad_spec, sc->res)) {
397 device_printf(dev, "could not allocate resources\n");
401 /* Memory interface */
403 for (i = 0; i < NPORTS; i++) {
404 sc->bst[i] = rman_get_bustag(sc->res[i]);
405 sc->bsh[i] = rman_get_bushandle(sc->res[i]);
409 sc->gpio_npins = NGPIO;
413 for (i = 0; i < NPORTS; i++) {
414 if ((bus_setup_intr(dev, sc->res[NPORTS + i],
415 INTR_TYPE_BIO | INTR_MPSAFE, port_intr,
416 NULL, sc, &sc->gpio_ih[i]))) {
418 "ERROR: Unable to register interrupt handler\n");
423 for (i = 0; i < sc->gpio_npins; i++) {
424 sc->gpio_pins[i].gp_pin = i;
425 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
427 if (get_bank(i, &bank, &pin_shift) != 0)
432 reg = READ4(sc, bank.port, bank.con);
433 if (reg & (PIN_OUT << pin_shift))
434 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
436 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
438 /* TODO: add other pin statuses */
440 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
441 "pad%d.%d", device_get_unit(dev), i);
444 device_add_child(dev, "gpioc", -1);
445 device_add_child(dev, "gpiobus", -1);
447 return (bus_generic_attach(dev));
451 pad_pin_max(device_t dev, int *maxpin)
459 pad_pin_getname(device_t dev, uint32_t pin, char *name)
461 struct pad_softc *sc;
464 sc = device_get_softc(dev);
465 for (i = 0; i < sc->gpio_npins; i++) {
466 if (sc->gpio_pins[i].gp_pin == pin)
470 if (i >= sc->gpio_npins)
474 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
481 pad_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
483 struct pad_softc *sc;
486 sc = device_get_softc(dev);
487 for (i = 0; i < sc->gpio_npins; i++) {
488 if (sc->gpio_pins[i].gp_pin == pin)
492 if (i >= sc->gpio_npins)
496 *caps = sc->gpio_pins[i].gp_caps;
503 pad_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
505 struct pad_softc *sc;
508 sc = device_get_softc(dev);
509 for (i = 0; i < sc->gpio_npins; i++) {
510 if (sc->gpio_pins[i].gp_pin == pin)
514 if (i >= sc->gpio_npins)
518 *flags = sc->gpio_pins[i].gp_flags;
525 pad_pin_get(device_t dev, uint32_t pin, unsigned int *val)
527 struct gpio_bank bank;
528 struct pad_softc *sc;
532 sc = device_get_softc(dev);
533 for (i = 0; i < sc->gpio_npins; i++) {
534 if (sc->gpio_pins[i].gp_pin == pin)
538 if (i >= sc->gpio_npins)
541 if (get_bank(pin, &bank, &pin_shift) != 0)
545 if (READ4(sc, bank.port, bank.con + 0x4) & (1 << pin_shift))
555 pad_pin_toggle(device_t dev, uint32_t pin)
557 struct gpio_bank bank;
558 struct pad_softc *sc;
563 sc = device_get_softc(dev);
564 for (i = 0; i < sc->gpio_npins; i++) {
565 if (sc->gpio_pins[i].gp_pin == pin)
569 if (i >= sc->gpio_npins)
572 if (get_bank(pin, &bank, &pin_shift) != 0)
576 reg = READ4(sc, bank.port, bank.con + 0x4);
577 if (reg & (1 << pin_shift))
578 reg &= ~(1 << pin_shift);
580 reg |= (1 << pin_shift);
581 WRITE4(sc, bank.port, bank.con + 0x4, reg);
589 pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin,
592 struct gpio_bank bank;
599 * Manage input/output
601 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
602 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
604 if (get_bank(pin->gp_pin, &bank, &pin_shift) != 0)
610 printf("bank is 0x%08x pin_shift %d\n", bank.con, pin_shift);
613 if (flags & GPIO_PIN_OUTPUT) {
614 pin->gp_flags |= GPIO_PIN_OUTPUT;
615 reg = READ4(sc, bank.port, bank.con);
616 reg &= ~(0xf << pin_shift);
617 reg |= (PIN_OUT << pin_shift);
618 WRITE4(sc, bank.port, bank.con, reg);
620 pin->gp_flags |= GPIO_PIN_INPUT;
621 reg = READ4(sc, bank.port, bank.con);
622 reg &= ~(0xf << pin_shift);
623 WRITE4(sc, bank.port, bank.con, reg);
632 pad_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
634 struct pad_softc *sc;
637 sc = device_get_softc(dev);
638 for (i = 0; i < sc->gpio_npins; i++) {
639 if (sc->gpio_pins[i].gp_pin == pin)
643 if (i >= sc->gpio_npins)
646 pad_pin_configure(sc, &sc->gpio_pins[i], flags);
652 pad_pin_set(device_t dev, uint32_t pin, unsigned int value)
654 struct pad_softc *sc;
655 struct gpio_bank bank;
660 sc = device_get_softc(dev);
661 for (i = 0; i < sc->gpio_npins; i++) {
662 if (sc->gpio_pins[i].gp_pin == pin)
666 if (i >= sc->gpio_npins)
669 if (get_bank(pin, &bank, &pin_shift) != 0)
673 reg = READ4(sc, bank.port, bank.con + 0x4);
674 reg &= ~(PIN_OUT << pin_shift);
676 reg |= (PIN_OUT << pin_shift);
677 WRITE4(sc, bank.port, bank.con + 0x4, reg);
683 static device_method_t pad_methods[] = {
684 DEVMETHOD(device_probe, pad_probe),
685 DEVMETHOD(device_attach, pad_attach),
688 DEVMETHOD(gpio_pin_max, pad_pin_max),
689 DEVMETHOD(gpio_pin_getname, pad_pin_getname),
690 DEVMETHOD(gpio_pin_getcaps, pad_pin_getcaps),
691 DEVMETHOD(gpio_pin_getflags, pad_pin_getflags),
692 DEVMETHOD(gpio_pin_get, pad_pin_get),
693 DEVMETHOD(gpio_pin_toggle, pad_pin_toggle),
694 DEVMETHOD(gpio_pin_setflags, pad_pin_setflags),
695 DEVMETHOD(gpio_pin_set, pad_pin_set),
699 static driver_t pad_driver = {
702 sizeof(struct pad_softc),
705 static devclass_t pad_devclass;
707 DRIVER_MODULE(pad, simplebus, pad_driver, pad_devclass, 0, 0);