2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/malloc.h>
38 #include <sys/taskqueue.h>
39 #include <sys/timeet.h>
40 #include <sys/timepps.h>
41 #include <sys/timetc.h>
42 #include <sys/watchdog.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/intr.h>
47 #include <dev/fdt/fdt_common.h>
48 #include <dev/ofw/openfirm.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
52 #include <machine/bus.h>
53 #include <machine/fdt.h>
55 #include <arm/ti/ti_prcm.h>
56 #include <arm/ti/ti_scm.h>
58 #define AM335X_NUM_TIMERS 8
60 #define DMT_TIDR 0x00 /* Identification Register */
61 #define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */
62 #define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */
63 #define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */
64 #define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */
65 #define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */
66 #define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */
67 #define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */
68 #define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */
69 #define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */
70 #define DMT_IRQ_OVF (1 << 1) /* IRQ: Overflow */
71 #define DMT_IRQ_TCAR (1 << 2) /* IRQ: Capture */
72 #define DMT_IRQ_MASK (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT)
73 #define DMT_TCLR 0x38 /* Control Register */
74 #define DMT_TCLR_START (1 << 0) /* Start timer */
75 #define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */
76 #define DMT_TCLR_PRES_MASK (7 << 2) /* Prescaler mask */
77 #define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */
78 #define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */
79 #define DMT_TCLR_PWM_HIGH (1 << 7) /* PWM default output high */
80 #define DMT_TCLR_CAPTRAN_MASK (3 << 8) /* Capture transition mask */
81 #define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */
82 #define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */
83 #define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */
84 #define DMT_TCLR_CAPTRAN_BOTH (3 << 8) /* Capture both transitions */
85 #define DMT_TCLR_TRGMODE_MASK (3 << 10) /* Trigger output mode mask */
86 #define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */
87 #define DMT_TCLR_TRGMODE_OVFL (1 << 10) /* Trigger on overflow */
88 #define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */
89 #define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */
90 #define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */
91 #define DMT_TCLR_GPO_CFG (1 << 14) /* (no descr in datasheet) */
92 #define DMT_TCRR 0x3C /* Counter Register */
93 #define DMT_TLDR 0x40 /* Load Reg */
94 #define DMT_TTGR 0x44 /* Trigger Reg */
95 #define DMT_TWPS 0x48 /* Write Posted Status Reg */
96 #define DMT_TMAR 0x4C /* Match Reg */
97 #define DMT_TCAR1 0x50 /* Capture Reg */
98 #define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */
99 #define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */
100 #define DMT_TCAR2 0x48 /* Capture Reg */
103 * Use timer 2 for the eventtimer. When PPS support is not compiled in, there's
104 * no need to use a timer that has an associated capture-input pin, so use timer
105 * 3 for timecounter. When PPS is compiled in we ignore the default and use
106 * whichever of timers 4-7 have the capture pin configured.
108 #define DEFAULT_ET_TIMER 2
109 #define DEFAULT_TC_TIMER 3
111 struct am335x_dmtimer_softc {
112 struct resource * tmr_mem_res[AM335X_NUM_TIMERS];
113 struct resource * tmr_irq_res[AM335X_NUM_TIMERS];
114 uint32_t sysclk_freq;
115 uint32_t tc_num; /* Which timer number is tc. */
116 uint32_t tc_tclr; /* Cached tc TCLR register. */
117 struct resource * tc_memres; /* Resources for tc timer. */
118 uint32_t et_num; /* Which timer number is et. */
119 uint32_t et_tclr; /* Cached et TCLR register. */
120 struct resource * et_memres; /* Resources for et timer. */
121 int pps_curmode; /* Edge mode now set in hw. */
122 struct task pps_task; /* For pps_event handling. */
123 struct cdev * pps_cdev;
124 struct pps_state pps;
125 struct timecounter tc;
126 struct eventtimer et;
129 static struct am335x_dmtimer_softc *am335x_dmtimer_sc;
131 static struct resource_spec am335x_dmtimer_mem_spec[] = {
132 { SYS_RES_MEMORY, 0, RF_ACTIVE },
133 { SYS_RES_MEMORY, 1, RF_ACTIVE },
134 { SYS_RES_MEMORY, 2, RF_ACTIVE },
135 { SYS_RES_MEMORY, 3, RF_ACTIVE },
136 { SYS_RES_MEMORY, 4, RF_ACTIVE },
137 { SYS_RES_MEMORY, 5, RF_ACTIVE },
138 { SYS_RES_MEMORY, 6, RF_ACTIVE },
139 { SYS_RES_MEMORY, 7, RF_ACTIVE },
142 static struct resource_spec am335x_dmtimer_irq_spec[] = {
143 { SYS_RES_IRQ, 0, RF_ACTIVE },
144 { SYS_RES_IRQ, 1, RF_ACTIVE },
145 { SYS_RES_IRQ, 2, RF_ACTIVE },
146 { SYS_RES_IRQ, 3, RF_ACTIVE },
147 { SYS_RES_IRQ, 4, RF_ACTIVE },
148 { SYS_RES_IRQ, 5, RF_ACTIVE },
149 { SYS_RES_IRQ, 6, RF_ACTIVE },
150 { SYS_RES_IRQ, 7, RF_ACTIVE },
154 static inline uint32_t
155 am335x_dmtimer_tc_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
158 return (bus_read_4(sc->tc_memres, reg));
162 am335x_dmtimer_tc_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
166 bus_write_4(sc->tc_memres, reg, val);
169 static inline uint32_t
170 am335x_dmtimer_et_read_4(struct am335x_dmtimer_softc *sc, uint32_t reg)
173 return (bus_read_4(sc->et_memres, reg));
177 am335x_dmtimer_et_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
181 bus_write_4(sc->et_memres, reg, val);
185 * PPS driver routines, included when the kernel is built with option PPS_SYNC.
187 * Note that this PPS driver does not use an interrupt. Instead it uses the
188 * hardware's ability to latch the timer's count register in response to a
189 * signal on an IO pin. Each of timers 4-7 have an associated pin, and this
190 * code allows any one of those to be used.
192 * The timecounter routines in kern_tc.c call the pps poll routine periodically
193 * to see if a new counter value has been latched. When a new value has been
194 * latched, the only processing done in the poll routine is to capture the
195 * current set of timecounter timehands (done with pps_capture()) and the
196 * latched value from the timer. The remaining work (done by pps_event()) is
197 * scheduled to be done later in a non-interrupt context.
200 #define PPS_CDEV_NAME "dmtpps"
203 am335x_dmtimer_set_capture_mode(struct am335x_dmtimer_softc *sc, bool force_off)
210 newmode = sc->pps.ppsparam.mode & PPS_CAPTUREBOTH;
212 if (newmode == sc->pps_curmode)
215 sc->pps_curmode = newmode;
216 sc->tc_tclr &= ~DMT_TCLR_CAPTRAN_MASK;
218 case PPS_CAPTUREASSERT:
219 sc->tc_tclr |= DMT_TCLR_CAPTRAN_LOHI;
221 case PPS_CAPTURECLEAR:
222 sc->tc_tclr |= DMT_TCLR_CAPTRAN_HILO;
225 /* It can't be BOTH, so it's disabled. */
228 am335x_dmtimer_tc_write_4(sc, DMT_TCLR, sc->tc_tclr);
232 am335x_dmtimer_tc_poll_pps(struct timecounter *tc)
234 struct am335x_dmtimer_softc *sc;
239 * Note that we don't have the TCAR interrupt enabled, but the hardware
240 * still provides the status bits in the "RAW" status register even when
241 * they're masked from generating an irq. However, when clearing the
242 * TCAR status to re-arm the capture for the next second, we have to
243 * write to the IRQ status register, not the RAW register. Quirky.
245 if (am335x_dmtimer_tc_read_4(sc, DMT_IRQSTATUS_RAW) & DMT_IRQ_TCAR) {
246 pps_capture(&sc->pps);
247 sc->pps.capcount = am335x_dmtimer_tc_read_4(sc, DMT_TCAR1);
248 am335x_dmtimer_tc_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_TCAR);
249 taskqueue_enqueue_fast(taskqueue_fast, &sc->pps_task);
254 am335x_dmtimer_process_pps_event(void *arg, int pending)
256 struct am335x_dmtimer_softc *sc;
260 /* This is the task function that gets enqueued by poll_pps. Once the
261 * time has been captured in the hw interrupt context, the remaining
262 * (more expensive) work to process the event is done later in a
263 * non-fast-interrupt context.
265 * We only support capture of the rising or falling edge, not both at
266 * once; tell the kernel to process whichever mode is currently active.
268 pps_event(&sc->pps, sc->pps.ppsparam.mode & PPS_CAPTUREBOTH);
272 am335x_dmtimer_pps_open(struct cdev *dev, int flags, int fmt,
275 struct am335x_dmtimer_softc *sc;
279 /* Enable capture on open. Harmless if already open. */
280 am335x_dmtimer_set_capture_mode(sc, 0);
286 am335x_dmtimer_pps_close(struct cdev *dev, int flags, int fmt,
289 struct am335x_dmtimer_softc *sc;
294 * Disable capture on last close. Use the force-off flag to override
295 * the configured mode and turn off the hardware capture.
297 am335x_dmtimer_set_capture_mode(sc, 1);
303 am335x_dmtimer_pps_ioctl(struct cdev *dev, u_long cmd, caddr_t data,
304 int flags, struct thread *td)
306 struct am335x_dmtimer_softc *sc;
312 * The hardware has a "capture both edges" mode, but we can't do
313 * anything useful with it in terms of PPS capture, so don't even try.
315 if ((sc->pps.ppsparam.mode & PPS_CAPTUREBOTH) == PPS_CAPTUREBOTH)
318 /* Let the kernel do the heavy lifting for ioctl. */
319 err = pps_ioctl(cmd, data, &sc->pps);
324 * The capture mode could have changed, set the hardware to whatever
325 * mode is now current. Effectively a no-op if nothing changed.
327 am335x_dmtimer_set_capture_mode(sc, 0);
332 static struct cdevsw am335x_dmtimer_pps_cdevsw = {
333 .d_version = D_VERSION,
334 .d_open = am335x_dmtimer_pps_open,
335 .d_close = am335x_dmtimer_pps_close,
336 .d_ioctl = am335x_dmtimer_pps_ioctl,
337 .d_name = PPS_CDEV_NAME,
341 * Set up the PPS cdev and the the kernel timepps stuff.
343 * Note that this routine cannot touch the hardware, because bus space resources
344 * are not fully set up yet when this is called.
347 am335x_dmtimer_pps_init(device_t dev, struct am335x_dmtimer_softc *sc)
349 int i, timer_num, unit;
350 unsigned int padstate;
357 {"GPMC_ADVn_ALE", "timer4", 4},
358 {"GPMC_BEn0_CLE", "timer5", 5},
359 {"GPMC_WEn", "timer6", 6},
360 {"GPMC_OEn_REn", "timer7", 7},
364 * Figure out which pin the user has set up for pps. We'll use the
365 * first timer that has an external caputure pin configured as input.
367 * XXX The hieroglyphic "(padstate & (0x01 << 5)))" checks that the pin
368 * is configured for input. The right symbolic values aren't exported
372 for (i = 0; i < nitems(padinfo) && timer_num == 0; ++i) {
373 if (ti_scm_padconf_get(padinfo[i].ballname, &padmux,
375 if (strcasecmp(padinfo[i].muxname, padmux) == 0 &&
376 (padstate & (0x01 << 5)))
377 timer_num = padinfo[i].timer_num;
381 if (timer_num == 0) {
382 device_printf(dev, "No DMTimer found with capture pin "
383 "configured as input; PPS driver disabled.\n");
384 return (DEFAULT_TC_TIMER);
388 * Indicate our capabilities (pretty much just capture of either edge).
389 * Have the kernel init its part of the pps_state struct and add its
392 sc->pps.ppscap = PPS_CAPTUREBOTH;
396 * Set up to capture the PPS via timecounter polling, and init the task
397 * that does deferred pps_event() processing after capture.
399 sc->tc.tc_poll_pps = am335x_dmtimer_tc_poll_pps;
400 TASK_INIT(&sc->pps_task, 0, am335x_dmtimer_process_pps_event, sc);
402 /* Create the PPS cdev. */
403 unit = device_get_unit(dev);
404 sc->pps_cdev = make_dev(&am335x_dmtimer_pps_cdevsw, unit,
405 UID_ROOT, GID_WHEEL, 0600, PPS_CDEV_NAME);
406 sc->pps_cdev->si_drv1 = sc;
408 device_printf(dev, "Using DMTimer%d for PPS device /dev/%s%d\n",
409 timer_num, PPS_CDEV_NAME, unit);
415 * End of PPS driver code.
419 am335x_dmtimer_tc_get_timecount(struct timecounter *tc)
421 struct am335x_dmtimer_softc *sc;
425 return (am335x_dmtimer_tc_read_4(sc, DMT_TCRR));
429 am335x_dmtimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
431 struct am335x_dmtimer_softc *sc;
432 uint32_t initial_count, reload_count;
437 * Stop the timer before changing it. This routine will often be called
438 * while the timer is still running, to either lengthen or shorten the
439 * current event time. We need to ensure the timer doesn't expire while
440 * we're working with it.
442 * Also clear any pending interrupt status, because it's at least
443 * theoretically possible that we're running in a primary interrupt
444 * context now, and a timer interrupt could be pending even before we
445 * stopped the timer. The more likely case is that we're being called
446 * from the et_event_cb() routine dispatched from our own handler, but
447 * it's not clear to me that that's the only case possible.
449 sc->et_tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
450 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
451 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
454 reload_count = ((uint32_t)et->et_frequency * period) >> 32;
455 sc->et_tclr |= DMT_TCLR_AUTOLOAD;
461 initial_count = ((uint32_t)et->et_frequency * first) >> 32;
463 initial_count = reload_count;
466 * Set auto-reload and current-count values. This timer hardware counts
467 * up from the initial/reload value and interrupts on the zero rollover.
469 am335x_dmtimer_et_write_4(sc, DMT_TLDR, 0xFFFFFFFF - reload_count);
470 am335x_dmtimer_et_write_4(sc, DMT_TCRR, 0xFFFFFFFF - initial_count);
472 /* Enable overflow interrupt, and start the timer. */
473 am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_SET, DMT_IRQ_OVF);
474 sc->et_tclr |= DMT_TCLR_START;
475 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
481 am335x_dmtimer_stop(struct eventtimer *et)
483 struct am335x_dmtimer_softc *sc;
487 /* Stop timer, disable and clear interrupt. */
488 sc->et_tclr &= ~(DMT_TCLR_START | DMT_TCLR_AUTOLOAD);
489 am335x_dmtimer_et_write_4(sc, DMT_TCLR, sc->et_tclr);
490 am335x_dmtimer_et_write_4(sc, DMT_IRQENABLE_CLR, DMT_IRQ_OVF);
491 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
496 am335x_dmtimer_intr(void *arg)
498 struct am335x_dmtimer_softc *sc;
502 /* Ack the interrupt, and invoke the callback if it's still enabled. */
503 am335x_dmtimer_et_write_4(sc, DMT_IRQSTATUS, DMT_IRQ_OVF);
504 if (sc->et.et_active)
505 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
507 return (FILTER_HANDLED);
511 am335x_dmtimer_probe(device_t dev)
514 if (!ofw_bus_status_okay(dev))
517 if (ofw_bus_is_compatible(dev, "ti,am335x-dmtimer")) {
518 device_set_desc(dev, "AM335x DMTimer");
519 return(BUS_PROBE_DEFAULT);
526 am335x_dmtimer_attach(device_t dev)
528 struct am335x_dmtimer_softc *sc;
533 * Note that if this routine returns an error status rather than running
534 * to completion it makes no attempt to clean up allocated resources;
535 * the system is essentially dead anyway without functional timers.
538 sc = device_get_softc(dev);
540 if (am335x_dmtimer_sc != NULL)
543 /* Get the base clock frequency. */
544 err = ti_prcm_clk_get_source_freq(SYS_CLK, &sc->sysclk_freq);
546 device_printf(dev, "Error: could not get sysclk frequency\n");
550 /* Request the memory resources. */
551 err = bus_alloc_resources(dev, am335x_dmtimer_mem_spec,
554 device_printf(dev, "Error: could not allocate mem resources\n");
558 /* Request the IRQ resources. */
559 err = bus_alloc_resources(dev, am335x_dmtimer_irq_spec,
562 device_printf(dev, "Error: could not allocate irq resources\n");
567 * Use the default eventtimer. Let the PPS init routine decide which
568 * timer to use for the timecounter.
570 sc->et_num = DEFAULT_ET_TIMER;
571 sc->tc_num = am335x_dmtimer_pps_init(dev, sc);
573 sc->et_memres = sc->tmr_mem_res[sc->et_num];
574 sc->tc_memres = sc->tmr_mem_res[sc->tc_num];
576 /* Enable clocks and power on the chosen devices. */
577 err = ti_prcm_clk_set_source(DMTIMER0_CLK + sc->et_num, SYSCLK_CLK);
578 err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->et_num);
579 err |= ti_prcm_clk_set_source(DMTIMER0_CLK + sc->tc_num, SYSCLK_CLK);
580 err |= ti_prcm_clk_enable(DMTIMER0_CLK + sc->tc_num);
582 device_printf(dev, "Error: could not enable timer clock\n");
586 /* Setup eventtimer interrupt handler. */
587 if (bus_setup_intr(dev, sc->tmr_irq_res[sc->et_num], INTR_TYPE_CLK,
588 am335x_dmtimer_intr, NULL, sc, &ihl) != 0) {
589 device_printf(dev, "Unable to setup the clock irq handler.\n");
593 /* Set up timecounter, start it, register it. */
594 am335x_dmtimer_tc_write_4(sc, DMT_TSICR, DMT_TSICR_RESET);
595 while (am335x_dmtimer_tc_read_4(sc, DMT_TIOCP_CFG) & DMT_TIOCP_RESET)
598 sc->tc_tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD;
599 am335x_dmtimer_tc_write_4(sc, DMT_TLDR, 0);
600 am335x_dmtimer_tc_write_4(sc, DMT_TCRR, 0);
601 am335x_dmtimer_tc_write_4(sc, DMT_TCLR, sc->tc_tclr);
603 sc->tc.tc_name = "AM335x Timecounter";
604 sc->tc.tc_get_timecount = am335x_dmtimer_tc_get_timecount;
605 sc->tc.tc_counter_mask = ~0u;
606 sc->tc.tc_frequency = sc->sysclk_freq;
607 sc->tc.tc_quality = 1000;
611 sc->et.et_name = "AM335x Eventtimer";
612 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
613 sc->et.et_quality = 1000;
614 sc->et.et_frequency = sc->sysclk_freq;
615 sc->et.et_min_period =
616 ((0x00000005LLU << 32) / sc->et.et_frequency);
617 sc->et.et_max_period =
618 (0xfffffffeLLU << 32) / sc->et.et_frequency;
619 sc->et.et_start = am335x_dmtimer_start;
620 sc->et.et_stop = am335x_dmtimer_stop;
622 et_register(&sc->et);
624 /* Store a pointer to the softc for use in DELAY(). */
625 am335x_dmtimer_sc = sc;
630 static device_method_t am335x_dmtimer_methods[] = {
631 DEVMETHOD(device_probe, am335x_dmtimer_probe),
632 DEVMETHOD(device_attach, am335x_dmtimer_attach),
636 static driver_t am335x_dmtimer_driver = {
638 am335x_dmtimer_methods,
639 sizeof(struct am335x_dmtimer_softc),
642 static devclass_t am335x_dmtimer_devclass;
644 DRIVER_MODULE(am335x_dmtimer, simplebus, am335x_dmtimer_driver, am335x_dmtimer_devclass, 0, 0);
645 MODULE_DEPEND(am335x_dmtimer, am335x_prcm, 1, 1, 1);
650 struct am335x_dmtimer_softc *sc;
652 uint32_t first, last;
654 sc = am335x_dmtimer_sc;
657 for (; usec > 0; usec--)
658 for (counts = 200; counts > 0; counts--)
659 /* Prevent gcc from optimizing out the loop */
664 /* Get the number of times to count */
665 counts = (usec + 1) * (sc->sysclk_freq / 1000000);
667 first = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
670 last = am335x_dmtimer_tc_read_4(sc, DMT_TCRR);
672 counts -= (int32_t)(last - first);
674 counts -= (int32_t)((0xFFFFFFFF - first) + last);